LM3463
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SNVS807A – MAY 2012 – REVISED MAY 2013
Dynamic Headroom Controller with Thermal Control Interface and Individual Channel
Dimming Control
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FEATURES
APPLICATIONS
•
•
•
1
2
•
•
•
•
•
•
•
•
•
•
Dynamic Headroom Control Output to
Maximize Efficiency
6 Channels Current Regulated LED Driver
High Precision Analog Dimming Control
Interface
4 Individual PWM Dimming Control Input
Dimming Control via Digital Data Bus
Built-In Maximum MOSFET Power Limiting
Mechanism
Allows Cascade Operation to Extend the
Output Channels
Fault Indicator Output
Thermal Shutdown
UVLO With Hysteresis
48L WQFN Package
DESCRIPTION
The LM3463 is a six channel linear LED driver with
Dynamic Headroom Control (DHC) interface that is
specialized for high power LED lighting applications.
The variation of the output current of every output
channel in the temperature range of -40°C to 125°C
is well controlled to less than ±1%. The output current
of every channel is accurately matched to each other
with less than ± 1% difference as well.
By interfacing the LM3463 to the output voltage
feedback node of a switching power supply via the
DHC interface, the system efficiency is optimized
automatically. The dynamic headroom control circuit
in the LM3463 minimizes power dissipation on the
external MOSFETs by adjusting the output voltage of
the primary switching power supply according to the
changing forward voltage of the LEDs. Comprising
the advantages of linear and switching converters,
the LM3463 delivers accurately regulated current to
LEDs while maximizing the system efficiency.
KEY SPECIFICATIONS
•
•
•
Streetlights
Solid State Lighting Solutions
Wide supply voltage range (12V-95V)
Thermal fold-back dimming control
DHC regulates the lowest MOSFET drain
voltage to 1V
The dimming control interface of the LM3463 accepts
both analog and PWM dimming control signals. The
analog dimming control input controls the current of
all LEDs while the PWM control inputs control the
dimming duty of output channels individually.
Typical Application
VRAIL
High Power LED Arrays
Voltage output
Voltage
feedback pin
RFB1
Primary power supply
CIN
RDHC
RFB2
D1
GND
U1
OutP
EN
Faultb
Faultb
MODE
MODE
DIM01
DIM01
DIM23
DIM23
DIM4
Vcc
VIN
VLedFB
EN
DR0
DR1
DR5
DIM4
DIM5
DIM5
VCC
RLMT1
DRVLIM
LM3463
CVCC
RLMT2
Q1
GD0
Q2
GD1
FS
CDHC
FCAP
RFS
Q6
GD5
CDHC
CFLT
SE5
RISNS6
VREF
GND
SE1
RIADJ1
RISNS2
SE0
IOUTADJ
CVREF
RISNS1
RIADJ2
GND
REFRTN
GND
REFRTN
GND
GND
GND
REFRTN
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
LM3463
SNVS807A – MAY 2012 – REVISED MAY 2013
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DESCRIPTION CONTINUED
The LM3463 provides a sophisticated protection mechanism that secures high reliability and stability of the
lighting system. The protection features include VIN Under-Voltage–Lock-Out (UVLO), thermal shut-down, LED
short / open circuit protection and MOSFET drain voltage limiting. The LED short circuit protection protects both
the LED and MOSFETS by limiting the power dissipation on the MOSFETS.
GD0
SE0
GD1
SE1
GD2
SE2
GD3
SE3
GD4
SE4
GD5
SE5
48
47
46
45
44
43
42
41
40
39
38
37
Connection Diagram
REFRTN
1
36
NC
IOUTADJ
2
35
DR0
VREF
3
34
NC
EN
4
33
DR1
FS
5
32
NC
Faultb
6
31
DR2
EP
22
23
24
NC
DR5
NC
25
VIN
12
21
CLKOUT
OutP
NC
20
26
VLedFB
11
19
SYNC
VCC
DR4
18
27
MODE
10
17
DIM5
GND
NC
16
DR3
28
15
29
9
FCAP
8
DIM4
CDHC
DIM23
14
NC
DRVLIM
30
13
7
ISR
DIM01
Figure 1. TOP VIEW
48-Lead Plastic WQFN
Package Number RHS
PIN DESCRIPTIONS
Pin
Name
Description
1
REFRTN
0V reference for small signal return
paths
Application information
This pin should connect to the end points of current sensing resistors with
individual connections to ensure channel to channel current accuracy.
2
IOUTADJ
Output current level adjust pin
The current of all output channels (defined by RISNSn) reduces according
to the voltage at this pin. This pin should connect to the VREF pin when
output current reduction is not required.
3
VREF
Precision reference voltage output
This pin is the output of a precision reference voltage regulator. This pin
must be bypassed through a ceramic capacitor to REFRTN.
Device enable pin with internal pull-up
4
EN
Enable input
Enable: VEN = Floating
Disable: VEN = GND
2
5
FS
6
Faultb
Internal oscillator control or external
clock input pin
Fault indicator output
Frequency setting pin. Connect a resistor across this pin to GND to set the
internal oscillator frequency.
The internal clock frequency can be defined by forcing an external clock
signal to this pin.
Fault indicator output. This pin is an open-drain output and is pulled low
when an open circuit of LED string is identified.
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PIN DESCRIPTIONS (continued)
Pin
7
8
9
10
11
Name
DIM01
Description
Application information
Multi-function input pin.
The function of this pin differs depending on the selected operation mode
that sets by the MODE pin.
Channel 0/1 PWM dimming control
Direct PWM mode: Apply a bi-level PWM signal (TTL logic high and low)
to this pin to enable/disable ch0 and ch1. Apply logic high to this pin to
enable channel 0 and 1.
Serial data input
In serial interface mode, this pin is configured as the serial data input.
DC voltage dimming control
In DC interface mode, the voltage on this pin is converted into PWM
dimming duty for channel 0 and 1.
Multi-function input pin.
The function of this pin differs depending on the selected operation mode
that sets by the MODE pin.
Channel 2/3 PWM dimming control
Direct PWM mode: apply bi-level PWM signal (TTL logic high and low) to
this pin to enable/disable ch2 and ch3. Apply a logic high to this pin to
enable both channel 2 and 3.
Serial clock input
In serial interface mode, this pin is configured as the serial clock signal
input.
DC voltage dimming control
In DC interface mode, the voltage on this pin is converted into PWM
dimming duty for channel 2 and 3.
Multi-function input pin.
The function of this pin differs depending on the selected operation mode
that sets by the MODE pin.
Channel 4 dimming control
Direct PWM mode: apply bi-level PWM signal to this pin to enable/disable
channel 4. Apply logic high to this pin to enable channel 4.
Load data control pin
In serial interface mode, this pin is configured as load pulse input, pulling
this pin low will latch the shifted-in data into internal register of the
LM3463. This pin is pulled low if the requested load operation is not
completed. User should check the status of this pin before writing data into
the LM3463 through this pin.
DC voltage dimming control
In DC interface mode, the voltage on this pin is converted into PWM
dimming duty for channel 4.
Multi-function input pin.
The function of this pin differs depending on the selected operation mode
that sets by the MODE pin.
Channel 5 dimming control
Direct PWM mode: Apply a bi-level PWM signal (TTL logic high and low)
to this pin to enable/disable channel 5. Apply a logic high to this pin to
enable channel 5.
Serial operation mode
This pin should connect to GND when serial operation mode is selected.
DC voltage dimming control
In DC interface mode, the voltage on this pin is converted into PWM
dimming duty for channel 5.
Serial data output for cascade
operation
Serial control signal output pin for cascade operation. This signal
synchronizes with the rising edge of the CLKOUT signal and carries
information to the slave devices to turn on LEDs.
Sync. pulse input in direct PWM
mode
This is a synchronization signal input pin for the slave device to perform
LED pretest upon system startup.
Dimming clock output for cascade
operation / Sync pulse output for
Direct PWM mode
Dimming clock output for cascade operation. The frequency at this pin
equal to 1/2 of the internal clock or externally applied clock frequency.
DIM23
DIM4
DIM5
SYNC
12
CLKOUT
13
ISR
Connect a resistor from this pin to GND to set the additional bias current
to the CDHC upon system startup.
Start up current control pin
The voltage on this pin defines the threshold of the drain voltage of the
external MOSFETs (VDRn) to begin output current reduction.
MOSFET power limit setting input
As the VDRn exceeds VDRVLIM, the LED driving current reduces according
to the increasing of VDRn at certain fixed rate. This function prevents the
MOSFET from over-heating. The maximum power dissipation is limited to
VDRVLIM * ILED(per ch.).
CDHC
Dynamic headroom control time
constant capacitor
Connect a capacitor (CDHC) from this pin to ground to program the DHC
loop response.
16
FCAP
Fault de-bounce capacitor
Connect a capacitor, CFLT from this pin to ground to program the fault debounce time.
17
GND
System ground
This pin should connect to the system ground
14
DRVLIM
15
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PIN DESCRIPTIONS (continued)
Pin
Name
Description
Application information
Operation mode selection input pin. Bias this pin externally to set the
LM3463 in different operation mode.
18
MODE
Direct PWM mode: VMODE = GND
Mode select input pin
Serial interface mode: VMODE = No Connection
DC interface mode: VMODE = VCC
19
VCC
20
VLedFB
Output terminal of the internal voltage regulator. This pin should be
bypassed to GND through a 1uf ceramic capacitor.
Internal regulator output
Rail voltage detection input pin
This pin detects the output voltage of the primary power supply (VRAIL).
LEDs will be turned on when the voltage at this pin reaches 2.5V.
Connect this pin to VCC to set a device as a slave.
21
OutP
22
NC
23
VIN
24
NC
25
DR5
26
NC
27
DR4
28
NC
29
DR3
30
NC
31
DR2
32
NC
33
DR1
34
NC
35
DR0
36
NC
No connection
Supply voltage input pin. This pin should be bypassed to GND using a 1uF
ceramic capacitor.
System supply
No connection
Channel 5 drain voltage feedback
input to facilitate DHC
Connect to the junction of the drain terminal of the external MOSFET and
the cathode of the LED string. This pin is connected to the internal
comparator to facilitate DHC.
No connection
Channel 4 drain voltage feedback
input to facilitate DHC
Connect to the junction of the drain terminal of the external MOSFET and
the cathode of the LED string. This pin is connected to the internal
comparator to facilitate DHC.
No connection
Channel 3 drain voltage feedback
input to facilitate DHC
Connect to the junction of the drain terminal of the external MOSFET and
the cathode of the LED string. This pin is connected to the internal
comparator to facilitate DHC.
No connection
Channel 2 drain voltage feedback
input to facilitate DHC
Connect to the junction of the drain terminal of the external MOSFET and
the cathode of the LED string. This pin is connected to the internal
comparator to facilitate DHC.
No connection
Channel 1 drain voltage feedback
input to facilitate DHC
Connect to the junction of the drain terminal of the external MOSFET and
the cathode of the LED string. This pin is connected to the internal
comparator to facilitate DHC.
No connection
Channel 0 drain voltage feedback
input to facilitate DHC
Connect to the junction of the drain terminal of the external MOSFET and
the cathode of the LED string. Voltage on this pin is being fed to the
internal comparator to facilitate DHC.
No connection
37
SE5
Channel 5 LED driver sense input
pin
38
GD5
channel 5 gate drive output pin
Gate driver output. Connect to the gate terminal of the external MOSFET.
39
SE4
Channel 4 LED driver sense input
pin
Connect to the junction of the source terminal of the external MOSFET
and the sense resistor to facilitate current regulation for channel 4.
40
GD4
channel 4 gate drive output pin
Gate driver output. Connect to the gate terminal of the external MOSFET.
41
SE3
Channel 3 LED driver sense input
pin
Connect to the junction of the source terminal of the external MOSFET
and the sense resistor to facilitate current regulation for channel 3.
42
GD3
channel 3 gate drive output pin
Gate driver output. Connect to the gate terminal of the external MOSFET.
43
SE2
Channel 2 LED driver sense input
pin
Connect to the junction of the source terminal of the external MOSFET
and the sense resistor to facilitate current regulation for channel 2.
44
GD2
channel 2 gate drive output pin
Gate driver output. Connect to the gate terminal of the external MOSFET.
SE1
Channel 1 LED driver sense input
pin
Connect to the junction of the source terminal of the external MOSFET
and the sense resistor to facilitate current regulation for channel 1.
45
4
This pin is an open drain output (current sink) which should connect to the
output voltage feedback node of the primary power supply through a
resistor and a diode to realize rail voltage adjustment.
DHC output Driver
Connect to the junction of the source terminal of the external MOSFET
and the sense resistor to facilitate current regulation for channel 5.
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PIN DESCRIPTIONS (continued)
Pin
Name
46
GD1
channel 1 gate drive output pin
Gate driver output. Connect to the gate terminal of the external MOSFET.
47
SE0
Channel 0 LED driver sense input
pin
Connect to the junction of the source terminal of the external MOSFET
and the sense resistor to facilitate current regulation for channel 0.
48
GD0
channel 0 gate drive output pin
Gate driver output. Connect to the gate terminal of the external MOSFET.
Thermal Pad
Connect to the GND pin. The EP has no internal connection to ground and
must connect to the GND pin externally. Place 9 vias from EP to copper
ground plane.
EP
Description
Application information
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
VIN to GND
-0.3V to 100V
DR0, DR1, DR2, DR3, DR4, DR5 to GND
-0.3V to 100V
EN
-0.3V to 5.5V
DRVLIM
-0.3V to 6V
Faultb
-0.3V to 20V
All other pins
-0.3V to 7V
ESD Rating, Human Body Model
(3)
±2 kV
Storage Temperature
−65°C to +150°C
Junction Temperature (TJ)
−40°C to +125°C
(1)
(2)
(3)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Human Body Model, applicable std. JESD22-A114-C.
Operating Ratings
Supply Voltage Range (VIN)
12V to 95V
−40°C to + 125°C
Junction Temperature Range (TJ)
Thermal Resistance (θJA)
24°C/W
Thermal Resistance (θJC) (1)
2.5°C/W
(1)
θJC measurements are performed in general accordance with Mil-Std 883B, Method 1012.1 and utilize the copper heat sink technique.
Copper Heat Sink @ 60°C.
Electrical Characteristics
Specification with standard type are for TA = TJ = +25°C only; limits in boldface type apply over the full Operating Junction
Temperature (TJ) range. Minimum and Maximum are specified through test, design or statistical correlation. Typical values
represent the most likely parametric norm at TJ = +25°C, and are provided for reference purposes only. Unless otherwise
stated, the following conditions apply: VIN = 48V.
Symbol
Parameter
Conditions
IIN
VIN Quiescent Current
ISD
VIN Shut-Down Current
Min
Typ
Max
Units
VEN pin floating
9.75
15
mA
VEN = 0V
550
800
µA
7.4
10
V
Supply
VIN UVLO
VIN-UVLO
VIN Turn-on Threshold
VIN Turn-off Threshold
4.5
VIN UVLO Hysteresis
7.1
V
300
mV
VCC Regulator
VCC
VCC Regulated Voltage
IVCC-LIM
VCC Current Limit
VCC-UVLO
VCC Turn-on Threshold
CVCC = 1 µF, IVCC=1mA
6.240
6.475
6.760
ICC = 10 mA
6.230
6.462
6.741
V
28
45
mA
4.5
4.7
V
VCC = 0V
VCC Turn-off Threshold
3.75
VCC UVLO hysteresis
VCC Decreasing
V
4.20
V
300
mV
Internal Reference Voltage Regulator
VVREF
Reference Voltage Regulator Output
Voltage
CVREF = 0.47 µF, No Load
2.453
2.499
2.564
IVREF = 2mA
2.443
2.496
2.545
V
IVREF-SC
VREF Pin Short-Circuit Current
VVREF = VREFRTN
7.0
8.2
10.5
mA
6
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Electrical Characteristics (continued)
Specification with standard type are for TA = TJ = +25°C only; limits in boldface type apply over the full Operating Junction
Temperature (TJ) range. Minimum and Maximum are specified through test, design or statistical correlation. Typical values
represent the most likely parametric norm at TJ = +25°C, and are provided for reference purposes only. Unless otherwise
stated, the following conditions apply: VIN = 48V.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Dimming Control Interfaces
Analog Mode
VDIMn-MAX
DIMn Voltage at 100% Output Duty Cycle MODE = VCC
5.65
V
VDIMn-MIN
DIMn Voltage at 0% Output Duty Cycle
MODE = VCC
807
mV
VDIMn-001H
DIMn Voltage at data code = 001h
MODE = VCC
826
mV
VDIM-LED-ON
DIMn Voltage Threshold at LED ON
MODE = GND
VDIM-LED-OFF
DIMn Voltage Threshold at LED OFF
VDIM-LED-HYS
DIMn Voltage Hysteresis at LED ON to
OFF
PWM Mode
1.50
1.1
1.75
V
1.4
V
100
mV
System Clock Generator
VFS
FS Pin Voltage
FS Pin = Open
IFS-SC
FS Pin Short-Circuit Current
VFS = 0V
fOSC
System Clock Frequency
RFS = 14 kΩ
1.173
0.90
1.235
1.297
V
110
140
µA
1.00
1.15
MHz
1.50
1.75
V
Bus Interface Mode
VSCLK-HIGH
(DIM23)
SCLK (Serial CLK) Logic High Threshold
MODE = Hi-Z
VSCLK-LOW
(DIM23)
SCLK (Serial CLK) Logic Low Threshold
MODE = Hi-Z
VSCLK-HYS
(DIM23)
SCLK (Serial CLK) Hysteresis
MODE = Hi-Z
VSDA-HIGH (DIM01)
SDA (Serial Data) Logic High Threshold
MODE = Hi-Z
VSDA-LOW (DIM01)
SDA (Serial Data) Logic Low Threshold
MODE = Hi-Z
VSDA-HYS
SDA (Serial Data) Hysteresis
(DIM01)
1.1
1.4
V
100
mV
1.50
1.1
1.75
V
1.4
V
MODE = Hi-Z
100
mV
0.95
V
Dynamic headroom Control
VDRn-DHC-STDEAY
The lowest VDRn when DHC is under
steady state
Measure at DRn pin
VVLedFB-TH
VLedFB Voltage Threshold for Turning
LEDs ON
VVLedFB Increasing
VVLedFB-HYS
VLedFB Voltage Hysteresis
VVLedFB decreasing
VVLedFBEN-SLAVE
VLedFB Pin Voltage Threshold for Slave
Mode
Measure at VLedFB pin
5.15
5.39
5.60
V
VOutP-MAX
OutP Max. Output Voltage
IOutP = 1mA
Current Sink
VCDHC = 0.5V
2.90
3.10
3.25
V
VOutP-MIN
OutP Min. Output Voltage
IOutP =1mA
Current Sink
VCDHC = 3.5V
0.050
0.120
0.235
V
VISR
ISR Pin Voltage
IISR = 1µA
Current Sink to GND
1.226
1.307
1.382
V
IISR = 10µA
Current Sink to GND
1.195
1.240
1.285
V
IISR = 100µA
Current Sink to GND
1.075
1.125
1.175
V
µA
2.325
2.500
2.625
1.21
V
V
ICDHC-SOURCE
CDHC Pin Max. Sourcing Current
Any VDRn < 0.9V
15
26
35
ICDHC-SINK
CDHC Pin Max. Sinking Current
Any VDRn > 0.9V
20
33
45
µA
RCDHC-SOURCE
CDHC Pin Output Impedance
Sourcing current from CDHC pin
1.20
1.70
2.25
MΩ
RCDHC-SINK
CDHC Pin Output Impedance
Sinking current from CDHC pin
0.7
1.1
1.4
MΩ
gmCDHC-OTA
CDHC Pin OTA Transconductance
VDRn ≥ 0.9V
75
µmho
VDRn < 0.9V
17
µmho
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Electrical Characteristics (continued)
Specification with standard type are for TA = TJ = +25°C only; limits in boldface type apply over the full Operating Junction
Temperature (TJ) range. Minimum and Maximum are specified through test, design or statistical correlation. Typical values
represent the most likely parametric norm at TJ = +25°C, and are provided for reference purposes only. Unless otherwise
stated, the following conditions apply: VIN = 48V.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
5.30
5.75
6.20
V
mA
LED Current Regulator
VGDn-MAX
GDn Gate Driver Maximum Output
Voltage
VSEn = 0V
IGDn-MAX
GDn Gate Driver Short Circuit Current
VGDn = 0V
10
16
IDRn-MAX
DRn pin Maximum Input Current
VDRn = 80V
35
50
65
µA
VSEn
Output Current Sensing Reference
Voltage w.r.t VREFRTN
VIOUTADJ = VVREF
190
200
210
mV
VIOUTADJ = VVREF / 2
85
100
115
mV
VIOUTADJ = VREFRTN
2.0
4.6
6.5
mV
Fault Detection and Handling
VSEn-LED-OPEN-FLT
LED Open Fault Detection Voltage
Threshold at SEn Pin
Measure at SEn pin
43
ISEn-LED-OPEN-FLT
LED Open Fault Detection Current
Threshold at SEn Pin
Measure at SEn pin
VDRn-LED-NORMAL
LED Open Fault Detection Voltage
Threshold at DRn Pin
Measure at DRn pin
IFCAP-CHG
Fault Cap. Charging Current
Fault = True
20
28
40
µA
VFCAP-FLT-TH
FCAP Pin Fault Confirm Voltage
Threshold
Measure at FCAP pin
3.3
3.6
3.9
V
VFCAP-RST-TH
FCAP Pin Fault Reset Voltage Threshold
Measure at FCAP pin
85
157
230
mV
2.6
3.3
V
15
22
mV
30
330
µA
mV
Device Enable
VEN-ENABLE
EN Pin Voltage Threshold for Device
Enable
VEN-DISABLE
EN Pin Voltage Threshold for Device
Disable
VEN-HYS
Device Enable Hysteresis
1.9
2.5
V
100
mV
Thermal Protection
TSD
Thermal shutdown temperature
TJ Rising
165
°C
TSD-HYS
Thermal shutdown temperature hysteresis TJ Falling
20
°C
8
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Typical Performance Characteristics
All curves taken at VIN = 48V with configuration in typical application for driving twelve power LEDs with six output channels
active and 350 mA output current per channel. TA = 25°C, unless otherwise specified.
VSEn vs Temperature, VIOUTADJ=VREF
VSEn vs Temperature, VIOUTADJ=0.5 VREF
103.0
0.203
102.5
0.202
102.0
VSEn(mV)
101.5
VSEn(V)
0.201
101.0
0.200
0.199
VIOUTADJ= VREF
100.5
CH0
CH1
CH2
CH3
CH4
CH5
100.0
99.5
0.198
VIOUTADJ=0.5*VREF
CH0
CH2
CH3
CH4
CH5
99.0
-40 -20 0
20 40 60 80 100 120 140
TA(°C)
-40 -20 0
20 40 60 80 100 120 140
TA(°C)
Figure 2.
Figure 3.
Variation of VSEn vs Temperature, VIOUTADJ=VREF
Variation of VSEn vs Temperature, VIOUTADJ=0.5 VREF
0.8
1.5
0.6
1.0
VIOUTADJ=VREF
0.2
ûVSEn(%)
ûVSEn(%)
0.4
0.0
-0.2
CH0
CH1
CH2
CH3
CH4
CH5
-0.4
-0.6
0.5
0.0
CH0
CH1
CH2
CH3
CH4
CH5
-0.5
-1.0
-0.8
-40 -20 0
VIOUTADJ=0.5*VREF
-1.5
20 40 60 80 100 120 140
TA(°C)
-40 -20 0
20 40 60 80 100 120 140
TA(°C)
Figure 4.
Figure 5.
CH-CH Variation of VSEn vs Temperature, VIOUTADJ=VREF
CH-CH Variation of VSEn vs Temperature, VIOUTADJ=0.5 VREF
0.29
0.56
VSEnCH-CH Variation (%)
VSEnCH-CH Variation (%)
0.26
0.24
0.22
0.20
0.18
0.16
0.15
0.12
VIOUTADJ=VREF
0.10
-40 -20 0
0.50
0.45
0.40
0.35
0.30
0.25
VIOUTADJ=0.5*VREF
0.20
20 40 60 80 100 120 140
TA(°C)
Figure 6.
-40 -20 0
20 40 60 80 100 120 140
TA(°C)
Figure 7.
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Typical Performance Characteristics (continued)
All curves taken at VIN = 48V with configuration in typical application for driving twelve power LEDs with six output channels
active and 350 mA output current per channel. TA = 25°C, unless otherwise specified.
VSEn vs VIOUTADJ, TA=125°C
VSEn vs VIOUTADJ (VIOUTADJ < 60 mV), TA=125°C
0.200
12
0.175
0.150
TA=125°C
10
TA=125°C
VSEn(V)
VSEn(mV)
0.125
0.100
0.075
8
6
CH0
CH1
CH2
CH3
CH4
CH5
4
0.050
2
0.025
0.000
0.0
0
0.5
1.0
1.5
VIOUTADJ(V)
2.0
2.5
0
20
30
40
VIOUTADJ(mV)
VSEn vs VIOUTADJ, TA=25°C
VSEn vs VIOUTADJ (VIOUTADJ < 60 mV), TA=25°C
12
TA=25°C
10
TA=25°C
VSEn(V)
VSEn(mV)
0.125
0.100
0.075
8
6
CH0
CH1
CH2
CH3
CH4
CH5
4
0.050
2
0.025
0.000
0
0.5
1.0
1.5
VIOUTADJ(V)
2.0
2.5
0
10
20
30
40
VIOUTADJ(mV)
VSEn vs VIOUTADJ, TA=–40°C
VSEn vs VIOUTADJ (VIOUTADJ < 60 mV), TA=–40°C
12
TA=-40°C
10
TA=-40°C
VSEn(V)
VSEn(mV)
0.125
0.100
0.075
8
6
CH0
CH1
CH2
CH3
CH4
CH5
4
0.050
2
0.025
0.000
0
0.5
1.0
1.5
VIOUTADJ(V)
2.0
2.5
Figure 12.
10
60
Figure 11.
0.175
0.0
50
Figure 10.
0.200
0.150
60
Figure 9.
0.175
0.0
50
Figure 8.
0.200
0.150
10
0
10
20
30
40
VIOUTADJ(mV)
50
60
Figure 13.
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Typical Performance Characteristics (continued)
All curves taken at VIN = 48V with configuration in typical application for driving twelve power LEDs with six output channels
active and 350 mA output current per channel. TA = 25°C, unless otherwise specified.
VREF vs Temperature
2.55
3.45
2.54
3.40
2.53
3.35
2.52
VREF(V)
VOutP-MAX(V)
VOutP-MAX vs Temperature
3.50
3.30
3.25
3.20
2.51
2.50
2.50
3.15
2.48
3.10
2.48
3.05
2.46
3.00
2.46
-40 -20 0
20 40 60 80 100 120 140
TA(°C)
-40 -20 0
Figure 14.
Figure 15.
VCC vs Temperature
Operating IIN vs Temperature
6.56
9.00
6.54
8.95
8.90
OPERATING IIN(mA)
6.52
VCC(V)
20 40 60 80 100 120 140
TA(°C)
6.50
6.48
6.46
6.44
8.85
8.80
8.75
8.70
8.65
8.60
6.42
8.56
6.40
-40 -20 0
20 40 60 80 100 120 140
TA(°C)
Figure 16.
8.50
-40 -20 0
20 40 60 80 100 120 140
TA(°C)
Figure 17.
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Block Diagram
LM3463
VREF
Pre-Regulator
IOUTADJ
Output current
control circuitry
REFRTN
Ref1
VIN
VCC
VBG
ADCRef
ISR
EN
OutP
CDHC
DHC circuitry
High voltage Fault detection
circuitry
VLedFB
DRVLIM
DR0
DR1
DR2
Faultb
Fault/Control Logic
DR3
DR4
MODE
DR5
C255
C223
Fault
GD0
S/H
Load
Shift Enable
PCLK
Serial IF
FCAP
DIM01
Fault
GD1
DIM23
Serial IF
Pulse Width Controller
Input Interface
32 bit shift register
S/H
DIM4
GD2
S/H
GD3
S/H
SE3
Ref1
Fault
Mode
Control
GD4
8-bit Timing
Decoder
C255
GD5
S/H
SE5
Ref1
GND
FS
Oscillator (ADC, duty PCLK
cycle control)
SE4
Ref1
Fault
PCLK
C223
SAR
ADC
S/H
C255
SYNC
CLKOUT
SE2
Ref1
Fault
Mode
Control
12
SE1
Ref1
Fault
DIM5
5 to 1
MUX
SE0
Ref1
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Overview
The LM3463 is a six channel linear current regulator which designed for LED lighting applications. The use of the
Dynamic Headroom Control (DHC) method secures high system power efficiency and prolongs system operation
lifetime by minimizing the power stress on critical components. The output currents of the LM3463 driver stage
are regulated by six individual low-side current regulators.
The current regulators are accompanied by a high precision current sensing circuit. In order to ensure excellent
current matching among output channels, the current sensing inputs are corresponding to a dedicated reference
point, the REFRTN pin to insulate the ground potential differences due to trace resistances. With this current
sensing circuit, the channel to channel output current difference is well controlled below ±10% when the output
current is reduced (DC LED current reduction) to 5%.
LED Current Regulators and Analog Dimming Control
The LM3463 provides six individual linear current regulators to perform LED current regulation. Each current
regulator includes an internal MOSFET driver and error amplifier and an external MOSFET and current sensing
resistor. The output current of every output channel is defined by the value of an external current sensing resistor
individually. The reference voltage of the regulators can be adjusted by changing the bias voltage at the
IOUTADJ pin.
When analog dimming control applies, the output current of all channels reduces proportional to the voltage
being applied to the IOUTADJ pin. Figure 18 shows the simplified block diagram of a current regulator.
VCC
VREF
VREF
Regulator
To LED
Cathode
LM3463
DHC Circuit
DRn
RIADJ1
IOUTADJ
GDn
SEn
RIADJ2
RISNSn
REFRTN
GND
Figure 18. Block diagram of a linear current regulator
Since the driving current of a LED string is determined by the resistance of the current sensing resistor RISNSn
individually, every channel can have different output current by using different value of RISNSn. The LED current,
IOUTn is calculated using the following expression:
(1)
AND since:
(2)
Thus,
(3)
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The above equations apply when VIOUTADJ is equal to or below VREF (2.5V). Generally the VIOUTADJ should not be
set higher than VREF. Applying a voltage high than VREF to the IOUTADJ pin could result in inaccurate LED
driving currents which fall out of the specification. Figure 19 shows the relationship of VIOUTADJ and VSEn.
0.25
VSEn(V)
0.20
0.15
0.10
0.05
0.00
0
1
2
3
4
5
VIOUTADJ(V)
6
7
Figure 19. VSEn versus VIOUTADJ
Since the analog dimming control interface is designed for slow brightness control only, the rate of change of the
voltage at the IOUTADJ pin must not be higher than 1.25V/sec to allow good tracking of the output current and
changing of the VIOUTADJ. The voltage at the IOUTADJ pin can be provided by an external voltage source as
shown in Figure 20.
LM3463
IOUTADJ
External
voltage source
0V - 2.5V
V
REFRTN
GND
GND
Figure 20. Adjust VSEn by external voltage
To secure high accuracy and linearity of dimming control, the voltage of the IOUTADJ pin can be provided by a
voltage divider connecting across the VREF and REFRTN pins as shown in Figure 21.
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LM3463
VREF
CVREF
RIADJ1
IOUTADJ
RIADJ2
REFRTN
GND
GND
Figure 21. Biasing IOUTADJ from VREF
VCC Regulator
The VCC regulator accepts an input voltage in the range of 12V to 95V from the VIN pin and delivers a 6.5V
typical constant voltage at the VCC pin to provide power and bias voltages to the internal circuits. The VCC pin
should be bypassed to ground by a low ESR capacitor across the VCC and GND pins. A 1uF 10V X7R capacitor
is suggested.
The output current of the VCC regulator is limited to 20 mA which includes the biasing currents to the internal
circuit. When using the VCC regulator to bias external circuits, it is suggested to sink no more than 10 mA from
the VCC regulator to prevent over-heating of the device.
VREF Regulator
The VREF regulator is used to provide precision reference voltage to internal circuits and the IOUTADJ pin.
Other than providing bias voltage to the IOUTADJ pin, the VREF pin should not be used to provide power to
external circuit. The VREF pin must be bypassed to ground by a low ESR capacitor across the VREF and
RETRTN pins. A 0.47uF 10V X7R capacitor is suggested.
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Q1
GD0
Q2
GD1
LM3463
Q6
GD5
SE5
RISNS6
VREF
SE1
RIADJ1
IOUTADJ
CVREF
RIADJ2
GND
RISNS2
SE0
RISNS1
REFRTN
GND
GND
GND
GND
Figure 22. Individual connections to REFRTN
REFRTN and GND
The REFRTN pin is the reference point for the high precision and low noise internal circuits. The pins which
referenced to the REFRTN are VREF, IOUTADJ, SE0, SE1, SE2, SE3, SE4 and SE5. To secure accurate
current regulations, the current sensing resistors, RISNSn should connect to the REFRTN pin directly using
dedicated connections. And the REFRTN and GND pins should be connected together using dedicated
connection as shown in Figure 22.
Device Enable
The LM3463 can be disabled by pulling the EN pin to ground. The EN pin is pulled up by an internal weak-pullup circuit, thus the LM3463 is enabled by default. Pulling the EN pin to ground will reset all fault status. A system
restart will be undertaken when the EN pin is released from pulling low.
Open Circuit of LED String(s)
When a LED string is disconnected, the LM3463 pulls the Faultb low to indicate a fault condition. The Faultb is
an open-drain output pin. An open circuit of a LED string is detected when a VSEn is below 43 mV and the VDRn
of the corresponding channel is below 300mV simultaneously. When the fault conditions are fulfilled, the LM3463
waits for a delay time to recognize whether there is a disconnected LED or not. If the conditions of open circuit of
LED is sustained longer than the delay time, a real fault is recognized. The delay time for fault recognition is
defined by the value of an external capacitor, CFLT, and governed by the following equation:
(4)
The fault indication can be reset by either applying a falling edge to the EN pin or performing a system repowering.
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System Clock Generator
The LM3463 includes an internal clock generator which is used to provide clock signal to the internal digital
circuits. The clock frequency at the CLKOUT pin is equal to 1/2 of the frequency of the internal system clock
generator. The system clock generator governs the rate of operation of the following functions:
• PWM dimming frequency in Serial Interface Mode
• PWM dimming frequency in DC Interface Mode
• Clock frequency in cascade operation (CLKOUT pin)
The system clock frequency is defined by the value of an external resistor, RFS following the equation:
(5)
Operation Mode
CLKOUT Freq.
Dimming Freq.
RFS
Serial Interface Mode
125 kHz
488. 3Hz
125 kΩ
DC Interface Mode
625 kHz
488.3Hz
62.2 kΩ
Direct PWM Mode
625 kHz
Virtually no limit
62.2 kΩ
Dynamic Headroom Control (DHC)
The Dynamic Headroom Control (DHC) is a control method which aimed at minimizing the voltage drops on the
linear regulators to optimize system efficiency. The DHC circuit inside the LM3463 controls the output voltage of
the primary power supply (VRAIL) until the voltage at any drain voltage sensing pin (VDRn) equals 1V. The LM3463
interacts with the primary power supply through the OutP pin in a slow manner which determined by the
capacitor, CDHC. Generally, the value of the CDHC defines the frequency response of the LM3463. The higher the
capacitance of the CDHC, the lower the frequency response of the DHC loop, and vice versa. Since the VRAIL is
controlled by the LM3463 via the DHC loop, the response of the LM3463 driver stage must be set one decade
lower than the generic response of the primary power supply to secure stable operation.
The cut-off frequency of the DHC loop is governed by the following equation:
(6)
Practically, the frequency response of the primary power supply might not be easily identified (e.g. off-the-shelf
AC/DC power supply). For the situations that the primary power supply has an unknown frequency response, it is
suggested to use a 2.2uF 10V X7R capacitor for CDHC as an initial value and decrease the value of the CDHC to
increase the response of the whole system as needed.
Holding VRAIL In Analog Dimming Control
Due to the V-I characteristic of the LED, the forward voltage of the LED strings decreases when the forward
current is decreased. In order to compensate the rising of the voltage drop on the linear regulators when
performing analog dimming control (due to the reduction of LED forward voltages), the DHC circuit in the LM3463
reduces the rail voltage (VRAIL) to maintain minimum voltage headroom (i.e. minimum VDRn).
In order to ensure good response of analog dimming control, the VRAIL is maintained at a constant level to
provide sufficient voltage headroom when the output currents are adjusted to a very low level. When the voltage
at the IOUTADJ pin is decreased from certain level to below 0.63V, the DHC circuit stops to react to the
changing of VDRn and maintains the VRAIL at the level while VIOUTADJ equals 0.63V. DHC resumes when the
VIOUTADJ is increased to above 0.63V. Figure 23 shows the relationship of the VRAIL, VSEn and VIOUTADJ.
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Due to the changing of LED
current, DHC adjusts the
VRAIL
VRAIL to maintain constant
voltage headroom
VRAIL(steady)
DHC resumes as
VRAIL maintains as the
VIOUTADJ increases
to above 0.63V
VIOUADJ equals 0.63V
0V
Time
VSEn
LED current changes
VSEn changes
with constant VRAIL
following VIOUTADJ
Time
0V
VIOUTADJ
2.5V
VRAIL remains
constant when the
0.63V
VIOUTADJ is equal
to or below 0.63V
Time
Figure 23. Holding VRAIL when VIOUTADJ is below 0.63V
System Startup
When the LM3463 is powered, the internal Operational Transconductance Amplifier (OTA) charges the capacitor
CDHC through the CDHC pin. As the voltage at the CDHC pin increases, the voltage at the OutP pin starts to
reduce from VCC. When the voltage of the OutP pin falls below VFB + 0.7V, the OutP pin sinks current from the
VFB node and eventually pulls up the output voltage of the primary power supply (VRAIL). As the VRAIL reaches
VDHC_READY, the LM3463 performs a test to identify the status of the LED strings (short / open circuit of LED
strings). The VDHC_REDAY is defined by an external voltage divider which consists of RFB1 and RFB2. The
VDHC_READY is calculated following the equation:
(7)
After the test is completed, the LM3463 turns on the LED strings with regulated output currents. At the moment
that the LM3463 turns the LEDs on, the OutP pin stops sinking current from the VFB node and in turn VRAIL slews
down. Along with the decreasing of VRAIL, the voltage at the VDRn pins falls to approach 1V. When a VDRn is
decreased to 1V, the DHC loop enters a steady state to maintain the lowest VDRn to 1V average at a slow
manner defined by CDHC. Figure 24 presents the changes of VRAIL from system power up to DHC loop enters
steady state.
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VRAIL
VRAIL(peak)
VDHC_READY
VRAIL(steady)
VRAIL(nom)
0
Time
Initiated by
Pushed up
primary power
by LM3463
supply
DHC activated
Figure 24. Changes of VRAIL during system startup
Shortening System Startup Time
The system startup time can be shortened by sinking current from the ISR pin to ground through a resistor, RISR.
The lower resistance the RISR carries, the shorter time the system startup takes. Sinking current from the ISR pin
increases the charging current to the capacitor, CDHCand eventually increases the rate of the increasing of VRAIL
during startup (VRAIL ramps up from VRAIL(nom) to VDHC_READY). Figure 25 shows how the system startup time is
shortened by using different value of RISR.
VRAIL
tST-1
tST-2
tST-3
VDHC_READY
VLED
VRAIL(nom)
VIN-UVLO
6.67V
Startup time
RISR
tST-1
open
tST-2
high
tST-3
low
Time
0
Figure 25. Setting different startup time using different RISR
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Generally, the system startup time tST is the longest when the ISR pin is left open (tST-1). The amount of the
decreasing of the startup time is inversely proportional to the current being drawn from the ISR pin, thus
determined by the value of the resistor, RISR. The rate of decreasing of the startup time is governed by the
following equation.
(8)
The practical startup time varies according to the settings of the VDHC_READY, VFB, CDHC and RISR with respect to
the following equations.
(9)
where
(10)
Sinking higher than 100 µA from the ISR pin could damage the device. The value of the RISR should be no lower
than 13 kΩ to prevent potential damages.
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PROCEDURES
REMARKS
Begin design
VLED-MAX-COLD, the highest forward
voltage of LED strings under low
temperature
Identify VLED-MAX-COLD
VLED-MIN-HOT, the lowest forward voltage
of LED strings under high temperature
Identify VLED-MIN-HOT
Adjust the nominal output voltage of the
primary power supply,
VRAIL(nom) = VLED-MIN-HOT - 5V
Set the peak output voltage of the primary
power supply (at VOutP = 0.15V),
VRAIL(peak) = VLED-MAX-COLD + 10V
Set the LED turn on voltage,
VDHC_READY = VLED-MAX-COLD + 5V
VRAIL(nom), the nominal output voltage
of the primary power supply.
e.g. Assume VFB = 2.5V,
R1 + R2
VRAIL(nom) = 2.5V
R2
VRAIL(peak), the output voltage of the
primary power supply when the OutP
pin is pulling to its minimum.
VRAIL(peak) = R1
VFB
R2
VFB - 0.15 - 0.6
RDHC
VFB
VDHC_READY, the LED turn on voltage is
defined by RFB1 and RFB2 connected to
the VLedFB pin.
RFB1 + RFB2
VDHC_READY = 2.5V
RFB2
End of design
Figure 26. Procedure of defining startup parameters
Setting the RDHC and VRAIL
Prior to defining the parameters for the operations in steady state, the value of the RDHC and different levels of
the supply rail voltage (VRAIL) during system startup must be determined. Figure 26 illustrates the procedures of
determining the value of the RDHC and voltage levels of the VRAIL(nom), VRAIL(peak) and VDHC_READY.
In Figure 26, the VLED-MAX-COLD and VLED-MIN-HOT are the maximum and minimum forward voltages of the LED
strings under the required lowest and highest operation temperatures respectively. In order to ensure all the LED
string are supplied with adequate forward current when turning on the LEDs, the VDHC_READY must be set higher
than the VLED-MAX-COLD. For most applications, the VDHC_READY can be set 5 V higher than the VLED-MAX-COLD.
In order to reserve voltage headroom to perform DHC under high operation temperature, the nominal output
voltage of the primary power supply must be set lower than the VLED-MIN-HOT. For most applications, the VRAIL(nom)
can be set 5 V lower than the VLED-MIN-HOT. Figure 27 shows an example connection diagram of interfacing the
LM3463 to a power supply of 2.5V feedback reference voltage.
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Primary power supply
VRAIL
LM3463
To control circuit of
primary power supply
R1
VFB
RDHC
OutP
2.5V
RFB1
VIN
VLedFB
GND
R2
REFRTN
RFB2
GND
Figure 27. Connecting the LM3463 to a power supply
PROCEDURES
REMARKS
Begin power
supply selection
Determine:
ILEDx, VRAIL(peak) and VRAIL(nom)
Calculate the required maximum output
Power, PRAIL(peak) of the power supply
Prepare a power converter which has a
maximum output power > POUT(nom) and a
maximum output voltage > VRAIL(peak)
Adjust R1 and R2 to reduce the nominal
output voltage of the power converter to
VRAIL(nom)
VRAIL(peak) is the highest output voltage
that the power converter needs to
deliver.
ILEDx is the forward current of an LED
string.
PRAIL(peak) =
No. of
output ch.
ILEDx
VRAIL(peak)
The power converter must be able to
deliver a power no less than PRAIL(peak)
even if the VRAIL is pushed to the
maximum by the LM3463, VRAIL(peak)
Adjust the value of R1 and R2 so as to
meet the equation:
R2
VRAIL(nom) = VFB
R1 + R2
End of power
supply selection
Figure 28. Procedures of selecting the primary power supply
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Choosing the proper Primary Power Supply
If the primary power supply is an off-the-shelf power converter, it is essential to make certain that the power
converter is able to withstand the VRAIL(peak). In order to allow DHC, the nominal output voltage of the primary
power supply needs to be adjusted to below VLED-MIN-HOT as well. The suggested procedures for selecting the
proper power supply are as shown in Figure 28.
Selection of External MOSFET
The selection of external MOSFET is dependent on the highest current and the highest voltage that could be
applied to the drain terminal of the MOSFET. Generally, the Drain-to-Source breakdown voltage (VDSS) and the
continuous drain current (ID) of the external MOSFET must be higher than the defined peak supply rail voltage
(VRAIL(peak)) and the maximum output LED current (IOUTn) respectively.
Testing LEDs at System Startup
As VRAIL increases to VDHC_READY, the voltage at the VLedFB pin equals 2.5V. When the voltage at the VLedFB
pin rises to 2.5V, the LM3463 sinks 100 µA through every LED strings from the supply rail into the DRn pins for
certain period of time to determine the status of the LED strings. The time for checking LED strings is defined by
the value of the external capacitor, CFLT and is governed by the following equation:
(11)
If the voltage at any DRn pin is detected lower than 350 mV in the LED test period, that particular output channel
will be disabled and excluded from the DHC loop. All disabled output channels will remain in OFF state until a
system restarting is undertaken. The LED test performs only once after the voltage at VLedFB pin hits 2.5V. The
disabled channel can be re-enabled by pulling the EN pin to GND for 10 ms (issuing a system restart) or repowering the entire system.
MOSFET Power Dissipation Limit
In order to protect the MOSFETs from thermal break down when a short circuit of the LED sting(s) is
encountered, the LM3463 reduces the output current according to the increment of the drain voltage of the
MOSFET (VDRn) when the drain voltage exceeds a certain preset threshold voltage to limit the power dissipation
on the MOSFETs. This threshold voltage is defined by the voltage being applied to the DRVLIM pin, VDRVLIM and
is roughly four times the voltage of the VDRVLIM. For example, if the desired drain threshold voltage to perform
output current reduction is 16V, the DRVLIM pin voltage should be biased to 4V. Figure 29 shows the relation
between VSEn, VDRn and VDRVLIM.
VSEn
VDRx = VDRVLIM x 4
VDRn
Figure 29. VSEn reduces as VDRn exceeds VDRVLIM x4
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Dimming Mode Control
The LM3463 provides three modes of PWM dimming control. The three modes are: Direct PWM dimming mode,
Serial interface mode and DC interface mode. Selection of the mode of dimming mode is made by leaving the
MODE pin open or connecting the MODE pin to GND or VCC. Regardless of the selection of the mode of PWM
dimming control, the output channels 0 and 1 are controlled commonly by the signal at the DIM01 pin and the
output channels 2 and 3 are controlled commonly by the PWM signal at the DIM23 pin. The dimming duty of the
channel 4 and 5 are controlled by the signals on DIM4 and DIM5 pins respectively.
The DIM01, DIM23, DIM4 and DIM5 pins are pulled down by an internal 2 MΩ weak pull-downs to prevent the
pins from floating. Thus the dimming control input pins are default to 'LED OFF' state and need external pulled
up resistors when the pins are connected to open collector/drain signal sources. Figure 30 shows a suggested
circuit for connecting the LM3463 to an open collector/drain dimming signal sources.
LM3463
VCC
External PWM
signal source
(e.g. MCU)
RPU
47 k
Open-drain output
O/P
BUF
VCC
Regulator
DIMn
BUF
To dimming
control
circuit
2M
PWM
signal
GND
GND
GND
Figure 30. Adding an external pull-up resistor to the DIMn pin
Direct PWM Dimming Mode
Connecting the MODE pin to ground enables direct PWM dimming mode. Every dimming control pin (DIM01 to
DIM5) in direct PWM control mode accepts active high TTL logic level signal. In direct PWM dimming mode, the
six output channels are separated into four individual groups to accept external PWM dimming signals. The
configuration of output channels are as listed in the following table:
Group A
CH0 and CH1, controlled by DIM01 pin
Group B
CH2 and CH3, controlled by DIM23 pin
Group C
CH4, controlled by DIM4 pin
Group D
CH5, controlled by DIM5 pin
In order to secure accurate current regulation, the pull-up time of every dimming control input must not be shorter
than 8 µs. If a 256 level (8-bit resolution) brightness control is needed, the PWM dimming frequency should be
no higher than 488Hz.
24
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Serial Interface Mode
Leaving MODE pin floating enables serial interface mode. In serial interface mode, the DIM01, DIM23 and DIM4
pins are used together as a serial data interface to accept external dimming control data frames serially. The
following table presents the functions of the DIM01, DIM23 and DIM4 pins in serial interface mode:
DIM01
Serial data packet input (8-bit packet size)
DIM23
Clock signal input for data bit latching
DIM4
End Of Frame (EOF) signal input for data packet loading
The DIM5 pin is not used in this mode and should connect to GND. Every data frame contains four 8–bit wide
data byte for PWM dimming control. Every data byte controls the PWM dimming duty of its corresponding output
channel(s): A hexadecimal 000h gives 0% dimming duty; a hexadecimal 0FFh gives 100% dimming duty.
Respectively, the first byte being loaded into the LM3463 controls the dimming duty of CH0 and CH1, the second
byte controls the dimming duty of CH2 and CH3, the third byte controls the dimming duty of CH4 and the forth
byte controls the dimming duty of CH5.
In serial interface mode, the six output channels are separated into four individual groups as listed in the
following table:
Group A
CH0 and CH1, controlled by the first byte
Group B
CH2 and CH3, controlled by the second byte
Group C
CH4, controlled by the third byte
Group D
controlled by the forth byte
A data bit is latched into the LM3463 by applying a rising edge to the DIM02 pin. After clocking 32 bits (4 data
bytes) into the LM3463, a falling edge should be applied to the DIM4 pin to indicate an EOF and load data bytes
from data buffer to output channels accordingly. Figure 31 shows the serial input waveforms to the LM3463 to
facilitate in serial interface mode. Figure 32 shows the timing parameters of the serial data interface. The PWM
dimming duty in the serial interface mode is governed by the following equation:
(12)
The PWM dimming duty at decimal data codes 01 (001h) and 02 (002h) are rounded up to 2/256. Thus the
minimum dimming duty in the serial interface mode is 2/256 or 0.781%. Figure 33 shows the relationship of the
PWM dimming duty and the code value of a data byte in the serial interface mode. The PWM dimming frequency
in serial interface mode is defined by the system clock of the LM3463. The dimming frequency in the serial
interface mode is equal to the system clock frequency divided by 256 which follows the equation below:
(13)
In order to achieve a 256 level (8–bit resolution) brightness control, the minimum on time of every channel
(1/(fSERIAL-DIM*256)) should be no shorter than 8us, thus a dimming frequency of 488Hz is suggested to use.
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DIM23
(Clock signal)
DIM01
(Data)
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
LSB
BIT7
MSB
One data byte
DIM23
(Clock signal)
BYTE1
(Group D)
DIM01
(Data)
BYTE2
(Group C)
BYTE3
(Group B)
BYTE4
(Group A)
DIM4
(End of Frame)
BOF
EOF
One data frame
Figure 31. Input waveform to the LM3463 in serial interface mode
DIM23
50%
50%
DIM01
tDS
tDS > 10 ns
tBIT
tBIT > 20 ns
50%
DIM4
tLATCH
tLATCH > 50 ns
Figure 32. Timing parameters of the serial data interface
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PWM dimming duty
256/256
255/256
254/256
253/256
252/256
6/256
5/256
4/256
3/256
2/256
(Skipped) 1/256
Input Data Code
(Decimal)
1
2
3
4
5
25
25
25
25
25
5
4
3
2
1
0
0
Figure 33. PWM dimming duty vs code value of a data byte
DC Interface Mode
Connecting the MODE pin to VCC enables DC interface mode. In this mode the LM3463 converts the voltage on
the dimming signal input pins into PWM dimming duty to the corresponding output channels. The six output
channels are separated into four individual groups to accept external PWM dimming signals as listed in the
following table:
Group A
CH0 and CH1, controlled by the voltage at DIM01 pin
Group B
CH2 and CH3, controlled by the voltage at DIM23 pin
Group C
CH4, controlled by the voltage at DIM4 pin
Group D
CH5, controlled by the voltage at DIM5 pin
In DC interface mode, the DIM01, DIM23, DIM4 and DIM5 pins accept DC voltages in the range of 0.8V to 5.7V
to facilitate PWM dimming control. The voltage at the DIMn pins (VDIMn) and the PWM dimming duty in the DC
interface mode (DDC-DIM) are governed by the following equation. Figure 34 shows the correlation of VDIMn and
DDC-DIM. The conversion characteristic is shown in Figure 35.
where
•
0.8V < VDIMn < 5.7V
(14)
The PWM dimming frequency in the DC interface mode is defined by the system clock of the LM3463. The
dimming frequency in the DC interface mode is equal to the system clock frequency divided by 1280 which
follows the equation below:
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(15)
In order to achieve a 256 level (8–bit resolution) brightness control, the minimum on time of every channel
(1/(fSERIAL-DIM*256)) should be no shorter than 8 us, thus a dimming frequency of 488Hz is suggested to use.
The LM3463 samples the analog voltage at the DIMn pins and updates the dimming duty of each output channel
at a rate of 1280 system clock cycle (1280/fCLKOUT). In order to ensure correct conversion of analog voltage to
PWM dimming duty, the slew rate of the analog voltage for dimming control is limited the following equation:
(16)
DIMMING DUTY (%)
100
80
60
40
20
0
0
1
2
3
4
VDIMn(V)
5
6
7
Figure 34. Dimming Duty vs VDIMn in DC interface mode
28
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PWM
dimming duty
256/256
255/256
254/256
253/256
252/256
VLSB =
5.7V - 0.8V
256
6/256
5/256
4/256
3/256
2/256
(Skipped) 1/256
Analog voltage
at the DIMn pin
5.7
0.8
5.7
V4V
L
V- SB
3
5.7 VLS
V2 B
5.7 VLS
B
VV
5.7 LSB
V
V
0.8
V+
VL
0.8
V+ SB
0.8 2VL
V+ SB
0.8 3VL
V+ SB
4V
L
SB
0
Figure 35. Conversion characteristic of the analog voltage to PWM dimming control circuit
Using Less than Six Output Channels
If less than 6 output channels are needed, the unused output channel(s) of the LM3463 can be disabled by not
installing the external MOSFET and current sensing resistor. The drain voltage sensing pin (DRn), gate driver
output pin (GDn) and current sensing input pin (SEn) of a disabled channel must be left floating to secure proper
operation. The output channel(s) which has no external MOSFET and current sensing resistor installed is
disabled and excluded from DHC loop at system startup while the VRAIL reaches VDHC_READY.
A total of five output channels of the LM3463 can be disabled. The channel 0 must be in use regardless of the
number of disabled channel. This feature also applies in cascade operation.
Cascading of LM3463
For the applications that require more than six output channels, two or more pieces of LM3463 can be cascaded
to expand the number of output channel. Dimming control is allowed in cascade operation. The connection
diagrams for cascade operation in different modes of dimming control are as shown in Figure 36.
Serial interface mode in cascade operation
In the serial interface mode, the master LM3463 accepts external data frames through the serial data interface
which consists of the DIM01, DIM23 and DIM4 pins and passes the frames to the following slave LM3463
through its serial data output interface (SYNC and CLKOUT pins). Every slave unit shifts data in and out bit by
bit to its following slave unit.
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DC interface mode in cascade operation
In the DC interface mode, the master unit accepts four individual analog dimming control signals from external
signal sources (via the DIM01, DIM23, DIM4 and DIM5 pins) and encodes the analog signals into 8-bit serial
dimming control signals. The master LM3463 passes the encoded dimming control signals serially to the
following slave unit through its serial data output interface (SYNC and CLKOUT pins). Every slave unit shifts data
in and out bit by bit to its following slave unit.
Direct PWM dimming mode in cascade operation
In the Direct PWM Dimming mode, the master and slave units share the PWM dimming control signals at the
DIM01, DIM23, DIM4 and DIM5 pin to facilitate dimming control. In this mode, the SYNC and CLKOUT of all
slave units should be connected to the SYNC and CLKOUT pin of the master unit accordingly to perform startup
synchronization. Since the dimming control signal inputs of all the LM3464 are connected in parallel to share the
control signals, it is essential to ensure the signal source is strong enough to drive all the LM3463 in parallel.
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Serial Data Interface
VRAIL (Vout from AC/DC converter)
Vcc
LM3463
Master
VLedFB
GND
Vcc
LM3463
Slave 1
LM3463
VLedFB
VLedFB
NC
MODE
SDAT
DIM01
DIM01
DIM01
SCLK
DIM23
DIM23
DIM23
LOAD
DIM4
DIM4
DIM4
DIM5
DIM5
Interface to MCU/
external logic control
circuit
MODE
NC
Slave 2
MODE
NC
DIM5
SYNC
SYNC
SYNC
CLKOUT
CLKOUT
CLKOUT
GND
DC Voltage Dimming Control Interface
VRAIL (Vout from AC/DC converter)
Vcc
LM3463
GND
Master
Vcc
LM3463
Slave 1
LM3463
VLedFB
VLedFB
VLedFB
Vcc
MODE
MODE
MODE
VDIM01
DIM01
DIM01
DIM01
VDIM23
DIM23
DIM23
DIM23
VDIM4
DIM4
DIM4
DIM4
VDIM5
DIM5
DIM5
DC voltages
controlling average
LED currents (PWM)
Slave 2
DIM5
SYNC
SYNC
SYNC
CLKOUT
CLKOUT
CLKOUT
Direct PWM Diming Control Interface
VRAIL (Vout from AC/DC converter)
Vcc
LM3463
Master
VLedFB
GND
DIM23
DIM4
LM3463
MODE
DIM01
DIM01
DIM23
DIM23
DIM4
DIM4
SYNC
CLKOUT
Slave 2
VLedFB
GND
MODE
DIM5
DIM5
Interface to PWM
dimming signal sources
Slave 1
VLedFB
GND
MODE
DIM01
GND
Vcc
LM3463
DIM5
SYNC
SYNC
CLKOUT
CLKOUT
Figure 36. Connect diagram for cascade operations in different modes of dimming control
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APPLICATION EXAMPLES
Figure 37. LM3463 typical application circuit for stand alone operation
VRAIL
High Power LED Arrays
VIN
Voltage output
Voltage
feedback pin
RFB1
Primary power supply
CIN
RDHC
RFB2
LED1
LED2
LED6
D1
U1
GND
EN
Vcc
PWM dimming
signal inputs
VIN
VLedFB
OutP
DR0
EN
Faultb
Faultb
MODE
MODE
DIM01
DIM01
DIM23
DIM23
DIM4
DIM4
DIM5
DIM5
DR1
DR5
VCC
Q1
GD0
RLMT1
DRVLIM
FS
LM3463
Q2
GD1
ISR
CVCC
RLMT2
CDHC
FCAP
RFS
RIBIAS
Q6
GD5
CDHC
CFLT
SE5
RISNS6
VREF
SE1
GND
RISNS2
SE0
IOUTADJ
RISNS1
CVREF
CLKOUT
SYNC
GND
REFRTN
GND
REFRTN
GND
GND
GND
REFRTN
Connections for
cascade operation
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Figure 38. LM3463 typical application circuit for true analog dimming control
VRAIL
High Power LED Arrays
VIN
Voltage output
Voltage
feedback pin
RFB1
Primary power supply
CIN
RDHC
RFB2
LED1
LED2
LED6
D1
U1
GND
EN
VIN
VLedFB
OutP
DR0
EN
Faultb
Faultb
DR1
MODE
DIM01
DIM23
GND
DR5
DIM4
Vcc
DIM5
VCC
Q1
GD0
RLMT1
DRVLIM
FS
LM3463
Q2
GD1
ISR
CVCC
RLMT2
CDHC
FCAP
RFS
RIBIAS
Q6
GD5
CDHC
CFLT
SE5
RISNS6
VREF
GND
SE1
RIADJ1
RISNS2
SE0
IOUTADJ
CVREF
RISNS1
CLKOUT
SYNC
GND
REFRTN
RIADJ2
GND
GND
REFRTN
GND
GND
REFRTN
Connections for
cascade operation
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Figure 39. White LEDs Only
LED Module 1
White
White
White
White
White
White
White
White
White
White
White
White
VRAIL
LED Module n
CH0
CH1
CH2
CH3
CH4
CH5
CH0
CH1
CH2
CH3
CH4
CH5
Primary Power Supply
(AC/DC Converter, Single Stage
PFC, DC Voltage Regulator, etc.)
Ropto
Opto1
R1
COUT
Ccomp
Output
Terminals of
the Primary
Power
Supply
LM3463
Master Unit
OutP
LM3463
Slave Unit
OutP
LM431
R2
Figure 40. White + Amber LEDs for Color Temperature Adjustment
LED Module 1
White
White
White
White
White
Amber
White
White
White
White
White
Amber
VRAIL
LED Module n
CH0
CH1
CH2
CH3
CH4
CH5
CH0
CH1
CH2
CH3
CH4
CH5
Primary Power Supply
(AC/DC Converter, Single Stage
PFC, DC Voltage Regulator, etc.)
Ropto
Opto1
R1
COUT
Ccomp
Output
Terminals of
the Primary
Power
Supply
OutP
LM3463
Master Unit
LM431
OutP
LM3463
Slave Unit
R2
34
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Figure 41. White + Red + Green LEDs for CRI Adjustment
LED Module 1
White
White
White
White
Red
Green
White
White
White
White
Red
Green
VRAIL
LED Module n
CH0
CH1
CH2
CH3
CH4
CH5
CH0
CH1
CH2
CH3
CH4
CH5
Primary Power Supply
(AC/DC Converter, Single Stage
PFC, DC Voltage Regulator, etc.)
Ropto
Opto1
R1
COUT
Ccomp
Output
Terminals of
the Primary
Power
Supply
LM3463
Master Unit
OutP
LM3463
Slave Unit
OutP
LM431
R2
Figure 42. Red + Green + Blue LEDs for Color Mixing
LED Module 1
Red
Red
Green
Green
Blue
Blue
Red
Red
Green
Green
Blue
Blue
LED Module n
CH0
CH1
CH2
CH3
CH4
CH5
CH0
CH1
CH2
CH3
CH4
CH5
VRAIL
Primary Power Supply
(AC/DC Converter, Single Stage
PFC, DC Voltage Regulator, etc.)
Ropto
Opto1
R1
COUT
Ccomp
Output
Terminals of
the Primary
Power
Supply
OutP
LM3463
Master Unit
LM431
OutP
LM3463
Slave Unit
R2
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REVISION HISTORY
Changes from Original (May 2013) to Revision A
•
36
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 35
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM3463SQ/NOPB
ACTIVE
WQFN
RHS
48
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
LM3463
LM3463SQX/NOPB
ACTIVE
WQFN
RHS
48
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
LM3463
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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