LM3481SEPICEVAL/NOPB

User's Guide SNVA461A – September 2011 – Revised April 2013 AN-2094 LM3481 SEPIC Evaluation Board 1 Introduction The LM3481 SEPIC evaluation board is designed to provide the design engineer with a fully functional power converter solution with two output voltage options. It produces a selectable output voltage of 12 V at 1.25A or 5V at 3A. The switching frequency for the converter is set to 500 kHz. The printed circuit board consists of 2 layers of FR4 material with 2 ounce copper on both layers. This document contains the evaluation board schematics, bill-of-materials (BOM) and a quick setup procedure. For complete circuit design information, see the LM3481/LM3481Q High Efficiency Low-Side N-Channel Controller for Switching Regulators Data Sheet (SNVS346). The performance of the evaluation board is as follows: 5V Output Voltage Option: Input Voltage Range : 4.5V to 25V Output Voltage : 5V ± 2% Output Current : 0A to 3A Switching Frequency : 500 kHz Load Regulation : 0.1% Board Size : 2.4 x 1.8 inches 12V Output Voltage Option: Input Voltage Range : 4.5V to 18V Output Voltage : 12V ± 2% Output Current : 0A to 1.25A Switching Frequency : 500 kHz Load Regulation : 0.1% Board Size : 2.4 x 1.8 inches All trademarks are the property of their respective owners. SNVA461A – September 2011 – Revised April 2013 Submit Documentation Feedback AN-2094 LM3481 SEPIC Evaluation Board Copyright © 2011–2013, Texas Instruments Incorporated 1 Powering and Loading Considerations 2 www.ti.com Powering and Loading Considerations Read this entire page prior to attempting to power the evaluation board. 2.1 Qucik Setup Procedure 1. Use an input power supply with at least 5A current capability. Connect the positive output of the power supply to the VIN terminal P1. Connect the negative output of the power supply to the input GND terminal P2. 2. Connect a load with 3A capability to the VOUT terminal P3 and GND terminal P4. 3. To set the output voltage to 5V, the J2 jumper should be out. If the desired output voltage is 12V, the J2 jumper should be in. 4. Set VIN to 12V with no load being applied. Turn on the input power supply. Once the input voltage is applied, the output voltage should be in regulation. 5. Adjust the input voltage and load current and set as desired while making sure that they are in range as described above. Note: Do not change jumper settings while the board is powered on. 3 Connection Diagram DVM VIN P1 0-25V, 6A DC Power Supply GND P2 LM3481 EVALUATION BOARD VOUT P3 Electronic Load 0A ± 3A GND P4 DVM Figure 1. Basic Test Setup for the LM3481 SEPIC Evaluation Board OSCILLOSCOPE Bare Wire COUT VOUT GND Figure 2. Output Voltage Ripple Measurement Setup 2 AN-2094 LM3481 SEPIC Evaluation Board SNVA461A – September 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Board Configuration www.ti.com 4 Board Configuration 4.1 Output Voltage Option A jumper has been provided on the evaluation board in order to select the output voltage option of 12V or 5V. Shorting the jumper ses the output voltage to 12V. Leaving the jumper open will set the output voltage to 5V. 4.2 Under-Voltage Lock-Out (UVLO) The LM3481 evaluation board has a resistor divider connected to the UVLO pin to set the on and off thresholds to 4.25V and 4.05V, respectively. There is also a jumper J1 on the board that provides the ‘Enable’ feature. If the jumper is open, the board will not produce an output voltage. 4.3 Output Voltage Ripple Output voltage ripple measurement should be taken directly across the output capacitor C12 between terminals P3 and P4. Care must be taken to minimize the loop area between the scope probe tip and the ground lead in order to minimize noise in the measurement. This can be achieved by removing the probe’s spring tip and ground lead and then wrap a bare wire around the scope probe shaft. The bare wire should be in contact with the probe shaft since this is the ground lead for the probe. The measurement can be taken by connecting the bare wire onto the ground side of the capacitor and the probe tip onto the positive side of the capacitor. Figure 2 shows a diagram of this measurement technique. 4.4 External Clock Synchronization A SYNC terminal has been provided on the evaluation board in order to synchronize the converter to an external clock or other fixed frequency signal. For complete information on setting up the external clock, see the LM3481/LM3481Q High Efficiency Low-Side N-Channel Controller for Switching Regulators Data Sheet (SNVS346). 4.5 Active Loads Many constant-current types of active loads can exhibit an initial short circuit, which is sustained well beyond the normal soft-start cycle. To avoid loss of regulation of the output voltage during current limit during startup, wait until the output voltage is up before turning on the load. Using an active load with a constant-resistance mode will avoid this startup timing issue. 4.6 SEPIC Operation and Advantages The Single Ended Primary Inductance Converter (SEPIC) is a DC-DC converter that allows the output voltage to be either higher than or lower than the input voltage. The SEPIC capacitor is charged to a voltage potential of approximately VIN. This capacitor acts as an AC short placing the two coils of the inductor in parallel. The duty cycle relationship and operation is similar to that of the Buck-Boost. During the on-time of the MOSFET a voltage of VIN is applied across the mutual inductor. During the off-time of MOSFET, the mutual inductor voltage flies to VOUT refreshing the charge on the output capacitor. Since the SEPIC capacitor is charged to VIN, the voltage across the MOSFET is VIN + VOUT. Additionally, the current through the MOSFET is IIN + IOUT. The SEPIC has quite a few advantages over the inverting Buck-Boost and the Flyback topology. The power MOSFET and the diode voltages in the Flyback topology are unclamped and are largely functions of the transformer leakage inductance and the stray capacitance. This causes large voltage spikes at the switching intervals. Compared to this for the SEPIC topology the MOSFET and the diode are clamped by the output and blocking capacitors and thus there is little circuit ringing. The SEPIC also has a common ground, unlike the Buck-Boost topology, which makes the input and output voltage sensing very easy. SNVA461A – September 2011 – Revised April 2013 Submit Documentation Feedback AN-2094 LM3481 SEPIC Evaluation Board Copyright © 2011–2013, Texas Instruments Incorporated 3 Board Configuration 4.7 www.ti.com Momentary Overload or Short Circuit Protection In case of an overload or a short circuit event, the voltage across the sense resistor would increase beyond 220 mV. This would then activate the short circuit current limit and limit the switching frequency by a factor of 8 while the event exists. In case of a prolonged overload/short circuit event, the large currents would cause the junction temperatures of the MOSFET and the diode to increase significantly and potentially cause thermal failure. 4 AN-2094 LM3481 SEPIC Evaluation Board SNVA461A – September 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Typical Performance Characteristics www.ti.com 5 Typical Performance Characteristics Efficiency at VOUT = 12V 100 80 90 70 80 EFFICIENCY (%) EFFICIENCY (%) Efficiency at VOUT = 5V 90 60 50 40 30 Vin = 4.5V Vin = 6V Vin = 12V Vin = 18V Vin = 25V 20 10 0 0.0 0.5 1.0 70 60 50 40 30 Vin = 4.5V Vin = 6V Vin = 12V Vin = 18V 20 10 0 1.5 2.0 ILOAD(A) 2.5 3.0 0.0 Startup at VOUT = 5V and VIN = 4.5V 0.5 1.0 1.5 2.0 ILOAD(A) 2.5 3.0 Startup at VOUT = 5V and VIN = 25V 6 27 6 6 4 4 VIN 3 3 VOUT 2 5 21 VIN 18 4 15 3 12 9 2 VOUT(V) 5 VIN(V) 5 VOUT(V) VIN(V) 24 2 6 1 1 0 0 2 4 6 0 0 8 10 12 14 16 18 20 TIME (ms) Startup at VOUT = 12V and VIN = 4.5V 5 0 2 4 6 Startup at VOUT = 12V and VIN = 18V 16 25 15 VOUT 14 4 2 VOUT 6 VIN(V) 8 VOUT(V) VIN(V) 10 3 VIN 20 12 VIN 8 10 12 14 16 18 20 TIME (ms) 12 15 9 10 6 5 3 0 0 VOUT(V) 0 1 VOUT 3 4 1 2 0 0 0 2 4 6 8 10 12 14 16 18 20 TIME (ms) SNVA461A – September 2011 – Revised April 2013 Submit Documentation Feedback 0 2 4 6 8 10 12 14 16 18 20 TIME (ms) AN-2094 LM3481 SEPIC Evaluation Board Copyright © 2011–2013, Texas Instruments Incorporated 5 Typical Performance Characteristics www.ti.com Load Transient at VIN = 5V VIN= 5V VOUT 5.2 Load Transient at VIN = 12V 6 13.0 5 12.5 6 VIN= 12V 5 ILOAD 4.0 3.6 3.2 0.0 0.5 1.0 TIME (ms) 1.5 1 10.5 1 0 10.0 0 5.5 21 5.0 20 4.5 19 4.0 VIN 20 3.5 3.0 16 12 8 4 0 1 2 3 4 5 6 7 TIME (ms) 8 Input Transient at Iload = 3A and VOUT = 12V 22 13.0 12.5 12.0 11.5 VOUT 18 11.0 17 10.5 VIN 16 10.0 15 9.5 2.0 14 9.0 1.5 13 8.5 1.0 12 9 10 8.0 0 1 2 3 4 5 6 7 TIME (ms) 8 9 10 Steady State Operation at VIN = 25V and Iload = 3A 5.5 42 VIN= 25V 5.0 35 4.5 28 4.0 21 16 11.0 12 10.5 8 3.5 14 10.0 4 3.0 7 9.5 0 2.5 0 0 2 4 6 TIME ( s) AN-2094 LM3481 SEPIC Evaluation Board 8 10 VOUT(V) 11.5 VSW(V) VOUT(V) ILOAD= 3A 2.5 Steady State Operation at VIN = 4.5V and Iload = 1.25A 12.5 24 VIN= 4.5V 12.0 20 6 VIN(V) VOUT 24 2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 TIME (ms) VOUT(V) VIN(V) 28 ILOAD 11.0 2.0 ILOAD= 3A 3 2 Input Transient at Iload = 3A and VOUT = 5V 36 6.0 32 11.5 ILOAD(A) 3 4 VOUT(V) 4.4 12.0 0 1 2 3 4 5 6 TIME ( s) 7 8 VSW(V) 4 VOUT(V) 4.8 ILOAD(A) VOUT(V) VOUT 9 10 SNVA461A – September 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Evaluation Board Schematic www.ti.com 6 Evaluation Board Schematic Figure 3. LM3481 Evaluation Board Schematic SNVA461A – September 2011 – Revised April 2013 Submit Documentation Feedback AN-2094 LM3481 SEPIC Evaluation Board Copyright © 2011–2013, Texas Instruments Incorporated 7 Evaluation Board Schematic www.ti.com Table 1. LM3481 Bill of Materials (BOM) 8 Qty Designator Value 1 C1 100 µF 2 C2, C3 4.7 µF 1 C4 0.027 µF 1 C5 1 1 Package Description Manufacturer Part Number Polarized Capacitor, 63V, 10% Sanyo 63CV100KX 1812 Ceramic, X7R, 50V, 10% MuRata C4532X7R1H475M 0603 Ceramic, X7R, 100V, 10% Kemet C0603C273K1RACTU 100 pF 0603 Ceramic, X7R, 100V, 10% AVX 06031C331KAT2A C6 4700 pF 0603 Ceramic, X7R, 100V, 10% AVX 06031C222KAT2A C7 2200 pF 0603 Ceramic, X7R, 16V, 10% TDK C1608X7R1C105K 1 C8 1000 pF 1206 Ceramic, X7R, 50V, 10% TDK C3216X7R1H105K 2 C9, C12 22 µF 1812 Ceramic, X7R, 20V, 20% TDK C4532X7R1C226M 2 C10, C11 180 µF Electrolytic capacitor Sanyo 16SVP180M 1 D1 Schottky Diode, 40V Central Semi CMSH5-40 2 J1, J2 Through Hole Jumpers Sullins Electronics PBC02SAAN Coupled Inductor, 8.25A Cooper DRQ127-4R7-R Terminal, Turret, TH Keystone Electronics 1598-2 SMC 1 L1 4 P1, P2, P3, P4 4.7 µH 1 Q1 PowerPAK N Channel MOSFET, 30V Vishay Si7386DP 1 R1 100 ohm 0603 RES, 1%, 0.1W Vishay-Dale CRCW0603100RFKEA 1 R2 40.2k ohm 0603 RES, 1%, 0.1W Vishay-Dale CRCW060340K2FKEA 1 R3 20.5k ohm 0603 RES, 1%, 0.1W Vishay-Dale CRCW060320K5FKEA 1 R4 10.7k ohm 0603 RES, 1%, 0.1W Vishay-Dale CRCW060310K7FKEA 1 R5 20.0k ohm 0603 RES, 1%, 0.1W Vishay-Dale CRCW060320K0FKEA 1 R6 59.0k ohm 0603 RES, 1%, 0.1W Vishay-Dale CRCW060359K0FKEA 1 R7 DNP Resistor 1 R8 20m ohm RES, 1%, 1W Vishay-Dale WSL2512R0200FEA 1 R9 6.8k ohm 0603 RES, 5%, 0.1W Vishay-Dale CRCW06036K80JNEA 1 R10 38.3k ohm 0603 3 TP1, TP2, TP3 1 U1 VSSOP AN-2094 LM3481 SEPIC Evaluation Board DNP Resistor RES, 1%, 0.1W Vishay-Dale CRCW060338K3FKEA Through Hole Test Point, Miniature, White Keystone Electronics 5002 Low-Side N-Channel Controller Texas Instruments LM3481 SNVA461A – September 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated PCB Layout www.ti.com 7 PCB Layout Figure 4. Top Layer Components and Overlay Figure 5. Top Layer Copper SNVA461A – September 2011 – Revised April 2013 Submit Documentation Feedback AN-2094 LM3481 SEPIC Evaluation Board Copyright © 2011–2013, Texas Instruments Incorporated 9 PCB Layout www.ti.com Figure 6. Bottom Overlay Figure 7. Bottom Layer Copper 10 AN-2094 LM3481 SEPIC Evaluation Board SNVA461A – September 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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