LM34914EVAL

User's Guide SNVA196B – January 2007 – Revised April 2013 AN-1549 LM34914 Evaluation Board 1 Introduction The LM34914EVAL evaluation board provides the design engineer with a fully functional buck regulator, employing the constant on-time (COT) operating principle. This evaluation board provides a 5V output over an input range of 8V to 40V. The circuit delivers load currents to 1A, with current limit set at ≊1.2A. The board is populated with all components except R3, C2, C11 and C12. These components provide options for managing the output ripple as described later in this user's guide. The board’s specification are: • Input Voltage: 8V to 40V • Output Voltage: 5V • Maximum load current: 1.0A • Minimum load current: 0A • Current Limit: ≊1.2A (Vin = 8V) • Measured Efficiency: 94.5% (VIN = 8V, IOUT = 200 mA) • Nominal Switching Frequency: 275 kHz • Size: 2.0 in. × 1.0 in. × 0.53 in 2 Example Circuit Figure 1. Evaluation Board - Top Side All trademarks are the property of their respective owners. SNVA196B – January 2007 – Revised April 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated AN-1549 LM34914 Evaluation Board 1 Theory of Operation 3 www.ti.com Theory of Operation Refer to the evaluation board schematic in Figure 2, which contains a simplified block diagram of the LM34914. When the circuit is in regulation, the buck switch is on each cycle for a time determined by R4 and VIN according to the equation: tON = 1.15 x 10-10 x (R4 + 1.4k) (VIN ± 1.5V) + 50 ns (1) The on-time of this evaluation board ranges from ≊2700 ns at VIN = 8V, to ≊500 ns at VIN = 40V. The ontime varies inversely with VIN to maintain a nearly constant switching frequency. At the end of each ontime the Minimum Off-Timer ensures the buck switch is off for at least 265 ns. In normal operation, the offtime is much longer. During the off-time, the load current is supplied by the output capacitor (C7). When the output voltage falls sufficiently that the voltage at FB is below 2.5V, the regulation comparator initiates a new on-time period. For stable, fixed frequency operation, a minimum of 25 mV of ripple is required at FB to switch the regulation comparator. The current limit threshold, which varies with Vin, is ≊1.2A at Vin = 8V, and ≊1.05A at Vin = 40V. For a more detailed block diagram and a complete description of the various functional blocks, see LM34914 Ultra Small 1.25A Step-Down Switching Regulator with Intelligent Current Limit (SNVS453). 8V to 40V IN C1 3.3 PF GND VIN Minimum Off Timer On Timer R4 150k 0.1 PF RON/SD 8 SS 7 C6 FB 0.022 PF 6 VCC 9 LM34914 10 C5 VIN BST 2 C4 C3 0.1 PF 0.022 PF L1 100 PH SW Logic 1 2.5V ISEN Current Limit Detect Regulation Comparator 5 EP RTN 3 SGND D1 R6 C9 90.9k 3300 pF C10 0.01 PF C12 5V VOUT R1 4.99k R3 C7 0.1 PF C2 C11 4 R2 4.99k C8 22 PF GND Figure 2. Evaluation Board Schematic 4 Board Layout and Probing Figure 1 shows the placement of the circuit components. The following should be kept in mind when the board is powered: • When operating at high input voltage and high load current, forced air flow may be necessary. • The LM34914, and diode D1 may be hot to the touch when operating at high input voltage and high load current. • Use CAUTION when probing the circuit at high input voltages to prevent injury, as well as possible damage to the circuit. • At maximum load current (1A), the wire size and length used to connect the load becomes important. Ensure there is not a significant drop in the wires between this evaluation board and the load. 2 AN-1549 LM34914 Evaluation Board SNVA196B – January 2007 – Revised April 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Board Connection/Start-up www.ti.com 5 Board Connection/Start-up The input connections are made to the J1 connector. The load is connected to the J2 (OUT) and J3 (GND) terminals. Ensure the wires are adequately sized for the intended load current. Before start-up a voltmeter should be connected to the input terminals, and to the output terminals. The load current should be monitored with an ammeter or a current probe. It is recommended that the input voltage be increased gradually to 8V, at which time the output voltage should be 5V. If the output voltage is correct with 8V at VIN, then increase the input voltage as desired and proceed with evaluating the circuit. DO NOT EXCEED 40V AT VIN. 6 Output Ripple Control The LM34914 requires a minimum of 25 mVp-p ripple at the FB pin, in phase with the switching waveform at the SW pin, for proper operation. The required ripple can be supplied from ripple at VOUT, through the feedback resistors, as described in option B and option C, or the ripple can be generated separately (using R6, C9, C10) keeping the ripple at VOUT to a minimum as described in option A. • Option A) Minimum Output Ripple: This evaluation board is supplied configured for minimum ripple at VOUT by using components R6, C9 and C10. The output ripple, which ranges from ≊3mVp-p at VIN = 8V to ≊8 mVp-p at VIN = 40V, is determined primarily by the ESR of output capacitor (C7), and the inductor’s ripple current, which ranges from 85 mAp-p to 190 mAp-p over the input voltage range. The ripple voltage required by the FB pin is generated by R6, C9 and C10 since the SW pin switches from 1V to VIN, and the right end of C9 is a virtual ground. The values for R6 and C9 are chosen to generate a 30-40 mVp-p triangle waveform at their junction. That triangle wave is then coupled to the FB pin through C10. The following procedure is used to calculate values for R6, C9 and C10: 1. Calculate the voltage VA: VA = VOUT - (VSW × (1 - (VOUT/VIN))) (2) where: VSW is the absolute value of the voltage at the SW pin during the off-time (typically 1V) VIN is the minimum input voltage For this circuit, VA calculates to 4.63V. This is the approximate DC voltage at the R6/C9 junction, and is used in the next equation. 2. Calculate the R6 × C9 product: R6 x C9 = (VIN ± VA) x tON 'V (3) where: tON is the maximum on-time (≊2700 ns), VIN is the minimum input voltage ΔV is the desired ripple amplitude at the R6/C9 junction, 30 mVp-p for this example. R6 x C9 = (8V ± 4.63V) x 2700 ns 0.03V = 3.03 x 10-4 (4) R6 and C9 are then chosen from standard value components to satisfy the above product. For example, C9 can be 3300 pF requiring R6 to be ≤91.8 kΩ. C10 is chosen to be 0.01 µF, large compared to C9. The circuit as supplied on this EVB is shown in Figure 3. SNVA196B – January 2007 – Revised April 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated AN-1549 LM34914 Evaluation Board 3 Output Ripple Control 8V to 40V IN C1 www.ti.com VIN GND RON/SD 8 SS 7 C6 FB 0.022 PF 6 Minimum Off Timer On Timer R4 150k 0.1 PF 3.3 PF VCC 9 LM34914 10 C5 VIN BST 2 C4 C3 0.1 PF 0.022 PF L1 100 PH SW Logic 1 2.5V ISEN Current Limit Detect Regulation Comparator EP 5 3 D1 R6 C9 90.9k 3300 pF C10 0.01 PF SGND VOUT R1 4.99k R2 4.99k 4 RTN 5V C7 C8 0.1 PF 22 PF GND Figure 3. Minimum Output Ripple Configuration Using R6,C9,C10 • Option B) Intermediate Ripple Level Configuration: This configuration generates more ripple at VOUT than the above configuration, but uses two less capacitors. If some ripple can be tolerated in the application, this configuration is slightly more economical, and simpler. R3, C2 and C12 are used instead of R6 and C7-C10, as shown in Figure 4. R3 is chosen to generate 25-30 mVp-p at VOUT knowing that the minimum ripple current is 85 mAp-p at minimum VIN. C12 couples that ripple to the FB pin without the attenuation of the feedback resistors. C12’s minimum value is calculated from: tON(max) C12 t (R1//R2) (5) where: tON(max) is the maximum on-time (at minimum VIN) R1//R2 is the equivalent parallel value of the feedback resistors For this evaluation board, tON(max) is approximately 2700 ns, and R1//R2 = 2.5 kΩ, and C12 calculates to a minimum of 1080 pF. In the circuit of Figure 4, the ripple at VOUT ranges from ≊30 mVp-p to ≊63 mVp-p over the input voltage range. 8V to 40V IN C1 3.3 PF GND VIN Minimum Off Timer On Timer R4 150k 0.1 PF RON/SD 8 SS 7 C6 FB 0.022 PF 6 VCC 9 LM34914 10 C5 VIN BST 2 C4 C3 0.1 PF 0.022 PF L1 100 PH SW Logic 5V 1 2.5V ISEN Current Limit Detect Regulation Comparator EP 5 RTN VOUT D1 1500 pF 3 C12 SGND R1 4.99k R2 4.99k 4 R3 0.33: C2 22 PF GND Figure 4. Intermediate Ripple Configuration Using C12 and R3 4 AN-1549 LM34914 Evaluation Board SNVA196B – January 2007 – Revised April 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Minimum Load Current www.ti.com • Option C) Lowest Cost Configuration: This configuration is the same as option B, but without C12. Since ≥25 mVp-p are required at the FB pin, R3 is chosen to generate ≥50 mV at VOUT, knowing that the minimum ripple current in this circuit is 85 mAp-p at minimum VIN. Using 0.68Ω for R3, the ripple at VOUT ranges from ≊60 mVp-p to ≊120 mVp-p over the input voltage range. If the application can tolerate this ripple level, this is the most economical solution. The circuit is shown in Figure 5. 8V to 40V IN C1 3.3 PF GND VIN Minimum Off Timer On Timer R4 150k 0.1 PF RON/SD 8 SS 7 C6 FB 0.022 PF 6 VCC 9 LM34914 10 C5 VIN BST 2 C4 C3 0.1 PF 0.022 PF L1 100 PH SW Logic 5V 1 2.5V ISEN Current Limit Detect Regulation Comparator EP 5 RTN VOUT D1 3 SGND 4 R1 4.99k R2 4.99k R3 0.68: C2 22 PF GND Figure 5. Lowest Cost Configuration 7 Minimum Load Current The LM34914 requires a minimum load current of ≊500 µA to ensure the boost capacitor (C4) is recharged sufficiently during each off-time. In this evaluation board, the minimum load current is provided by the feedback resistor (R1, R2), allowing the board’s minimum load current VOUT to be specified at zero. SNVA196B – January 2007 – Revised April 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated AN-1549 LM34914 Evaluation Board 5 Bill of Materials 8 6 www.ti.com Bill of Materials Item Description Mfg., Part Number Package Value C1 Ceramic Capacitor TDK C3225X7R1H475M 1210 4.7 µF, 50V C2 Ceramic Capacitor Unpopulated 1206 C3 Ceramic Capacitor TDK C2012X7R2A104M 0805 0.1 µF, 16V C4 Ceramic Capacitor TDK C2012X7R1C104M 0805 0.022 µF, 16V C5 Ceramic Capacitor TDK C2012X7R1C223M 0805 0.1 µF, 100V C6 Ceramic Capacitor TDK C2012X7R1C223M 0805 0.022 µF, 16V C7 Ceramic Capacitor TDK C3225X7R1C226M 1206 22 µF, 16V C8 Ceramic Capacitor TDK C2012X7R2A104M 0805 0.1 µF, 16V C9 Ceramic Capacitor TDK C2012X7R2A332M 0805 3300 pF C10 Ceramic Capacitor TDK C2012X7R2A103M 0805 0.01 µF C11 Ceramic Capacitor Unpopulated 0805 C12 Ceramic Capacitor Unpopulated 0805 D1 Schottky Diode Zetex ZLLS2000 SOT23-6 40V, 2.2A L1 Power Inductor TDK SLF12575T-101M1R9, or Cooper Bussmann DR125-101 12.5 mm × 12.5 mm 100 µH, 1.9A R1 Resistor CRCW08054991F 0805 4.99 kΩ R2 Resistor CRCW08054991F 0805 4.99 kΩ R3 Resistor Unpopulated 0805 R4 Resistor CRCW08051503F 0805 150 kΩ R6 Resistor CRCW08059092F 0805 90.9 kΩ U1 Switching Regulator Texas Instruments LM34914 WSON 3 × 3 AN-1549 LM34914 Evaluation Board SNVA196B – January 2007 – Revised April 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Circuit Performance www.ti.com 9 Circuit Performance 100 100 Vin = 8V 95 12V 90 EFFICIENCY (%) EFFICIENCY (%) 95 24V 85 40V 80 75 70 Load Current = 400 mA 90 200 mA 85 50 mA 80 75 0 200 400 600 800 70 1000 0 5 10 15 LOAD CURRENT (mA) 25 30 35 40 VIN (V) Figure 6. Efficiency vs Load Current Figure 7. Efficiency vs Input Voltage 200 350 Load Current = 400 mA 150 100 FREQUENCY (kHz) OUTPUT RIPPLE AMPLITUDE (mVp-p) 20 Option C Option B 50 300 250 200 Load Current = 400 mA Option A 0 0 5 10 15 20 25 30 35 150 40 0 5 VIN (V) 10 15 20 25 30 35 40 VIN (V) Figure 8. Output Voltage Ripple Figure 9. Switching Frequency vs. Load Current 1.4 LOAD CURENT (A) 1.3 1.2 1.1 1.0 0.9 0 5 10 15 20 25 30 35 40 VIN (V) Figure 10. Current Limit vs Input Voltage SNVA196B – January 2007 – Revised April 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated AN-1549 LM34914 Evaluation Board 7 PC Board Layout 10 www.ti.com PC Board Layout Figure 11. Board Silkscreen Figure 12. Board Top Layer Figure 13. Board Bottom Layer (Viewed from Top) 8 AN-1549 LM34914 Evaluation Board SNVA196B – January 2007 – Revised April 2013 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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