LM36274YFFR

Order Now Product Folder Support & Community Tools & Software Technical Documents LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 Four-Channel LCD Backlight Driver With Integrated Bias Power 1 Features 3 Description • The LM36274 is an integrated four-channel WLED driver and LCD bias supply. The ultra-compact size, high efficiency, high level of integration, and programmability allow the LM36274 to address a variety of applications without the need for hardware changes while minimizing the overall solution area. 1 • • • • • • • • Drives up to Four Parallel White LED Strings (29-V Maximum VOUT) 11-Bit Exponential and Linear Dimming Control PWM and I2C Brightness Control Backlight Operation With 4.7-µH to 15-µH Inductor Backlight and LCD Bias Efficiency up to 92% Programmable LCD Bias Voltages (±4 V to ±6.5 V With 50-mV resolution) With Up to 80-mA per Output 0.2% Matched LED Current From 60 µA to 30 mA 1% Accurate LED Current From 60 µA to 30 mA 2.7-V to 5-V Input Voltage Range 2 Applications • • • • The backlight boost provides the power to bias four parallel LED strings with up to 29-V total output voltage. The 11-bit LED current is programmable via the I2C bus and/or controlled via a logic level PWM input from 60 µA to 30 mA. Each LED string can be independently enabled or disabled to provide zone dimming capabilities. The backlight boost can be operated efficiently with an inductance range from 4.7 µH to 15 µH, allowing for efficiency and solution size optimization. The LCD bias boost provides the power to both a positive LDO and an inverting charge pump. Both positive and negative bias supplies have programmable output voltages of ±4 V to ±6.5 V with 50-mV steps and up to ±80 mA of current capability. An auto-sequencing feature provides a programmed delay from positive to negative bias activation, with additional programmable voltage slew rate control. Two wake-up modes allow both bias outputs to be controlled with a single external signal and stay active while consuming very low quiescent current. LCD Panels With up to 24 LEDs Smart Phones Tablets and Gaming Tablets Home Automation Panels space space Simplified Schematic DSCH LBL Device Information(1) IN BL_SW BL_SW CBL_OUT PART NUMBER BL_OUT LM36274 LLCM LED1 DSBGA (24) BODY SIZE (MAX) 2.44 mm × 1.67 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. LCM_SW VBATT PACKAGE LED2 SCL Backlight Efficiency, 4P6S LED3 SDA 95 LM36274 LED4 90 Up to 8 LEDs / String PWM 85 C+ CFLY CLCM_EN1 LCM_OUT LCM_EN2 CLCM CVPOS VNEG AGND LCM_GND CP_GND BL_GND VPOS CVNEG Efficiency (%) HWEN 80 75 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 Copyright © 2017, Texas Instruments Incorporated 0 10 20 30 40 50 60 70 Load (mA) 80 90 100 110 120 D053 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 1 1 1 2 3 5 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information ................................................. 5 Electrical Characteristics .......................................... 6 I2C Timing Requirements (Fast Mode) .................... 9 Typical Characteristics ............................................ 10 Detailed Description ............................................ 15 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Features Description ............................................... Device Functional Modes........................................ 15 16 16 32 7.5 Programming........................................................... 33 7.6 Register Maps ......................................................... 37 8 Application and Implementation ........................ 47 8.1 Application Information............................................ 47 8.2 Typical Application .................................................. 47 9 Power Supply Recommendations...................... 75 10 Layout................................................................... 75 10.1 Layout Guidelines ................................................ 75 10.2 Layout Example ................................................... 76 11 Device and Documentation Support ................. 77 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Device Support...................................................... Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 77 77 77 77 77 77 77 12 Mechanical, Packaging, and Orderable Information ........................................................... 78 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (June 2017) to Revision D • Added added silicon rev A1 to revision register. ................................................................................................................. 37 Changes from Revision A (January 2017) to Revision B • 2 Page Changed row(s) in Abs Max table: BL_SW from 30 V to 35 V, BL_OUT and current sink inputs (LEDX) remain at 30 V ... 5 Changes from Original (February 2016) to Revision A • Page Page Changed "Orderable Device" suffix on POA from "YFRR" to "YFFR" ................................................................................... 1 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 5 Pin Configuration and Functions YFF Package 24-Pin DSBGA Top View 1 2 3 4 A VNEG C- CP_GND C+ B IN LCM_ EN2 LCM_ EN1 VPOS C LED4 SCL SDA LCM_ OUT D LED3 PWM HWEN LCM_SW E LED2 AGND LCM_ GND BL_GND F LED1 BL_OUT BL_SW BL_SW Pin Functions PIN NUMBER NAME A1 VNEG TYPE DESCRIPTION O Inverting charge pump output. Bypass VNEG with a 10-µF ceramic capacitor to CP_GND. A2 C- O Inverting charge-pump flying capacitor negative connection A3 CP_GND — Charge pump GND. Connect the CNEG capacitor negative terminal to this pin. A4 C+ O Inverting charge-pump flying capacitor positive connection B1 IN I Input voltage connection. Bypass IN with a 10-µF ceramic capacitor to GND. B2 LCM_EN2 I Enable for LCD bias negative output; 300-kΩ internal pulldown resistor between LCM_EN2 and GND. B3 LCM_EN1 I Enable for LCD bias positive output; 300-kΩ internal pulldown resistor between LCM_EN1 and GND. B4 VPOS O Positive LCD bias output. Bypass VPOS with a 10-µF ceramic capacitor to GND. C1 LED4 I Current sink 4 input. Connect the cathode of LED string 4 to this pin. C2 SCL I Serial clock connection for I2C-compatible interface C3 SDA I/O Serial clock connection for I2C-compatible interface C4 LCM_OUT O LCD bias boost output voltage. Bypass LCM_OUT with a 10-µF ceramic capacitor to LCM_GND. D1 LED3 I Current sink 3 input. Connect the cathode of LED string 3 to this pin. Leave this pin disconnected if not used. D2 PWM I PWM input for duty cycle current control; 300-kΩ internal pulldown resistor between PWM and GND. D3 HWEN I Active high chip enable; 300-kΩ internal pulldown resistor between HWEN and GND. D4 LCM_SW O LCD bias boost inductor connection E1 LED2 I Current sink 2 input. Connect the cathode of LED string 2 to this pin. Leave this pin disconnected if not used. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 3 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com Pin Functions (continued) PIN TYPE DESCRIPTION NUMBER NAME E2 AGND — Analog ground connection. Connect AGND directly to GND on the PCB. E3 LCM_GND — LCD bias boost GND connection. Connect LCM_GND to the negative terminal of the LCD bias output capacitor. E4 BL_GND — Backlight boost output capacitor GND connection F1 LED1 I Current sink 1 input. Connect the cathode of LED string 1 to this pin. Leave this pin disconnected if not used. F2 BL_OUT O Backlight boost output voltage sense connection. Connect to the positive terminal of backlight boost output capacitor. F3 BL_SW O Backlight boost inductor connection F4 BL_SW O Backlight boost inductor connection 4 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT Voltage on IN, HWEN, LCM_EN1, LCM_EN2, SCL, SDA, PWM –0.3 6 V Voltage on LCM_SW, LCM_OUT, VPOS, C+ –0.3 9 V –7 0.3 V Voltage on BL_SW –0.3 35 V Voltage on BL_OUT, LED1, LED2, LED3, LED4 –0.3 30 V 150 °C 150 °C Voltage on VNEG, C– Continuous power dissipation Internally limited Maximum junction temperature, TJ(MAX) Storage temperature, Tstg (1) (2) –45 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the AGND pin. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted) (1) (2) . Input voltage, VIN Operating ambient temperature, TA (1) (2) (3) (3) MIN MAX 2.7 5 UNIT V –40 85 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the AGND pin. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX). 6.4 Thermal Information LM36274 THERMAL METRIC (1) DSBGA (YFF) UNIT (24 PINS) RθJA Junction-to-ambient thermal resistance 63.1 °C/W RθJC Junction-to-case (top) thermal resistance 0.4 °C/W RθJB Junction-to-board thermal resistance 11.6 °C/W ΨJT Junction-to-top characterization parameter 1.6 °C/W ΨJB Junction-to-board characterization parameter 11.6 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 5 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com 6.5 Electrical Characteristics Unless otherwise specified, typical limits apply at 25°C, minimum and maximum limits apply over the full operating ambient temperature range (−40°C ≤ TA ≤ 85°C), and VIN = 3.6 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.2 2.8 µA 1 7 µA 0.5 10 µA CURRENT CONSUMPTION ISD Shutdown current HWEN = 0 IQ Quiescent current, device not switching HWEN = VIN, LCM boost disabled ILCM_EN Bias power no load supply current VPOS, VNEG enabled with no load, backlight boost disabled, typical application circuit (not ATE tested) BACKLIGHT LED CURRENT SINKS (LED1, LED2, LED3, LED4) ILED_MAX Maximum output current (per string) 2.7 V ≤ VIN ≤ 5 V, linear or exponential mode ILED LED current accuracy (1) 2.7 V ≤ VIN ≤ 5 V, 60 µA < ILED < 30 mA, linear or exponential mode –3% IMATCH ILED current matching (2) 2.7 V ≤ VIN ≤ 5 V, 60 µA ≤ ILED ≤ 30 mA, linear or exponential mode –2% ILED_MIN Minimum LED current (per string) Linear or exponential mode LED current step size (code to code) Exponential mode (3) 0.3% Linear mode 14.63 ISTEP 30 mA 3% 0.2% 2% 60 µA µA BACKLIGHT BOOST ON threshold, 2.7 V ≤ VIN ≤ 5 V OVP threshold 011 to 111 28.5 29 29.5 010 24.5 25 25.5 001 20.5 21 21.5 000 16.3 17 17.7 OVP hysteresis OFF threshold Efficiency Boost efficiency VIN = 3.6 V, IBLED = 5 mA/string, (POUT/PIN), Typical Application Circuit (not ATE tested) VHR Regulated current-sink headroom voltage (boost feedback voltage) VHR_MIN Current-sink minimum headroom voltage ILED = 95% of nominal, ILED = 5 mA RDSON NMOS switch on resistance ISW = 250 mA ICL NMOS switch current limit 0.5 V V 90% ILED = 30 mA 310 mV ILED = 5 mA 120 mV 2.7 V ≤ VIN ≤ 5 V 30 50 mV 0.2 Ω 00 792 900 1008 mA 01 1056 1200 1344 mA 10 1320 1500 1680 mA 11 1584 1800 2016 mA 500-kHz mode 450 500 550 1-MHz mode 900 1000 1100 93% 94% ƒBL_SW Switching frequency 2.7 V ≤ VIN ≤ 5 V DMAX Maximum duty cycle VIN = 2.7 V, ƒLED_SW = 1 MHz kHz DEVICE PROTECTION TSD (1) (2) (3) 6 Thermal shutdown Not ATE tested 140 °C Output current accuracy is the difference between the actual value of the output current and programmed value of this current. LED current matching is the maximum difference between any string current and the average string current, divided by the average string current. This is calculated as (ILEDX – ILED_AVE) / ILED_AVE × 100. LED current step size from code to code in exponential mode is typically 0.304%, given as (1 – (ILED(CODE+1) / ILED(CODE)). Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 Electrical Characteristics (continued) Unless otherwise specified, typical limits apply at 25°C, minimum and maximum limits apply over the full operating ambient temperature range (−40°C ≤ TA ≤ 85°C), and VIN = 3.6 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DISPLAY BIAS (LCM BOOST) VOVP_LCM LCM bias boost overvoltage protection On threshold, 2.7 V ≤ VIN ≤ 5 V ƒLCM_SW Switching frequency (4) 2.7 V ≤ VIN ≤ 5 V (continuous conduction mode) LCM boost output voltage range VLCM_OUT 7.8 2500 4 VIN = 3.6 V, VLCM_OUT = 5.9 V, 6 mA < ILCM_OUT < 160mA, Typical Application Circuit (not ATE tested) Efficiency RDSON_LCM VLCM_OUT_ Valley current limit VLCM_OUT_LINE_ TRANSIENT VLCM_OUT_LOAD_ TRANSIENT tLCM_OUT_ST 7.15 V 50 mV 1000 mA High-side MOSFET on resistance VIN = VGS = 3.6 V 170 Low-side MOSFET on Resistance VIN = VGS = 3.6 V 290 Peak-to-peak ripple voltage (4) ILOAD_LCM_BOOST = 5 mA and 50 mA, CBST = 20 µF LCM_OUT line transient response (4) VIN + 500 mVp-p AC square wave, Tr = 100 mV/µs, 200 Hz, 12.5% DS at 5 mA, ILOAD = 5 mA, CIN = 10 µF LCM_OUT load transient response (4) 0 mA to 150 mA, tRISE/FALL = 100 mA/µs, CIN = 10 µF Start-up time (LCM_OUT), VLCM_OUT = 10% to 90% (4) CLCM_OUT = 20 µF RIPPLE kHz 92% Output voltage step size ILCM_BOOST_CL V mΩ 50 –50 ±25 –150 mVpp 50 mV 150 mV 1000 µs 6.5 V DISPLAY BIAS POSITIVE OUTPUT (VPOS) Programmable output voltage range VVPOS 4 Output voltage step size 50 Output voltage accuracy IVPOS_MAX Maximum output current IVPOS_CL Output current limit Output voltage = 5.4 V VLCM_OUT = 6.3 V, VPOS = 5.8 V, CVPOS = 10 µF (nominal) VVPOS_ LDO_VPOS line transient response (4) VIN + 500 mVp-p AC square wave, Tr = 100 mV/µs, 200 Hz at 25 mA, CIN = 10 µF (nominal) NSIENT LDO_VPOS load transient response (4) Load current step 0 mA to 50 mA, CVPOS = 10 µF (nominal) VVPOS_DC_REG DC load regulation (4) 0 mA ≤ ILOAD_VPOS ≤ ILOAD_VPOS_MAX (5) VPOS dropout voltage PSSRVPOS Power supply rejection ratio (LDO_VPOS) (4) ƒ = 10 Hz to 500 kHz at IMAX/2 VLCM_OUT – VVPOS ≥ 300 mV tST_VPOS Start-up time (LDO_VPOS) (6) VVPOS = 10% to 90% (4) CVPOS = 10 µF v RPD_VPOS Output pulldown resistor (VPOS) VPOS pulldown in shutdown Pulldown resistance on LCM_EN1 Not ATE tested mA 250 mA –50 50 mV –50 50 mV 20 mV 160 mV ILOAD_VPOS = ILOAD_VPOS_MAX VVPOS = 5.7 V VDO_VPOS (4) (5) (6) mA 180 (4) Peak start-up inrush current VVPOS_LOAD_TRA mV 1.5% 80 IRUSH_PK_VPOS LINE_TRANSIENT –1.5% 25 dB 800 30 80 µs 270 300 Ω kΩ Limits set by characterization and/or simulation only. VIN_VPOS – VVPOS when VVPOS has dropped 100 mV below target. Typical value only for information. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 7 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com Electrical Characteristics (continued) Unless otherwise specified, typical limits apply at 25°C, minimum and maximum limits apply over the full operating ambient temperature range (−40°C ≤ TA ≤ 85°C), and VIN = 3.6 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DISPLAY BIAS NEGATIVE OUTPUT (VNEG) VNEG_SHORT NEG output short circuit protection VNEG to CP_GND, VNEG rises to % of target 84% Efficiency (6) VLCM_OUT = 5.7 V, VNEG = –5.4 V, INEG > –5 mA 92% Programmable output voltage range VVNEG –6.5 –4 Output voltage step size 50 Output accuracy Output voltage = –5.4 V ILOAD_VNEG_MAX Maximum output current VLCM_OUT = 5.9 V, VNEG = –5.4 V IVNEG_CL Output current limit RDSON_VNEG CP FET ON resistance –1.5% 350 Q2 240 Q3 240 VVNEG_LINE_TRAN VNEG line transient response (4) VIN + 500 mVp-p AC square wave, 100 mV/µs 200 Hz, 12.5% duty at 5 mA VVNEG load transient response (4) 0 to –50 mA step, tRISE/FALL = 1 µs, CVNEG = 10 µF (nominal) tSU_VNEG VVNEG start-up time, VVNEG = 10% to 90% (4) VVNEG = –6.5 V, CVNEG = 10 µF (nominal) RVNEG Output pullup resistor (VNEG to CP_GND) (4) VNEG pullup in shutdown NSIENT Pulldown resistance on LCM_EN2 mA Q1 INEG = –5 mA and –50 mA, CVNEG = 10 µF (nominal) VVNEG_LOAD_TRA 1.5% 135 Peak-to-peak ripple voltage (4) SIENT mV 80 VVNEG_RIPPLE –50 ±25 6 Not ATE tested V mA mΩ 60 mVpp 50 mV 100 mV 1 ms 20 Ω 300 kΩ PWM INPUT ƒPWM_INPUT PWM input frequency (6) Minimum pulse ON time (4) tMIN_ON 2.7 V ≤ VIN ≤ 5 V 50 24-MHz sample rate 183.3 4-MHz sample rate 1100 1-MHz sample rate 4400 24-MHz sample rate 183.3 4-MHz sample rate 1100 1-MHz sample rate 4400 50000 Hz ns tMIN_OFF Minimum pulse OFF timet (4) tSTART-UP Turnon delay from PWM = 0 to PWM = 50% duty cycle 4-MHz sample rate 3.5 ms PWMRES PWM input resolution 50 Hz < ƒPWM < 11 kHz 11 bits tGLITCH PWM input glitch rejection ns Filter = 00 0 Filter = 01 100 Filter = 10 150 Filter = 11 200 ns LOGIC INPUTS (PWM, HWEN, EN_POS, EN_NEG, SCL, SDA, EN_BL) VIL Input logic low 2.7 V ≤ VIN ≤ 5 V 0 0.4 V VIH Input logic high 2.7 V ≤ VIN ≤ 5 V 1.2 VIN V 0.4 V LOGIC OUTPUTS (SDA) VOL 8 Output logic low 2.7 V ≤ VIN ≤ 5 V, IOL = 3 mA Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 6.6 I2C Timing Requirements (Fast Mode) Over operating free-air temperature range; limits apply over 2.5 V ≤ VIN ≤ 5 V (unless otherwise noted). See Figure 1. MIN tLOW_SCL SCL low clock period 0.5 tHIGH_SCL SCL high clock period 0.26 ƒSCL SCL clock frequency tSU_DAT Data in setup time to SCL high tV_DAT Data valid time tHD_DAT Data out stable after SCL low tSTART SDA low setup time to SCL low (start) tSTOP SDA high hold time after SCL high (stop) µs µs 1 MHz 50 ns 0.45 tRISE SDA/SCL rise time tFALL SDA/SCL fall time VPULLUP = 1.8 V, RPULLUP = 1 kΩ, CBUS = 100 pF µs 260 ns 260 ns 120 ns 120 ns tSU_DAT tRISE 70% UNIT 0 VPULLUP = 1.8 V, RPULLUP = 1 kΩ, CBUS = 100 pF tFALL MAX 70% 70% 70% 70% SDA 30% 30% 30% tFALL 70% 30% 30% tSTOP tRISE tHIGH tHD_DAT 70% tV_DAT 70% SCL 30% tSTART 30% 30% 30% 1/fSCL tLOW Start 9th Clock Pulse Stop Start Figure 1. I2C Timing Parameters Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 9 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com 6.7 Typical Characteristics Ambient temperature is 25°C and VIN is 3.7 V unless otherwise noted. 30 30 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 25 25 20 ILED (mA) ILED (mA) 20 15 15 10 10 5 5 0 0 0 256 512 768 1024 1280 Brightness Code 1536 1792 2048 0 256 Figure 2. Backlight LED Current, Linear Control 1536 1792 2048 D002 Figure 3. Backlight LED Current, Exponential Control VIN = 2.7 V VIN = 3.7 V VIN = 5 V 0.8 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 0.9 0.8 0.7 Matching (%) 0.7 0.6 0.5 0.4 0.6 0.5 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0.0 0.0 0 5 10 15 ILED (mA) 20 25 30 0 5 10 D003 Figure 4. Backlight LED Current Matching 15 ILED (mA) 20 25 30 D004 Figure 5. Backlight LED Current Matching 0.6 0.6 VIN = 2.7 V VIN = 3.7 V VIN = 5 V TA = -40qC TA = 25qC TA = 85qC 0.5 LED Step Ratio (%) 0.5 LED Step Ratio (%) 768 1024 1280 Brightness Code 1.0 0.9 0.4 0.3 0.2 0.1 0.4 0.3 0.2 0.1 0.0 0.0 0 256 512 768 1024 1280 Brightness Code 1536 1792 2048 0 256 D005 Figure 6. Backlight LED Current-Step Ratio 10 512 D001 1.0 Matching (%) VIN = 2.7 V VIN = 3.7 V VIN = 5 V 512 768 1024 1280 Brightness Code 1536 1792 2048 D006 Figure 7. Backlight LED Current-Step Ratio Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 Typical Characteristics (continued) 3.0 3.0 2.0 2.0 1.0 1.0 Accuracy (%) Accuracy (%) Ambient temperature is 25°C and VIN is 3.7 V unless otherwise noted. 0.0 -1.0 VIN = 2.7 V VIN = 3.7 V VIN = 5 V -2.0 0.0 -1.0 TA = -40qC TA = 25qC TA = 85qC -2.0 -3.0 -3.0 0 256 512 768 1024 1280 Brightness Code 1536 1792 0 2048 256 1080 540 1060 530 1040 520 1020 1000 980 960 940 920 3.1 3.4 3.7 4 4.3 VIN (V) 4.6 4.9 5.2 2048 510 500 490 480 TA = -40qC TA = 25qC TA = 85qC 450 2.5 5.5 2.8 3.1 3.4 3.7 D009 4 4.3 VIN (V) 4.6 4.9 5.2 5.5 D010 ƒ = 500 kHz Figure 10. Backlight Boost Frequency Figure 11. Backlight Boost Frequency 275 0.32 270 0.30 265 0.28 260 0.26 VHEADROOM (V) Frequency (kHz) 1792 D008 460 ƒ = 1 MHz 255 250 245 0.24 0.22 0.20 0.18 240 235 0.16 TA = -40qC TA = 25qC TA = 85qC 230 225 2.5 1536 470 TA = -40qC TA = 25qC TA = 85qC 2.8 768 1024 1280 Brightness Code Figure 9. Backlight LED Current Accuracy 550 Frequency (kHz) Frequency (kHz) Figure 8. Backlight LED Current Accuracy 1100 900 2.5 512 D007 2.8 3.1 3.4 3.7 4 4.3 VIN (V) 4.6 4.9 5.2 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 0.14 0.12 5.5 0 D011 5 10 15 ILED (mA) 20 25 30 D027 ƒ = 250 kHz Figure 12. Backlight Boost Frequency Figure 13. Backlight Regulated Headroom Voltage Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 11 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com Typical Characteristics (continued) Ambient temperature is 25°C and VIN is 3.7 V unless otherwise noted. 0.32 4.875 TA = -40qC TA = 25qC TA = 85qC 0.30 4.850 0.26 VLCM_OUT (V) VHEADROOM (V) 0.28 0.24 0.22 0.20 0.18 0.16 TA = -40qC TA = 25qC TA = 85qC 0.14 4.825 4.800 4.775 4.750 4.725 0.12 0 5 10 15 ILED (mA) 20 25 0 30 20 40 60 D028 80 100 Load (mA) 120 140 160 D012 VLCM_OUT = 4.8 V Figure 15. VLCM_OUT Load Regulation Figure 14. Backlight Regulated Headroom Voltage 5.900 5.900 TA = -40qC TA = 25qC TA = 85qC 5.875 5.850 5.850 VLCM_OUT (V) VLCM_OUT (V) VIN = 2.7 V VIN = 3.7 V VIN = 5 V 5.875 5.825 5.800 5.775 5.825 5.800 5.775 5.750 5.750 5.725 5.725 5.700 5.700 0 20 40 60 80 100 Load (mA) 120 140 160 0 20 40 60 D013 VLCM_OUT = 5.8 V 80 100 Load (mA) 120 140 160 D014 VLCM_OUT = 5.8 V Figure 16. VLCM_OUT Load Regulation Figure 17. VLCM_OUT Load Regulation 4.06 6.900 TA = -40qC TA = 25qC TA = 85qC 6.875 4.04 4.02 6.825 VVPOS (V) VLCM_OUT (V) 6.850 6.800 6.775 4.00 3.98 6.750 TA = -40qC TA = 25qC TA = 85qC 3.96 6.725 3.94 6.700 0 20 40 60 80 100 Load (mA) 120 140 160 0 VLCM_OUT = 6.8 V 20 VVPOS = 4 V Figure 18. VLCM_OUT Load Regulation 12 10 D015 Submit Documentation Feedback 30 40 50 Load (mA) 60 70 80 D016 VLCM_OUT = 4.3 V Figure 19. VVPOS Load Regulation Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 Typical Characteristics (continued) 5.58 5.58 5.56 5.56 5.54 5.54 5.52 5.52 VVPOS (V) VVPOS (V) Ambient temperature is 25°C and VIN is 3.7 V unless otherwise noted. 5.50 5.48 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 5.50 5.48 5.46 5.46 TA = -40qC TA = 25qC TA = 85qC 5.44 5.44 5.42 5.42 0 10 20 VVPOS = 5.5 V 30 40 50 Load (mA) 60 70 0 80 10 20 30 D017 VLCM_OUT = 5.8 V VVPOS = 5.5 V Figure 20. VVPOS Load Regulation 40 50 Load (mA) 60 70 80 D018 VLCM_OUT = 5.8 V Figure 21. VVPOS Load Regulation -3.94 6.60 6.58 -3.96 6.56 -3.98 6.52 VVNEG (V) VVPOS (V) 6.54 6.50 6.48 -4.00 -4.02 6.46 6.44 TA = -40qC TA = 25qC TA = 85qC 6.42 TA = -40qC TA = 25qC TA = 85qC -4.04 -4.06 6.40 0 10 20 VVPOS = 6.5 V 30 40 50 Load (mA) 60 70 0 80 10 VLCM_OUT = 6.8 V VVNEG = –4 V Figure 22. VVPOS Load Regulation 30 40 50 Load (mA) 60 70 80 D020 VLCM_OUT = 4.3 V Figure 23. VVNEG Load Regulation -5.42 -5.42 -5.44 -5.44 -5.46 -5.46 -5.48 -5.48 VVNEG (V) VVNEG (V) 20 D019 -5.50 -5.52 -5.54 VIN = 2.7 V VIN = 3.7 V VIN = 5 V -5.50 -5.52 -5.54 TA = -40qC TA = 25qC TA = 85qC -5.56 -5.56 -5.58 -5.58 0 10 20 VVNEG = –5.5 V 30 40 50 Load (mA) 60 70 80 0 10 20 D021 VLCM_OUT = 5.8 V VVNEG = –5.5 V Figure 24. VVNEG Load Regulation 30 40 50 Load (mA) 60 70 Product Folder Links: LM36274 D022 VLCM_OUT = 5.8 V Figure 25. VVNEG Load Regulation Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated 80 13 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com Typical Characteristics (continued) -6.40 1.0 -6.42 0.9 -6.44 0.8 -6.46 0.7 ISHUTDOWN (P$) VVNEG (V) Ambient temperature is 25°C and VIN is 3.7 V unless otherwise noted. -6.48 -6.50 -6.52 -6.54 TA = -40qC TA = 25qC TA = 85qC 0.6 0.5 0.4 0.3 -6.56 0.2 TA = -40qC TA = 25qC TA = 85qC -6.58 0.1 -6.60 0 10 20 30 VVNEG = –6.5 V 40 50 Load (mA) 60 70 0.0 2.5 80 2.8 3.1 VLCM_OUT = 6.8 V Figure 26. VVNEG Load Regulation 2.0 3.7 4 4.3 VIN (V) 4.6 4.9 5.2 5.5 D024 I2C = 0 V VHWEN = 0 V Figure 27. Iq Shutdown 2.4 2.2 3.4 D023 10 TA = -40qC TA = 25qC TA = 85qC TA = -40qC TA = 25qC TA = 85qC 9 8 7 1.6 ISTANDBY (P$) ISTANDBY (P$) 1.8 1.4 1.2 1.0 0.8 6 5 4 3 0.6 2 0.4 0.2 1 0.0 2.5 0 2.5 2.8 3.1 VHWEN = VIN 3.4 3.7 4 4.3 VIN (V) 4.6 I2C = VIN 4.9 5.2 5.5 2.8 VHWEN = 1.8 V Figure 28. IQ Standby 14 3.1 D025 3.4 3.7 4 4.3 VIN (V) 4.6 4.9 5.2 5.5 D026 I2C = 1.8 V Figure 29. IQ Standby Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 7 Detailed Description 7.1 Overview The LM36274 is a single-chip, complete backlight and LCM power solution. The device operates over the 2.7-V to 5-V input voltage range. The backlight block consists of an inductive boost plus four current sink white-LED drivers designed to power from one to four LED strings with up to six LEDs each (up to 28 V typical), with a maximum of 30 mA per string. A higher number of LEDs per string can be supported if the total output power requirement for the boost does not exceed 2.5 Watts. The power for the LED strings comes from an integrated asynchronous backlight boost converter with three selectable switching frequencies to optimize performance or solution area. LED current is regulated by the low-headroom current sinks. The inductive backlight boost automatically adjusts its output voltage to keep the active current sinks in regulation, while minimizing current sink headroom voltage. The 11-bit LED current is set via an I2C interface, via a logic level PWM input, or a combination of both. The LCM bias power portion of the LM36274 consists of a synchronous LCM bias boost converter, inverting charge pump, and an integrated LDO. The LCM positive bias voltage VPOS (up to 6.5 V) is post-regulated from the LCM bias boost converter output voltage. The LCM negative bias voltage VNEG (down to –6.5 V) is generated from the LCM bias boost converter output using a regulated inverting charge pump. The LM36274 flexible control interface consists of an HWEN active low reset input, LCM_EN1 and LCM_EN2 inputs for VPOS and VNEG enable control, PWM input for content adaptive backlight control (CABC), and an I2C-compatible interface. Additionally, there is a flag register with flag and status bits. The user can read back this register and determine if a fault or warning message has been generated. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 15 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com 7.2 Functional Block Diagram BL_SW Reference and Thermal Shutdown IN HWEN POR (1.8V) Global Active-low Reset BL_SW Programmable Overvoltage Protection (17 V, 21 V, 25 V, 29 V) BL_OUT Programmable 500 kHz/1 MHz Oscillator Backlight Boost Converter LED1 Overcurrent Protection LED2 VHR Feedback PWM PWM Sampler SDA I2C Compatible Interface SCL BL_GND LED3 Backlight LED Control LED4 1. 11-bit Brightness Adjustment 2. Exponential/Linear Dimming 3. LED Current Ramping 4. Auto Frequency Mode BL LED Drivers VPOS (LCM Postive Bias) VPOS LCM_EN1 LCM Bias Output Control LCM Boost Converter LCM_EN2 C+ VNEG (LCM Negative Bias) Internal Logic AGND VNEG C- LCM_SW LCM_GND LCM_OUT CP_GND Copyright © 2017, Texas Instruments Incorporated 7.3 Features Description 7.3.1 Enabling the LM36274 The LM36274 has a logic level input HWEN which serves as the master enable/disable for the device. When HWEN is low the device is disabled, the registers are reset to their default state, the I2C bus is inactive, and the device is placed in a low-power shutdown mode. When HWEN is forced high the device is enabled, and I2C writes are allowed to the device. 16 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 Features Description (continued) 7.3.2 Backlight The high voltage required by the LED strings is generated with an asynchronous backlight boost converter. An adaptive voltage control loop automatically adjusts the output voltage based on the voltage over the LED drivers LED1, LED2, LED3 and LED4. The LM36274 has three switching frequency modes, 1 MHz, 500 kHz, and 250 kHz. These are set via the BL_FREQ Select bit, register 0x03 bit[7] and by utilizing the auto-frequency feature (refer to Auto Switching Frequency). Operation in low-frequency mode results in better efficiency at lighter load currents due to the decreased switching losses. Operation in high-frequency mode gives better efficiency at higher load currents due to the reduced inductor current ripple and the resulting lower conduction losses in the MOSFET and inductor. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 17 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com Features Description (continued) BL_SW BL_SW BL_GND Overvoltage Protection 17 V 21 V 25 V 29 V BL_OUT OVP 0.2 Fault Detection Overvoltage Current Limit Thermal Shutdown Boost Control OCP Boost Switching Frequency 1 MHz 500 kHz 250 kHz TSD Thermal Shutdown 140oC Auto Frequency Mode SDA Boost Current Limit 900 mA 1200 mA 1500 mA 1800 mA 2 I C Interface Min Headroom Select SCL Adaptive Headroom Current Sinks LED1 PWM Sample Rate 1 MHz 4 MHz 24 MHz LED2 11-Bit Brightness Code LED Current Mapping Exponential Linear LED3 LED4 PWM PWM Sampler LED Current Ramping 16 - Levels 0 to 8 s LED String Enables Copyright © 2017, Texas Instruments Incorporated Figure 30. Backlight Block Diagram 18 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 Features Description (continued) 7.3.2.1 Current Sink Enable Each current sink in the device has a separate enable input. This allows for a one-string, two-string, three-string or four-string application. Once the correct LED string configuration is programmed and a non-zero code is written to the brightness registers, the device can be enabled by writing the backlight enable bit high (register 0x08 bit[4]). The default settings for the device are backlight enable bit set to 0, all backlight strings disabled, PWM input disabled, linear mapped mode, and the brightness level set to 30 mA per string. When PWM is enabled, the LM36274 actively monitors the PWM input. After a non-zero PWM duty cycle is detected, the LM36274 multiplies the duty cycle with the programmed I2C brightness code to give an 11-bit brightness value between 60 µA and 30 mA. Figure 31 and Figure 32 describe the start-up timing for operation with I2C controlled current and with PWM controlled current. VIN HWEN I2C I2C Registers In Reset I2C Data Valid I2C Brightness Data Sent I2C LED Strings Enable ILED tBRT_DAC tHWEN_I2C (< 50 µs) tDAC_LED (< 30 µs) (< 800 µs) Figure 31. Enabling the LM36274 via I2C VIN HWEN I2C I2C Registers In Reset I2C Data Valid I2C PWM Pin Enable I2C LED Strings Enable PWM ILED tPWM_DAC tHWEN_I2C (< 50 µs) tDAC_LED (< 30 µs) tDD_LED tPWM_STBY (< 800 µs) Figure 32. Enabling the LM36274 via PWM The LM36274 backlight can be enabled or disabled in various ways. When disabled, the device is considered shut down, and the quiescent current drops to ISHDN. When the device is in standby, it returns to the ISTANDBY current level retaining all programmed register values. Table 1 describes the different backlight operating states for the LM36274. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 19 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com Features Description (continued) Table 1. Backlight Operating Modes HWEN BL_EN 0x08[4] PWM INPUT IC BRIGHTNESS 0x05[7:0] 0x04[2:0] CURRENT SINK ENABLES 0x08[3:0] PWM EN 0x02[0] PWM RAMP 0x02[1] FEEDBACK DISABLES 0x10[6:3] MAPPING MODE 0x02[3] 0 X X X X X X X X Shutdown 1 0 X X X X X X X Standby (1) 1 1 X 0x000 0000 X X X X Standby (1) 1 1 X ≥0x001 ≥0001 0 X 0 ≥0x001 ≥0001 1 1 1111 0 = Exponential Mode 1 = Linear Mode -Backlight boost disabled -Selected current sink(s) enabled -I2C × PWM (before ramper) Standby implies the backlight boost and current sinks are shut down. Register writes are still possible. Shutdown implies that the device is in reset and no I2C communication is possible. 7.3.2.2 Brightness Mapping There are two different ways to map the brightness code (or PWM duty cycle) to the LED current: linear and exponential mapping. 7.3.2.2.1 Linear Mapping For linear mapped mode the LED current increases proportionally to the 11-bit brightness code and follows the relationship: ILED = 45.37 µA + 14.63 µA × Code (1) 2 This is valid from codes 1 to 2047. Code 0 programs 0 current. Code is an 11-bit code that can be the I C brightness code or the product of the I2C brightness code and the PWM duty cycle. 7.3.2.2.2 Exponential Mapping In exponential mapped mode the LED current follows the relationship: ILED = 60 µA × 1.003040572Code (2) This results in an LED current step size of approximately 0.304% per code. This is valid for codes from 1 to 2047. Code 0 programs 0 current. Code is an 11-bit code that can be the I2C brightness code or the product of the I2C brightness code and the PWM duty cycle. Figure 33 details the LED current exponential response. The 11-bit (0.304%) per code step is small enough such that the transition from one code to the next in terms of LED brightness is not distinguishable to the eye. This, therefore, gives a perfectly smooth brightness increase between adjacent codes. 20 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 100 LED Current (mA) 10 1 0.1 0.01 0 256 512 768 1024 1280 1536 11-Bit Brightness Code 1792 2048 Figure 33. LED Current vs Brightness Code (Exponential Mapping) 7.3.2.3 Backlight Brightness Control Modes The LM36274 has 2 brightness control modes: 1. I2C only brightness control 2. I2C × PWM brightness control 7.3.2.3.1 I2C Brightness Control (PWM Pin Disabled) If the PWM pin is disabled the I2C brightness registers are in control of the LED current, and the PWM input is disabled. The brightness data (BRT) is the concatenation of the two brightness registers (3 LSBs) and (8 MSBs) (registers 0x04 and 0x05, respectively). The LED current only changes when the MSBs are written, meaning that to do a full 11-bit current change via I2C, first the 3 LSBs are written and then the 8 MSBs are written. In this mode the ramper only controls the time from one I2C brightness set-point to the next Figure 34. VOUT Boost Digital Domain Analog Domain Min VHR RAMP_RATE Bits ILED1 ILED2 ILED3 ILED4 Driver_1 BRT Code = I2C Code I2C Brightness Reg Ramper DACi Mapper DAC Driver_2 Driver_3 MAP_MODE Driver_4 Figure 34. I2C Only Brightness Control Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 21 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com 7.3.2.3.2 I2C × PWM Brightness Control (PWM Pin Enabled) If the PWM pin is enabled both the I2C brightness code and the PWM duty-cycle control the LED current. With linear mapping the PWM duty cycle-to-current response is approximated by Equation 3: ILED = 45.37 µA + 14.63 µA × I2C BRGT CODE × PWM D/C (3) With exponential mapping the PWM duty cycle-to-current response is approximated by Equation 4: ILED = 60 µA × 1.003040572I2C BRGT CODE × PWM D/C (4) 7.3.2.3.2.1 PWM Ramper The PWM ramp option (register 0x02 bit[1]) determines whether the ramper is active or inactive during a change in PWM duty cycle. The ramper smooths the transition from one brightness value to another. Ramp time can be adjusted from 0 ms to 8000 ms with LED Current Ramp [3:0] bits (register 0x03 bits [6:3]). Ramp time is used for sloping both up and down. Ramp time always remains the same regardless of the amount of change in brightness. In PWM mode the behavior of the ramper depends on the state of the PWM Ramp bit (register 0x02, bit [1]). If the PWM Ramp bit is set to 0, there is no LED current ramping between PWM duty cycle changes. The PWM duty cycle is multiplied with the I2C brightness code at the output of the ramper (see Figure 35). If this bit is set to 1, ramping is achieved between I2C × PWM currents (see Figure 36). VOUT Boost Digital Domain Analog Domain Min VHR RAMP_RATE Bits ILED1 ILED2 ILED3 ILED4 Driver_1 BRT Code = I2C × Duty Cycle I2C Brightness Reg Ramper DACi Mapper DAC Driver_2 Driver_3 MAP_MODE Driver_4 PWM Input PWM Detector Figure 35. (I2C + PWM) Brightness Control, PWM Ramper Disabled 22 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 VOUT Boost Digital Domain Analog Domain Min VHR ILED1 RAMP_RATE Bits ILED2 ILED3 ILED4 Driver_1 BRT Code = I2C × Duty Cycle DACi I2C Brightness Reg Ramper Mapper Driver_2 DAC Driver_3 PWM Input MAP_MODE PWM Detector Driver_4 Figure 36. (I2C + PWM) Brightness Control, PWM Ramper Enabled 7.3.2.4 Boost Switching Frequency The LM36274 has two programmable switching frequencies: 500 kHz and 1 MHz. These are set via the Backlight Configuration 2 register (register 0x03 bit [7]). Operation at 1 MHz is primarily beneficial when efficiency at high load current is more important. For maximum efficiency across the entire load current range the device incorporates an automatic frequency shift mode (see Auto Switching Frequency). 7.3.2.4.1 Minimum Inductor Select The LM36274 can use inductors in the range of 4.7 µH to 15 µH. In order to optimize the converter response to changes in VIN and load, the Backlight Boost L Select bits (register 0x11 bits [7:6]) must be selected depending on the nominal value of inductance chosen. 7.3.2.5 Boost Feedback Gain Select The Boost Integral and Proportional Feedback Gain Select bits in Option 2 register (bits [3:2] and bits[5:4] in register 0x11) contain adjustment parameters for the LM36274 internal loop gain. The optimized settings using a 1-uF capacitor at BL_OUT are the default settings of 01 and 11 for Integral and Proportional, respectively. 7.3.2.6 Auto Switching Frequency To take advantage of frequency vs load dependent losses, the LM36274 can automatically change the boost switching frequency based on the programmed brightness code. In addition to the register programmable switching frequencies of 500 kHz and 1 MHz, the auto-frequency mode also incorporates a low-frequency selection of 250 kHz. It is important to note that the 250-kHz frequency is only accessible in auto-frequency mode and has a maximum boost duty cycle (DMAX) of 50%. Auto-frequency mode operates by using two programmable registers (Backlight Auto Frequency Low Threshold (register 0x06) and Backlight Auto Frequency High Threshold (register 0x07)). The high threshold determines the switchover from 1 MHz to 500 kHz. The low threshold determines the switchover from 500 kHz to 250 kHz. Both the High and Low Threshold registers take an 8-bit code which is compared against the 8 MSB of the brightness register (register 0x05). Table 2 details the boundaries for this mode. Table 2. Auto Switching Frequency Operation BRIGHTNESS CODE MSBs (Register 0x05 bits[7:0]) < Auto Frequency Low Threshold (register 06 Bits[7:0]) > Auto Frequency Low Threshold (Register 06 Bits[7:0]) and < Auto Frequency High Threshold (Register 07 Bits[7:0]) BOOST SWITCHING FREQUENCY 250 kHz (DMAX = 50%) 500 kHz Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 23 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com Table 2. Auto Switching Frequency Operation (continued) BRIGHTNESS CODE MSBs (Register 0x05 bits[7:0]) BOOST SWITCHING FREQUENCY ≥ Auto Frequency High Threshold (register 07 Bits[7:0]) 1 MHz Automatic-frequency mode is enabled whenever there is a non-zero code in either the Auto-Frequency High or Auto-Frequency Low registers. To disable the auto-frequency shift mode, set both registers to 0x00. When automatic-frequency select mode is disabled, the switching frequency operates at the programmed frequency (Register 0x03 bit[7]) across the entire LED current range. Table 3 provides a guideline for selecting the auto frequency threshold settings at VIN = 3.7 V. The actual setting must be verified in the application and optimized for the desired input voltage range. Table 3. Auto Frequency Threshold Settings Examples, VIN = 3.7 V CONDITION (Vf = 3.35 V at ILED = 30 mA) INDUCTOR (µH) 2 × 4 LEDs 10 0x65 (12 mA) 0x43 (8 mA) 2 × 5 LEDs 10 0x5C (11 mA) 0x42 (7.9 mA) 2 × 6 LEDs 10 0x54 (10 mA) 0x3F (7.5 mA) 2 × 7 LEDs 10 0x4F (9.4 mA) 0x36 (6.5 mA) 2 × 8 LEDs 10 0x65 (12 mA) 0x3F (7.5 mA) 3 × 4 LEDs 10 0x4C (9 mA) 0x2A (5.1 mA) 3 × 5 LEDs 10 0x43 (8mA) 0x28 (4.8 mA) 3 × 6 LEDs 10 0x3B (7 mA) 0x27 (4.7 mA) 3 × 7 LEDs 10 0x35 (6.4 mA) 0x26 (4.6 mA) 3 × 8 LEDs 10 0x43 (8 mA) 0x25 (4.5 mA) 4 × 4 LEDs 10 0x5C (11 mA) 0x2B (5.2 mA) 4 × 5 LEDs 10 0x50 (9.5 mA) 0x28 (4.8 mA) 4 × 6 LEDs 10 0x50 (9.5 mA) 0x28 (4.8 mA) RECOMMENDED AUTO FREQUENCY HIGH THRESHOLD RECOMMENDED AUTO FREQUENCY LOW THRESHOLD 7.3.2.7 PWM Input The PWM input is a sampled input which converts the input duty cycle information into an 11-bit brightness code. The use of a sampled input eliminates any noise and current ripple that traditional PWM controlled LED drivers are susceptible to. It also allows the PWM duty cycle to LED current response to have the same high accuracy and matching that is offered in the I2C brightness control. The PWM input uses logic level thresholds with VIH_MIN = 1.25 V and VIL_MAX = 0.4 V. Because this is a sampled input, there are limits on the maximum PWM input frequency as well as the resolution that can be achieved. 7.3.2.7.1 PWM Sample Frequency There are three selectable sample rates for the PWM input. The choice of sample rate depends on three factors: 1. Required PWM resolution (input duty cycle to brightness code, with 11 bits maximum) 2. PWM input frequency 3. Efficiency 7.3.2.7.1.1 PWM Resolution and Input Frequency Range The PWM input frequency range is 50 Hz to 50 kHz. To achieve the full 11-bit maximum resolution of PWM duty cycle to the LED brightness code (BRT), the input PWM duty cycle must be ≥ 11 bits, and the PWM sample period (1/ƒSAMPLE) must be smaller than the minimum PWM input pulse width. Figure 37 shows the possible brightness code resolutions based on the input PWM frequency. The minimum PWM frequency for each PWM sample rate is described in PWM Timeout. 24 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 Max Achievable Resolution (bits) 12 11 10 9 8 7 6 Sample Freq = 1 MHz Sample Freq = 4 MHz Sample Freq = 24 MHz 5 4 100 1000 10000 PWM Frequency (Hz) 100000 Figure 37. PWM Sample Rate, Resolution, and PWM Input Frequency 7.3.2.7.1.2 PWM Sample Rate and Efficiency Efficiency is maximized when the lowest ƒSAMPLE is chosen because this lowers the quiescent operating current of the device. Table 4 describes the typical efficiency tradeoffs for the different sample clock settings. Table 4. PWM Sample Rate Trade-Offs PWM SAMPLE RATE (ƒSAMPLE) TYPICAL INPUT CURRENT, DEVICE ENABLED ILED = 10 mA/string, 4 × 6 LEDs TYPICAL EFFICIENCY 0x03 Bit[2] 0x12 Bit[0] ƒSW = 1 MHz VIN = 3.7 V 0 0 1.805 mA 89.5% 1 0 1.875 mA 89.47% X 1 2.598 mA 89.1% 7.3.2.7.1.2.1 PWM Sample Rate Example The number of bits of resolution on the PWM input varies according to the PWM sample rate and PWM input frequency (see Table 5). Table 5. PWM Resolution vs PWM Sample Rate PWM FREQUENCY (kHz) RESOLUTION (PWM SAMPLE RATE = 1 MHz) RESOLUTION (PWM SAMPLE RATE = 4 MHz) RESOLUTION (PWM SAMPLE RATE = 24 MHz) 0.4 11 11 11 2 9 11 11 12 6.4 8.4 11 7.3.2.7.2 PWM Hysteresis To prevent jitter at the input PWM signal from feeding through the PWM path and causing oscillations in the LED current, the LM36274 offers 4 selectable hysteresis settings. The hysteresis options for the 1-MHz and 4-MHz PWM sample rate settings are 1, 2, 4, and 6 bits and for the 24-MHz PWM sample rate setting 0, 1, 2, and 3 bits. The hysteresis works by forcing a specific number of 11-bit LSB code transitions to occur in the input duty cycle before the LED current changes. Table 6 describes the hysteresis. The hysteresis only applies during the change in direction of brightness currents. Once a change in the direction of the LED current has taken place, the PWM input must over come the required LSB(s) of the hysteresis setting before the brightness change takes effect. Once the initial hysteresis has been overcome and the direction in brightness change remains the same, the PWM to current response changes with no hysteresis. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 25 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com Table 6. PWM Input Hysteresis HYSTERESIS SETTING (0x03 Bits[1:0]) MIN CHANGE IN PWM PULSE WIDTH (Δt) REQUIRED TO CHANGE LED CURRENT, AFTER DIRECTION CHANGE (for ƒPWM < 11.7 kHz) MIN CHANGE IN PWM DUTY CYCLE (ΔD) REQUIRED TO CHANGE LED CURRENT AFTER DIRECTION CHANGE MIN (ΔILED), INCREASE FOR INITIAL CODE CHANGE EXPONENTIAL MODE LINEAR MODE 0 LSB (24 MHz sample rate only) 1/(ƒPWM × 2047) 0.05% 0.30% 0.05% 1 LSB 1/(ƒPWM × 1023) 0.10% 0.61% 0.10% 2 LSBs 1/(ƒPWM × 511) 0.20% 1.21% 0.20% 3 LSBs (24-MHz sample rate only) 1/(ƒPWM × 255) 0.39% 2.40% 0.39% 4 LSBs (1-MHz and 4MHz sample rate only) 1/(ƒPWM × 127) 0.78% 4.74% 0.78% 6 LSBs (1-MHz and 4MHz sample rate only ) 1/(ƒPWM × 31) 3.12% 17.66% 3.12% tJITTER tJITTER D/fPWM 1/fPWM x x x D is tJITTER x fPWM or equal to #/6%¶V = ¨' [ 2048 codes. For 11-bit resolution, #LSBs is equal to a hysteresis setting of LN(#/6%¶V)/LN(2). For example, with a tJITTER of 1 µs and a fPWM of 5 kHz, the hysteresis setting should be: LN(1 µ s x 5 kHz x 2048)/LN(2) = 3.35 (4 LSBs). Figure 38. PWM Hysteresis Example 7.3.2.7.3 PWM Step Response The LED current response due to a step change in the PWM input is approximately 2 ms to go from minimum LED current to maximum LED current. 7.3.2.7.4 PWM Timeout The LM36274 PWM timeout feature turns off the boost output when the PWM is enabled and there is no PWM pulse detected. The timeout duration changes based on the PWM sample rate selected which results in a minimum supported PWM input frequency. The sample rate, timeout, and minimum supported PWM frequency are summarized in Table 7. 26 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 Table 7. PWM Timeout and Minimum Supported PWM Frequency vs PWM Sample Rate SAMPLE RATE TIMEOUT MINIMUM SUPPORTED PWM FREQUENCY 1 MHz 25 msec 48 Hz 4 MHz 3 msec 400 Hz 24 MHz 0.6 msec 2000 Hz 7.3.2.7.5 PWM-to-Digital Code Readback In PWM mode, registers 0x12 and 0x13 contain the PWM duty cycle to the 11-bit code conversion information. Register 0x12 contains the 8 LSBs of the brightness code and register 0x13 the 3 MSBs. To translate this reading to the actual LED current setting of the LM36274, convert it to the corresponding duty cycle and multiply it by the brightness level setting in the brightness registers (0x04 and 0x05). For example, if the 11-bit brightness code is set to 0x554 (decimal 1364) and the PWM-to-digital code readback is 0x3FF (decimal 1023) in linear mode, the expected LED current is approximately: ILED = 45.37 µA + ( ( 1023 / 2047 ) × 14.63 × 1364 ) µA = 10.018 mA (approximately 50% duty cycle). 7.3.2.8 Regulated Headroom Voltage In order to optimize efficiency, current accuracy, and string-to-string matching the LED current sink regulated headroom voltage (VHR) varies with the target LED current. Figure 39 details the typical variation of VHR with LED current. This allows for increased solution efficiency as the dropout voltage of the LED driver changes. Furthermore, in order to ensure that all current sinks remain in regulation whenever there is a mismatch in string voltages, the minimum headroom voltage between VLED1, VLED2, VLED3, VLED4 becomes the regulation point for the boost converter. For example, if the LEDs connected to LED1 require 12 V, the LEDs connected to LED2 require 12.5 V, the LEDs connected to LED3 require 13 V and the LEDs connected to LED4 require 13.5 V at the programmed current, then the voltage at LED1 is VHR + 1.5 V, the voltage at LED2 is VHR + 1 V, the voltage at LED3 is VHR + 0.5, and the voltage at LED4 is regulated at VHR. In other words, the boost makes the cathode of the highest voltage LED string the regulation point. 0.32 0.3 0.28 0.26 VHR (V) 0.24 0.22 0.2 0.18 0.16 0.14 0.12 0.1 0.1 1 LED Current (mA) 10 50 Figure 39. LM36274 Typical Exponential Regulated Headroom Voltage vs Programmed LED Current 7.3.2.9 Backlight Fault Protection and Faults 7.3.2.9.1 Backlight Overvoltage Protection (OVP) The LM36274 provides an OVP that monitors the LED boost output voltage (VBL_OUT) and protects BL_OUT and BL_SW from exceeding safe operating voltages. The OVP threshold can be set to 17 V, 21 V, 25 V, or 29 V with register 0x02 bits[7:5]. Once an OVP event has been detected, the BL_OVP flag is set in the Flags Register, and the subsequent behavior depends on the state of bit OVP_Mode in the Backlight Configuration 1 Register: If OVP_Mode is set to 0, as soon as VBL_OUT falls below the backlight OVP threshold, the LM36274 begins switching again. If OVP_Mode is set to 1 and the device detects three occurrences of VBL_OUT > VOVP_BL while any of the enabled current sink headroom voltages drops below 40 mV, the Backlight Boost OVP flag is set, the Backlight Enable bit is cleared, and the LM36274 enters standby mode. When the device is shut down due to a Backlight Boost OVP fault, the Flags register must be read back before the device can be reenabled. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 27 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com 7.3.2.9.2 Backlight Overcurrent Protection (OCP) The LM36274 has 4 selectable OCP thresholds (900 mA, 1200 mA, 1500 mA, and 1800 mA). These are programmable in register 0x11 bits[1:0]. The OCP threshold is a cycle-by-cycle current limit and is detected in the internal low-side NFET. Once the threshold is hit the NFET turns off for the remainder of the switching period. If enough overcurrent threshold events occur, the BL_OCP Flag (register 0x0F, bit[0]) is set. To avoid transient conditions from inadvertently setting the BL_OCP Flag, a pulse density counter monitors OCP threshold events over a 128-µs period. If 8 consecutive 128-µs periods occur where the pulse density count has found 2 or more OCP events, then the BL_OCP Flag is set. During device start-up and during brightness code changes, there is a 4-ms blank time where BL OCP events are ignored. As a result, if the device starts up in an overcurrent condition there is an approximate 5-ms delay before the BL_OCP Flag is set. 7.3.3 LCM Bias 7.3.3.1 Display Bias Boost Converter (VVPOS, VVNEG) A single high-efficiency boost converter provides a positive voltage rail, VLCM_OUT, which serves as the power rail for the LCM VPOS and VNEG outputs. • The VVPOS output LDO has a programmable range from 4 V up to 6.5 V with 50-mV steps and can supply up to 80 mA. • The VVNEG output is generated from a regulated, inverting charge pump and has an adjustable range of –6.5 V up to –4 V with 50-mV steps and a maximum load of 80 mA. Boost voltage also has a programmable range from 4 V up to 7.15 V with 50-mV steps. Refer to Table 22, Table 23 and Table 24 for VLCM_OUT, VVPOS and VVNEG voltage settings. When selecting a suitable boost-output voltage, the following estimation can be used: VLCM_OUT = max(VVPOS, |VVNEG|) + VHR, where VHR ≥ 200 mV for lower currents and VHR ≥ 300 mV for higher currents. When the device input voltage (VIN) is greater than the programmed LCM boost output voltage, the boost voltage is regulated to VIN + 100 mV. VVPOS and VVNEG voltage settings cannot be changed while they are enabled. VVPOS and VVNEG register setting targets take effect only after the outputs are disabled and re-enabled. However, the VLCM_OUT target changes immediately upon a register write. 28 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 VPOS 4 V to 6.5 V 50 mV steps LDO (VPOS) VPOS Inverting Charge Pump (VNEG) VNEG ENP SCL Auto Sequence SDA ENP Bias Registers ENN Slew Rate Control LCM_EN1 VNEG -4 V to -6.5 V -50 mV steps POR TSD LCM_EN2 VBST 4 V to 7.15 V 50 mV steps Current Limit 1A 2.5 MHz LCM Boost control ENN 0.29 LCM_OUT LCM_SW 0.17 C- C+ Figure 40. LCM Boost Block Diagram The LCM Bias outputs can be controlled either by pins LCM_EN1 and LCM_EN2 or register bits VPOS_EN and VNEG_EN, register 0x09 bits[2:1]. Setting bit EXT_EN, register 0x09 bit[0], to 1 allows pins LCM_EN1 and LCM_EN2 to control VPOS and VNEG, respectively, while setting this bit to 0 yields control to bits VPOS_EN and VNEG_EN. Refer to Table 8 for LCM bias control information. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 29 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com Table 8. LCM Operating Modes HWEN LCM_EN2 INPUT LCM_EN1 INPUT LCM_EN MODE 0x09[7:5] VPOS_EN 0x09[2] VNEG_EN 0x09[1] EXT_EN 0x09[0] 0 X X XXX X X X Device shutdown 1 0 0 000 X X 1 Standby (1) 1 X X 100 0 0 0 Standby (1) 1 0 1 100 X X 1 VPOS enabled via external input 1 1 0 100 X X 1 VNEG enabled via external input 1 1 1 100 X X 1 VPOS and VNEG enabled via external input 1 X X 100 1 0 0 VPOS enabled via I2C 1 X X 100 0 1 0 VNEG enabled via I2C 1 X X 100 1 1 0 VPOS and VNEG enabled via I2C 1 X X 101 1 1 0 VPOS and VNEG enabled via I2C with auto-sequencing 1 1 X 101 X X 1 VPOS and VNEG enabled via LCM_EN2 with auto-sequencing 1 1 X 110 1 0 X WAKE1 VVPOS = VIN VVNEG = GND 1 1 X 110 0 1 X WAKE1 VVPOS = GND VVNEG = –VIN 1 1 X 110 1 1 X WAKE1 VVPOS = VIN VVNEG = –VIN 1 0 X 110 1 1 X WAKE1 Standby (1) 1 1 X 110 0 0 X WAKE1 Standby (1) 1 1 X 111 1 0 X WAKE2 VVPOS = programmed target VVNEG = disabled 1 1 X 111 0 1 X WAKE2 VVPOS = disabled VVNEG = programmed target 1 1 X 111 1 1 X WAKE2 VVPOS = programmed target VVNEG = programmed target 1 1 X 111 0 0 X WAKE2 Standby (1) 1 0 X 111 1 1 X WAKE2 Standby (1) (1) ACTION Standby implies that VPOS and VNEG are either high impedance or being internally pulled low via the active pulldown, and that the LCM boost is off. Shutdown implies that the device is in reset and no I2C communication is possible. 7.3.3.2 Auto Sequence Mode If this mode is selected the LM36274 controls the turnon and turnoff of VPOS and VNEG as shown in Figure 41. VPOS VPOS VNEG VNEG TR = 256 µs to 1024 µs • 1 ms TF = 512 µs to 8192 µs • 1 ms Figure 41. Auto Sequence Timing 30 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 7.3.3.3 Wake-up Mode If wake-up mode is selected the LM36274 allows on/off control of both VPOS and VNEG with only one external pin (LCM_EN2). Any combination of VPOS or VNEG can be turned on based on the state of bits VPOS_EN and VNEG_EN in register 0x09. In these modes the internal shutdown timing of the VPOS and VNEG blocks is modified to allow for lower quiescent current in standby mode, therefore reducing the average current consumption during a sequence of on/off events. There are two wake-up modes available on the LM36274: wake1 and wake2. 7.3.3.3.1 Wake1 Mode In wake1 mode the LM36274 passes VIN through to the LCM boost output and the enabled VPOS, VNEG outputs. Due to the impedance of the LCM boost, the VPOS LDO and the VNEG charge pump, the respective outputs are regulated close to VIN only at very light load current and droop below VIN as the load increases. 7.3.3.3.2 Wake2 Mode In wake2 mode the LM36274 regulates the LCM boost output as well as the enabled VPOS and VNEG outputs to their programmed voltage. 7.3.3.4 Active Discharge An optional active discharge is available for the VPOS and VNEG output rails. An internal switch resistance for this discharge function is implemented on each output rail. The VPOS active discharge function is enabled with register 0x09 bit[4] and the VNEG active discharge with register 0x09 bit[3]. 7.3.3.5 LCM Bias Protection and Faults The LCM bias block of the LM36274 provides three protection mechanisms in order to prevent damage to the device. Note that none of these have any effect on backlight operation. 7.3.3.5.1 LCM Overvoltage (OVP) Protection The LM36274 provides OVP that monitors the LCM bias boost output voltage (VLCM_OUT) and protects LCM_OUT and LCM_SW from exceeding safe operating voltages. The OVP threshold is set to 7.8 V (typical). If an LCM bias overvoltage condition is detected, the LCM_OVP flag, register 0x0F bit[5], is set. Once the OVP condition is removed, the flag can be cleared with an I2C read back of the register. An LCM OVP condition does not cause the LCM bias to shut down; it is a report-only flag. 7.3.3.5.2 VPOS Short-Circuit Protection If the current at VPOS exceeds 180 mA (typical), the LM36274 sets the VPOS_SHORT flag, register 0x0F bit[3]. A readback of register 0x0F is required to clear the flag. The outcome of a VPOS_SHORT detection depends on the configuration of the bias short-circuit mode option, register 0x0A bits[7:6]. The options are report-only flag, shutdown VPOS/VNEG, and shutdown VPOS/VNEG and backlight. To prevent narrow spikes from falsely triggering a VPOS short-circuit condition, the LM36274 provides four programmable VPOS short-circuit filter options: 100 µs, 500 µs, 1 ms, and 2 ms. These are selected in register 0x0B bits[3:2]. 7.3.3.5.3 VNEG Short-Circuit Protection If the voltage at VNEG rises (towards GND) to above 84% of its programmed value (typical), the LM36274 sets the VNEG_SHORT flag, register 0x0F bit[2]. A readback of register 0x0F is required to clear the flag. The outcome of a VNEG_SHORT detection depends on the configuration of the bias short-circuit mode option, register 0x0A bits[7:6]. The options are report-only flag, shut down VPOS/VNEG, and shut down VPOS/VNEG and backlight. To prevent narrow spikes from falsely triggering a VNEG short circuit condition, the LM36274 provides four programmable VNEG short circuit filter options: 100 µs, 500 µs, 1 ms, and 2 ms. These are selected in register 0x0B bits[1:0]. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 31 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com 7.3.4 Software Reset Bit[7] (SWR_RESET) of the Enable Register (0x08) is a software reset bit. Writing a 1 to this bit resets all I2C register values to their default values. Once the LM36274 has finished resetting all registers, it auto-clears the SWR_RESET bit. 7.3.5 HWEN Input The HWEN pin is a global hardware enable for the LM36274. This pin must be pulled to logic HIGH to enable the device and the I2C-compatible interface. There is a 300-kΩ internal resistor between HWEN and GND. When this pin is at logic LOW, the LM36274 is placed in shutdown, the I2C-compatible interface is disabled, and the internal registers are reset to their default state. TI recommends that VIN has risen above 2.7 V before setting HWEN HIGH. 7.3.6 Thermal Shutdown (TSD) The LM36274 has TSD protection which shuts down the backlight boost, all backlight current sinks, LCM bias boost, inverting charge pump, and the LDO when the die temperature reaches or exceeds 140°C (typical). The I2C interface remains active during a TSD event. If a TSD fault occurs the TSD fault is set (register 0x0F bit[6]). The fault is cleared by an I2C read of register 0x0F or by toggling the HWEN pin. 7.4 Device Functional Modes 7.4.1 Modes of Operation Shutdown: The LM36274 is in shutdown when the HWEN pin is low. Standby: After the HWEN pin is set high the LM36274 goes into standby mode. In standby mode, I2C writes are allowed but references, bias currents, the oscillator, LCM powers, and backlight are all disabled to keep the quiescent supply current low (2 µA typical). Normal mode: Both main blocks of the LM36274 are independently controlled. For enabling each of the blocks in all available modes, see Table 1 and Table 8. 32 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 7.5 Programming 7.5.1 I2C-Compatible Serial Bus Interface 7.5.1.1 Interface Bus Overview The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the devices connected to the bus. The two interface lines are the Serial Data Line (SDA) and the Serial Clock Line (SCL). These lines must be connected to a positive supply via a pullup resistor and remain HIGH even when the bus is idle. Every device on the bus is assigned a unique address and acts as either a Master or a Slave, depending whether it generates or receives the serial clock (SCL). 7.5.1.2 Data Transactions One data bit is transferred during each clock pulse. Data is sampled during the high state of the SCL. Consequently, throughout the clock’s high period, the data remains stable. Any changes on the SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data is sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock. SCL SDA data change allowed data valid data change allowed data change allowed data valid Figure 42. Data Validity Each data transaction is composed of a start condition, a number of byte transfers (set by the software), and a stop condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an acknowledge signal must follow. The following sections provide further details of this process. Data Output by Receiver Data Output by Transmitter Transmitter Stays off the Bus During the Acknowledge Clock SCL Acknowledge Signal from Receiver 1 2 3...6 7 8 9 S Start Condition Figure 43. Acknowledge Signal Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 33 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com Programming (continued) The Master device on the bus always generates the start and stop conditions (control codes). After a Start Condition is generated, the bus is considered busy, and it retains this status until a certain time after a stop condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a start condition. A low-to-high transition of the SDA line while the SCL is high indicates a stop condition. SDA SCL S P START condition STOP condition Figure 44. Start and Stop Conditions In addition to the first start condition, a repeated start condition can be generated in the middle of a transaction. This allows another device to be accessed, or a register read cycle. 7.5.1.3 Acknowledge Cycle The acknowledge cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device. The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte. 7.5.1.4 Acknowledge After Every Byte Rule The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received. There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. 7.5.1.5 Addressing Transfer Formats Each device on the bus has a unique slave address. The LM36274 operates as a slave device with the 7-bit address. If an 8-bit address is used for programming, the 8th bit is 1 for read and 0 for write. The 7-bit address for the device is 0x11. Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device sends an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address — the eighth bit. When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1: read, 0: write), the device acts as a transmitter or a receiver. MSB ADR6 Bit7 LSB ADR5 bit6 ADR4 bit5 ADR3 bit4 ADR2 bit3 ADR1 bit2 ADR0 bit1 R/W bit0 I2C SLAVE address (chip address) Figure 45. I2C Device Address 34 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 Programming (continued) • • • • • • • • • • • • • • • • • • • • Control Register Write Cycle Master device generates start condition. Master device sends slave address (7 bits) and the data direction bit (r/w = 0). Slave device sends acknowledge signal if the slave address is correct. Master sends control register address (8 bits). Slave sends acknowledge signal. Master sends data byte to be written to the addressed register. Slave sends acknowledge signal. If master sends further data bytes the control register address is incremented by one after acknowledge signal. Write cycle ends when the master creates stop condition. Control Register Read Cycle Master device generates a start condition. Master device sends slave address (7 bits) and the data direction bit (r/w = 0). Slave device sends acknowledge signal if the slave address is correct. Master sends control register address (8 bits). Slave sends acknowledge signal Master device generates repeated start condition. Master sends the slave address (7 bits) and the data direction bit (r/w = 1). Slave sends acknowledge signal if the slave address is correct. Slave sends data byte from addressed register. If the master device sends acknowledge signal, the control register address is incremented by one. Slave device sends data byte from addressed register. Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition. Table 9. I2C Data Read/Write (1) ADDRESS MODE (1) Data Read [Ack] [Ack] [Ack] [Register Data] ...additional reads from subsequent register address possible Data Write [Ack] [Ack] [Ack] ...additional writes to subsequent register address possible < > = Data from master, [ ] = Data from slave Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 35 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com ack from slave ack from slave start msb Chip Address lsb w ack msb Register Addr lsb ack w ack address = 02h ack ack from slave msb Data lsb ack stop ack stop SCL SDA start id = 001 0001b address 02h data Figure 46. Register Write Format When a READ function is to be accomplished, a WRITE function must precede the READ function, as show in the Read Cycle waveform. ack from slave start msb Chip Address lsb w ack from slave repeated start msb Register Add lsb rs ack from slave data from slave nack from master msb Chip Address lsb r msb Data lsb stop r ack address 00h data nack stop SCL SDA start id = 001 0001b w ack address = 00h ack rs id = 001 0001b Figure 47. Register Read Format NOTE w = write (SDA = 0), r = read (SDA = 1), ack = acknowledge (SDA pulled down by either master or slave), rs = repeated start id = 7-bit chip address 7.5.1.6 Register Programming For glitch-free operation, the following bits and/or registers must only be programmed while the LED Enable bits are 0 (Register 0x08, Bit [3:0] = 0) and/or Backlight Enable bit is 0 (Register 0x08, Bit[4] = 0): 1. Register 0x02 Bit[0] (PWM Enable) 2. Register 0x02 Bits[1] (PWM Ramp) 3. Register 0x02 Bit[2] (PWM Config) 4. Register 0x02 Bits[3] (LED Current Mapping) 5. Register 0x03 Bit[1:0] (PWM Hysteresis) 6. Register 0x03 Bit[2] (PWM Sample) 7. Register 0x03 Bit[6:3] (LED Current Ramp) 8. Register 0x10 Bit[0] (PWM HF Sample) 9. Register 0x10 Bit[1] (PWM Glitch Filter) 10. Register 0x10 Bit [6:3] (LED Feedback Enable) 11. Register 0x06 (auto frequency high threshold) 12. Register 0x07 (auto frequency low threshold) 36 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 7.6 Register Maps Table 10. Register Default Values 2 I C ADDRESS REGISTER NAME READ/WRITE POWER ON/RESET VALUE SECTION 0x01 Revision Register R 0x01 Go 0x02 Backlight Configuration1 Register R/W 0x28 Go 0x03 Backlight Configuration 2 Register R/W 0x8D Go 0x04 Backlight Brightness LSB Register R/W 0x07 Go 0x05 Backlight Brightness MSB Register R/W 0xFF Go 0x06 Backlight Auto-Frequency Low Register R/W 0x00 Go 0x07 Backlight Auto-Frequency High Register R/W 0x00 Go 0x08 Backlight Enable Register R/W 0x00 Go 0x09 Display Bias Configuration 1 Register R/W 0x18 Go 0x0A Display Bias Configuration 2 Register R/W 0x11 Go 0x0B Display Bias Configuration 3 Register R/W 0x00 Go 0x0C LCM Boost Bias Register R/W 0x28 Go 0x0D VPOS Bias Register R/W 0x1E Go 0x0E VNEG Bias Register R/W 0x1C Go 0x0F Flags Register R 0x00 Go 0x10 Backlight Option 1 Register R/W 0x06 Go 0x11 Backlight Option 2 Register R/W 0x35 Go 0x12 PWM-to-Digital Code Readback LSB Register R 0x00 Go 0x13 PWM-to-Digital Code Readback MSB Register R 0x00 Go 7.6.1 Revision Register (Address = 0x01)[Reset = 0x01] Figure 48. Revision Register 7 DEV_REV[6] R-0 6 DEV_REV[5] R-0 5 DEV_REV[4] R-0 4 DEV_REV[3] R-0 3 DEV_REV[1] R-0 2 DEV_REV[0] R-0 1 DEV_REV[1] R-0 0 DEV_REV[0] R-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 11. Revision Register Field Descriptions Bit Field Type Reset Description 7-5 DEVICE REVISION R 000000 or 000001 DEV_REVISION, A0 = 000000 A1 = 000001 1-0 VENDOR R 01 VENDOR, Texas Instruments = 01 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 37 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com 7.6.2 Backlight Configuration1 Register (Address = 0x02)[Reset = 0x28] Figure 49. Backlight Configuration 1 Register 7 BL_OVP[2] R/W-0 6 BL_OVP[1] R/W-0 5 BL_OVP[0] R/W-1 4 OVP_MODE R/W-0 3 BLED_MAP R/W-1 2 PWM_CONFIG R/W-0 1 PWM_RAMP R/W-0 0 PWM_ENABLE R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 12. Backlight Configuration 1 Register Field Descriptions Bit Field Type Reset Description 7-5 BL_OVP R/W 001 Backlight OVP 000: 17 V 001: 21 V 010: 25 V 011: 29 V 100 to 111 = 29 V 4 OVP_MODE R/W 0 0: OVP is report only 1: OVP causes shutdown 3 BLED_MAP R/W 1 0: Exponential 1: Linear 2 PWM_CONFIG R/W 0 0: Active high 1: Active low 1 PWM_RAMP R/W 0 0: No PWM ramp 1: LED current ramps with changes in duty cycle 0 PWM_ENABLE R/W 0 0: PWM disabled 1: PWM enabled 7.6.3 Backlight Configuration 2 Register (Address = 0x03)[Reset = 0x8D] Figure 50. Backlight Configuration 2 Register 7 BL BOOST FREQUENCY R/W-1 6 LED CURRENT RAMP[3] R/W-0 5 LED CURRENT RAMP[2] R/W-0 4 LED CURRENT RAMP[1] R/W-0 3 LED CURRENT RAMP[0] R/W-1 2 PWM SAMPLE (1) 1 PWM HYST[1] 0 PWM HYST[0] R/W-1 R/W-0 R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset (1) 38 (Note: register 0x10 bit[0] = 1 enables 24-MHz sample mode.) Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 Table 13. Backlight Configuration 2 Register Field Descriptions Bit 7 Field Type BL BOOST FREQUENCY Reset Description 1 Sets the backlight boost switch frequency 0: 500 kHz 1: 1 MHz (Default) 6-3 2 1-0 LED CURRENT RAMP R/W 0001 Controls backlight LED ramping time. The transient time is a constant time that the backlight takes to transition from an existing programmed code to a new programmed code. 0000: 0 µs 0001: 500 µs 0010: 750 µs 0011: 1 ms 0100: 2 ms 0101: 5 ms 0110: 10 ms 0111: 20 ms 1000: 50 ms 1001: 100 ms 1010: 250 ms 1011: 800 ms 1100: 1 s 1101: 2 s 1110: 4 s 1111: 8 s PWM SAMPLE R/W 1 Sets PWM sampling frequency 0: 1 MHz 1: 4 MHz (Default0 Note: register 0x10 bit[0] = 1 enables 24MHz sample mode PWM HYST R/W 01 Sets the minimum change in PWM input duty cycle that results in a change of backlight LED brightness level PWM Sample Frequency = 1 MHz or 4 MHz: 00: 1 bit 01: 2 bits 10: 4 bits 11: 6 bits PWM Sample Frequency = 24 MHz: 00: 0 01: 1 bit 10: 2 bits 11: 3 bits Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 39 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com 7.6.4 Backlight Brightness LSB Register (Address = 0x04)[Reset = 0x07] Figure 51. Backlight Brightness LSB Register 7 6 5 NOT USED 4 3 2 BRT[2] R/W-1 1 BRT[1] R/W-1 0 BRT[0] R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 14. Backlight Brightness LSB Register Field Descriptions Bit Field 7-3 NOT USED 2-0 BRT Type Reset Description R/W 111 11-bit brightness code LSBs 7.6.5 Backlight Brightness MSB Register (Address = 0x05)[Reset = 0xFF] Figure 52. Backlight Brightness MSB Register 7 BRT[10] R/W-1 6 BRT[9] R/W-1 5 BRT[8] R/W-1 4 BRT[7] R/W-1 3 BRT[6] R/W-1 2 BRT[5] R/W-1 1 BRT[4] R/W-1 0 BRT[3] R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 15. Backlight Brightness MSB Register Field Descriptions Bit Field Type Reset Description 7-0 BRT R/W 11111111 11-bit brightness code MSBs 7.6.6 Backlight Auto-Frequency Low Threshold Register (Address = 0x06)[Reset = 0x00] Figure 53. Backlight Auto-Frequency Low Threshold Register 7 AFLT[7] R/W-0 6 AFLT[6] R/W-0 5 AFLT[5] R/W-0 4 AFLT[4] R/W-0 3 AFLT[3] R/W-0 2 AFLT[2] R/W-0 1 AFLT[1] R/W-0 0 AFLT[0] R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 16. Backlight Auto-Frequency Low Threshold Field Descriptions Bit Field Type Reset Description 7-0 AFLT R/W 00000000 Compared against 8 MSB’s of Brightness Code (register 0x05) 7.6.7 Backlight Auto-Frequency High Threshold Register (Address = 0x07)[Reset = 0x00] Figure 54. Backlight Auto-Frequency High Threshold Register 7 AFHT[7] R/W-0 6 AFHT[6] R/W-0 5 AFHT[5] R/W-0 4 AFHT[4] R/W-0 3 AFHT[3] R/W-0 2 AFHT[2] R/W-0 1 AFHT[1] R/W-0 0 AFHT[0] R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17. Backlight Auto-Frequency High Threshold Field Descriptions 40 Bit Field Type Reset Description 7-0 AFHT R/W 00000000 Compared against 8 MSB’s of Brightness Code (register 0x05) Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com 7.6.8 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 Backlight Enable Register (Address = 0x08)[Reset = 0x00] Figure 55. Backlight Enable Register 7 SOFTWARE_ RESET R/W-0 6 5 NOT USED 4 BL_EN 3 LED4_EN 2 LED3_EN 1 LED2_EN 0 LED1_EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18. Backlight Enable Register Field Descriptions Bit 7 6-5 Field Type Reset Description SOFTWARE_RESET R/W 0 0 = No reset 1 = Device reset (automatically returns to 0 after reset) NOT USED 4 BL_EN R/W 0 0 = BL disabled 1 = BL enabled 3 LED4_EN R/W 0 0 = Current sink 4 disabled 1 = Current sink 4 enabled 2 LED3_EN R/W 0 0 = Current sink 3 disabled 1 = Current sink 3 enabled 1 LED2_EN R/W 0 0 = Current sink 2 disabled 1 = Current sink 2 enabled 0 LED1_EN R/W 0 0 = Current sink 1 disabled 1 = Current sink 1 enabled 7.6.9 Bias Configuration 1 Register (Address = 0x09)[Reset = 0x18] Figure 56. Bias Configuration 1 Register 7 LCM_EN[2] R/W-0 6 LCM_EN[1] R/W-0 5 LCM_EN[0] R/W-0 4 VPOS_DISCH R/W-1 3 VNEG_DISCH R/W-1 2 VPOS_EN R/W-0 1 VNEG_EN R/W-0 0 EXT_EN R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 19. Bias Configuration 1 Register Field Descriptions Bit Field Type Reset Description 7:5 LCM_EN R/W 000 000 = Bias supply off (I2C and external) 100 = Normal mode 101 = Auto sequence 110 = Wake1 111 = Wake2 4 VPOS_DISCH R/W 1 0 = No pulldown on VPOS 1 = Pulldown on VPOS when in shutdown 3 VNEG_DISCH R/W 1 0 = No pulldown on VNEG 1 = Pulldown on VNEG when in shutdown 2 VPOS_EN R/W 0 0 = VPOS disabled 1 = VPOS enabled 1 VNEG_EN R/W 0 0 = VNEG disabled 1 = VNEG enabled 0 EXT_EN R/W 0 Activates external enables (LCM_EN1 and LCM_EN2) 0 = External enables are disabled. VPOS and VNEG can only be enabled via bit VPOS_EN and VNEG_EN, respectively. (Default) 1 = External enables are enabled. VPOS and VNEG can only be enabled via pin LCM_EN1 and LCM_EN2, respectively. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 41 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com 7.6.10 Bias Configuration 2 register (Address = 0x0A)[Reset = 0x11] Figure 57. Bias Configuration 2 Register 7 BIAS_SHORT _MODE[1] R/W-0 6 BIAS_SHORT _MODE[0] R/W-0 5 VPOS _RAMP[1] R/W-0 4 VPOS _RAMP[0] R/W-1 3 VNEG _RAMP[3] R/W-0 2 VNEG _RAMP[2] R/W-0 1 VNEG _RAMP[1] R/W-0 0 VNEG _RAMP[0] R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 20. Bias Configuration 2 Register Field Descriptions Bit Field Type Reset Description 7:6 BIAS_SHORT_MODE R/W 00 0X = Flag only 10 = Flag + shutdown VPOS/VNEG 11 = Flag + shutdown VPOS/VNEG/Backlight 5:4 VPOS_RAMP R/W 01 VPOS ramp time, low to high: 00 = 256 µs 01 = 512 µs 10 = 768 µs 11 = 1024 µs 3:0 VNEG_RAMP R/W 0001 VNEG ramp time, high to low: 0000 = 512 µs 0001 = 1024 µs 0010 = 1536 µs 0011 = 2048 µs 0100 = 2560 µs 0101 = 3072 µs 0110 = 3584 µs 0111 = 4096 µs 1000 = 4608 µs 1001 = 5120 µs 1010 = 5632 µs 1011 = 6144 µs 1100 = 6656 µs 1101 = 7168 µs 1110 = 7680 µs 111 = 8192 µs 7.6.11 Bias Configuration 3 Register (Address = 0x0B)[Reset = 0x00] Figure 58. Bias Configuration 3 Register 7 6 5 4 3 VPOS_SC _FILT[1] R/W-0 NOT USED 2 VPOS_SC _FILT[0] R/W-0 1 VNEG_SC _FILT[1] R/W-0 0 VNEG_SC _FILT[0] R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 21. Bias Configuration 3 Register Field Descriptions 42 Bit Field Type Reset Description 7:4 NOT USED 5:4 VPOS_SC_FILT R/W 00 VPOS short circuit filter timer 00 = 2 ms 01 = 1 ms 10 = 500 µs 11 = 100 µs 1:0 VNEG_SC_FILT R/W 00 VNEG short circuit filter timer 00 = 2 ms 01 = 1 ms 10 = 500 µs 11 = 100 µs Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 7.6.12 LCM Boost Bias Register (Address = 0x0C)[Reset = 0x28] Figure 59. LCM Boost Bias Register 7 6 NOT USED 5 LCM_OUT[5] R/W-1 4 LCM_OUT[4] R/W-0 3 LCM_OUT[3] R/W-1 2 LCM_OUT[2] R/W-0 1 LCM_OUT[1] R/W-0 0 LCM_OUT[0] R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22. LCM Boost Bias Register Field Descriptions Bit Field 7-6 NOT USED 5-0 LCM_OUT Type Reset Description R/W 101000 LCM_OUT voltage (50-mV steps): LCM_OUT = 4 V + (Code × 50 mV) 000000 = 4 V 000001 = 4.55V : 101000 = 6 V (Default) : 111111 = 7.15 V 7.6.13 VPOS Bias Register (Address = 0x0D)[Reset = 0x1E] Figure 60. VPOS Bias Register 7 6 NOT USED 5 VPOS[5] R/W-0 4 VPOS[4] R/W-0 3 VPOS[3] R/W-1 2 VPOS[2] R/W-1 1 VPOS[1] R/W-1 0 VPOS[0] R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23. VPOS Bias Register Field Descriptions Bit Field 7-6 NOT USED 5-0 VPOS Type Reset Description R/W 011110 VPOS voltage (50-mV steps): VPOS = 4 V + (Code × 50 mV), 6.5 V max 000000 = 4 V 000001 = 4.05 V : 011110 = 5.5 V (Default) : 110010 = 6.5 V 110011 to 111111 map to 6.5 V 7.6.14 VNEG Bias Register (Address = 0x0E)[Reset = 0x1C] Figure 61. VNEG Bias Register 7 6 NOT USED 5 VNEG[5] R/W-0 4 VNEG[4] R/W-1 3 VNEG[3] R/W-1 2 VNEG[2] R/W-1 1 VNEG[1] R/W-0 0 VNEG[0] R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 43 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com Table 24. VNEG Bias Register Field Descriptions Bit Field 7-6 NOT USED 5-0 VNEG Type Reset Description R/W 011100 VNEG voltage (–50-mV steps): VNEG = -4 V - (Code × 50 mV), -6.5 V min 000000 = –4 V 000000 = –4.05 V : 011100 = -5.4 V (Default) : 110010 = –6.5 V 110011 to 111111 map to –6.5 V 7.6.15 Flags Register (Address = 0x0F)[Reset = 0x00] Figure 62. Flags Register 7 NOT USED 6 TSD R-0 5 LCM_OVP R-0 4 NOT USED 3 VPOS_SHORT R-0 2 VNEG_SHORT R-0 1 BL_OVP R-0 0 BL_OCP R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 25. Flags Register Field Descriptions Bit 44 Field 7 NOT USED 6 TSD 5 LCM_OVP 4 NOT USED 3 VPOS_SHORT 2 VNEG_SHORT 1 BL_OVP 0 BL_OCP Type Reset Description R 0 0 = Normal operation 1 = Thermal shutdown triggered (die temperature > 140°C) R 0 0 = Normal operation 1 = VLCM_OUT > 7.8 V R 0 0 = Normal operation 1 = VPOS output has hit the overcurrent threshold R 0 0 = Normal operation 1 = VVNEG > 0.84 × VVNEG_target R 0 0 = Normal operation 1 = Backlight boost output > OVP threshold R 0 0 = Normal operation 1 = Backlight boost switch current > OCP threshold Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 7.6.16 Option 1 Register (Address = 0x10)[Reset = 0x06] Figure 63. Option 1 Register 7 NOT USED 6 LED4_FB 5 LED3_FB 4 LED2_FB 3 LED1_FB 2 PWM_FILT[1] 1 PWM_ FILT[0] RW-0 RW-0 RW-0 RW-0 RW-0 RW-1 RW-1 0 PWM_24MHZ_ SAMPLE RW-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 26. Option 1 Register Field Descriptions Bit Field Type Reset Description LED4_FEEDBACK_DISABLE R/W 0 0 = Feedback enabled 1 = Feedback disabled 5 LED3_FEEDBACK_DISABLE R/W 0 0 = Feedback enabled 1 = Feedback disabled 4 LED2_FEEDBACK_DISABLE R/W 0 0 = Feedback enabled 1 = Feedback disabled 3 LED1_FEEDBACK_DISABLE R/W 0 0 = Feedback enabled 1 = Feedback disabled PWM_FILT R/W 11 PWM Glitch Filter 00 = No filter 01 = 100 ns 10 = 150 ns 11 = 200 ns PWM_24MHz_SAMPLE R/W 0 0 = Low-frequency options (see 0x03 bit[2]) 1 = 24-MHz PWM sample frequency 7 NOT USED 6 2:1 0 7.6.17 Option 2 Register (Address = 0x11)[Reset = 0x35] Figure 64. Option 2 Register 7 BL_L SELECT[1] RW-0 6 BL_L SELECT[0] RW-0 5 BL_SEL_P[1] 4 BL_SEL_P[0] 3 BL_SEL_I[1] 2 BL_SEL_I[0] RW-1 RW-1 RW-0 RW-1 1 BL_CURRENT _LIMIT[1] RW-0 0 BL_CURRENT _LIMIT[0] RW-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 27. Option 2 Register Field Descriptions Bit Field Type Reset Description 7-6 BACKLIGHT_BOOST_L_SELECT RW 00 00 01 10 11 5-4 BACKLIGHT_SEL_P RW 11 These bits must be written to 11 (default values) to ensure backlight boost stability with recommended external components for all LED configurations 3-2 BACKLIGHT_SEL_I RW 01 These bits must be written to 01 (default values) to ensure backlight boost stability with recommended external components for all LED configurations 1-0 BACKLIGHT_BOOST_CURRENT_ LIMIT RW 01 00 01 10 11 = 4.7 µH = 10 µH = 15 µH = 15 µH = 0.9 A = 1.2 A = 1.5 A = 1.8 A Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 45 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com 7.6.18 PWM-to-Digital Code Readback LSB Register (Address = 0x12)[Reset = 0x00] Figure 65. PWM-to-Digital Code Readback LSB Register 7 PWM_TO _DIG[7] R-0 6 PWM_TO _DIG[6] R-0 5 PWM_TO _DIG[5] R-0 4 PWM_TO _DIG[4] R-0 3 PWM_TO _DIG[3] R-0 2 PWM_TO _DIG[2] R-0 1 PWM_TO _DIG[1] R-0 0 PWM_TO _DIG[0] R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28. PWM-to-Digital Code Readback LSB Register Field Descriptions Bit Field Type Reset Description 7-0 PWM_TO_DIG R 00000000 11-bit PWM-to-digital conversion code LSBs 7.6.19 PWM-to-Digital Code Readback MSB Register (Address = 0x13)[Reset = 0x00] Figure 66. PWM-to-Digital Code Readback MSB Register 7 6 5 RESERVED 4 3 R-0 R-0 R-0 R-0 R-0 2 PWM_TO _DIG[10] R-0 1 PWM_TO _DIG[9] R-0 0 PWM_TO _DIG[8] R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 29. PWM-to-Digital Code Readback MSB Register Field Descriptions 46 Bit Field Type Reset Description 7-3 RESERVED R 00000 Reserved 2-0 PWM_TO_DIG R 000 11-bit PWM-to-digital conversion code MSBs Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LM36274 integrates an LCD backlight driver and LCM positive and negative bias voltages into a single device. The backlight boost converter generates the high voltage required for the LEDs. The device can drive one, two, three, or four LED strings with up to eight white LEDs per string. Positive and negative bias voltages are post-regulated from the LCM bias boost output voltage. The LM36274 offers high performance, is highly configurable, and can support multiple LED configurations as well as independent control of the bias outputs. 8.2 Typical Application D1 L1 10 µH C2 1 µF VBATT IN BL_SW LCM_SW 2.7 V to 5 V BL_SW L2 2.2 µH C1 20 µF BL_OUT LED1 LED2 SCL LED3 SDA LED4 LM36274 PWM C+ µC/µP HWEN CFLY 10 µF C- +5.8 V LCM_EN1 LCM_OUT VPOS C5 10 µF VNEG AGND LCM_GND CP_GND -5.5 V BL_GND C4 10 µF +5.5 V LCM_EN2 C6 10 µF Copyright © 2017, Texas Instruments Incorporated Figure 67. LM36274 Typical Application Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 47 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com Typical Application (continued) 8.2.1 Design Requirements DESIGN PARAMETER EXAMPLE VALUE Input voltage range (VIN) 2.7 V to 4.5 V (single Li-Ion cell battery) LED parallel/series configuration 4 parallel, 6 series LED maximum forward voltage (Vf) 3.35 V Backlight LED current maximum 30 mA / string Backlight boost maximum voltage 29 V Backlight boost SW frequency 1 MHZ, 500 kHz, 250 kHz (auto-frequency option) Backlight boost inductor 10-μH, 1.5-A saturation current Backlight boost Schottky diode NSR05F30NXT5G LCM boost output voltage 5.8 V VPOS output voltage 5.5 V VNEG output voltage –5.5 V LCM boost inductor 2.2-µH, 1.5-A saturation current The number of LED strings, number of series LEDs, and minimum input voltage are needed in order to calculate the peak input current. This information guides the designer to make the appropriate backlight boost inductor selection for the application. The LM36274 backlight boost converter output voltage (VOUT) is calculated as follows: number of series LEDs × Vƒ + 0.31 V. The LM36274 boost converter output current (IOUT) is calculated as follows: number of parallel LED strings × 30 mA. The LM36274 peak input current is calculated using Equation 5. 8.2.2 Detailed Design Procedure 8.2.2.1 Component Selection Table 30 shows examples of external components for the LM36274. Boost converter output capacitors can be replaced with dual output capacitors of lower capacitance as long as the minimum effective capacitance requirement is met. DC bias effect of the ceramic capacitors must be taken into consideration when choosing the output capacitors. This is especially true for the high output-voltage backlight-boost converter. Table 30. Recommended External Components DESIGNATOR DESCRIPTION VALUE EXAMPLE C1, C4, C5, C6, CFLY Ceramic capacitor 10 µF, 10 V C1608X5R0J106M C2 Ceramic capacitor 1 µF, 35 V C2012X7R1H105K125AB L1 Inductor 4.7 µH, 1.94 A VLF504012MT-4R7M L1 Inductor 10 µH, 1.44 A VLF504015MT-100M L1 Inductor 15 µH, 1.25 A VLF504015MT-150M L2 Inductor 2.2 µH, 1.5 A DFE201612P-2R2M D1 Schottky diode 30 V, 500 mA NSR053F30NXT5G 8.2.2.1.1 Inductor Selection The LM36274 backlight boost requires a typical inductance in the range of 4.7 µH to 15 µH. To ensure boost stability the Backlight Boost L Select bit (register 0x11 bits [7:6]) must be selected depending on the value of inductance chosen. Use the 4.7-µH setting with a 6.8-µH inductor. The LCM boost is internally compensated for a typical inductance in the range of 1 µH to 2.2 µH. If the LCM boost output setting is greater than 6.3 V a 2.2-µH inductor must be used. 48 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 There are two main considerations when choosing an inductor: the inductor RMS current rating must be greater than the RMS inductor current for the application, and the inductor saturation current must be greater than the peak inductor current for the application. Different saturation current rating specifications are followed by different manufacturers so attention must be given to details. Saturation current ratings are typically specified at 25°C. However, ratings at the maximum ambient temperature of the application should be requested from the manufacturer. The saturation current must be greater than the sum of the maximum load current and the worstcase average-to-peak inductor current. When the boost device is boosting (VOUT > VIN) the inductor is one of the largest area of efficiency loss in the circuit. Therefore, choosing an inductor with the lowest possible series resistance is important, especially for an LCM bias converter. For proper inductor operation and circuit performance, ensure that the inductor saturation and the peak current limit setting of the LM36274 are greater than IPEAK in Equation 5: IPEAK ILOAD VOUT VIN u (VOUT - VIN u K) u + 'ILOAD where 'ILOAD = K VIN 2 u fSW u L u VOUT (5) See detailed information in Understanding Boost Power Stages in Switch Mode Power Supplies http://focus.ti.com/lit/an/slva061/slva061.pdf. Power Stage Designer™ Tools can be used for the boost calculation: http://www.ti.com/tool/powerstage-designer. Also, the peak current calculated in Equation 5 is different from the peak inductor current setting (ISAT). The NMOS switch current limit setting (ICL_MIN) must be greater than IPEAK from Equation 5. 8.2.2.1.2 Boost Output Capacitor Selection At least an 1-μF capacitor is recommended for the backlight boost converter output capacitor. A high-quality ceramic type X5R or X7R is recommended. Voltage rating must be greater than the maximum output voltage that is used. The effective output capacitance must always remain higher than 0.4 μF for stable operation. Table 31 lists possible backlight output capacitors that can be used with the LM36274. Figure 68 shows the DC bias of the four TDK capacitors. The useful voltage range is determined from the effective output voltage range for a given capacitor as determined by Equation 6: DC Voltage Derating t 0.4 PF (1 Tol) u (1 Temp_co) (6) Table 31. Recommended Backlight Output Capacitors NOMINAL CAPACITANCE (µF) TOLERANCE (%) TEMPERATURE COEFFICIENT (%) RECOMMENDED MAX OUTPUT VOLTAGE (FOR SINGLE CAPACITOR) 50 1 ±10 ±15 22 50 2.2 ±10 ±15 24 0603 35 2.2 ±10 ±15 12 0603 50 1 ±10 ±15 15 PART NUMBER MANUFACTURER CASE SIZE VOLTAGE RATING (V) C2012X5R1H105K085AB TDK 0805 C2012X5R1H225K085AB TDK 0805 C1608X5R1V225K080AC TDK C1608X5R1H105K080AB TDK For example, with a 10% tolerance, and a 15% temperature coefficient, the DC voltage derating must be ≥ 0.4 / (0.9 × 0.85) = 0.523 µF. For the C1608X5R1H225K080AB (0603, 50-V) device, the useful voltage range occurs up to the point where the DC bias derating falls below 0.523 µF, or around 12 V. For configurations where VOUT is > 15 V, two of these capacitors can be paralleled, or a larger capacitor such as the C2012X5R1H105K085AB must be used. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 49 LM36274 Capacitance (µF) SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 C2012X5R1H105K085AB C2012X5R1H225K085AB C1608X5R1V225K080AC C1608X5R1H105K080AB 0 2 4 6 8 10 12 14 16 18 20 22 24 26 DC Bias 28 C006 Figure 68. DC Bias Derating for 0805 Case Size and 0603 Case Size 35-V and 50-V Ceramic Capacitors For the LCM bias boost output a high-quality 10-μF ceramic type X5R or X7R capacitor is recommended. Voltage rating must be greater than the maximum output voltage that is used. 8.2.2.1.3 Input Capacitor Selection Choosing the correct size and type of input capacitor helps minimize the voltage ripple caused by the switching of the LM36274 boost converters and reduce noise on the input pin that can feed through and disrupt internal analog signals. For the LM36274 a 10-μF ceramic input capacitor works well. It is important to place the input capacitor as close to the input (IN) pin as possible. This reduces the series resistance and inductance that can inject noise into the device due to the input switching currents. 50 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 8.2.3 Application Curves 8.2.3.1 Backlight Curves Ambient temperature is 25°C and VIN is 3.7 V unless otherwise noted. Backlight system efficiency is defined as PLED / PIN, where PLED is actual power consumed in backlight LEDs. External components are from Table 30. 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) 8.2.3.1.1 Two LED Strings 75 70 65 60 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 75 TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 5 10 15 20 25 30 35 Load (mA) 2p8s 40 45 50 55 60 0 ƒ = 1 MHz L = 10 µH 15 20 95 95 90 90 85 85 80 80 75 70 65 60 40 45 50 55 60 D202 ƒ = 1 MHz L = 10 µH 75 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 25 30 35 Load (mA) Figure 70. Backlight System Efficiency Efficiency (%) Efficiency (%) 10 2p8s Figure 69. Backlight Boost Efficiency TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 5 10 15 20 25 30 35 Load (mA) 2p8s 40 45 50 55 0 60 5 10 15 20 D203 ƒ = 500 kHz L = 10 µH 25 30 35 Load (mA) 2p8s Figure 71. Backlight Boost Efficiency 40 95 95 90 90 85 85 80 80 75 70 65 TA = -40qC TA = 25qC TA = 85qC 55 2 4 2p8s 6 8 10 12 Load (mA) 14 16 18 60 D204 75 70 65 TA = -40qC TA = 25qC TA = 85qC 50 20 0 2 4 D205 ƒ = 250 kHz 55 L = 10 µH 55 50 0 50 ƒ = 500 kHz 60 60 45 Figure 72. Backlight System Efficiency Efficiency (%) Efficiency (%) 5 D201 L = 10 µH Figure 73. Backlight Boost Efficiency 2p8s 6 8 10 12 Load (mA) ƒ = 250 kHz 14 16 18 20 D206 L = 10 µH Figure 74. Backlight System Efficiency Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 51 LM36274 www.ti.com 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 75 70 65 60 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 75 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 5 10 15 20 2p8s 25 30 35 Load (mA) 40 45 50 55 60 0 5 ƒ = 1 MHz L = 10 µH 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) 20 75 70 65 40 45 50 55 60 D208 ƒ = 1 MHz L = 10 µH 75 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 25 30 35 Load (mA) Figure 76. Backlight System Efficiency 95 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 5 10 15 20 2p8s 25 30 35 Load (mA) 40 45 50 55 60 0 5 10 15 20 D209 ƒ = 500 kHz L = 10 µH 2p8s Figure 77. Backlight Boost Efficiency 95 95 90 90 85 85 80 80 75 70 65 60 40 45 50 55 60 D210 ƒ = 500 kHz L = 10 µH 75 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 25 30 35 Load (mA) Figure 78. Backlight System Efficiency Efficiency (%) Efficiency (%) 15 2p8s Figure 75. Backlight Boost Efficiency TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 5 10 2p7s 15 20 25 30 35 Load (mA) 40 45 50 55 60 0 5 10 15 D211 ƒ = 1 MHz L = 10 µH Figure 79. Backlight Boost Efficiency 52 10 D207 Submit Documentation Feedback 2p7s 20 25 30 35 Load (mA) 40 ƒ = 1 MHz 45 50 55 60 D212 L = 10 µH Figure 80. Backlight System Efficiency Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) www.ti.com 75 70 65 75 70 65 60 60 TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 5 10 15 20 25 30 35 Load (mA) 2p7s 40 45 50 55 TA = -40qC TA = 25qC TA = 85qC 55 0 60 5 ƒ = 500 kHz 20 95 95 90 90 85 85 80 80 75 70 65 60 40 45 50 55 60 D214 ƒ = 500 kHz L = 10 µH 75 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 25 30 35 Load (mA) Figure 82. Backlight System Efficiency Efficiency (%) Efficiency (%) 15 2p7s L = 10 µH Figure 81. Backlight Boost Efficiency TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 2 4 6 8 2p7s 10 12 Load (mA) 14 16 18 20 0 2 4 6 8 D215 ƒ = 250 kHz L = 10 µH 2p7s Figure 83. Backlight Boost Efficiency 95 95 90 90 85 85 80 80 75 70 65 60 14 16 18 20 D216 ƒ = 250 kHz L = 10 µH 75 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 10 12 Load (mA) Figure 84. Backlight System Efficiency Efficiency (%) Efficiency (%) 10 D213 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 5 10 2p7s 15 20 25 30 35 Load (mA) 40 45 50 55 60 0 5 10 D217 ƒ = 1 MHz L = 10 µH Figure 85. Backlight Boost Efficiency 2p7s 15 20 25 30 35 Load (mA) 40 ƒ = 1 MHz 45 50 55 D218 L = 10 µH Figure 86. Backlight System Efficiency Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 60 53 LM36274 www.ti.com 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 75 70 65 60 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 75 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 5 10 15 20 2p7s 25 30 35 Load (mA) 40 45 50 55 60 0 5 ƒ = 500 kHz L = 10 µH 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) 20 75 70 65 40 45 50 55 60 D220 ƒ = 500 kHz L = 10 µH 75 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 25 30 35 Load (mA) Figure 88. Backlight System Efficiency 95 60 TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 5 10 15 20 2p6s 25 30 35 Load (mA) 40 45 50 55 60 0 5 10 15 20 D221 ƒ = 1 MHz L = 10 µH 2p6s Figure 89. Backlight Boost Efficiency 25 30 35 Load (mA) 40 45 95 95 90 90 85 85 80 80 75 70 65 TA = -40qC TA = 25qC TA = 85qC 55 5 10 2p6s 15 20 25 30 35 Load (mA) 40 45 50 55 75 70 65 TA = -40qC TA = 25qC TA = 85qC 50 60 0 5 10 15 D223 ƒ = 500 kHz 60 L = 10 µH 55 50 0 55 D222 ƒ = 1 MHz 60 60 50 Figure 90. Backlight System Efficiency Efficiency (%) Efficiency (%) 15 2p7s Figure 87. Backlight Boost Efficiency L = 10 µH Figure 91. Backlight Boost Efficiency 54 10 D219 Submit Documentation Feedback 2p6s 20 25 30 35 Load (mA) 40 ƒ = 500 kHz 45 50 55 60 D224 L = 10 µH Figure 92. Backlight System Efficiency Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) www.ti.com 75 70 65 60 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 75 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 2 4 6 8 2p6s 10 12 Load (mA) 14 16 18 20 0 2 ƒ = 250 kHz L = 10 µH 8 95 95 90 90 85 85 80 80 75 70 65 60 14 16 18 20 D226 ƒ = 250 kHz L = 10 µH 75 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 10 12 Load (mA) Figure 94. Backlight System Efficiency Efficiency (%) Efficiency (%) 6 2p6s Figure 93. Backlight Boost Efficiency VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 5 10 15 20 2p6s 25 30 35 Load (mA) 40 45 50 55 60 0 5 10 15 20 D227 ƒ = 1 MHz L = 10 µH 2p6s Figure 95. Backlight Boost Efficiency 95 95 90 90 85 85 80 80 75 70 65 60 40 45 50 55 60 D228 ƒ = 1 MHz L = 10 µH 75 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 25 30 35 Load (mA) Figure 96. Backlight System Efficiency Efficiency (%) Efficiency (%) 4 D225 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 5 10 2p6s 15 20 25 30 35 Load (mA) 40 45 50 55 60 0 5 10 D229 ƒ = 500 kHz L = 10 µH Figure 97. Backlight Boost Efficiency 2p6s 15 20 25 30 35 Load (mA) 40 ƒ = 500 kHz 45 50 55 D230 L = 10 µH Figure 98. Backlight System Efficiency Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 60 55 LM36274 www.ti.com 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 75 70 65 60 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 75 TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 5 10 15 20 2p8s 25 30 35 Load (mA) 40 45 50 55 60 0 5 ƒ = 1 MHz L = 4.7 µH 90 85 85 80 80 75 75 Efficiency (%) Efficiency (%) 20 70 65 60 40 45 50 55 60 D232 ƒ = 1 MHz L = 4.7 µH 70 65 60 55 TA = -40qC TA = 25qC TA = 85qC 50 25 30 35 Load (mA) Figure 100. Backlight System Efficiency 90 55 TA = -40qC TA = 25qC TA = 85qC 50 45 45 0 5 10 15 20 2p8s 25 30 35 Load (mA) 40 45 50 55 0 60 5 10 15 20 D233 ƒ = 500 kHz L = 4.7 µH 2p8s Figure 101. Backlight Boost Efficiency 90 90 85 85 80 80 75 75 70 65 60 55 40 45 50 55 60 D234 ƒ = 500 kHz L = 4.7 µH 70 65 60 55 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 50 25 30 35 Load (mA) Figure 102. Backlight System Efficiency Efficiency (%) Efficiency (%) 15 2p8s Figure 99. Backlight Boost Efficiency VIN = 2.7 V VIN = 3.7 V VIN = 5 V 50 45 45 0 5 10 2p8s 15 20 25 30 35 Load (mA) 40 ƒ = 1 MHz 45 50 55 60 0 5 10 15 D235 L = 4.7 µH Figure 103. Backlight Boost Efficiency 56 10 D231 Submit Documentation Feedback 2p8s 20 25 30 35 Load (mA) 40 ƒ = 1 MHz 45 50 55 60 D236 L = 4.7 µH Figure 104. Backlight System Efficiency Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 90 90 85 85 80 80 75 75 Efficiency (%) Efficiency (%) www.ti.com 70 65 60 55 65 60 55 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 50 70 TA = -40qC TA = 25qC TA = 85qC 50 45 45 0 5 10 15 20 2p8s 25 30 35 Load (mA) 40 45 50 55 60 0 5 ƒ = 500 kHz L = 4.7 µH 20 90 90 85 85 80 80 75 75 70 65 60 55 40 45 50 55 60 D238 ƒ = 500 kHz L = 4.7 µH 70 65 60 55 TA = -40qC TA = 25qC TA = 85qC 50 25 30 35 Load (mA) Figure 106. Backlight System Efficiency Efficiency (%) Efficiency (%) 15 2p8s Figure 105. Backlight Boost Efficiency TA = -40qC TA = 25qC TA = 85qC 50 45 45 0 5 10 15 20 2p6s 25 30 35 Load (mA) 40 45 50 55 0 60 5 10 15 20 D239 ƒ = 1 MHz L = 4.7 µH 2p6s Figure 107. Backlight Boost Efficiency 90 90 85 85 80 80 75 75 70 65 60 55 40 45 50 55 60 D240 ƒ = 1 MHz L = 4.7 µH 70 65 60 55 TA = -40qC TA = 25qC TA = 85qC 50 25 30 35 Load (mA) Figure 108. Backlight System Efficiency Efficiency (%) Efficiency (%) 10 D237 TA = -40qC TA = 25qC TA = 85qC 50 45 45 0 5 10 2p6s 15 20 25 30 35 Load (mA) 40 45 ƒ = 500 kHz 50 55 60 0 5 10 D241 L = 4.7 µH Figure 109. Backlight Boost Efficiency 2p6s 15 20 25 30 35 Load (mA) 40 ƒ = 500 kHz 45 50 55 D242 L = 4.7 µH Figure 110. Backlight System Efficiency Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 60 57 LM36274 www.ti.com 90 90 85 85 80 80 75 75 Efficiency (%) Efficiency (%) SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 70 65 60 70 65 60 55 55 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 50 45 45 0 5 10 15 20 2p6s 25 30 35 Load (mA) 40 45 50 55 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 50 0 60 5 ƒ = 1 MHz 20 90 90 85 85 80 80 75 75 70 65 60 55 40 45 50 55 60 D244 ƒ = 1 MHz L = 4.7 µH 70 65 60 55 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 50 25 30 35 Load (mA) Figure 112. Backlight System Efficiency Efficiency (%) Efficiency (%) 15 2p6s L = 4.7 µH Figure 111. Backlight Boost Efficiency VIN = 2.7 V VIN = 3.7 V VIN = 5 V 50 45 45 0 5 10 2p6s 15 20 25 30 35 Load (mA) 40 ƒ = 500 kHz 45 50 55 60 0 5 10 15 D245 L = 4.7 µH Figure 113. Backlight Boost Efficiency 58 10 D243 Submit Documentation Feedback 2p6s 20 25 30 35 Load (mA) 40 ƒ = 500 kHz 45 50 55 60 D246 L = 4.7 µH Figure 114. Backlight System Efficiency Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) 8.2.3.1.2 Three LED Strings 75 70 65 60 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 75 TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 10 20 30 3p8s 40 50 Load (mA) 60 70 80 90 0 10 ƒ = 1 MHz L = 10 µH 95 95 90 90 85 85 80 80 75 70 65 60 60 70 80 90 D302 ƒ = 1 MHz L = 10 µH 75 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 40 50 Load (mA) Figure 116. Backlight System Efficiency Efficiency (%) Efficiency (%) 30 3p8s Figure 115. Backlight Boost Efficiency TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 10 20 30 3p8s 40 50 Load (mA) 60 70 80 90 0 10 20 30 D303 ƒ = 500 kHz L = 10 µH 3p8s Figure 117. Backlight Boost Efficiency 90 90 85 85 80 80 75 75 70 65 60 55 60 70 80 90 D304 ƒ = 500 kHz L = 10 µH 70 65 60 55 TA = -40qC TA = 25qC TA = 85qC 50 40 50 Load (mA) Figure 118. Backlight System Efficiency Efficiency (%) Efficiency (%) 20 D301 TA = -40qC TA = 25qC TA = 85qC 50 45 45 0 3 6 3p8s 9 12 15 18 Load (mA) 21 ƒ = 250 kHz 24 27 30 0 3 6 D305 L = 10 µH Figure 119. Backlight Boost Efficiency 3p8s 9 12 15 18 Load (mA) ƒ = 250 kHz 21 24 27 D306 L = 10 µH Figure 120. Backlight System Efficiency Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 30 59 LM36274 www.ti.com 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 75 70 65 60 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 75 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 10 20 30 3p8s 40 50 Load (mA) 60 70 80 0 90 ƒ = 1 MHz L = 10 µH 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) 30 75 70 65 60 70 80 90 D308 ƒ = 1 MHz L = 10 µH 75 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 40 50 Load (mA) Figure 122. Backlight System Efficiency 95 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 10 20 30 3p8s 40 50 Load (mA) 60 70 80 90 0 10 20 30 D309 ƒ = 500 kHz L = 10 µH 3p8s Figure 123. Backlight Boost Efficiency 95 95 90 90 85 85 80 80 75 70 65 60 60 70 80 90 D310 ƒ = 500 kHz L = 10 µH 75 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 40 50 Load (mA) Figure 124. Backlight System Efficiency Efficiency (%) Efficiency (%) 20 3p8s Figure 121. Backlight Boost Efficiency TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 10 20 3p6s 30 40 50 Load (mA) 60 ƒ = 1 MHz 70 80 90 0 10 20 D311 L = 10 µH Figure 125. Backlight Boost Efficiency 60 10 D307 Submit Documentation Feedback 3p6s 30 40 50 Load (mA) 60 ƒ = 1 MHz 70 80 90 D312 L = 10 µH Figure 126. Backlight System Efficiency Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) www.ti.com 75 70 65 60 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 75 TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 10 20 30 3p6s 40 50 Load (mA) 60 70 80 90 0 10 ƒ = 500 kHz L = 10 µH 95 95 90 90 85 85 80 80 75 70 65 60 60 70 80 90 D314 ƒ = 500 kHz L = 10 µH 75 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 40 50 Load (mA) Figure 128. Backlight System Efficiency Efficiency (%) Efficiency (%) 30 3p6s Figure 127. Backlight Boost Efficiency TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 3 6 9 12 15 18 Load (mA) 3p6s 21 24 27 30 0 3 6 9 12 15 18 Load (mA) D315 ƒ = 250 kHz L = 10 µH 3p6s Figure 129. Backlight Boost Efficiency 95 95 90 90 85 85 80 80 75 70 65 60 24 27 30 D316 ƒ = 250 kHz L = 10 µH 75 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 21 Figure 130. Backlight System Efficiency Efficiency (%) Efficiency (%) 20 D313 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 10 20 3p6s 30 40 50 Load (mA) 60 ƒ = 1 MHz 70 80 90 0 10 20 D317 L = 10 µH Figure 131. Backlight Boost Efficiency 3p6s 30 40 50 Load (mA) 60 ƒ = 1 MHz 70 80 D318 L = 10 µH Figure 132. Backlight System Efficiency Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 90 61 LM36274 www.ti.com 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 75 70 65 60 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 75 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 10 20 30 3p6s 40 50 Load (mA) 60 70 80 90 0 ƒ = 500 kHz L = 10 µH 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) 30 75 70 65 60 70 80 90 D320 ƒ = 500 kHz L = 10 µH 75 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 40 50 Load (mA) Figure 134. Backlight System Efficiency 95 60 TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 10 20 30 3p8s 40 50 Load (mA) 60 70 80 0 90 10 20 30 D321 ƒ = 1 MHz L = 15 µH 3p8s Figure 135. Backlight Boost Efficiency 95 95 90 90 85 85 80 80 75 70 65 60 60 70 80 90 D322 ƒ = 1 MHz L = 15 µH 75 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 40 50 Load (mA) Figure 136. Backlight System Efficiency Efficiency (%) Efficiency (%) 20 3p6s Figure 133. Backlight Boost Efficiency TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 10 20 3p8s 30 40 50 Load (mA) 60 ƒ = 500 kHz 70 80 90 0 10 20 D323 L = 15 µH Figure 137. Backlight Boost Efficiency 62 10 D319 Submit Documentation Feedback 3p8s 30 40 50 Load (mA) 60 ƒ = 500 kHz 70 80 90 D324 L = 15 µH Figure 138. Backlight System Efficiency Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) www.ti.com 75 70 65 60 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 75 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 10 20 30 3p8s 40 50 Load (mA) 60 70 80 90 0 ƒ = 1 MHz L = 15 µH 30 95 95 90 90 85 85 80 80 75 70 65 60 60 70 80 90 D326 ƒ = 1 MHz L = 15 µH 75 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 40 50 Load (mA) Figure 140. Backlight System Efficiency Efficiency (%) Efficiency (%) 20 3p8s Figure 139. Backlight Boost Efficiency VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 10 20 30 3p8s 40 50 Load (mA) 60 70 80 90 0 10 20 30 D327 ƒ = 500 kHz L = 15 µH 3p8s Figure 141. Backlight Boost Efficiency 90 90 85 85 80 80 75 75 70 65 60 55 60 70 80 90 D328 ƒ = 500 kHz L = 15 µH 70 65 60 55 TA = -40qC TA = 25qC TA = 85qC 50 40 50 Load (mA) Figure 142. Backlight System Efficiency Efficiency (%) Efficiency (%) 10 D325 TA = -40qC TA = 25qC TA = 85qC 50 45 45 0 10 20 3p8s 30 40 50 Load (mA) 60 ƒ = 1 MHz 70 80 90 0 10 20 D329 L = 4.7 µH Figure 143. Backlight Boost Efficiency 3p8s 30 40 50 Load (mA) 60 ƒ = 1 MHz 70 80 D330 L = 4.7 µH Figure 144. Backlight System Efficiency Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 90 63 LM36274 www.ti.com 90 90 85 85 80 80 75 75 Efficiency (%) Efficiency (%) SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 70 65 60 55 65 60 55 TA = -40qC TA = 25qC TA = 85qC 50 70 TA = -40qC TA = 25qC TA = 85qC 50 45 45 0 10 20 30 3p8s 40 50 Load (mA) 60 70 80 0 90 ƒ = 500 kHz L = 4.7 µH 90 85 85 80 80 75 75 Efficiency (%) Efficiency (%) 30 70 65 60 60 70 80 90 D332 ƒ = 500 kHz L = 4.7 µH 70 65 60 55 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 50 40 50 Load (mA) Figure 146. Backlight System Efficiency 90 55 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 50 45 45 0 10 20 30 3p8s 40 50 Load (mA) 60 70 80 90 0 10 20 30 D333 ƒ = 1 MHz L = 4.7 µH 3p8s Figure 147. Backlight Boost Efficiency 90 90 85 85 80 80 75 75 70 65 60 55 60 70 80 90 D334 ƒ = 1 MHz L = 4.7 µH 70 65 60 55 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 50 40 50 Load (mA) Figure 148. Backlight System Efficiency Efficiency (%) Efficiency (%) 20 3p8s Figure 145. Backlight Boost Efficiency VIN = 2.7 V VIN = 3.7 V VIN = 5 V 50 45 45 0 10 20 3p8s 30 40 50 Load (mA) 60 ƒ = 500 kHz 70 80 90 0 10 20 D335 L = 4.7 µH Figure 149. Backlight Boost Efficiency 64 10 D331 Submit Documentation Feedback 3p8s 30 40 50 Load (mA) 60 ƒ = 500 kHz 70 80 90 D336 L = 4.7 µH Figure 150. Backlight System Efficiency Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) 8.2.3.1.3 Four LED Strings 75 70 65 60 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 75 TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 10 20 30 40 4p6s 50 60 70 Load (mA) 80 0 90 100 110 120 10 ƒ = 1 MHz L = 10 µH 40 50 60 70 Load (mA) 95 95 90 90 85 85 80 80 75 70 65 60 90 100 110 120 D402 ƒ = 1 MHz L = 10 µH 75 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 80 Figure 152. Backlight System Efficiency Efficiency (%) Efficiency (%) 30 4p6s Figure 151. Backlight Boost Efficiency TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 10 20 30 40 50 60 70 Load (mA) 4p6s 80 90 100 110 120 0 10 20 30 40 50 60 70 Load (mA) D403 ƒ = 500 kHz L = 10 µH 4p6s Figure 153. Backlight Boost Efficiency 90 90 85 85 80 80 75 75 70 65 60 55 90 100 110 120 D404 ƒ = 500 kHz L = 10 µH 70 65 60 55 TA = -40qC TA = 25qC TA = 85qC 50 80 Figure 154. Backlight System Efficiency Efficiency (%) Efficiency (%) 20 D401 TA = -40qC TA = 25qC TA = 85qC 50 45 45 0 5 4p6s 10 15 20 25 Load (mA) 30 ƒ = 250 kHz 35 40 0 5 D405 L = 10 µH Figure 155. Backlight Boost Efficiency 4p6s 10 15 20 25 Load (mA) ƒ = 250 kHz 30 35 40 D406 L = 10 µH Figure 156. Backlight System Efficiency Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 65 LM36274 www.ti.com 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 75 70 65 60 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 75 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 10 20 30 40 4p6s 50 60 70 Load (mA) 80 90 100 110 120 0 10 ƒ = 1 MHz L = 10 µH 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) 40 75 70 65 80 90 100 110 120 D408 ƒ = 1 MHz L = 10 µH 75 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 60 70 Load (mA) Figure 158. Backlight System Efficiency 95 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 10 20 30 40 4p6s 50 60 70 Load (mA) 80 90 100 110 120 0 10 20 30 40 D409 ƒ = 500 kHz L = 10 µH 4p6s Figure 159. Backlight Boost Efficiency 50 60 70 Load (mA) 80 95 95 90 90 85 85 80 80 75 70 65 D410 ƒ = 500 kHz TA = -40qC TA = 25qC TA = 85qC 55 70 65 10 20 4p4s 30 40 50 60 70 Load (mA) 80 ƒ = 1 MHz TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 L = 10 µH 75 60 60 90 100 110 120 Figure 160. Backlight System Efficiency Efficiency (%) Efficiency (%) 30 4p6s Figure 157. Backlight Boost Efficiency 90 100 110 120 0 10 20 30 D411 L = 10 µH Figure 161. Backlight Boost Efficiency 66 20 D407 Submit Documentation Feedback 4p4s 40 50 60 70 Load (mA) 80 ƒ = 1 MHz 90 100 110 120 D412 L = 10 µH Figure 162. Backlight System Efficiency Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) www.ti.com 75 70 65 60 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 75 TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 10 20 30 40 50 60 70 Load (mA) 4p4s 80 90 100 110 120 0 10 ƒ = 500 kHz L = 10 µH 40 95 95 90 90 85 85 80 80 75 70 65 60 80 90 100 110 120 D414 ƒ = 500 kHz L = 10 µH 75 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 50 60 70 Load (mA) Figure 164. Backlight System Efficiency Efficiency (%) Efficiency (%) 30 4p4s Figure 163. Backlight Boost Efficiency TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 5 10 15 4p4s 20 25 Load (mA) 30 35 40 0 5 10 15 D415 ƒ = 250 kHz L = 10 µH 4p4s Figure 165. Backlight Boost Efficiency 95 95 90 90 85 85 80 80 75 70 65 60 ƒ = 250 kHz 30 35 40 D416 L = 10 µH 75 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 20 25 Load (mA) Figure 166. Backlight System Efficiency Efficiency (%) Efficiency (%) 20 D413 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 10 20 4p4s 30 40 50 60 70 Load (mA) 80 90 100 110 120 ƒ = 1 MHz 0 10 20 D417 L = 10 µH Figure 167. Backlight Boost Efficiency 4p4s 30 40 50 60 70 Load (mA) 80 ƒ = 1 MHz 90 100 110 120 D418 L = 10 µH Figure 168. Backlight System Efficiency Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 67 LM36274 www.ti.com 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 75 70 65 60 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 75 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 10 20 30 40 4p4s 50 60 70 Load (mA) 80 0 90 100 110 120 10 ƒ = 500 kHz L = 10 µH 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) 40 75 70 65 80 90 100 110 120 D420 ƒ = 500 kHz L = 10 µH 75 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 50 60 70 Load (mA) Figure 170. Backlight System Efficiency 95 60 TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 10 20 30 40 4p6s 50 60 70 Load (mA) 80 90 100 110 120 0 10 20 30 40 D421 ƒ = 1 MHz L = 15 µH 4p6s Figure 171. Backlight Boost Efficiency 50 60 70 Load (mA) 80 95 95 90 90 85 85 80 80 75 70 65 D422 ƒ = 1 MHz TA = -40qC TA = 25qC TA = 85qC 55 70 65 10 20 4p6s 30 40 50 60 70 Load (mA) 80 ƒ = 500 kHz TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 L = 15 µH 75 60 60 90 100 110 120 Figure 172. Backlight System Efficiency Efficiency (%) Efficiency (%) 30 4p4s Figure 169. Backlight Boost Efficiency 90 100 110 120 0 10 20 30 D423 L = 15 µH Figure 173. Backlight Boost Efficiency 68 20 D419 Submit Documentation Feedback 4p6s 40 50 60 70 Load (mA) 80 ƒ = 500 kHz 90 100 110 120 D424 L = 15 µH Figure 174. Backlight System Efficiency Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) www.ti.com 75 70 65 60 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 75 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 10 20 30 40 4p6s 50 60 70 Load (mA) 80 90 100 110 120 0 10 ƒ = 1 MHz L = 15 µH 40 95 95 90 90 85 85 80 80 75 70 65 60 80 90 100 110 120 D426 ƒ = 1 MHz L = 15 µH 75 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 60 70 Load (mA) Figure 176. Backlight System Efficiency Efficiency (%) Efficiency (%) 30 4p6s Figure 175. Backlight Boost Efficiency VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 50 50 0 10 20 30 40 4p6s 50 60 70 Load (mA) 80 90 100 110 120 0 10 20 30 40 D427 ƒ = 500 kHz L = 15 µH 4p6s Figure 177. Backlight Boost Efficiency 95 95 90 90 85 85 80 80 75 70 65 60 80 90 100 110 120 D428 ƒ = 500 kHz L = 15 µH 75 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 50 60 70 Load (mA) Figure 178. Backlight System Efficiency Efficiency (%) Efficiency (%) 20 D425 TA = -40qC TA = 25qC TA = 85qC 55 50 50 0 10 20 4p6s 30 40 50 60 70 Load (mA) 80 90 100 110 120 ƒ = 1 MHz 0 10 20 D429 L = 4.7 µH Figure 179. Backlight Boost Efficiency 4p6s 30 40 50 60 70 Load (mA) 80 ƒ = 1 MHz 90 100 110 120 D430 L = 4.7 µH Figure 180. Backlight System Efficiency Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 69 LM36274 www.ti.com 90 90 85 85 80 80 75 75 Efficiency (%) Efficiency (%) SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 70 65 60 55 65 60 55 TA = -40qC TA = 25qC TA = 85qC 50 70 TA = -40qC TA = 25qC TA = 85qC 50 45 45 0 10 20 30 40 4p6s 50 60 70 Load (mA) 80 90 100 110 120 0 10 ƒ = 500 kHz L = 4.7 µH 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) 40 50 60 70 Load (mA) 80 90 100 110 120 D432 ƒ = 500 kHz L = 4.7 µH Figure 182. Backlight System Efficiency 75 70 65 60 55 75 70 65 60 55 50 50 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 45 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 45 40 40 0 10 20 30 40 4p6s 50 60 70 Load (mA) 80 90 100 110 120 0 10 20 30 40 D433 ƒ = 1 MHz L = 4.7 µH 4p6s Figure 183. Backlight Boost Efficiency 50 60 70 Load (mA) 80 90 100 110 120 D434 ƒ = 1 MHz L = 4.7 µH Figure 184. Backlight System Efficiency 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) 30 4p6s Figure 181. Backlight Boost Efficiency 75 70 65 60 55 75 70 65 60 55 50 50 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 45 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 45 40 40 0 10 20 4p6s 30 40 50 60 70 Load (mA) 80 ƒ = 500 kHz 90 100 110 120 0 10 20 30 D435 L = 4.7 µH Figure 185. Backlight Boost Efficiency 70 20 D431 Submit Documentation Feedback 4p6s 40 50 60 70 Load (mA) 80 ƒ = 500 kHz 90 100 110 120 D436 L = 4.7 µH Figure 186. Backlight System Efficiency Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 8.2.3.2 LCM Bias Curves 100 100 95 95 90 90 Efficiency (%) Efficiency (%) Ambient temperature is 25°C and VIN is 3.7 V unless otherwise noted. VPOS, VNEG and VPOS/VNEG efficiency is defined as POUT / PIN, where POUT is actual power consumed in VPOS, VNEG and (VPOS + VNEG) outputs, respectively. External components are from Table 30. 85 80 75 85 80 75 70 70 TA = -40qC TA = 25qC TA = 85qC 65 TA = -40qC TA = 25qC TA = 85qC 65 60 60 0 20 40 60 80 100 Load (mA) 120 140 0 160 20 VLCM_OUT = 4.3 V 80 100 Load (mA) 120 140 160 D102 Figure 188. LCM Boost Efficiency 100 100 95 95 90 90 Efficiency (%) Efficiency (%) 60 VLCM_OUT = 5.3 V Figure 187. LCM Boost Efficiency 85 80 75 85 80 75 70 70 TA = -40qC TA = 25qC TA = 85qC 65 0 20 40 60 80 100 Load (mA) 120 140 VIN = 2.7 V VIN = 3.7 V VIN = 4.5 V 65 60 60 0 160 20 40 60 D103 80 100 Load (mA) 120 140 160 D104 VLCM_OUT = 4.8 V VLCM_OUT = 6.3 V Figure 190. LCM Boost Efficiency Figure 189. LCM Boost Efficiency 100 100 95 95 90 90 Efficiency (%) Efficiency (%) 40 D101 85 80 75 70 85 80 75 70 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 65 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 65 60 60 0 20 40 60 80 100 Load (mA) 120 140 160 0 20 40 D105 VLCM_OUT = 5.8 V 60 80 100 Load (mA) 120 140 160 D106 VLCM_OUT = 6.8 V Figure 191. LCM Boost Efficiency Figure 192. LCM Boost Efficiency Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 71 LM36274 www.ti.com 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 75 70 65 60 75 70 65 60 55 55 TA = -40qC TA = 25qC TA = 85qC 50 TA = -40qC TA = 25qC TA = 85qC 50 45 45 0 10 20 VVPOS = 4 V 30 40 50 Load (mA) 60 70 80 0 10 20 VLCM_OUT = 4.3 V VVPOS = 5 V 95 95 90 90 85 85 80 80 75 70 65 60 60 70 80 D108 VLCM_OUT = 5.3 V 75 70 65 60 55 55 TA = -40qC TA = 25qC TA = 85qC 50 VIN = 2.7 V VIN = 3.7 V VIN = 4.5 V 50 45 45 0 10 20 VVPOS = 6 V 30 40 50 Load (mA) 60 70 80 0 10 20 30 D109 40 50 Load (mA) 60 70 80 D110 VLCM_OUT = 6.3 V Figure 195. VPOS Efficiency Figure 196. VPOS Efficiency 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) 40 50 Load (mA) Figure 194. VPOS Efficiency Efficiency (%) Efficiency (%) Figure 193. VPOS Efficiency 75 70 65 60 75 70 65 60 55 55 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 50 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 50 45 45 0 10 VVPOS = 6 V 20 30 40 50 Load (mA) 60 VLCM_OUT = 6.3 V 70 80 0 10 20 D111 VVPOS = 6.5 V Figure 197. VPOS Efficiency 72 30 D107 30 40 50 Load (mA) 60 70 80 D112 VLCM_OUT = 6.8 V Figure 198. VPOS Efficiency Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 90 90 85 85 80 80 75 75 Efficiency (%) Efficiency (%) www.ti.com 70 65 60 70 65 60 55 55 50 50 TA = -40qC TA = 25qC TA = 85qC 45 40 40 0 10 20 VVNEG = -4 V 30 40 50 Load (mA) 60 70 TA = -40qC TA = 25qC TA = 85qC 45 0 80 10 VVNEG = -5 V VLCM_OUT = 4.3 V 90 95 85 90 80 85 75 80 Efficiency (%) Efficiency (%) 30 40 50 Load (mA) 60 70 80 D114 VLCM_OUT = 5.3 V Figure 200. VNEG Efficiency Figure 199. VNEG Efficiency 70 65 60 55 75 70 65 60 50 55 TA = -40qC TA = 25qC TA = 85qC 45 VIN = 2.7 V VIN = 3.7 V VIN = 4.5 V 50 40 45 0 10 20 VVNEG = -6 V 30 40 50 Load (mA) 60 70 80 0 10 20 30 D115 VLCM_OUT = 6.3 V VVNEG = –4.5 V Figure 201. VNEG Efficiency 40 50 Load (mA) 60 70 80 D116 VLCM_OUT = 4.8 V Figure 202. VNEG Efficiency 95 95 90 90 85 85 80 80 Efficiency (%) Efficiency (%) 20 D113 75 70 65 60 75 70 65 60 55 55 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 50 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 50 45 45 0 10 VVNEG = –5.5 V 20 30 40 50 Load (mA) 60 VLCM_OUT = 5.8 V 70 80 0 10 D117 VVNEG = –6.5 V Figure 203. VNEG Efficiency 20 30 40 50 Load (mA) 60 70 80 D118 VLCM_OUT = 6.8 V Figure 204. VNEG Efficiency Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 73 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com 95 95 90 90 85 80 Efficiency (%) Efficiency (%) 85 75 70 65 80 75 70 65 60 TA = -40qC TA = 25qC TA = 85qC 55 TA = -40qC TA = 25qC TA = 85qC 60 50 55 0 10 20 30 VVPOS = 4 V 40 50 Load (mA) VVNEG = –4 V 60 70 80 0 10 20 30 D119 VLCM_OUT = 4.3 V VVPOS = 5 V Figure 205. VPOS/VNEG Efficiency 40 50 Load (mA) VVNEG = –5 V 60 70 80 D120 VLCM_OUT = 5.3 V Figure 206. VPOS/VNEG Efficiency 95 95 90 90 85 Efficiency (%) Efficiency (%) 85 80 75 70 75 70 65 60 TA = -40qC TA = 25qC TA = 85qC 65 80 VIN = 2.7 V VIN = 3.7 V VIN = 4.5 V 55 60 50 0 10 20 30 VVPOS = 6 V 40 50 Load (mA) VVNEG = –6 V 60 70 80 0 10 VLCM_OUT = 6.3 V VVPOS = 4.5 V 30 40 50 Load (mA) VVNEG = –4.5 V 60 70 80 D122 VLCM_OUT = 4.8 V Figure 208. VPOS/VNEG Efficiency 95 95 90 90 85 85 80 Efficiency (%) Efficiency (%) Figure 207. VPOS/VNEG Efficiency 75 70 65 80 75 70 65 60 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 55 0 10 20 VVPOS = 5.5 V 30 40 50 Load (mA) VVNEG = –5.5 V 60 70 VIN = 2.7 V VIN = 3.7 V VIN = 5 V 60 55 50 80 0 10 20 D123 VLCM_OUT = 5.8 V VVPOS = 6.5 V Figure 209. VPOS/VNEG Efficiency 74 20 D121 Submit Documentation Feedback 30 40 50 Load (mA) VVNEG = –6.5 V 60 70 80 D124 VLCM_OUT = 6.8 V Figure 210. VPOS/VNEG Efficiency Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 9 Power Supply Recommendations The LM36274 is designed to operate from an input voltage supply range from 2.7 V to 5 V. This input supply must be well regulated and capable to supply the required input current. If the input supply is located far from the LM36274 additional bulk capacitance may be required in addition to the ceramic bypass capacitors. 10 Layout 10.1 Layout Guidelines • • • • • • Place the boost converter output capacitors as close to the output voltage and GND pins as possible. Minimize the boost converter switching loops by placing the input capacitors and inductors close to GND and switch pins. If possible, route the switching loops on top layer only. For best efficiency, try to minimize copper on the switch node to minimize switch pin parasitic capacitance while preserving adequate routing width. VIN input voltage pin must be bypassed to ground with a low-ESR bypass capacitor. Place the capacitor as close as possible to VIN pin. Place the output capacitor of the LDO as close to the output pins as possible. Also place the charge pump flying capacitor and output capacitor close to their respective pins. Route the internal pins on the second layer. Use offset micro vias to go from top layer to mid-layer1. Avoid routing the signal traces directly under the switching loops of the boost converters. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 75 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com 10.2 Layout Example VIAs to GND Plane VIAs to GND Plane CVNEG CFLY VINL CVPOS VNEG C- CP_GND C+ IN LCM_EN2 LCM_EN1 VPOS LED4 SCL SDA LCM_OUT LED3 PWM HWEN LCM_SW CIN VINL CLCM LED2 AGND LCM_GND BL_GND LED1 BL_OUT BL_SW BL_SW CBL_OUT LLCM VIAs to GND Plane LBL D1 VINL VIAs to GND Plane Figure 211. LM36274 Layout Example 76 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 LM36274 www.ti.com SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.2 Development Support Power Stage Designer™ tools can be used for the boost calculation: http://www.ti.com/tool/powerstage-designer 11.2 Documentation Support 11.2.1 Related Documentation For related documentation, see the following: • AN-1112 DSBGA Wafer Level Chip Scale Package • Understanding Boost Power Stages in Switch Mode Power Supplies 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 77 LM36274 SNVSAJ9D – FEBRUARY 2016 – REVISED MARCH 2018 www.ti.com 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 78 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: LM36274 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LM36274YFFR ACTIVE DSBGA YFF 24 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 LM36274 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of