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LM43600-Q1
SNVSA99C – JULY 2015 – REVISED NOVEMBER 2017
LM43600-Q1 3.5-V to 36-V, 0.5-A Synchronous Step-Down Voltage Converter
1 Features
3 Description
•
•
The LM43600-Q1 regulator is an easy-to-use
synchronous step-down DC-DC converter capable of
driving up to 0.5 A of load current from an input
voltage ranging from 3.5 V to 36 V (42 V transient).
The LM43600-Q1 provides exceptional efficiency,
output accuracy and dropout voltage in a very small
solution size. An extended family is available in 1 A, 2
A, and 3 A load current options in pin-to-pin
compatible packages. Peak current mode control is
employed
to
achieve
simple
control
loop
compensation and cycle-by-cycle current limiting.
Optional features such as programmable switching
frequency,
synchronization,
power-good
flag,
precision enable, internal soft start, extendable soft
start, and tracking provide a flexible and easy to use
platform for a wide range of applications.
Discontinuous conduction and automatic frequency
modulation at light loads improve light load efficiency.
The family requires few external components and pin
arrangement allows simple, optimum PCB layout.
Protection features include thermal shutdown, VCC
undervoltage lockout, cycle-by-cycle current limit, and
output short-circuit protection. The LM43600-Q1
device is available in the 16-pin, leaded HTSSOP
(PWP) package (6.6 mm × 5.1 mm × 1.2 mm) with
0.65-mm lead pitch. The device is pin-to-pin
compatible with the LM4360x and LM4600x families.
The LM43600A-Q1 version is optimized for PFM
operation and recommended for new designs.
1
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•
•
•
•
•
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
33-µA Quiescent Current in Regulation
High Efficiency at Light Load (DCM and PFM)
Tested to EN55022/CISPR 22 EMI standards
Integrated Synchronous Rectification
Adjustable Frequency Range: 200 kHz to 2.2 MHz
(500 kHz Default)
Frequency Synchronization to External Clock
Internal Compensation
Stable with Almost Any Combination of Ceramic,
Polymer, Tantalum, and Aluminum Capacitors
Power-Good Flag
Soft Start into Pre-Biased Load
Internal Soft Start: 4.1 ms
Extendable Soft-Start Time by External Capacitor
Output Voltage Tracking Capability
Precision Enable to Program System UVLO
Output Short-Circuit Protection with Hiccup Mode
Overtemperature Thermal Shutdown Protection
Create a Custom Design Using the LM43600-Q1
With the WEBENCH® Power Designer
2 Applications
•
•
•
•
Device Information(1)
PART NUMBER
Sub-AM Band Automotive
Telecommunications Systems
General Purpose Wide VIN Regulation
High Efficiency Point-Of-Load Regulation
HTSSOP (16)
70
6.60 mm × 5.10 mm
space
Simplified Schematic
L
VIN
Vertical Polarization
BODY SIZE (NOM)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Radiated Emission (VIN = 12 V, VOUT = 3.3 V
FS = 500 kHz, IOUT = 0.5 A)
dBuV
80
PACKAGE
LM43600-Q1,
LM43600A-Q1
VIN
CIN
VOUT
SW
LM43600-Q1
CBOOT
COUT
CBIAS
CFF
Horizontal Polarization
60
50
EN 55022 Class B Limit
40
ENABLE
CBOOT
BIAS
PGOOD
30
SS/TRK
20
10
Evaluation Board Emissions
30
100
Frequency (MHz)
1000
RT
SYNC
AGND
RFBT
FB
VCC
CVCC
RFBB
PGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM43600-Q1
SNVSA99C – JULY 2015 – REVISED NOVEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
5
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 23
8
Applications and Implementation ...................... 25
8.1 Application Information............................................ 25
8.2 Typical Applications ................................................ 25
9 Power Supply Recommendations...................... 42
10 Layout................................................................... 42
10.1 Layout Guidelines ................................................. 42
10.2 Layout Example .................................................... 45
11 Device and Documentation Support ................. 46
11.1
11.2
11.3
11.4
11.5
11.6
Development Support ...........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
46
46
46
46
46
46
12 Mechanical, Packaging, and Orderable
Information ........................................................... 46
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2017) to Revision C
Page
•
Added LM43600A-Q1 information on page 1 ........................................................................................................................ 1
•
Added RPGOOD values for LM43600A-Q1 ............................................................................................................................... 6
Changes from Revision A (August 2015) to Revision B
Page
•
No technical changes; editorial only ...................................................................................................................................... 1
•
Added links for WEBENCH ................................................................................................................................................... 1
Changes from Original (July 2015) to Revision A
•
2
Page
Changed from Preview to Production Data ............................................................................................................................ 1
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SNVSA99C – JULY 2015 – REVISED NOVEMBER 2017
5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View
SW
1
SW
2
16
15
PGND
PGND
CBOOT
VCC
3
4
14
VIN
13
BIAS
5
VIN
12
SYNC
EN
6
11
RT
PGOOD
SS/TRK
7
8
10
AGND
PAD
FB
9
Pin Functions
PIN
NAME
NUMBER
I/O
DESCRIPTION
(1)
1, 2
P
Switching output of the regulator. Internally connected to both power MOSFETs. Connect to
power inductor.
CBOOT
3
P
Bootstrap capacitor connection for high-side driver. Connect a high-quality 470-nF capacitor
from CBOOT to SW.
VCC
4
P
Internal bias supply output for bypassing. Connect bypass capacitor from this pin to AGND.
Do not connect external load to this pin. Never short this pin to ground during operation.
BIAS
5
P
Optional internal LDO supply input. To improve efficiency, it is recommended to tie to VOUT
when 3.3 V ≤ VOUT ≤ 28 V, or tie to an external 3.3 V or 5 V rail if available. When used,
place a bypass capacitor (1 to 10 µF) from this pin to ground. Tie to ground when not in use.
Do not float
SYNC
6
A
Clock input to synchronize switching action to an external clock. Use proper high speed
termination to prevent ringing. Connect to ground if not used. Do not float.
RT
7
A
Connect a resistor RT from this pin to AGND to program switching frequency. Leave floating
for 500 kHz default switching frequency.
PGOOD
8
A
Open drain output for power-good flag. Use a 10-kΩ to 100-kΩ pullup resistor to logic rail or
other DC voltage no higher than 12 V.
FB
9
A
Feedback sense input pin. Connect to the midpoint of feedback divider to set VOUT. Do not
short this pin to ground during operation.
AGND
10
G
Analog ground pin. Ground reference for internal references and logic. Connect to system
ground.
SS/TRK
11
A
Soft-start control pin. Leave floating for internal soft-start slew rate. Connect to a capacitor to
extend soft start time. Connect to external voltage ramp for tracking.
EN
12
A
Enable input to the LM43600-Q1: High = ON and low = OFF. Connect to VIN, or to VIN
through resistor divider,or to an external voltage or logic source. Do not float.
VIN
13, 14
P
Supply input pins to internal LDO and high side power FET. Connect to power supply and
bypass capacitors CIN. Path from VIN pin to high frequency bypass CIN and PGND must be
as short as possible.
PGND
15, 16
G
Power ground pins, connected internally to the low side power FET. Connect to system
ground, PAD, AGND, ground pins of CIN and COUT. Path to CIN must be as short as possible.
—
G
Low impedance connection to AGND. Connect to PGND on PCB . Major heat dissipation
path of the die. Must be used for heat sinking to ground plane on PCB.
SW
PAD
(1)
P = Power, G = Ground, A = Analog
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
Input voltages
Output voltages
PARAMETER
MIN
MAX
VIN to PGND
–0.3
42
EN to PGND
–0.3
VIN + 0.3
FB, RT, SS/TRK to AGND
–0.3
3.6
PGOOD to AGND
–0.3
15
SYNC to AGND
–0.3
5.5
BIAS to AGND
–0.3
30
AGND to PGND
–0.3
0.3
SW to PGND
–0.3
VIN + 0.3
SW to PGND less than 10-ns transients
–3.5
42
CBOOT to SW
–0.3
5.5
VCC to AGND
–0.3
3.6
–65
150
Storage temperature, Tstg
(1)
UNIT
V
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
UNIT
±2000
Charged-device model (CDM), per AEC Q100-011
V
±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted) (1)
Input voltages
PARAMETER
MIN
MAX
VIN to PGND
3.5
36
EN
–0.3
VIN
FB
–0.3
1.1
PGOOD
–0.3
12
BIAS input not used
–0.3
0.3
BIAS input used
3.3
VIN or 28 (2)
AGND to PGND
–0.1
0.1
1
28
Output voltage
VOUT
Output current
IOUT
Temperature
Operating junction temperature range, TJ
(1)
(2)
4
UNIT
V
V
0
0.5
A
–40
125
°C
Recommended Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For specified specifications, see Electrical Characteristics.
Whichever is lower.
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6.4 Thermal Information
LM43600
THERMAL METRIC (1) (2)
PWP (HTSSOP)
UNIT
16 PINS
39.9 (3)
°C/W
Junction-to-case (top) thermal resistance
26.9
°C/W
Junction-to-board thermal resistance
21.7
°C/W
ψJT
Junction-to-top characterization parameter
0.8
°C/W
ψJB
Junction-to-board characterization parameter
21.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.3
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
(1)
(2)
(3)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The package thermal impedance is calculated in accordance with JESD 51-7 standard with a 4-layer board and 1 W power dissipation.
RθJA is highly related to PCB layout and heat sinking. See Figure 107 for measured RθJA vs PCB area from a 2-layer board and a 4layer board.
6.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PINS)
VIN-MIN-ST
Minimum input voltage for start-up
ISHDN
Shutdown quiescent current
VEN = 0 V
3.8
V
1.1
3.1
µA
IQ-NONSW
Operating quiescent current (nonswitching) from VIN
VEN = 3.3 V
VFB = 1.5 V
VBIAS = 3.4 V external
6
11
µA
IBIAS-NONSW
Operating quiescent current (nonswitching) from external VBIAS
VEN = 3.3 V
VFB = 1.5 V
VBIAS = 3.4 V external
85
140
µA
Operating quiescent current
(switching)
VEN = 3.3 V
IOUT = 0 A
RT = open
VBIAS = VOUT = 3.3 V
RFBT = 1 Meg
IQ-SW
33
µA
ENABLE (EN PIN)
VEN-VCC-H
Voltage level to enable the internal
LDO output VCC
VEN-VCC-L
Voltage level to disable the internal
VENABLE low level
LDO output VCC
VEN-VOUT-H
Precision enable level for switching
VENABLE high level
and regulator output: VOUT
VEN-VOUT-HYS
Hysteresis voltage between VOUT
precision enable and disable
thresholds
VENABLE hysteresis
ILKG-EN
Enable input leakage current
VEN = 3.3 V
0.8
VIN ≥ 3.8 V
3.3
V
VCC rising threshold
3.14
V
Hysteresis voltage between rising and
falling thresholds
–567
mV
VBIAS rising threshold
2.96
Hysteresis voltage between rising and
falling thresholds
–74
VENABLE high level
1.2
2
V
2.1
0.4
V
2.42
V
–305
mV
1.75
µA
INTERNAL LDO (VCC PIN AND BIAS PIN)
VCC
Internal LDO output voltage VCC
VCC-UVLO
Undervoltage lockout (UVLO)
thresholds for VCC
VBIAS-ON
Internal LDO input change over
threshold to BIAS
3.2
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mV
5
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Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TJ = 25°C
1.009
1.016
1.023
TJ = –40°C to 85°C
0.999
1.016
1.031
TJ = –40°C to 125°C
0.999
UNIT
VOLTAGE REFERENCE (FB PIN)
VFB
Feedback voltage
ILKG-FB
Input leakage current at FB pin
1.016
1.039
FB = 1.011 V
0.2
65
Shutdown threshold
160
Recovery threshold
150
V
nA
THERMAL SHUTDOWN
TSD (1)
Thermal shutdown
°C
CURRENT LIMIT AND HICCUP
IHS-LIMIT
Peak inductor current limit
1.04
1.33
1.56
A
ILS-LIMIT
Inductor current valley limit
0.46
0.60
0.75
A
1.17
2.2
2.85
µA
SOFT START (SS/TRK PIN)
ISSC
Soft-start charge current
RSSD
Soft-start discharge resistance
UVLO, TSD, OCP, or EN = 0 V
16
kΩ
POWER GOOD (PGOOD PIN)
VPGOOD-HIGH
Power-good flag overvoltage
tripping threshold
% of FB voltage
VPGOOD-LOW
Power-good flag undervoltage
tripping threshold
% of FB voltage
VPGOOD-HYS
Power-good flag recovery
hysteresis
% of FB voltage
RPGOOD
PGOOD pin pulldown resistance
when power bad
110%
83%
113%
90%
6%
LM43600-Q1: VEN = 3.3 V
40
125
LM43600-Q1: VEN = 0 V
60
150
LM43600A-Q1: VEN = 3.3 V
69
150
LM43600A-Q1: VEN = 0 V
150
350
Ω
MOSFETS (2)
RDS-ON-HS
High-side MOSFET ON-resistance
IOUT = 0.5 A
VBIAS = VOUT = 3.3 V
419
mΩ
RDS-ON-LS
Low-side MOSFET ON-resistance
IOUT = 0.5 A
VBIAS = VOUT = 3.3 V
231
mΩ
(1)
(2)
6
Specified by design.
Measured at package pins.
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6.6 Timing Requirements
MIN
NOM
MAX
UNIT
CURRENT LIMIT AND HICCUP
NOC
Hiccup wait cycles when LS current limit tripped
32
Cycles
TOC
Hiccup retry delay time
5.5
ms
3.86
ms
TPGOOD-RISE Power-good flag rising transition deglitch delay
220
µs
TPGOOD-FALL Power-good flag falling transition deglitch delay
220
µs
SOFT START (SS/TRK PIN)
TSS
Internal soft-start time when SS pin open circuit
POWER GOOD (PGOOD PIN)
6.7 Switching Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SW (SW PIN)
tON-MIN (1)
Minimum high side MOSFET ON
time
125
165
ns
tOFF-MIN (1)
Minimum high side MOSFET OFF
time
200
250
ns
500
570
kHz
OSCILLATOR (SW PINS AND SYNC PIN)
FOSC-
Oscillator default frequency
RT pin open circuit
445
DEFAULT
Minimum adjustable frequency
FADJ
Maximum adjustable frequency
With 1% resistors at RT pin
Frequency adjust accuracy
200
kHz
2200
kHz
10%
VSYNC-HIGH Sync clock high level threshold
2
V
VSYNC-LOW
Sync clock low level threshold
DSYNC-MAX
Sync clock maximum duty cycle
90%
DSYNC-MIN
Sync clock minimum duty cycle
10%
TSYNC-MIN
Minimum sync clock ON-time and
OFF-time
(1)
0.4
80
V
ns
Specified by design.
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6.8 Typical Characteristics
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz, L = 22 µH, COUT = 100 µF, CFF = 33 pF. See Application
Performance Curves for bill of materials (BOM) for other VOUT and FS combinations.
60
50
VIN = 8V
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
40
30
20
10
0
0.001
0.01
VOUT = 3.3 V
0
0.001
VOUT = 5 V
80
70
70
60
50
40
VIN = 12V
30
VIN = 18V
Efficiency (%)
Efficiency (%)
90
80
0.1
C004
FS = 200 kHz
50
40
0
0.001
0.1
VIN = 24V
VIN = 28V
0.01
0.1
Load Current (A)
C003
FS = 500 kHz
VIN = 12V
VIN = 18V
10
VIN = 36V
Load Current (A)
60
20
VIN = 28V
10
VOUT = 5 V
Figure 3. Efficiency
C005
FS = 1 MHz
Figure 4. Efficiency
100
100
90
90
80
80
70
70
60
50
VIN = 24V
40
30
VIN = 28V
20
Efficiency (%)
Efficiency (%)
0.01
30
VIN = 24V
20
60
50
40
30
20
10
VIN = 36V
0.01
Load Current (A)
FS = 500 kHz
0
0.001
0.1
VIN = 36V
10
0.01
Load Current (A)
C007
VOUT = 24 V
Figure 5. Efficiency
8
VIN = 36V
Figure 2. Efficiency
90
VOUT = 12 V
VIN = 28V
Load Current (A)
C002
100
0
0.001
VIN = 24V
10
Figure 1. Efficiency
VOUT = 5 V
VIN = 18V
20
FS = 500 kHz
0.01
VIN = 12V
40
100
0
0.001
VIN = 8V
50
30
0.1
Load Current (A)
60
0.1
C008
FS = 500 kHz
Figure 6. Efficiency
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz, L = 22 µH, COUT = 100 µF, CFF = 33 pF. See Application
Performance Curves for bill of materials (BOM) for other VOUT and FS combinations.
3.40
5.15
3.38
5.10
3.36
5.05
3.32
Vout (V)
Vout (V)
3.34
3.30
3.28
3.26
3.24
3.22
3.20
0.001
VIN = 8V
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
0.01
4.95
4.90
0.1
FS = 500 kHz
VOUT = 5 V
5.15
5.15
5.10
5.10
5.05
5.05
5.00
4.80
0.001
0.01
4.80
0.001
0.1
C014
FS = 200 kHz
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
0.01
0.1
Load Current (A)
C013
FS = 500 kHz
VOUT = 5 V
C015
FS = 1 MHz
Figure 10. VOUT Regulation
25.0
12.4
24.8
12.3
24.6
12.2
24.4
12.1
24.2
Vout (V)
Vout (V)
0.01
4.85
Figure 9. VOUT Regulation
12.0
11.9
11.8
24.0
23.8
23.6
VIN = 24V
11.7
VIN = 28V
11.6
VIN = 36V
0.01
0.1
Load Current (A)
VOUT = 12 V
VIN = 36V
5.00
12.5
11.5
0.001
VIN = 28V
4.90
0.1
Load Current (A)
VOUT = 5 V
VIN = 24V
4.95
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
4.85
VIN = 18V
Figure 8. VOUT Regulation
5.20
Vout (V)
Vout (V)
Figure 7. VOUT Regulation
5.20
4.90
VIN = 12V
Load Current (A)
C012
4.95
VIN = 8V
4.85
4.80
0.001
Load Current (A)
VOUT = 3.3 V
5.00
FS = 500 kHz
23.4
VIN = 36V
23.2
23.0
0.001
0.01
0.1
Load Current (A)
C017
VOUT = 24 V
Figure 11. VOUT Regulation
C018
FS = 500 kHz
Figure 12. VOUT Regulation
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz, L = 22 µH, COUT = 100 µF, CFF = 33 pF. See Application
Performance Curves for bill of materials (BOM) for other VOUT and FS combinations.
3.5
5.2
3.4
5.0
3.3
4.8
3.1
VOUT (V)
VOUT (V)
3.2
3.0
2.9
Load = 0.2A
2.8
4.6
Load = 0.2A
4.4
Load = 0.3A
Load = 0.3A
2.7
Load = 0.4A
2.6
Load = 0.4A
4.2
Load = 0.5A
Load = 0.5A
2.5
4.0
3.5
3.7
3.9
4.1
4.3
4.5
VIN (V)
VOUT = 3.3 V
5.0
5.4
FS = 500 kHz
VOUT = 5 V
5.8
5.0
5.0
4.8
4.8
VOUT (V)
5.2
4.6
Load = 0.2A
C024
FS = 200 kHz
4.6
Load = 0.2A
4.4
Load = 0.3A
Load = 0.3A
4.2
6.0
Figure 14. Dropout Curve
5.2
4.4
5.6
VIN (V)
Figure 13. Dropout Curve
VOUT (V)
5.2
C022
Load = 0.4A
4.2
Load = 0.4A
Load = 0.5A
Load = 0.5A
4.0
4.0
5.0
5.2
5.4
5.6
5.8
6.0
VIN (V)
VOUT = 5 V
5.0
5.2
5.4
5.6
5.8
6.0
VIN (V)
C023
FS = 500 kHz
VOUT = 5 V
Figure 15. Dropout Curve
C025
FS = 1 MHz
Figure 16. Dropout Curve
12.4
24.5
12.2
24.0
VOUT (V)
VOUT (V)
12.0
11.8
11.6
Load = 0.2A
11.4
Load = 0.3A
11.2
Load = 0.4A
23.5
23.0
Load = 0.2A
Load = 0.3A
22.5
Load = 0.4A
Load = 0.5A
Load = 0.5A
11.0
12.0
12.5
13.0
13.5
VIN (V)
VOUT = 12 V
FS = 500 kHz
14.0
22.0
24.0
VOUT = 24 V
Figure 17. Dropout Curve
10
24.5
25.0
25.5
VIN (V)
C027
26.0
C028
FS = 500 kHz
Figure 18. Dropout Curve
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz, L = 22 µH, COUT = 100 µF, CFF = 33 pF. See Application
Performance Curves for bill of materials (BOM) for other VOUT and FS combinations.
1000000
Frequency (Hz)
Frequency (Hz)
1000000
100000
Load = 0.01 A
Load = 0.01 A
Load = 0.1 A
Load = 0.1 A
Load = 0.5 A
10000
3.4
3.6
3.8
4.0
4.2
4.4
4.6
4.8
Load = 0.5 A
10000
5.0
VIN (V)
VOUT = 3.3 V
100000
5.0
5.2
5.4
FS = 500 kHz
VOUT = 5 V
Figure 19. Switching Frequency vs VIN in Dropout Operation
dBuV
80
Vertical Polarization
70
Horizontal Polarization
60
5.6
5.8
6.0
6.2
6.4
6.6
6.8
7.0
VIN (V)
C001
C001
FS = 1 MHz
(TBD)
Figure 20. Switching Frequency vs VIN in Dropout Operation
dBuV
80
Vertical Polarization
70
Horizontal Polarization
60
50
50
EN 55022 Class B Limit
40
30
20
20
10
EN 55022 Class B Limit
40
30
10
Evaluation Board Emissions
30
100
Frequency (MHz)
Evaluation Board Emissions
1000
VOUT = 3.3 V
FS = 500 kHz
IOUT = 0.5 A
Measured on the LM43600QPWPEVM with default BOM. No input
filter used.
30
Figure 22. Radiated EMI Curve
dBuV
100
90
dBuV
100
90
80
80
Quasi Peak Limit
60
Average Limit
50
1000
VOUT = 5 V
FS = 500 kHz
IOUT = 0.5 A
Measured on the LM43600QPWPEVM with L = 44 µH, COUT = 66
µF, CFF = 33 pF. No input filter used.
Figure 21. Radiated EMI Curve
70
100
Frequency (MHz)
40
30
70
Quasi Peak Limit
60
Average Limit
50
40
30
20
10
0.15
20
10
Measured Peak Emissions
1
Frequency (MHz)
10
30
VOUT = 3.3 V
FS = 500 kHz
IOUT = 0.5 A
Measured on the LM43600QPWPEVM with default BOM. Input
filter: Lin = 1 µH Cd = 47 µF CIN4 = 68 µF
0.15
Measured Peak Emissions
1
Frequency (MHz)
10
30
VOUT = 5 V
FS = 500 kHz
IOUT = 0.5 A
Measured on the LM43600QPWPEVM with L = 44 µH, COUT = 66
µF, CFF = 33 pF. Input filter Lin = 1 µH Cd = 47 µF CIN4 = 68 µF
Figure 23. Conducted EMI Curve
Figure 24. Conducted EMI Curve
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz, L = 22 µH, COUT = 100 µF, CFF = 33 pF. See Application
Performance Curves for bill of materials (BOM) for other VOUT and FS combinations.
4
700
3.5
Shutdown Current ( A)
800
Rdson (mohm)
600
500
400
300
200
HS
100
3
2.5
2
1.5
1
VIN = 12V
0.5
VIN = 24V
LS
0
0
-50
0
50
100
Temperature (ƒC)
-50
150
0
50
100
150
Temperature (ƒC)
C001
Figure 25. High-Side and Low-side On Resistance vs
Junction Temperature
C001
Figure 26. Shutdown Current vs Junction Temperature
2.5
1.4
1.2
1.5
EN Leakage Current ( A)
Enable Threshold (V)
2
EN-VOUT Rising TH
EN-VOUT Falling TH
EN-VCC Rising TH
EN-VCC Falling TH
1
0.5
1
0.8
0.6
0.4
0.2
0
VEN = 3.3V
0
-50
0
50
100
Temperature (ƒC)
150
-50
100
150
C001
Figure 28. Enable Leakage Current vs
Junction Temperature
120%
1.030
115%
1.025
110%
1.020
105%
VFB (V)
PGOOD Threshold / VOUT (%)
50
Temperature (ƒC)
Figure 27. Enable Threshold vs Junction Temperature
100%
95%
1.015
1.010
1.005
90%
OVP Trip Level
OVP Recover Level
UVP Recover Level
UVP Trip Level
85%
80%
75%
-50
0
50
Temperature (ƒC)
100
1.000
VIN = 12V
0.995
VIN = 24V
0.990
150
-50
0
50
Temperature (ƒC)
C001
Figure 29. PGOOD Threshold vs Junction Temperature
12
0
C001
100
150
C001
Figure 30. Feedback Voltage vs Junction Temperature
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz, L = 22 µH, COUT = 100 µF, CFF = 33 pF. See Application
Performance Curves for bill of materials (BOM) for other VOUT and FS combinations.
2.0
70
1.8
60
1.6
50
1.2
IQ ( A)
Current (A)
1.4
1.0
0.8
0.6
40
30
20
0.4
IL Peak Limit
0.2
10
IL Valley Limit
0.0
0
-50
0
50
Temperature (ƒC)
VIN = 12 V
VOUT = 3.3 V
100
150
0
FS = 500 kHz
Figure 31. Peak and Valley Current Limits vs Temperature
10
20
30
40
VIN (V)
C001
VOUT = 3.3 V
FS = 500 kHz
C001
IOUT = 0 A
Figure 32. Operation IQ vs VIN with BIAS Connected to VOUT
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7 Detailed Description
7.1 Overview
The LM43600-Q1 regulator is an easy to use synchronous step-down DC-DC converter that operates from 3.5-V
to 36-V supply voltage. It is capable of delivering up to 0.5-A DC load current with exceptional efficiency and
thermal performance in a very small solution size. An extended family is available in 1-A, 2-A, and 3-A load
options in pin-to-pin compatible packages.
The LM43600-Q1 employs fixed frequency peak current mode control with discontinuous conduction mode
(DCM) and pulse frequency modulation (PFM) mode at light load to achieve high efficiency across the load
range. The device is internally compensated, which reduces design time, and requires fewer external
components. The switching frequency is programmable from 200 kHz to 2.2 MHz by an external resistor, RT. It
defaults at 500 kHz without RT. The LM43600-Q1 is also capable of synchronization to an external clock within
the 200 kHz to 2.2 MHz frequency range. The wide switching frequency range allows the device to be optimized
to fit small board space at higher frequency, or high efficient power conversion at lower frequency.
Optional features are included for more comprehensive system requirements, including power-good (PGOOD)
flag, precision enable, synchronization to external clock, extendable soft-start time, and output voltage tracking.
These features provide a flexible and easy to use platform for a wide range of applications. Protection features
include over temperature shutdown, VCC undervoltage lockout (UVLO), cycle-by-cycle current limit, and shortcircuit protection with hiccup mode.
The family requires few external components and the pin arrangement was designed for simple, optimum PCB
layout. The LM43600-Q1 device is available in the 16-pin, leaded HTSSOP (PWP) package (6.6 mm × 5.5 mm ×
1.2 mm) with 0.65-mm lead pitch.
7.2 Functional Block Diagram
ENABLE
VCC
Enable
Internal
SS
ISSC
BIAS
VCC
LDO
VIN
Precision
Enable
SS/TRK
CBOOT
HS I Sense
+
EA
REF
RC
+
±
+±
TSD
UVLO
CC
PGOOD
AGND
OV/UV
Detector
FB
SW
PWM CONTROL LOGIC
PFM
Detector
PGood
Slope
Comp
Freq
Foldback
Zero
Cross
HICCUP
Detector
Oscillator
LS I Sense
FB
PGood
SYNC
14
PGND
RT
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7.3 Feature Description
7.3.1 Fixed Frequency Peak Current Mode Controlled Step-Down Regulator
The following operating description of the LM43600-Q1 refers to the Functional Block Diagram and to the
waveforms in Figure 33. The LM43600-Q1 is a step-down buck regulator with both high-side (HS) switch and
low-side (LS) switch (synchronous rectifier) integrated. The LM43600-Q1 supplies a regulated output voltage by
turning on the HS and LS NMOS switches with controlled ON time. During the HS switch ON time, the SW pin
voltage VSW swings up to approximately VIN, and the inductor current IL increases with a linear slope (VIN – VOUT)
/ L. When the HS switch is turned off by the control logic, the LS switch is turned on after a anti-shoot-through
dead time. Inductor current discharges through the LS switch with a slope of –VOUT / L. The control parameter of
Buck converters are defined as Duty Cycle D = tON / TSW, where tON is the HS switch ON-time and TSW is the
switching period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In
an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely
proportional to the input voltage: D = VOUT / VIN.
VSW
D = tON / TSW
SW Voltage
VIN
tOFF
tON
0
t
-VD1
Inductor Current
iL
TSW
ILPK
IOUT
ûiL
0
t
Figure 33. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The LM43600-Q1 synchronous buck converter employs peak current mode control topology. A voltage feedback
loop is used to get accurate DC voltage regulation by adjusting the peak current command based on voltage
offset. The peak inductor current is sensed from the HS switch and compared to the peak current to control the
ON time of the HS switch. The voltage feedback loop is internally compensated, which allows for fewer external
components, makes it easy to design, and provides stable operation with almost any combination of output
capacitors. The regulator operates with fixed switching frequency in continuous conduction mode (CCM) and
discontinuous conduction mode (DCM). At very light load, the LM43600-Q1 operates in PFM to maintain high
efficiency, and the switching frequency decreases with reduced load current.
7.3.2 Light Load Operation
DCM operation is employed in the LM43600-Q1 when the inductor current valley reaches zero. The LM43600-Q1
is in DCM when load current is less than half of the peak-to-peak inductor current ripple in CCM. In DCM, the LS
switch is turned off when the inductor current reaches zero. Switching loss is reduced by turning off the LS FET
at zero current and the conduction loss is lowered by not allowing negative current conduction. Power conversion
efficiency is higher in DCM than CCM under the same conditions.
In DCM, the HS switch ON-time reduces with lower load current. When either the minimum HS switch ON-time
(TON-MIN) or the minimum peak inductor current (IPEAK-MIN) is reached, the switching frequency will decrease to
maintain regulation. At this point, the LM43600-Q1 operates in PFM. In PFM, switching frequency is decreased
by the control loop when load current reduces to maintain output voltage regulation. Switching loss is further
reduced in PFM operation due to less frequent switching actions. Figure 34 shows an example of switching
frequency decreases with decreased load current.
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Feature Description (continued)
Frequency (Hz)
1000000
100000
VIN = 8 V
VIN = 12 V
VIN = 18 V
VIN = 24 V
10000
0.001
VIN = 36 V
0.01
0.1
Load (A)
C001
Figure 34. Switching Frequency Decreases with Lower Load Current in PFM Operation
VOUT = 5 V FS = 1 MHz
In PFM operation, a small positive DC offset is required at the output voltage to activate the PFM detector. The
lower the frequency in PFM, the more DC offset is needed at VOUT. See Typical Characteristics for typical DC
offset at very light load. If the DC offset on VOUT is not acceptable for a given application, a static load at output is
recommended to reduce or eliminate the offset. Lowering values of the feedback divider RFBT and RFBB can also
serve as a static load. In conditions with low VIN and/or high frequency, the LM43600-Q1 may not enter PFM
mode if the output voltage cannot be charged up to provide the trigger to activate the PFM detector. Once the
LM43600-Q1 is operating in PFM mode at higher VIN, it will remain in PFM operation when VIN is reduced.
7.3.3 Adjustable Output Voltage
The voltage regulation loop in the LM43600-Q1 regulates output voltage by maintaining the voltage on FB pin
(VFB) to be the same as the internal REF voltage (VREF). A resistor divider pair is needed to program the ratio
from output voltage VOUT to VFB. The resistor divider is connected from the VOUT of the LM43600-Q1 to ground
with the mid-point connecting to the FB pin.
VOUT
RFBT
FB
RFBB
Figure 35. Output Voltage Setting
The voltage reference system produces a precise voltage reference over temperature. The internal REF voltage
is 1.016 V typically. To program the output voltage of the LM43600-Q1 to be a certain value VOUT, RFBB can be
calculated with a selected RFBT by
VFB
RFBB
RFBT
VOUT VFB
(1)
The choice of the RFBT depends on the application. RFBT in the range from 10 kΩ to 100 kΩ is recommended for
most applications. A lower RFBT value can be used if static loading is desired to reduce VOUT offset in PFM
operation. Lower RFBT will reduce efficiency at very light load. Less static current goes through a larger RFBT and
might be more desirable when light load efficiency is critical. But RFBT larger than 1 MΩ is not recommended
because it makes the feedback path more susceptible to noise. Larger RFBT value requires more carefully
designed feedback path on the PCB. The tolerance and temperature variation of the resistor dividers affect the
output voltage regulation. It is recommended to use divider resistors with 1% tolerance or better and temperature
coefficient of 100 ppm or lower.
16
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Feature Description (continued)
If the resistor divider is not connected properly, output voltage cannot be regulated since the feedback loop is
broken. If the FB pin is shorted to ground, the output voltage will be driven close to VIN, since the regulator sees
very low voltage on the FB pin and tries to regulate it up. The load connected to the output could be damaged
under such a condition. Do not short FB pin to ground when the LM43600-Q1 is enabled. It is important to route
the feedback trace away from the noisy area of the PCB. For more layout recommendations, see Layout section.
7.3.4 Enable (ENABLE)
Voltage on the ENABLE pin (VEN) controls the ON or OFF functionality of the LM43600-Q1. Applying a voltage
less than 0.4 V to the ENABLE input shuts down the operation of the LM43600-Q1. In shutdown mode the
quiescent current drops to typically 1.1 µA at VIN = 12 V.
The internal LDO output voltage VCC is turned on when VEN is higher than 1.2 V. The switching action and output
regulation are enabled when VEN is greater than 2.1 V (typical). The LM43600-Q1 supplies regulated output
voltage when enabled and output current up to 0.5 A.
The ENABLE pin is an input and cannot be open circuit or floating. The simplest way to enable the operation of
the LM43600-Q1 is to connect the ENABLE pin to VIN pins directly. This allows self-start-up when VIN is within
the operation range.
Many applications will benefit from the employment of an enable divider RENT and RENB in Figure 36 to establish
a precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power
as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such
as a battery discharge level. An external logic signal can also be used to drive EN input for system sequencing
and protection.
VIN
RENT
ENABLE
RENB
Figure 36. System UVLO By Enable Dividers
7.3.5 VCC, UVLO and BIAS
The LM43600-Q1 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The
nominal voltage for VCC is 3.3 V. The VCC pin is the output of the LDO and must be properly bypassed. A high
quality ceramic capacitor with 2.2 µF to 10 µF capacitance and 6.3 V or higher rated voltage should be placed as
close as possible to VCC and grounded to the exposed PAD and ground pins. The VCC output pin should not be
loaded, left floating, or shorted to ground during operation. Shorting VCC to ground during operation may cause
damage to the LM43600-Q1.
Undervoltage lockout (UVLO) prevents the LM43600-Q1 from operating until the VCC voltage exceeds 3.14 V
(typical). The VCC UVLO threshold has 567 mV of hysteresis (typically) to prevent undesired shuting down due to
temperary VIN droops.
The internal LDO has two inputs: primary from VIN and secondary from BIAS input. The BIAS input powers the
LDO when VBIAS is higher than the change-over threshold. Power loss of an LDO is calculated by ILDO * (VIN-LDO VOUT-LDO). The higher the difference between the input and output voltages of the LDO, the more power loss
occur to supply the same output current. The BIAS input is designed to reduce the difference of the input and
output voltages of the LDO to reduce power loss and improve LM43600-Q1 efficiency, especially at light load. It
is recommended to tie the BIAS pin to VOUT when VOUT ≥ 3.3V. The BIAS pin should be grounded in applications
with VOUT less than 3.3 V. BIAS input can also come from an external voltage source, if available, to reduce
power loss. When used, a 1µF to 10µF high quality ceramic capacitor is recommended to bypass the BIAS pin to
ground.
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Feature Description (continued)
7.3.6 Soft-Start and Voltage Tracking (SS/TRK)
The LM43600-Q1 has a flexible and easy to use start up rate control pin: SS/TRK. Soft-start feature is to prevent
inrush current impacting the LM43600-Q1 and its supply when power is first applied. Soft-start is achieved by
slowly ramping up the target regulation voltage when the device is first enabled or powered up.
The simplest way to use the device is to leave the SS/TRK pin open circuit or floating. The LM43600-Q1 will
employ the internal soft-start control ramp and start up to the regulated output voltage in 4.1 ms typically.
In applications with a large amount of output capacitors, or higher VOUT, or other special requirements, the softstart time can be extended by connecting an external capacitor CSS from SS/TRK pin to AGND. Extended softstart time further reduces the supply current needed to charge up output capacitors and supply any output
loading. An internal current source (ISSC = 2.2 µA) charges CSS and generates a ramp from 0 V to VFB to control
the ramp-up rate of the output voltage. For a desired soft start time tSS, the capacitance for CSS can be found by
CSS ISSC u t SS
(2)
The soft start capacitor CSS is discharged by an internal FET when VOUT is shutdown by hiccup protection due to
excessive load, temperature shutdown due to overheating or ENABLE = logic low. A large CSS cap will take a
long time to discharge when ENABLE is toggled low. If ENABLE is toggled high again before the CSS is
completely discharged, then the next resulting soft-start ramp will follow the internal soft-start ramp. Only when
the soft-start voltage reaches the left-over voltage on CSS, will the output follow the ramp programmed by CSS.
This behavior will look as if there are two slopes at startup. If this is not acceptable by a certain application, a RC low-pass filter can be added to ENABLE to slow down the shutting down of VCC, which allows more time to
discharge CSS.
The LM43600-Q1 is capable of start up into prebiased output conditions. When the inductor current reaches
zero, the LS switch will be turned off to avoid negative current conduction. This operation mode is also called
diode emulation mode. It is built-in by the DCM operation in light loads. With a prebiased output voltage, the
LM43600-Q1 will wait until the soft-start ramp allows regulation above the prebiased voltage and then follow the
soft-start ramp to the regulation level.
When an external voltage ramp is applied to the SS/TRK pin, the LM43600-Q1 FB voltage follows the ramp if the
ramp magnitude is lower than the internal soft-start ramp. A resistor divider pair can be used on the external
control ramp to the SS/TRK pin to program the tracking rate of the output voltage. The final voltage seen by the
SS/TRK pin should not fall below 1.2 V to avoid abnormal operation.
EXT RAMP
RTRT
SS/TRK
RTRB
Figure 37. Soft Start Tracking External Ramp
VOUT tracked to an external voltage ramp has the option of ramping up slower or faster than the internal voltage
ramp. VFB always follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin.
Figure 38 shows the case when VOUT ramps slower than the internal ramp, while Figure 39 shows when VOUT
ramps faster than the internal ramp. Faster start up time may result in inductor current tripping current protection
during start-up. Use with special care.
Enable
Internal SS Ramp
Ext Tracking Signal to SS pin
VOUT
Figure 38. Tracking with Longer Start-up Time Than The Internal Ramp
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Feature Description (continued)
Enable
Internal SS Ramp
Ext Tracking Signal to SS pin
VOUT
Figure 39. Tracking with Shorter Start-up Time Than The Internal Ramp
7.3.7 Switching Frequency (RT) and Synchronization (SYNC)
The switching frequency of the LM43600-Q1 can be programmed by the impedance RT from the RT pin to
ground. The frequency is inversely proportional to the RT resistance. The RT pin can be left floating and the
LM43600-Q1 will operate at 500 kHz default switching frequency. The RT pin is not designed to be shorted to
ground.
For a desired frequency, typical RT resistance can be found by Equation 3.
RT(kΩ) = 40200 / Freq (kHz) - 0.6
(3)
Figure 40 shows RT resistance vs switching frequency FS curve.
250
RT Resistance (kŸ)
200
150
100
50
0
0
500
1000
1500
Switching Frequency (kHz)
2000
2500
C008
Figure 40. RT Resistance vs Switching Frequency
Table 1 provides typical RT values for a given FS.
Table 1. Typical Frequency Setting RT Resistance
FS (kHz)
RT (kΩ)
200
200
350
115
500
80.6
750
53.6
1000
39.2
1500
26.1
2000
19.6
2200
17.8
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Feature Description (continued)
The LM43600-Q1 switching action can also be synchronized to an external clock from 200 kHz to 2.2 MHz.
Connect an external clock to the SYNC pin, with proper high speed termination, to avoid ringing. The SYNC pin
should be grounded if not used.
SYNC
EXT CLOCK
RTERM
Figure 41. Frequency Synchronization
The recommendations for the external clock include high level no lower than 2 V, low level no higher than 0.4 V,
duty cycle between 10% and 90% and both positive and negative pulse width no shorter than 80 ns. When the
external clock fails at logic high or low, the LM43600-Q1 will switch at the frequency programmed by the RT
resistor after a time-out period. It is recommended to connect a resistor RT to the RT pin such that the internal
oscillator frequency is the same as the target clock frequency when the LM43600-Q1 is synchronized to an
external clock. This allows the regulator to continue operating at approximately the same switching frequency if
the external clock fails.
The choice of switching frequency is usually a compromise between conversion efficiency and the size of the
circuit. Lower switching frequency implies reduced switching losses (including gate charge losses, switch
transition losses, etc.) and usually results in higher overall efficiency. However, higher switching frequency allows
use of smaller LC output filters and hence a more compact design. Lower inductance also helps transient
response (higher large signal slew rate of inductor current), and reduces the DCR loss. The optimal switching
frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis.
It is related to the input voltage, output voltage, most frequent load current level(s), external component choices,
and circuit size requirement. The choice of switching frequency may also be limited if an operating condition
triggers TON-MIN or TOFF-MIN.
7.3.8 Minimum ON-Time, Minimum OFF-Time and Frequency Foldback at Dropout Conditions
Minimum ON-time, TON-MIN, is the smallest duration of time that the HS switch can be on. TON-MIN is typically 125
ns in the LM43600-Q1. Minimum OFF-time, TOFF-MIN, is the smallest duration that the HS switch can be off. TOFFMIN is typically 200 ns in the LM43600-Q1.
In CCM operation, TON-MIN and TOFF-MIN limits the voltage conversion range given a selected switching frequency.
The minimum duty cycle allowed is
DMIN = TON-MIN × FS
(4)
And the maximum duty cycle allowed is
DMAX = 1 - TOFF-MIN × FS
(5)
Given fixed TON-MIN and TOFF-MIN, the higher the switching frequency the narrower the range of the allowed duty
cycle. In the LM43600-Q1, frequency foldback scheme is employed to extend the maximum duty cycle when
TOFF-MIN is reached. The switching frequency will decrease once longer duty cycle is needed under low VIN
conditions. The switching frequency can be decreased to approximately 1/10 of the programmed frequency by RT
or the synchronization clock. Such wide range of frequency foldback allows the LM43600-Q1 output voltage to
stay in regulation with a much lower supply voltage VIN. This leads to a lower effective dropout voltage. See
Typical Characteristics for more details.
Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution
size and efficiency. The maximum operating supply voltage can be found by
VIN-MAX = VOUT / (FS × TON-MIN )
(6)
At lower supply voltage, the switching frequency will decrease once TOFF-MIN is tripped. The minimum VIN without
frequency foldback can be approximated by
VIN-MIN = VOUT / (1 – FS × TOFF-MIN )
(7)
Taking considerations of power losses in the system with heavy load operation, VIN-MIN is higher than the result
calculated in Equation 7 . With frequency foldback, VIN-MIN is lowered by decreased FS. Figure 42 gives an
example of how FS decreases with decreasing supply voltage VIN at dropout operation.
20
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Feature Description (continued)
Frequency (Hz)
1000000
100000
Load = 0.01 A
Load = 0.1 A
Load = 0.5 A
10000
5.0
5.2
5.4
5.6
5.8
6.0
6.2
6.4
VIN (V)
6.6
6.8
7.0
C001
Figure 42. Switching Frequency Decreases in Dropout Operation
VOUT = 5 V FS = 1 MHz
7.3.9 Internal Compensation and CFF
The LM43600-Q1 is internally compensated with RC = 400 kΩ and CC = 50 pF as shown in Functional Block
Diagram. The internal compensation is designed such that the loop response is stable over the entire operating
frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can
be low with all ceramic capacitors. An external feed-forward cap CFF is recommended to be placed in parallel
with the top resistor divider RFBT for optimum transient performance as shown in Figure 43.
VOUT
RFBT
CFF
FB
RFBB
Figure 43. Feedforward Capacitor for Loop Compensation
The feedforward capacitor CFF in parallel with RFBT places an additional zero before the crossover frequency of
the control loop to boost phase margin. The zero frequency can be found by
fZ-CFF = 1 / (2π × RFBT × CFF).
(8)
An additional pole is also introduced with CFF at the frequency of
fP-CFF = 1 / (2π × CFF × (RFBT // RFBB)).
(9)
Select the CFF so that the bandwidth of the control loop without the CFF is centered between fZ-CFF and fP-CFF. The
zero fZ-CFF adds phase boost at the crossover frequency and improves transient response. The pole fP-CFF helps
maintaining proper gain margin at frequency beyond the crossover.
Designs with different combinations of output capacitors need different CFF. Different types of capacitors have
different Equivalent Series Resistance (ESR). Ceramic capacitors have the smallest ESR and need the most
CFF. Electrolytic capacitors have much larger ESR and the ESR zero frequency
fZ-ESR = 1 / ( 2π × ESR × COUT)
(10)
would be low enough to boost the phase up around the crossover frequency. Designs using mostly electrolytic
capacitors at the output may not need any CFF.
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Feature Description (continued)
The CFF creates a time constant with RFBT that couples in the attenuated output voltage ripple to the FB node. If
the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. It could also couple
too much transient voltage deviation and falsely trip PGOOD thresholds. Therefore, CFF should be calculated
based on output capacitors used in the system. At cold temperatures, the value of CFF might change based on
the tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB
node. To avoid this, more capacitance can be added to the output or the value of CFF can be reduced. See
Detailed Design Procedure for the calculation of CFF.
7.3.10 Bootstrap Voltage (BOOT)
The driver of the HS switch requires a bias voltage higher than VIN when the HS switch is ON. The capacitor
connected between CBOOT and SW pins works as a charge pump to boost voltage on the CBOOT pin to (VSW +
VCC). The boot diode is integrated on the LM43600-Q1 die to minimize the bill of material (BOM). A synchronous
switch is also integrated in parallel with the boot diode to reduce voltage drop on CBOOT. TI recommends a
high-quality ceramic 0.47-µF, 6.3-V or higher capacitor CBOOT.
7.3.11 Power Good (PGOOD)
The LM43600-Q1 has a built-in power-good flag shown on PGOOD pin to indicate whether the output voltage is
within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails or fault
protection. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate DC voltage.
Voltage seen by the PGOOD pin should never exceed 12 V. A resistor divider pair can be used to divide the
voltage down from a higher potential. A typical range of pullup resistor value is 10 kΩ to 100 kΩ.
When the FB voltage is within the power-good band, +4% above and -4% below the internal reference VREF
typically, the PGOOD switch will be turned off and the PGOOD voltage will be pulled up to the voltage level
defined by the pull up resistor or divider. When the FB voltage is outside of the tolerance band, +10 % above or
–10 % below VREF typically, the PGOOD switch will be turned on and the PGOOD pin voltage will be pulled low
to indicate power bad. Both rising and falling edges of the power-good flag have a built-in 220 µs (typical)
deglitch delay.
7.3.12 Overcurrent and Short-Circuit Protection
The LM43600-Q1 is protected from over-current conditions by cycle-by-cycle current limiting on both peak and
valley of the inductor current. Hiccup mode will be activated if a fault condition persists to prevent over heating.
High-side MOSFET over-current protection is implemented by the nature of the Peak Current Mode control. The
HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is
compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. See
Functional Block Diagram for more details. The peak current of the HS switch is limited by the maximum EA
output voltage minus the slope compensation at every switching cycle. The slope compensation magnitude at the
peak current is proportional to the duty cycle.
When the LS switch is turned on, the current going through it is also sensed and monitored. The LS switch will
not be turned OFF at the end of a switching cycle if its current is above the LS current limit ILS-LIMIT. The LS
switch will be kept ON so that inductor current keeps ramping down, until the inductor current ramps below ILSLIMIT. Then the LS switch will be turned OFF and the HS switch will be turned on after a dead time. If the current
of the LS switch is higher than the LS current limit for 32 consecutive cycles and the power-good flag is low,
hiccup current protection mode will be activated. In hiccup mode, the regulator will be shutdown and kept off for
5.5 ms typically before the LM43600-Q1 tries to start again. If over-current or short-circuit fault condition still
exist, hiccup will repeat until the fault condition is removed. Hiccup mode reduces power dissipation under severe
over-current conditions, prevents over heating and potential damage to the device.
Hiccup is only activated when power-good flag is low. Under non-severe over-current conditions when VOUT has
not fallen outside of the PGOOD tolerance band, the LM43600-Q1 will reduce the switching frequency and keep
the inductor current valley clamped at the LS current limit level. This operation mode allows slight over current
operation during load transients without tripping hiccup. If the power-good flag becomes low, hiccup operation
will start after LS current limit is tripped 32 consecutive cycles.
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Feature Description (continued)
7.3.13 Thermal Shutdown
Thermal shutdown is a built-in self protection to limit junction temperature and prevent damages due to over
heating. Thermal shutdown turns off the device when the junction temperature exceeds 160°C typically to
prevent further power dissipation and temperature rise. Junction temperature will reduce after thermal shutdown.
The LM43600-Q1 will attempt to restart when the junction temperature drops to 150°C.
7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the LM43600-Q1. When VEN is below 0.4 V, the device is
in shutdown mode. Both the internal LDO and the switching regulator are off. In shutdown mode the quiescent
current drops to 2.3 µA typically with VIN = 24 V. The LM43600-Q1 also employs undervoltage lockout protection.
If VCC voltage is below the UVLO level, the output of the regulator will be turned off.
7.4.2 Stand-by Mode
The internal LDO has a lower enable threshold than the regulator. When VEN is above 1.2 V and below the
precision enable falling threshold (1.8 V typically), the internal LDO regulates the VCC voltage at 3.2 V. The
precision enable circuitry is turned on once VCC is above the UVLO threshold. The switching action and voltage
regulation are not enabled unless VEN rises above the precision enable threshold (2.1 V typically).
7.4.3 Active Mode
The LM43600-Q1 is in Active Mode when VEN is above the precision enable threshold and VCC is above its
UVLO level. The simplest way to enable the LM43600-Q1 is to connect the EN pin to VIN. This allows self startup when the input voltage is in the operation range: 3.5 V to 60 V. See Enable (ENABLE) and VCC, UVLO and
BIAS for details on setting these operating levels.
In Active Mode, depending on the load current, the LM43600-Q1 will be in one of four modes:
1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the
peak-to-peak inductor current ripple;
2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of
the peak-to-peak inductor current ripple in CCM operation;
3. Pulse Frequency Modulation (PFM) when switching frequency is decreased at very light load;
4. Fold-back mode when switching frequency is decreased to maintain output regulation at lower supply voltage
VIN.
7.4.4 CCM Mode
Continuous Conduction Mode (CCM) operation is employed in the LM43600-Q1 when the load current is higher
than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed unless the
minimum HS switch ON-time (TON_MIN), the minimum HS switch OFF-time (TOFF_MIN) or LS current limit is
exceeded. Output voltage ripple will be at a minimum in this mode and the maximum output current of 2 A can
be supplied by the LM43600-Q1
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Device Functional Modes (continued)
7.4.5 Light Load Operation
When the load current is lower than half of the peak-to-peak inductor current in CCM, the LM43600-Q1 will
operate in Discontinuous Conduction Mode (DCM), also known as Diode Emulation Mode (DEM). In DCM
operation, the LS FET is turned off when the inductor current drops to 0 A to improve efficiency. Both switching
losses and conduction losses are reduced in DCM, comparing to forced PWM operation at light load.
At even lighter current loads, Pulse Frequency Mode (PFM) is activated to maintain high efficiency operation.
When the HS switch ON-time reduces to TON_MIN or peak inductor current reduces to its minimum IPEAK-MIN, the
switching frequency will reduce to maintain proper regulation. Efficiency is greatly improved by reducing
switching and gate drive losses.
7.4.6 Self-Bias Mode
For highest efficiency of operation, it is recommended that the BIAS pin be connected directly to VOUT when VOUT
≥ 3.3 V. In this self-bias mode of operation, the difference between the input and output voltages of the internal
LDO are reduced and therefore the total efficiency is improved. These efficiency gains are more evident during
light load operation. During this mode of operation, the LM43600-Q1 operates with a minimum quiescent current
of 27 µA (typical). See VCC, UVLO and BIAS for more details.
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM43600-Q1 is a step down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 0.5 A. The following design procedure can be used to select
components for the LM43600-Q1. Alternately, the WEBENCH® software may be used to generate complete
designs. When generating a design, the WEBENCH® software utilizes iterative design procedure and accesses
comprehensive databases of components. See for more details.
8.2 Typical Applications
The LM43600-Q1 only requires a few external components to convert from a wide range of supply voltage to
output voltage. Figure 44 shows a basic schematic when BIAS is connected to VOUT . This is recommended for
VOUT ≥ 3.3 V. For VOUT < 3.3 V, BIAS should be connected to ground, as shown in Figure 45.
L
VIN
VIN
CIN
VOUT
SW
LM43600-Q1
ENABLE
COUT
CBOOT
AGND
CIN
VOUT
SW
LM43600-Q1
CBOOT
COUT
CBOOT
ENABLE
CBIAS
CFF
SS/TRK
SYNC
VIN
CBOOT
BIAS
PGOOD
RT
L
VIN
PGOOD
RFBT
RT
FB
VCC
CVCC
SYNC
RFBB
AGND
PGND
Figure 44. LM43600-Q1 Basic Schematic for
VOUT ≥ 3.3 V, Tie BIAS to VOUT
BIAS
CFF
SS/TRK
RFBT
FB
VCC
CVCC
RFBB
PGND
Figure 45. LM43600-Q1 Basic Schematic for
VOUT < 3.3 V, Tie BIAS to Ground
The LM43600-Q1 also integrates a full list of optional features to aid system design requirements, such as
precision enable, VCC UVLO, programmable soft start, output voltage tracking, programmable switching
frequency, clock synchronization and power-good indication. Each application can select the features for a more
comprehensive design. A schematic with all features utilized is shown in Figure 46.
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Typical Applications (continued)
L
VIN
RENT
VIN
CIN
LM43600-Q1
CBOOT
COUT
VCC
SS/TRK
CSS
CFF
RFBT
CBOOT
FB
ENABLE
RENB
VOUT
SW
RFBB
CVCC
RT
BIAS
RT
CBIAS
SYNC
PGOOD
RSYNC
Tie BIAS to PGND
when VOUT < 3.3 V
PGND
AGND
Figure 46. LM43600-Q1 Schematic with All Features
The external components have to fulfill the needs of the application, but also the stability criteria of the device's
control loop. The LM43600-Q1 is optimized to work within a range of external components. The LC output filter's
inductance and capacitance have to be considered in conjunction, creating a double pole, responsible for the
corner frequency of the converter. Table 2 can be used to simplify the output filter component selection.
Table 2. L, COUT and CFF Typical Values
FS (kHz)
L (µH)
(1)
COUT (µF)
(2)
CFF (pF)
(3) (4)
RT (kΩ)
RFBB (kΩ)
(3) (4)
VOUT = 1 V
200
22
500
none
200
100
500
10
330
none
80.6 or open
100
1000
4.8
180
none
39.2
100
2200
2.2
100
none
17.8
100
200
68
220
44
200
442
500
22
100
33
80.6 or open
442
1000
15
47
18
39.2
442
2200
6.8
27
12
17.8
442
200
82
150
68
200
255
500
33
66
33
80.6 or open
255
1000
18
33
22
39.2
255
2200
6.8
22
18
17.8
255
200
150
33
200
90.9
500
56
22
47
80.6 or open
90.9
1000
27
15
33
39.2
90.9
VOUT = 3.3 V
VOUT = 5 V
VOUT = 12 V
(1)
(2)
(3)
(4)
(5)
26
see note
(5)
Inductor values are calculated based on typical VIN = 12 V. For VOUT = 12 V, typical VIN = 24 V.
All the COUT values are after derating. Add more when using ceramics.
RFBT = 0 Ω for VOUT = 1 V. RFBT = 1 MΩ for all other VOUT settings.
For designs with RFBT other than 1 MΩ, adjust CFF such that (CFF × RFBT) is unchanged and adjust RFBB such that (RFBT / RFBB) is
unchanged.
High ESR COUT gives enough phase boost and CFF not needed.
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Typical Applications (continued)
8.2.1 Design Requirements
A detailed design procedure is described based on a design example. For this design example, use the
parameters listed in Table 3 as the input parameters.
Table 3. Design Example Parameters
DESIGN PARAMETER
VALUE
Input voltage VIN
12 V typical, range from 3.8 V to 36 V
Output voltage VOUT
3.3 V
Input ripple voltage
400 mV
Output ripple voltage
30 mV
Output current rating
0.5 A
Operating frequency
500 kHz
Soft-start time
10 ms
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM43600-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Setpoint
The output voltage of the LM43600-Q1 device is externally adjustable using a resistor divider network. The
divider network is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. The following
equation is used to determine the output voltage of the converter:
VFB
RFBB
RFBT
VOUT VFB
(11)
Choose the value of the RFBT to be 1 MΩ to minimize quiescent current to improve light load efficiency in this
application. With the desired output voltage set to be 3.3 V and the VFB = 1.016 V, the RFBB value can then be
calculated using Equation 11. The formula yields a value of 444.83 kΩ. Choose the closest available value of 442
kΩ for the RFBB. See Adjustable Output Voltage for more details.
8.2.2.3 Switching Frequency
The default switching frequency of the LM43600-Q1 device is set at 500 kHz when RT pin is open circuit. The
switching frequency is selected to be 500 kHz in this application for one less passive components. If other
frequency is desired, use Equation 12 to calculate the required value for RT.
RT(kΩ) = 40200 / Freq (kHz) – 0.6
(12)
For 500 kHz, the calculated RT is 79.8 kΩ and standard value 80.6 kΩ can also be used to set the switching
frequency at 500 kHz.
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8.2.2.4 Input Capacitors
The LM43600-Q1 device requires high frequency input decoupling capacitor(s) and a bulk input capacitor,
depending on the application. The typical recommended value for the high frequency decoupling capacitor is 4.7
µF to 10 µF. A high-quality ceramic type X5R or X7R with sufficiency voltage rating is recommended. The
voltage rating must be greater than the maximum input voltage. To compensate the derating of ceramic
capacitors, a voltage rating of twice the maximum input voltage is recommended. Additionally, some bulk
capacitance can be required, especially if the LM43600-Q1 circuit is not located within approximately 5 cm from
the input voltage source. This capacitor is used to provide damping to the voltage spiking due to the lead
inductance of the cable or trace. The value for this capacitor is not critical but must be rated to handle the
maximum input voltage including ripple. For this design, a 10 µF, X7R dielectric capacitor rated for 100 V is used
for the input decoupling capacitor. The equivalent series resistance (ESR) is approximately 3 mΩ, and the
current-rating is 3 A. Include a capacitor with a value of 0.1 µF for high-frequency filtering and place it as close
as possible to the device pins.
NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will
have a strong influence on the final effective capacitance. Therefore the right capacitor
value has to be chosen carefully. Package size and voltage rating in combination with
dielectric material are responsible for differences between the rated capacitor value and
the effective capacitance.
8.2.2.5 Inductor Selection
The first criterion for selecting an output inductor is the inductance itself. In most buck converters, this value is
based on the desired peak-to-peak ripple current, ΔiL, that flows in the inductor along with the DC load current.
As with switching frequency, the selection of the inductor is a tradeoff between size and cost. Higher inductance
gives lower ripple current and hence lower output voltage ripple with the same output capacitors. Lower
inductance could result in smaller, less expensive component. An inductance that gives a ripple current of 20% to
40% of the 0.5 A at the typical supply voltage is a good starting point. ΔiL = (1/5 to 2/5) x IOUT. The peak-to-peak
inductor current ripple can be found by Equation 13 and the range of inductance can be found by Equation 14
with the typical input voltage used as VIN.
'iL
(VIN
VOUT ) u D
L u FS
(13)
(VIN VOUT ) u D
(V
VOUT ) u D
d L d IN
0.4 u FS u IL MAX
0.2 u FS u IL MAX
(14)
D is the duty cycle of the converter which in a buck converter it can be approximated as D = VOUT / VIN, assuming
no loss power conversion. By calculating in terms of amperes, volts, and megahertz, the inductance value will
come out in micro Henries. The inductor ripple current ratio is defined by:
'iL
r
IOUT
(15)
The second criterion is the inductor saturation current rating. The inductor should be rated to handle the
maximum load current plus the ripple current:
IL-PEAK = ILOAD-MAX + Δ iL
(16)
The LM43600-Q1 has both valley current limit and peak current limit. During an instantaneous short, the peak
inductor current can be high due to a momentary increase in duty cycle. The inductor current rating should be
higher than the HS current limit. It is advised to select an inductor with a larger core saturation margin and
preferably a softer roll off of the inductance value over load current.
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In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low
of an inductance can generate too large of an inductor current ripple such that over current protection at the full
load could be falsely triggered. It also generates more conduction loss, since the RMS current is slightly higher
relative that with lower current ripple at the same DC current. Larger inductor current ripple also implies larger
output voltage ripple with the same output capacitors. With peak current mode control, it is not recommended to
have too small of an inductor current ripple. Enough inductor current ripple improves signal-to-noise ratio on the
current comparator and makes the control loop more immune to noise.
Once the inductance is determined, the type of inductor must be selected. Ferrite designs have very low core
losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and
preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when
the peak design current is exceeded. The ‘hard’ saturation results in an abrupt increase in inductor ripple current
and consequent output voltage ripple. Do not allow the core to saturate!
For the design example, a standard 22 μH inductor from Würth, Coiltronics, or Vishay can be used for the 3.3 V
output with plenty of current rating margin.
8.2.2.6 Output Capacitor Selection
The device is designed to be used with a wide variety of LC filters. It is generally desired to use as little output
capacitance as possible to keep cost and size down. The output capacitor (s), COUT, should be chosen with
care since it directly affects the steady state output voltage ripple, loop stability and the voltage over/undershoot
during load current transients.
The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple going
through the equivalent series resistance (ESR) of the output capacitors:
ΔVOUT-ESR = ΔiL × ESR
(17)
The other is caused by the inductor current ripple charging and discharging the output capacitors:
ΔVOUT-C = ΔiL/ ( 8 × FS × COUT )
(18)
The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the
sum of the two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation in the presence of large current steps and fast slew rates. When a fast large load transient happens,
output capacitors provide the required charge before the inductor current can slew to the appropriate level. The
initial output voltage step is equal to the load current step multiplied by the ESR. VOUT continues to droop until
the control loop response increases or decreases the inductor current to supply the load. To maintain a small
over- or under-shoot during a transient, small ESR and large capacitance are desired. But these also come with
higher cost and size. Thus, the motivation is to seek a fast control loop response to reduce the output voltage
deviation.
For a given input and output requirement, Equation 19 an approximation for an absolute minimum output capacitr
required:
COUT !
ª§ r 2
·
1
u «¨ u (1 Dc) ¸
¨
¸
(FS u r u 'VOUT / IOUT ) ¬«© 12
¹
º
Dc u (1 r) »
¼»
(19)
Along with this for the same requirement, calculate the maximum ESR per Equation 20:
ESR
Dc
1
u ( 0.5)
FS u COUT r
where
•
•
•
•
•
r = Ripple ratio of the inductor ripple current (ΔIL / IOUT)
ΔVOUT = target output voltage undershoot
D’ = 1 – duty cycle
FS = switching frequency
IOUT = load current
(20)
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A general guideline for COUT range is that COUT should be larger than the minimum required output capacitance
calculated by Equation 19, and smaller than 10 times the minimum required output capacitance or 1 mF. In
applications with VOUT less than 3.3 V, it is critical that low ESR output capacitors are selected. This will limit
potential output voltage overshoots as the input voltage falls below the device normal operating range. To
optimize the transient behavior a feed-forward capacitor could be added in parallel with the upper feedback
resistor. For this design example, two 47 µF,10 V, X7R ceramic capacitors are used in parallel.
8.2.2.7 Feedvorward Capacitor
The LM43600-Q1 is internally compensated and the internal R-C values are 400 kΩ and 50 pF, respectively.
Depending on the VOUT and frequency FS, if the output capacitor COUT is dominated by low ESR (ceramic types)
capacitors, it could result in low phase margin. To improve the phase boost an external feedforward capacitor
CFF can be added in parallel with RFBT. CFF is chosen such that phase margin is boosted at the crossover
frequency without CFF. A simple estimation for the crossover frequency without CFF (fx) is shown in Equation 21,
assuming COUT has very small ESR.
1.5
fx
VOUT u COUT
(21)
Equation 22 for CFF was tested:
CFF
1
1
u
2Sfx
RFBT u (RFBT / /RFBB )
(22)
Equation 22 indicates that the crossover frequency is geometrically centered on the zero and pole frequencies
caused by the CFF capacitor.
For designs with higher ESR, CFF is not needed when COUT has very high ESR and CFF calculated from
Equation 22 should be reduced with medium ESR. Table 2 can be used as a quick starting point.
For the application in this design example, a 33-pF COG capacitor is selected.
8.2.2.8 Bootstrap Capacitors
Every LM43600-Q1 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor is 0.47
μF and rated at 6.3 V or higher. The bootstrap capacitor is located between the SW pin and the CBOOT pin. The
bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature
stability.
8.2.2.9 VCC Capacitor
The VCC pin is the output of an internal LDO for LM43600-Q1. The input for this LDO comes from either VIN or
BIAS (please refer to Functional Block Diagram for LM43600-Q1). To insure stability of the part, place a
minimum of 2.2 µF, 10 V capacitor from this pin to ground.
8.2.2.10 BIAS Capacitors
For an output voltage of 3.3 V and greater, the BIAS pin can be connected to the output in order to increase light
load efficiency. This pin is an input for the VCC LDO. When BIAS is not connected, the input for the VCC LDO
will be internally connected into VIN. Because this is an LDO, the voltage differences between the input and
output will affect the efficiency of the LDO. If necessary, a capacitor with a value of 1 μF can be added close to
the BIAS pin as an input capacitor for the LDO.
30
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8.2.2.11 Soft-Start Capacitors
The user can leave the SS/TRK pin floating, and the LM43600-Q1 will implement a soft start time of 4.1 ms
typically. In order to use an external soft start capacitor, the capacitor should be sized such that the soft start
time will be longer than 4.1 ms. Use the following equation in order to calculate the soft start capacitor value:
CSS ISSC u t SS
where
•
•
•
CSS = soft-start capacitor value (µF)
ISS = soft-start charging current (µA)
tSS = desired soft-start time (s)
(23)
For the desired soft-start time of 10 ms and soft start charging current of 2.2 µA, Equation 23 yields a soft-start
capacitor value of 0.022 µF.
8.2.2.12 Undervoltage Lockout Setpoint
The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. RENT
is connected between VIN and the EN pin of the LM43600-Q1 device. RENB is connected between the EN pin
and the GND pin. The UVLO has two thresholds, one for power up when the input voltage is rising and one for
power down or brown outs when the input voltage is falling. The following equation can be used to determine the
VIN (UVLO) level.
VEN = VIN-UVLO × RENB / (RENB + RENT)
(24)
The EN rising threshold for LM43600-Q1 is set to be 2.2 V. Choose the value of RENB to be 1 MΩ to minimize
input current going into the converter. If the desired VIN (UVLO) level is at 3.5 V, then the value of RENT can be
calculated using the equation above and yield a value of 590 kΩ.
8.2.2.13 PGOOD
A typical pullup resistor value is 10 kΩ to 100 kΩ from the PGOOD pin to a voltage no higher than 12 V. If it is
desired to pull up the PGOOD pin to a voltage higher than 12 V, a resistor can be added from the PGOOD pin to
ground to divide the voltage seen by the PGOOD pin to a value no higher than 12 V.
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8.2.3 Application Performance Curves
See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
100
90
VOUT = 1 V FS = 500 kHz
80
RT
LM43600-Q1 SW
CBOOT
CBOOT
0.47 µF
Efficiency (%)
70
L=10 µH
VOUT
COUT
330 µF
BIAS
CBIAS
1 µF
VCC
CVCC
2.2 µF
RFBB
100
kŸ
FB
60
50
40
VIN = 3.5V
30
VIN = 5V
20
VIN = 8V
10
VIN = 12V
0
0.001
0.01
0.1
Load Current (A)
VOUT = 1 V
FS = 500 kHz
VIN = 12 V
VOUT = 1 V
Figure 47. BOM for VOUT = 1 V FS = 500 kHz
C001
FS = 500 kHz
Figure 48. Efficiency
1.04
VDROP_ON_0.1Ÿ_LOAD
(50 mV/DIV)
1.03
Vout (V)
1.02
VOUT (50 mV/DIV)
1.01
1.00
VIN = 3.5V
VIN = 5V
0.99
IL (500 mA/DIV)
VIN = 8V
VIN = 12V
0.98
0.001
0.01
Time (200 µs/DIV)
0.1
Load Current (A)
VOUT = 1 V
C011
FS = 500 kHz
VOUT = 1 V
Figure 49. Output Voltage Regulation
FS = 500 kHz
VIN = 12 V
Figure 50. Load Transient Between 0 A and 0.5 A
0.6
VDROP_ON_0.1Ÿ_LOAD
(50 mV/DIV)
0.5
Current (A)
0.4
VOUT (50 mV/DIV)
0.3
0.2
R,JA = 10 ƒC/W
IL (500 mA/DIV)
0.1
R,JA = 20 ƒC/W
R,JA = 30 ƒC/W
0
Time (200 µs/DIV)
50
60
70
80
90
100
Temperature (ƒC)
VOUT = 1 V
FS = 500 kHz
VIN = 12 V
VOUT = 1 V
Figure 51. Load Transient Between 0.05 A and 0.5 A
32
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FS = 500 kHz
110
120
C001
VIN = 12 V
Figure 52. Derating Curve
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See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
100
90
VOUT = 3.3 V FS = 500 kHz
80
RT
LM43600-Q1 SW
CBOOT
Efficiency (%)
70
L=22 µH
VOUT
CBOOT
0.47 µF
COUT
100 µF
CBIAS
1 µF
CFF
BIAS
VCC
CVCC
2.2 µF
RFBT
1 MŸ
33 pF
FB
60
50
VIN = 8V
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
40
30
20
RFBB
442
kŸ
10
0
0.001
0.01
0.1
Load Current (A)
VOUT = 3.3 V
FS = 500 kHz
VIN = 12 V
VOUT = 3.3 V
Figure 54. Efficiency
3.40
3.5
3.38
3.4
3.36
3.3
3.34
3.2
3.32
3.1
VOUT (V)
Vout (V)
Figure 53. BOM for VOUT = 3.3 V FS = 500 kHz
3.30
3.28
3.26
VIN = 8V
3.24
2.9
Load = 0.2A
Load = 0.3A
2.7
VIN = 24V
VIN = 28V
3.20
0.001
3.0
2.8
VIN = 12V
VIN = 18V
3.22
C002
FS = 500 kHz
Load = 0.4A
2.6
VIN = 36V
Load = 0.5A
2.5
0.01
0.1
3.5
Load Current (A)
VOUT = 3.3 V
3.7
3.9
4.1
4.3
4.5
VIN (V)
C012
FS = 500 kHz
VOUT = 3.3 V
Figure 55. Output Voltage Regulation
C022
FS = 500 kHz
Figure 56. Dropout Curve
0.6
VDROP_ON_0.75Ÿ_LOAD
(375 mV/DIV)
0.5
VOUT (200 mV/DIV)
Current (A)
0.4
0.3
0.2
R,JA = 10 ƒC/W
IL (500 mA/DIV)
0.1
R,JA = 20 ƒC/W
R,JA = 30 ƒC/W
0
Time (200 µs/DIV)
50
60
70
80
90
100
110
120
Temperature (ƒC)
VOUT = 3.3 V
FS = 500 kHz
VIN = 12 V
VOUT = 3.3 V
Figure 57. Load Transient Between 0.05 A and 0.5 A
FS = 500 kHz
C001
VIN = 12 V
Figure 58. Derating Curve
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See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
100
90
VOUT = 5 V FS = 500 kHz
80
RT
LM43600-Q1 SW
CBOOT
Efficiency (%)
70
L=33 µH
VOUT
CBOOT
0.47 µF
COUT
66 µF
CBIAS
1 µF
CFF
VCC
33 pF
FB
50
40
VIN = 12V
RFBT
1 MŸ
30
VIN = 18V
RFBB
255
kŸ
10
BIAS
CVCC
2.2 µF
60
VIN = 24V
20
VIN = 28V
VIN = 36V
0
0.001
0.01
0.1
Load Current (A)
VOUT = 5 V
FS = 500 kHz
VIN = 12 V
VOUT = 5 V
C003
FS = 500 kHz
Figure 59. BOM for VOUT = 5 V FS = 500 kHz
Figure 60. Efficiency
5.2
5.20
5.15
5.0
4.8
5.05
VOUT (V)
Vout (V)
5.10
5.00
4.95
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
VIN = 36V
4.90
4.85
4.80
0.001
0.01
Load = 0.2A
4.4
Load = 0.3A
4.2
Load = 0.4A
Load = 0.5A
4.0
0.1
5.0
Load Current (A)
VOUT = 5 V
4.6
5.2
5.4
5.6
5.8
6.0
VIN (V)
C013
FS = 500 kHz
VOUT = 5 V
Figure 61. Output Voltage Regulation
C023
FS = 500 kHz
Figure 62. Dropout Curve
0.6
VDROP_ON_0.5Ÿ_LOAD
(200 mV/DIV)
0.5
VOUT (200 mV/DIV)
Current (A)
0.4
0.3
0.2
R,JA = 10 ƒC/W
IL (500 mA/DIV)
0.1
R,JA = 20 ƒC/W
R,JA = 30 ƒC/W
0
Time (200 µs/DIV)
50
60
70
80
90
100
Temperature (ƒC)
VOUT = 5 V
FS = 500 kHz
VIN = 12 V
VOUT = 5 V
Figure 63. Load Transient Between 0.05 A and 0.5 A
34
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FS = 500 kHz
110
120
C001
VIN = 12 V
Figure 64. Derating Curve
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SNVSA99C – JULY 2015 – REVISED NOVEMBER 2017
See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
100
90
VOUT = 5 V FS = 200 kHz
80
RT
RT
200
kŸ
LM43600-Q1 SW
CBOOT
CBOOT
0.47 µF
Efficiency (%)
70
L=82 µH
VOUT
COUT
150 µF
BIAS
CBIAS
1 µF
VCC
CVCC
2.2 µF
68 pF
FB
VIN = 8V
50
VIN = 12V
40
VIN = 18V
30
RFBT
1 MŸ
CFF
60
VIN = 24V
20
RFBB
255
kŸ
VIN = 28V
10
VIN = 36V
0
0.001
0.01
0.1
Load Current (A)
VOUT = 5 V
FS = 200 kHz
VIN = 12 V
VOUT = 5 V
Figure 65. BOM for VOUT = 5 V FS = 200 kHz
Figure 66. Efficiency
5.15
5.2
5.10
5.0
5.05
4.8
VOUT (V)
Vout (V)
C004
FS = 200 kHz
5.00
4.95
4.6
Load = 0.2A
4.4
4.90
Load = 0.3A
VIN = 8V
VIN = 12V
VIN = 18V
Load = 0.4A
4.2
4.85
VIN = 24V
4.80
0.001
VIN = 28V
VIN = 36V
Load = 0.5A
4.0
0.01
0.1
5.0
Load Current (A)
VOUT = 5 V
5.2
5.4
5.6
5.8
6.0
VIN (V)
C014
FS = 200 kHz
VOUT = 5 V
Figure 67. Output Voltage Regulation
C024
FS = 200 kHz
Figure 68. Dropout Curve
0.6
VDROP_ON_0.75Ÿ_LOAD
(500 mV/DIV)
0.5
VOUT (200 mV/DIV)
Current (A)
0.4
0.3
0.2
R,JA = 10 ƒC/W
IL (500 mA/DIV)
0.1
R,JA = 20 ƒC/W
R,JA = 30 ƒC/W
0
Time (200 µs/DIV)
50
60
70
80
90
100
110
120
Temperature (ƒC)
VOUT = 5 V
FS = 200 kHz
VIN = 12 V
VOUT = 5 V
Figure 69. Load Transient Between 0.05 A and 0.5 A
FS = 200 kHz
C001
VIN = 12 V
Figure 70. Derating Curve
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See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
100
90
VOUT = 5 V FS = 1 MHz
80
RT
RT
39.2
kŸ
Efficiency (%)
70
L=18 µH
VOUT
LM43600-Q1 SW
CBOOT
CBOOT
0.47 µF
COUT
33 µF
CBIAS
1 µF
CFF
BIAS
VCC
CVCC
2.2 µF
22 pF
FB
60
50
40
RFBT
1 MŸ
30
RFBB
255
kŸ
10
VIN = 12V
VIN = 18V
20
VIN = 24V
VIN = 28V
0
0.001
0.01
0.1
Load Current (A)
VOUT = 5 V
FS = 1 MHz
VIN = 12 V
VOUT = 5 V
C005
FS = 1 MHz
Figure 71. BOM for VOUT = 5 V FS = 1 MHz
VIN = 12 V
Figure 72. Efficiency
5.2
5.20
5.15
5.0
4.8
5.05
VOUT (V)
Vout (V)
5.10
5.00
4.95
4.6
Load = 0.2A
4.4
Load = 0.3A
VIN = 12V
VIN = 18V
VIN = 24V
VIN = 28V
4.90
4.85
4.80
0.001
0.01
Load = 0.5A
4.0
0.1
5.0
Load Current (A)
VOUT = 5 V
Load = 0.4A
4.2
5.2
5.4
5.6
5.8
6.0
VIN (V)
C015
FS = 1 MHz
VOUT = 5 V
Figure 73. Output Voltage Regulation
C025
FS = 1 MHz
Figure 74. Dropout Curve
0.6
VDROP_ON_0.75Ÿ_LOAD
(375 mV/DIV)
0.5
VOUT (200 mV/DIV)
Current (A)
0.4
0.3
0.2
R,JA = 10 ƒC/W
IL (500 mA/DIV)
0.1
R,JA = 20 ƒC/W
R,JA = 30 ƒC/W
0
Time (200 µs/DIV)
50
60
70
80
90
100
Temperature (ƒC)
VOUT = 5 V
FS = 1 MHz
VIN = 12 V
VOUT = 5 V
Figure 75. Load Transient Between 0.05 A and 0.5 A
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FS = 1 MHz
110
120
C001
VIN = 12 V
Figure 76. Derating Curve
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See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
100
90
VOUT = 5 V FS = 2.2 MHz
80
RT
RT
17.8
kŸ
Efficiency (%)
70
L=6.8 µH
VOUT
LM43600-Q1 SW
CBOOT
CBOOT
0.47 µF
COUT
22 µF
CBIAS
1 µF
CFF
BIAS
VCC
CVCC
2.2 µF
18 pF
FB
60
50
40
RFBT
1 MŸ
30
RFBB
255
kŸ
10
20
VIN = 12V
0
0.001
0.01
0.1
Load Current (A)
VOUT = 5 V
FS = 2.2 MHz
VIN = 12 V
VOUT = 5 V
C006
FS = 2.2 MHz
Figure 77. BOM for VOUT = 5 V FS = 2.2 MHz
VIN = 12 V
Figure 78. Efficiency
5.2
5.20
5.15
5.0
4.8
5.05
VOUT (V)
Vout (V)
5.10
5.00
4.95
4.6
Load = 0.2A
4.4
Load = 0.3A
4.90
4.2
4.85
Load = 0.4A
VIN = 12V
4.80
0.001
Load = 0.5A
4.0
0.01
0.1
5.0
Load Current (A)
VOUT = 5 V
5.2
5.4
5.6
5.8
6.0
VIN (V)
C016
FS = 2.2 MHz
VOUT = 5 V
Figure 79. Output Voltage Regulation
C026
FS = 2.2 MHz
Figure 80. Dropout Curve
0.6
VDROP_ON_0.75Ÿ_LOAD
(375 mV/DIV)
0.5
VOUT (200 mV/DIV)
Current (A)
0.4
0.3
0.2
R,JA = 10 ƒC/W
IL (500 mA/DIV)
0.1
R,JA = 20 ƒC/W
R,JA = 30 ƒC/W
0
Time (200 µs/DIV)
50
60
70
80
90
100
110
120
Temperature (ƒC)
VOUT = 5 V
FS = 2.2 MHz
VIN = 12 V
VOUT = 5 V
Figure 81. Load Transient Between 0.05 A and 0.5 A
FS = 2.2 MHz
C001
VIN = 12 V
Figure 82. Derating Curve
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See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
100
90
VOUT = 12 V FS = 500 kHz
80
RT
LM43600-Q1 SW
CBOOT
Efficiency (%)
70
L=56 µH
VOUT
CBOOT
0.47 µF
COUT
22 µF
CBIAS
1 µF
CFF
BIAS
VCC
CVCC
2.2 µF
RFBT
1 MŸ
47 pF
FB
60
50
VIN = 24V
40
30
VIN = 28V
20
RFBB
90.9
kŸ
10
VIN = 36V
0
0.001
0.01
0.1
Load Current (A)
VOUT = 12 V
FS = 500 kHz
VIN = 24 V
VOUT = 12 V
Figure 83. BOM for VOUT = 12 V FS = 500 kHz
C007
FS = 500 kHz
Figure 84. Efficiency
12.5
12.4
12.4
12.2
12.3
12.0
12.1
VOUT (V)
Vout (V)
12.2
12.0
11.9
11.8
VIN = 24V
11.7
VIN = 28V
11.6
VIN = 36V
11.5
0.001
0.01
0.1
Load Current (A)
VOUT = 12 V
11.8
11.6
Load = 0.2A
11.4
Load = 0.3A
11.2
Load = 0.4A
Load = 0.5A
11.0
12.0
12.5
13.0
13.5
14.0
VIN (V)
C017
FS = 500 kHz
VOUT = 12 V
Figure 85. Output Voltage Regulation
C027
FS = 500 kHz
Figure 86. Dropout Curve
0.6
0.5
ILOAD (500 mA/DIV)
VOUT (500 mV/DIV)
Current (A)
0.4
0.3
0.2
R,JA = 10 ƒC/W
IL (500 mA/DIV)
0.1
R,JA = 20 ƒC/W
R,JA = 30 ƒC/W
0
Time (200 µs/DIV)
50
60
70
80
90
100
Temperature (ƒC)
VOUT = 12 V
FS = 500 kHz
VIN = 24 V
VOUT = 12 V
Figure 87. Load Transient Between 0.05 A and 0.5 A
38
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FS = 500 kHz
110
120
C001
VIN = 24 V
Figure 88. Derating Curve
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0.6
0.6
0.5
0.5
0.4
0.4
Current (A)
Current (A)
See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
0.3
0.2
0.3
0.2
Vin = 12V
Vin = 12V
Vin = 24V
0.1
Vin = 24V
0.1
Vin = 36V
Vin = 36V
0
0
50
60
70
80
90
100
110
120
Temperature (ƒC)
VOUT = 3.3 V
FS = 500 kHz
50
RθJA = 20 °C/W
80
VOUT = 5 V
90
100
110
120
FS = 500 kHz
C001
RθJA = 20 °C/W
Figure 90. Derating Curve with RθJA = 20 °C/W
0.6
0.6
0.5
0.5
0.4
0.4
Current (A)
Current (A)
70
Temperature (ƒC)
Figure 89. Derating Curve with RθJA = 20 °C/W
0.3
0.2
0.3
0.2
Vin = 12V
Vin = 12V
Vin = 24V
0.1
Vin = 24V
0.1
Vin = 36V
Vin = 36V
0
0
50
60
70
80
90
100
110
120
Temperature (ƒC)
VOUT = 5 V
FS = 200 kHz
50
60
70
80
90
100
RθJA = 20 °C/W
VOUT = 5 V
FS = 1 MHz
C001
RθJA = 20 °C/W
1.E+06
Switching Frequency (Hz)
1.E+05
1.E+04
VIN = 8V
1.E+05
1.E+04
VIN = 12V
VIN = 24V
VIN = 12V
VIN = 24V
0.010
0.100
LOAD CURRENT (A)
VOUT = 3.3 V
120
Figure 92. Derating Curve with RθJA = 20 °C/W
1.E+06
1.E+03
0.001
110
Temperature (ƒC)
C001
Figure 91. Derating Curve with RθJA = 20 °C/W
Switching Frequency (Hz)
60
C001
1.000
1.E+03
0.001
VOUT = 5 V
Figure 93. Switching Frequency vs IOUT in PFM Operation
0.100
1.000
LOAD CURRENT (A)
C006
FS = 500 kHz
VIN = 36V
0.010
C007
FS = 1 MHz
Figure 94. Switching Frequency vs IOUT in PFM Operation
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See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
SW (10 V/DIV)
SW (10 V/DIV)
VOUT (5 mV/DIV)
VOUT (5 mV/DIV)
IL (500 mA/DIV)
IL (500 mA/DIV)
Time (2 µs/DIV)
VOUT = 3.3 V
FS = 500 kHz
Time (2 µs/DIV)
IOUT = 0.5 A
Figure 95. Switching Waveform in CCM Operation
VOUT = 3.3 V
FS = 500 kHz
IOUT =10 mA
Figure 96. Switching Waveform in DCM Operation
SW (10 V/DIV)
PGOOD (2 V/DIV)
VOUT (5 mV/DIV)
VOUT (2 V/DIV)
IL (500 mA/DIV)
IL (500 mA/DIV)
Time (500 µs/DIV)
VOUT = 3.3 V
FS = 500 kHz
Time (2 ms/DIV)
IOUT = 0 mA
Figure 97. Switching Waveform in PFM Operation
VIN = 12 V
VOUT = 3.3 V
Figure 98. Startup Into Full Load with Internal Soft-Start
Rate
PGOOD (2 V/DIV)
PGOOD (2 V/DIV)
VOUT (2 V/DIV)
VOUT (2 V/DIV)
IL (100 mA/DIV)
IL (250 mA/DIV)
Time (2 ms/DIV)
VIN = 12 V
VOUT = 3.3 V
Time (2 ms/DIV)
RLOAD = 13.2 Ω
Figure 99. Startup Into Half Load with Internal Soft-Start
Rate
40
RLOAD = 6.6 Ω
VIN = 12 V
VOUT = 3.3 V
RLOAD = 33 Ω
Figure 100. Startup Into 100 mA with Internal Soft-Start
Rate
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See Table 2 for bill of materials for each VOUT and FS combination. Unless otherwise stated, application performance curves
were taken at TA = 25 °C.
PGOOD (10 V/DIV)
PGOOD (2 V/DIV)
VOUT (1 V/DIV)
VOUT (10 V/DIV)
IL (500 mA/DIV)
IL (500 mA/DIV)
Time (2 ms/DIV)
VIN = 12 V
VOUT = 3.3 V
Time (5 ms/DIV)
RLOAD = Open
VIN = 24 V
Figure 101. Startup Into 1 V Pre-biased Voltage
VOUT = 12 V
RLOAD = 6 Ω
Figure 102. Startup with External Capacitor CSS
VIN (10 V/DIV)
VIN (10 V/DIV)
VOUT (50 mV/DIV)
VOUT (50 mV/DIV)
IL (500 mA/DIV)
IL (500 mA/DIV)
Time (2 ms/DIV)
VOUT = 3.3 V
FS = 500 kHz
Time (2 ms/DIV)
IOUT = 0.25 A
Figure 103. Line Transient: VIN Transitions Between 12 V
and 36 V
VOUT = 3.3 V
FS = 500 kHz
IOUT = 0.5 A
Figure 104. Line Transient: VIN Transitions Between 12 V
and 36 V
PGOOD (5 V/DIV)
VOUT (2 V/DIV)
IL (500 mA/DIV)
Time (10 ms/DIV)
VOUT = 3.3 V
FS = 500 kHz
VIN = 12 V
Figure 105. Short-Circuit Protection and Recover
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9 Power Supply Recommendations
The LM43600-Q1 is designed to operate from an input voltage supply range between 3.5 V and 60 V. This input
supply must be able to withstand the maximum input current and maintain a voltage above 3.5 V. The resistance
of the input supply rail must be low enough that an input current transient does not cause a high enough drop at
the LM43600-Q1 supply voltage that can cause a false UVLO fault triggering and system reset.
If the input supply is located more than a few inches from the LM43600-Q1 additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47 µF
or 100 µF electrolytic capacitor is a typical choice.
10 Layout
The performance of any switching converter depends as much upon the layout of the PCB as the component
selection. The following guidelines will help users design a PCB with the best power conversion performance,
thermal performance, and minimized generation of unwanted EMI.
10.1 Layout Guidelines
1. Place ceramic high frequency bypass CIN as close as possible to the LM43600-Q1 VIN and PGND pins.
Grounding for both the input and output capacitors should consist of localized top side planes that connect to
the PGND pins and PAD.
2. Place bypass capacitors for VCC and BIAS close to the pins and ground the bypass capacitors to device
ground.
3. Minimize trace length to the FB pin. Both feedback resistors, RFBT and RFBB must be located close to the FB
pin. Place CFF directly in parallel with RFBT. If VOUT accuracy at the load is important, make sure VOUT sense
is made at the load. Route VOUT sense path away from noisy nodes and preferably through a layer on the
other side of a shielding layer.
4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path.
5. Have a single point ground connection to the plane. The ground connections for the feedback, soft-start, and
enable components should be routed to the ground plane. This prevents any switched or load currents from
flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load
regulation or erratic output voltage ripple behavior.
6. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
7. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the
ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be
connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking
to keep the junction temperature below 125°C.
10.1.1 Compact Layout for EMI Reduction
Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to
minimize radiated EMI is to identify the pulsing current path and minimize the area of the path. In Buck
converters, the pulsing current path is from the VIN side of the input capacitors to HS switch, to the LS switch,
and then return to the ground of the input capacitors, as shown in Figure 106.
BUCK
CONVERTER
VIN
VIN
SW
L
CIN
VOUT
COUT
PGND
High di/dt
current
PGND
Figure 106. Buck Converter High di / dt Path
42
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Layout Guidelines (continued)
High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of
the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the
key to EMI reduction.
The SW pin connecting to the inductor should be as short as possible, and just wide enough to carry the load
current without excessive heating. Short, thick traces or copper pours (shapes) should be used for high current
conduction path to minimize parasitic resistance. The output capacitors should be place close to the VOUT end of
the inductor and closely grounded to PGND pin and exposed PAD.
The bypass capacitors on VCC and BIAS pins should be placed as close as possible to the pins respectively and
closely grounded to PGND and the exposed PAD.
10.1.2 Ground Plane and Thermal Considerations
It is recommended to use one of the middle layers as a solid ground plane. Ground plane provides shielding for
sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. The AGND and
PGND pins should be connected to the ground plane using vias right next to the bypass capacitors. PGND pins
are connected to the source of the internal LS switch. They should be connected directly to the grounds of the
input and output capacitors. The PGND net contains noise at the switching frequency and may bounce due to
load variations. The PGND trace, as well as PVIN and SW traces, should be constrained to one side of the
ground plane. The other side of the ground plane contains much less noise and should be used for sensitive
routes.
It is recommended to provide adequate device heat sinking by utilizing the PAD of the IC as the primary thermal
path. Use a minimum 4 by 4 array of 10 mil thermal vias to connect the PAD to the system ground plane for heat
sinking. The vias should be evenly distributed under the PAD. Use as much copper as possible for system
ground plane on the top and bottom layers for the best heat dissipation. It is recommended to use a four-layer
board with the copper thickness, for the four layers, starting from the top one, 2 oz / 1 oz / 1 oz / 2 oz. Four layer
boards with enough copper thickness and proper layout provides low current conduction impedance, proper
shielding and lower thermal resistance.
The thermal characteristics of the LM43600-Q1 are specified using the parameter RθJA, which characterize the
junction temperature of the silicon to the ambient temperature in a specific system. Although the value of RθJA is
dependant on many variables, it still can be used to approximate the operating junction temperature of the
device. To obtain an estimate of the device junction temperature, one may use the following relationship:
TJ = PD× RθJA + TA
where
•
•
•
•
•
TJ = junction temperature in °C
PD = VIN × IIN × (1 − efficiency) − 1.1 × IOUT × DCR
RθJA = junction-to-ambient thermal resistance of the device in °C/W
TA = ambient temperature in °C.
(25)
The maximum operating junction temperature of the LM43600-Q1 is 125°C. RθJA is highly related to PCB size
and layout, as well as environmental factors such as heat sinking and air flow. Figure 107 shows measured
results of RθJA with different copper area on a 2-layer board and a 4-layer board.
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Layout Guidelines (continued)
50.0
1W @ 0fpm - 2 layer
2W @ 0fpm - 2 layer
R,JA (ƒC/W)
45.0
1W @ 0fpm - 4 layer
2W @ 0fpm - 4 layer
40.0
35.0
30.0
25.0
20.0
20mm x 20mm
30mm x 30mm
40mm x 40mm
Copper Area
50mm x 50mm
C030
Figure 107. Measured RθJA vs PCB Copper Area on a 2-layer Board and a 4-layer Board
10.1.3 Feedback Resistors
To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and
CFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high
impedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces the
trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace
from VOUT to the resistor divider can be long if short path is not available.
If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so will correct
for voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to
the feedback resistor divider should be routed away from the SW node path, the inductor and VIN path to avoid
contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most
important when high value resistors are used to set the output voltage. It is recommended to route the voltage
sense trace on a different layer than the inductor, SW node and VIN path, such that there is a ground plane in
between the feedback trace and inductor / SW node / VIN polygon. This provides further shielding for the voltage
feedback path from switching noises.
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10.2 Layout Example
VOUT distribution point
is away from inductor
and past COUT
VOUT sense point is away
from inductor and past COUT
GND
GND
+
VOUT
As much copper area as possible,
for better thermal performance
COUT
L
Place ceramic bypass caps
close to VIN and PGND pins
CBOOT
SW
PAD (17)
PGND
16
PGND
15
2
SW
3
CBOOT
VIN
14
4
VCC
VIN
13
5
BIAS
EN
12
6
SYNC
SS/TRK
11
7
RT
AGND
10
8
PGOOD
CVCC
Place bypass
caps close to
pins
CBIAS
Ground
bypass caps
to DAP
FB
CIN
9
RFBT
GND
GND
+
1
Place CBOOT
close to pins
VIN
Place RFBB
close to FB
and AGND
RFBB
Trace to
FB short
and thin
Route VOUT
sense trace
away from
SW and VIN
nodes.
Preferably
shielded in an
alternative
layer
CFF
VOUT
sense
As much copper area as possible, for better thermal performance
Preferably use GND Plane as a middle layer for shielding and heat dissipation
Preferably place and route on top layer and use solid copper on bottom layer for heat dissipation
Figure 108. LM43600-Q1 PCB Layout Example
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11 Device and Documentation Support
11.1 Development Support
11.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM43600-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
46
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM43600AQPWPRQ1
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
43600AQ
LM43600AQPWPTQ1
ACTIVE
HTSSOP
PWP
16
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
43600AQ
LM43600QPWPRQ1
NRND
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
43600Q1
LM43600QPWPTQ1
NRND
HTSSOP
PWP
16
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
43600Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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