0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
LM43602DSUT

LM43602DSUT

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    VFDFN16

  • 描述:

    LM43602 3.5V TO 36V, 2A SYNCHRON

  • 数据手册
  • 价格&库存
LM43602DSUT 数据手册
Order Now Product Folder Support & Community Tools & Software Technical Documents LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 LM43602 3.5-V to 36-V, 2-A Synchronous Step-Down Voltage Converter 1 Features 3 Description • • • • • The LM43602 regulator is an easy-to-use synchronous step-down DC-DC converter capable of driving up to 2 A of load current from an input voltage ranging from 3.5 V to 36 V (42-V absolute maximum). The LM43602 provides exceptional efficiency, output accuracy, and dropout voltage in a very small solution size. An extended family is available in 0.5-A, 1-A, and 3-A load current options in pin-to-pin compatible packages. Peak current-mode control is employed to achieve simple control loop compensation and cycleby-cycle current limiting. Optional features such as programmable switching frequency, synchronization, power-good flag, precision enable, internal soft start, extendable soft start, and tracking provide a flexible and easy-to-use platform for a wide range of applications. Discontinuous conduction and automatic frequency modulation at light loads improve light-load efficiency. The family requires few external components and terminal arrangement allows simple, optimum PCB layout. Protection features include thermal shutdown, VCC undervoltage lockout, cycleby-cycle current limit, and output short circuit protection. The LM43602 device is available in a 16lead HTSSOP package (5.1 mm × 6.6 mm × 1.2 mm) and 16-pin VSON package with wettable flanks. 1 • • • • • • • • • • • • 27-µA Quiescent Current in Regulation High Efficiency at Light Load (DCM and PFM) Meets EN55022/CISPR 22 EMI standards Integrated Synchronous Rectification Adjustable Frequency Range: 200 kHz to 2.2 MHz (500 kHz Default) Frequency Synchronization to External Clock Internal Compensation Stable with Almost Any Combination of Ceramic, Polymer, Tantalum, and Aluminum Capacitors Power-Good Flag Soft-Start into a Pre-Biased Load Internal Soft Start: 4.1 ms Extendable Soft-Start Time by External Capacitor Output Voltage Tracking Capability Precision Enable to Program System UVLO Output Short Circuit Protection with Hiccup Mode Overtemperature Thermal Shutdown Protection Create a Custom Design Using the LM43602 with the WEBENCH® Power Designer Device Information 2 Applications Industrial Power Supplies Telecommunications Systems Sub-AM Band Automotive General Purpose Wide VIN Regulation High Efficiency Point-Of-Load Regulation space Simplified Schematic L VIN VIN CIN ENABLE CBOOT CBIAS SS/TRK RT COUT CBOOT BIAS PGOOD CFF RFBT FB SYNC VCC AGND PGND CVCC PACKAGE BODY SIZE HTSSOP (16) 5.10 mm × 6.60 mm VSON (16) 4.10 mm × 5.10 mm LM43602PWPEVM Radiated Emission Graph 12VIN to 3.3 VOUT, FS = 500 kHz, IOUT = 2 A VOUT SW LM43602 LM43602 RFBB 80 Radiated EMI Emissions (dBµV/m) • • • • • ORDER NUMBER Evaluation Board 70 EN 55022 Class B Limit EN 55022 Class A Limit 60 50 40 30 20 10 0 0 200 400 600 800 1000 C001 Frequency (MHz) C001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 4 4 4 5 5 6 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 7.1 Overview ................................................................. 12 7.2 Functional Block Diagram ....................................... 12 7.3 Feature Description................................................. 13 7.4 Device Functional Modes........................................ 20 8 Applications and Implementation ...................... 22 8.1 Application Information............................................ 22 8.2 Typical Applications ................................................ 22 9 Power Supply Recommendations...................... 33 10 Layout................................................................... 33 10.1 Layout Guidelines ................................................. 33 10.2 Layout Example .................................................... 36 11 Device and Documentation Support ................. 37 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 Device Support .................................................... Documentation Support ....................................... Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 37 37 37 38 38 38 38 38 12 Mechanical, Packaging, and Orderable Information ........................................................... 38 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (February 2017) to Revision C Page • No technical changes, editorial only ...................................................................................................................................... 1 • Changed Handling Ratings to ESD Ratings per latest format requirements; move "storage temperature" to Absolute Maximum Ratings table ......................................................................................................................................................... 4 Changes from Revision A (April 2014) to Revision B Page • Added new package ............................................................................................................................................................... 1 • Added pinout drawing ............................................................................................................................................................ 3 • Added pin functions for VSON................................................................................................................................................ 3 • Updated BIAS Pin Abs Max .................................................................................................................................................. 4 • Updating Recommended Operation Voltage for BIAS ........................................................................................................... 4 • Added new Thermal Information (VSON) .............................................................................................................................. 5 • Changed PGOOD Resistance values on EC Table ............................................................................................................... 6 • Updating EN Falling Threshold Figure 13 ............................................................................................................................ 10 • Updating Figure 14 EN Rising Threshold ............................................................................................................................ 10 • Updating Figure 15 EN Hysteresis ...................................................................................................................................... 10 • Added Equation 25 .............................................................................................................................................................. 28 • Added Equation 26 .............................................................................................................................................................. 28 Changes from Original (April 2014) to Revision A • 2 Page Changed device from Product Preview to Production Data ................................................................................................... 1 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 5 Pin Configuration and Functions PWP Package 16-Pin HTSSOP Top View SW 1 SW 2 CBOOT VCC 3 4 BIAS 5 PAD DSU Package 16-Pin VSON Top View 16 15 PGND PGND 14 SW 1 VIN SW 13 VIN 12 EN SW CBOOT 2 3 4 SYNC 6 11 SS/TRK RT PGOOD 7 8 10 AGND 9 FB VCC BIAS 5 SYNC 7 8 RT PAD 6 16 15 PGND 14 13 VIN 12 11 PGND VIN EN 10 SS/TRK FB 9 PGOOD Pin Functions PIN NAME SW CBOOT NUMBER VSON 1,2 1,2,3 P Switching output of the regulator. Internally connected to both power MOSFETs. Connect to power inductor. 3 4 P Boot-strap capacitor connection for high-side driver. Connect a high quality 470-nF capacitor from CBOOT to SW. 4 5 P Internal bias supply output for bypassing. Connect bypass capacitor from this pin to AGND. Do not connect external loading to this pin. Never short this pin to ground during operation. VCC BIAS SYNC RT PGOOD FB AGND SS/TRK 5 6 P Optional internal LDO supply input. To improve efficiency, it is recommended to tie to VOUT when 3.3 V ≤ VOUT ≤ 28 V, or tie to an external 3.3 V or 5 V rail if available. When used, place a bypass capacitor (1 to 10 µF) from this pin to ground. Tie to ground when not in use. 6 7 A Clock input to synchronize switching action to an external clock. Use proper high speed termination to prevent ringing. Connect to ground if not used. 7 8 A Connect a resistor RT from this pin to AGND to program switching frequency. Leave floating for 500 kHz default switching frequency. 8 9 A Open drain output for power-good flag. Use a 10 kΩ to 100 kΩ pull-up resistor to logic rail or other DC voltage no higher than 12 V. 9 10 A Feedback sense input pin. Connect to the midpoint of feedback divider to set VOUT. Do not short this pin to ground during operation. 10 — G Analog ground pin. Ground reference for internal references and logic. Connect to system ground. 11 11 A Soft-start control pin. Leave floating for internal soft-start slew rate. Connect to a capacitor to extend soft start time. Connect to external voltage ramp for tracking. 12 12 A Enable input to the internal LDO and regulator. High = ON and low = OFF. Connect to VIN, or to VIN through resistor divider,or to an external voltage or logic source. Do not float. 13,14 13,14 P Supply input pins to internal LDO and high side power FET. Connect to power supply and bypass capacitors CIN. Path from VIN pin to high frequency bypass CIN and PGND must be as short as possible. 15,16 15,16 G Power ground pins, connected internally to the low side power FET. Connect to system ground, PAD, AGND, ground pins of CIN and COUT. Path to CIN must be as short as possible. — — — Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation path of the die. Must be used for heat sinking to ground plane on PCB. EN VIN PGND PAD (1) DESCRIPTION TYPE (1) TSSOP P = Power, A = Analog, G = Ground Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 3 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) over the recommended operating junction temperature (TJ) range of –40°C to +125°C (unless otherwise noted) PARAMETER MIN MAX VIN to PGND –0.3 42 (2) EN to PGND –0.3 VIN + 0.3 FB, RT, SS/TRK to AGND –0.3 3.6 PGOOD to AGND –0.3 15 SYNC to AGND –0.3 5.5 BIAS to AGND –0.3 30 or VIN (3) AGND to PGND –0.3 0.3 SW to PGND –0.3 VIN + 0.3 SW to PGND less than 10-ns transients –3.5 42 CBOOT to SW –0.3 5.5 VCC to AGND –0.3 3.6 Operating junction temperature TJ –40 125 °C Storage temperature, Tstg –65 150 °C Input voltages Output voltages (1) (2) (3) UNIT V V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. At maximum duty cycle of 0.01% Whichever is lower 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT ±1000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions (1) over the recommended operating junction temperature (TJ) range of –40°C to +125°C (unless otherwise noted) Input voltages PARAMETER MIN MAX VIN to PGND 3.5 36 EN –0.3 VIN FB –0.3 1.1 PGOOD –0.3 12 BIAS input not used –0.3 0.3 BIAS input used 3.3 28 or VIN (2) AGND to PGND –0.1 0.1 1 28 Output voltage VOUT Output current IOUT Temperature Operating junction temperature range, TJ (1) (2) 4 UNIT V V 0 2 A –40 125 °C Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical Characteristics. Whichever is lower Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 6.4 Thermal Information THERMAL METRIC LM43602 (1) (2) HTSSOP VSON (16 PINS) (16 PINS) UNIT 38.9 (3) 31.3 °C/W RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance 24.3 22.8 °C/W RθJB Junction-to-board thermal resistance 19.9 9.6 °C/W ψJT Junction-to-top characterization parameter 0.7 0.2 °C/W ψJB Junction-to-board characterization parameter 19.7 9.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7 1.3 °C/W (1) (2) (3) The package thermal impedance is calculated in accordance with JESD 51-7. Thermal Resistances were simulated on a 4 layer, JEDEC board. See Figure 64 for θJA vs Copper Area Curve. 6.5 Electrical Characteristics Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz. PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN PIN) VIN-MIN-ST Minimum input voltage for start-up ISHDN Shutdown quiescent current VEN = 0 V IQ-NONSW Operating quiescent current (nonswitching) from VIN IBIAS-NONSW IQ-SW 3.8 V 1.2 3.1 µA VEN = 3.3 V VFB = 1.5 V VBIAS = 3.4 V external 5 10 µA Operating quiescent current (nonswitching) from external VBIAS VEN = 3.3 V VFB = 1.5 V VBIAS = 3.4 V external 85 130 µA Operating quiescent current (switching) VEN = 3.3 V IOUT = 0 A RT = open VBIAS = VOUT = 3.3 V RFBT = 1.0 Meg 27 µA ENABLE (EN PIN) VEN-VCC-H Voltage level to enable the internal LDO output VCC VEN-VCC-L Voltage level to disable the internal LDO VENABLE low level output VCC VEN-VOUT-H Precision enable level for switching and regulator output: VOUT VENABLE high level VEN-VOUT-HYS Hysteresis voltage between VOUT precision enable and disable thresholds VENABLE hysteresis –290 ILKG-EN Enable input leakage current VEN = 3.3 V 0.85 3.28 V 3.1 V VENABLE high level 1.2 2 V 2.2 0.525 V 2.42 V mV 1.75 µA INTERNAL LDO (VCC and BIAS PINS) VCC Internal LDO output voltage VCC VIN ≥ 3.8 V VCC rising threshold VCC-UVLO Undervoltage lock out (UVLO) thresholds for VCC VBIAS-ON Internal LDO input change over threshold to BIAS Hysteresis voltage between rising and falling thresholds –520 VBIAS rising threshold 2.94 Hysteresis voltage between rising and falling thresholds –75 mV 3.15 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 V mV 5 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com Electrical Characteristics (continued) Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz. PARAMETER CONDITIONS MIN TYP MAX TJ = 25ºC 1.004 1.011 1.018 TJ = –40ºC to 85ºC 0.994 1.011 1.026 TJ = –40ºC to 125ºC 0.994 UNIT VOLTAGE REFERENCE (FB PIN) Feedback voltage VFB ILKG-FB Input leakage current at FB pin V 1.011 1.030 FB = 1 V 0.2 65 Shutdown threshold 160 °C Recovery threshold 150 °C nA THERMAL SHUTDOWN TSD Thermal shutdown (1) CURRENT LIMIT AND HICCUP IHS-LIMIT Peak inductor current limit 3.65 4.5 5.15 A ILS-LIMIT Inductor current valley limit 1.75 2 2.25 A 1.25 2 2.75 µA SOFT START (SS/TRK PIN) ISSC Soft-start charge current RSSD Soft-start discharge resistance UVLO, TSD, OCP, or EN = 0 V 18 kΩ POWER GOOD (PGOOD PIN) VPGOOD-HIGH Power-good flag overvoltage tripping threshold % of FB voltage VPGOOD-LOW Power-good flag undervoltage tripping threshold % of FB voltage VPGOOD-HYS Power-good flag recovery hysteresis % of FB voltage RPGOOD PGOOD pin pulldown resistance when power bad VEN = 3.3 V 69 150 VEN = 0 V 150 350 High-side MOSFET ON-resistance IOUT = 1 A VBIAS = VOUT = 3.3 V 120 mΩ Low-side MOSFET ON-resistance IOUT = 1 A VBIAS = VOUT = 3.3 V 65 mΩ MOSFETS RDS-ON-HS RDS-ON-LS (1) (2) 110% 77% 113% 88% 6% Ω (2) Specified by design Measured at the pins 6.6 Timing Requirements MIN NOM MAX UNIT CURRENT LIMIT AND HICCUP NOC Hiccup wait cycles when LS current limit tripped 32 Cycles TOC Hiccup retry delay time 5.5 ms 4.1 ms TPGOOD-RISE Power-good flag rising transition deglitch delay 220 µs TPGOOD-FALL Power-good flag falling transition deglitch delay 220 µs SOFT START (SS/TRK PIN) TSS Internal soft-start time when SS pin open circuit POWER GOOD (PGOOD PIN) 6 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 6.7 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SW (SW PIN) tON-MIN (1) Minimum high side MOSFET ONtime 125 165 ns tOFF-MIN (1) Minimum high side MOSFET OFFtime 200 250 ns 500 580 kHz OSCILLATOR (SW and SYNC PINS) FOSC- Oscillator default frequency RT pin open circuit 425 DEFAULT Minimum adjustable frequency FADJ Maximum adjustable frequency With 1% resistors at RT pin Frequency adjust accuracy 200 kHz 2200 kHz 10% VSYNC-HIGH Sync clock high level threshold 2 V VSYNC-LOW Sync clock low level threshold DSYNC-MAX Sync clock maximum duty cycle 90% DSYNC-MIN Sync clock minimum duty cycle 10% TSYNC-MIN Mininum sync clock ON and OFF time (1) 0.4 80 V ns Specified by design Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 7 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com 6.8 Typical Characteristics 100 100 90 90 80 80 Efficiency (%) Efficiency (%) Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz, L = 6.8 µH, COUT = 120 µF, CFF = 100 pF. See Application Performance Curves for Bill of materials for other VOUT and FS combinations. 70 60 70 60 5VIN 50 5VIN 50 12VIN 12VIN 24VIN 40 0.001 24VIN 40 0.01 0.1 1 Current (A) VOUT = 3.3V 0 1 1.5 FS = 500 kHz VOUT = 3.3V 90 90 80 80 Efficiency (%) 100 70 60 FS = 500 kHz 70 60 5VIN 12VIN 50 12VIN 24VIN 24VIN 40 0.001 0.01 0.1 VOUT = 3.3V 40 0.001 1 Current (A) 0.1 1 Current (A) FS = 500 kHz VOUT = 5V C001 FS = 500 kHz Figure 4. Efficiency at Room Temperature 100 100 90 90 80 80 Efficiency (%) Efficiency (%) 0.01 C001 Figure 3. Efficiency at 85°C 70 60 70 60 12VIN 12VIN 50 50 24VIN 24VIN 40 0 0.5 1 1.5 2 Current (A) VOUT = 5V 40 0.001 0.01 FS = 500 kHz 0.1 Current (A) C001 VOUT = 5V Figure 5. Efficiency at Room Temperature 8 C001 Figure 2. Efficiency at Room Temperature 100 50 2 Current (A) Figure 1. Efficiency at Room Temperature Efficiency (%) 0.5 C001 Submit Documentation Feedback 1 C001 FS = 500 kHz Figure 6. Efficiency at 85°C Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 Typical Characteristics (continued) Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz, L = 6.8 µH, COUT = 120 µF, CFF = 100 pF. See Application Performance Curves for Bill of materials for other VOUT and FS combinations. 3.40 5.25 5VIN 3.38 3.36 24VIN 5.10 VOUT (V) VOUT (V) 12VIN 5.15 24VIN 3.34 3.32 3.30 3.28 5.05 5.00 4.95 3.26 4.90 3.24 4.85 3.22 4.80 3.20 0.001 0.01 0.1 VOUT = 3.3V 4.75 0.001 1 Current (A) 0.01 0.1 FS = 500 kHz VOUT = 5V C004 FS = 500 kHz Figure 8. VOUT Regulation 3.5 5.4 3.4 5.2 5.0 VOUT (V) 3.3 3.2 0.1A 4.8 4.6 0.1A 0.5A 1A 1.5A 2A 0.5A 3.1 4.4 1A 1.5A 3.0 4.2 2A 2.9 3.5 3.7 3.9 4.1 4.3 4.0 5.00 5.20 5.40 5.60 5.80 6.00 6.20 6.40 6.60 6.80 7.00 4.5 VIN (V) VOUT = 3.3V VIN (V) C007 FS = 500 kHz VOUT = 5V Figure 9. Dropout Curve C007 FS = 500 kHz Figure 10. Dropout Curve 1000000 Frequency (Hz) 1000000 FREQUENCY (Hz) 1 Current (A) C001 Figure 7. VOUT Regulation VOUT (V) 8VIN 5.20 12VIN 100000 0.1A 0.5A 10000 3.9 4.1 VIN (V) VOUT = 3.3V FS = 500 kHz 4.3 0.5A 1A 1.5A 1.5A 1000 3.7 0.1A 1A 2A 3.5 100000 4.5 2A 10000 5.00 5.20 5.40 5.60 5.80 6.00 6.20 6.40 6.60 6.80 7.00 VIN (V) C007 VOUT = 5V Figure 11. Frequency vs VIN C007 FS = 500 kHz Figure 12. Frequency vs VIN Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 9 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com Typical Characteristics (continued) Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz, L = 6.8 µH, COUT = 120 µF, CFF = 100 pF. See Application Performance Curves for Bill of materials for other VOUT and FS combinations. 2.200 2.000 1.950 2.150 EN Voltage (V) EN Voltage (V) 1.900 1.850 1.800 1.750 2.100 2.050 2.000 1.700 1.950 1.650 1.900 1.600 ±40 ±25 ±10 5 20 35 50 65 80 95 Temperature (deg C) 110 125 ±40 ±25 ±10 5 20 35 50 65 80 95 110 125 Temperature (deg C) C001 Figure 13. EN Falling Threshold vs Junction Temperature C001 Figure 14. EN Rising Threshold vs Junction Temperature 1.020 310 1.015 FB Voltage (V) EN Hysteresis (mV) 300 290 280 270 1.010 1.005 260 1.000 250 ±40 ±25 ±10 5 20 35 50 65 80 95 Temperature (deg C) ±40 ±25 ±10 110 125 5 20 35 50 65 80 95 110 125 Temperature (deg C) C001 C001 Figure 16. FB Voltage vs Junction Temperature Figure 15. EN Hysteresis vs Junction Temperature 4.200 2.200 LS Current Limit (A) HS Current Limit (A) 4.100 4.000 3.900 3.800 2.100 2.000 1.900 3.700 3.600 1.800 ±40 ±25 ±10 5 20 35 50 65 Temperature (deg C) 80 95 110 125 Figure 17. HS Current Limit vs Junction Temperature 10 ±40 ±25 ±10 5 20 35 50 65 Temperature (deg C) C001 80 95 110 125 C001 Figure 18. LS Current Limit vs Junction Temperature Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 Typical Characteristics (continued) 190 90 180 85 170 80 160 75 LS Rds-on (mŸ) HS Rds-on (mŸ) Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz, L = 6.8 µH, COUT = 120 µF, CFF = 100 pF. See Application Performance Curves for Bill of materials for other VOUT and FS combinations. 150 140 130 120 60 55 50 100 45 40 ±40 ±25 ±10 5 20 35 50 65 80 95 Temperature (deg C) ±40 ±25 ±10 110 125 5 20 35 50 65 80 95 110 125 Temperature (deg C) C001 Figure 19. High Side FET On Resistance vs Junction Temperature C001 Figure 20. Low Side FET On Resistance vs Junction Temperature 107.0 Percentage of FB Voltage (%) 112.0 Percentage of FB Voltage (%) 65 110 90 111.5 111.0 110.5 110.0 109.5 109.0 106.5 106.0 105.5 105.0 104.5 104.0 ±40 ±25 ±10 5 20 35 50 65 80 95 Temperature (deg C) 110 125 ±40 ±25 ±10 5 20 35 50 65 80 95 110 125 Temperature (deg C) C001 Figure 21. PGOOD OVP Falling Threshold vs Junction Temperature C001 Figure 22. PGOOD OVP Rising Threshold vs Junction Temperature 98.0 Percentage of FB Voltage (%) 92.0 Percentage of FB Voltage (%) 70 91.0 90.0 89.0 88.0 87.0 86.0 97.0 96.0 95.0 94.0 93.0 92.0 ±40 ±25 ±10 5 20 35 50 65 Temperature (deg C) 80 95 110 125 ±40 ±25 ±10 Figure 23. PGOOD UVP Falling Threshold vs Junction Temperature 5 20 35 50 65 80 95 110 125 Temperature (deg C) C001 C001 Figure 24. PGOOD UVP Rising Threhsold vs Junction Temperature Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 11 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com 7 Detailed Description 7.1 Overview The LM43602 regulator is an easy to use synchronous step-down DC-DC converter that operates from 3.5 V to 36 V supply voltage. It is capable of delivering up to 2 A DC load current with exceptional efficiency and thermal performance in a very small solution size. An extended family is available in 0.5 A, 1A, and 3 A load options in pin to pin compatible packages. The LM43602 employs fixed frequency peak current mode control with Discontinuous Conduction Mode (DCM) and Pulse Frequency Modulation (PFM) mode at light load to achieve high efficiency across the load range. The device is internally compensated, which reduces design time, and requires fewer external components. The switching frequency is programmable from 200 kHz to 2.2 MHz by an external resistor RT. It is default at 500 kHz without RT resistor. The LM43602 is also capable of synchronization to an external clock within the 200-kHz to 2.2-MHz frequency range. The wide switching frequency range allows the device to be optimized to fit small board space at higher frequency, or high efficient power conversion at lower frequency. Optional features are included for more comprehensive system requirements, including power-good (PGOOD) flag, precision enable, synchronization to external clock, extendable soft-start time, and output voltage tracking. These features provide a flexible and easy to use platform for a wide range of applications. Protection features include overtemperature shutdown, VCC undervoltage lockout (UVLO), cycle-by-cycle current limit, and shortcircuit protection with hiccup mode. The family requires few external components and the pin arrangement was designed for simple, optimum PCB layout. The LM43602 device is available in the 16-lead HTSSOP (PWP) and 16-pin VSON packages. 7.2 Functional Block Diagram ENABLE VCC Enable Internal SS ISSC BIAS VCC LDO VIN Precision Enable SS/TRK CBOOT HS I Sense + EA REF RC + ± +± TSD UVLO CC PGOOD AGND OV/UV Detector FB SW PWM CONTROL LOGIC PFM Detector PGood Slope Comp Freq Foldback Zero Cross HICCUP Detector Oscillator LS I Sense FB PGood SYNC 12 PGND RT Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 7.3 Feature Description 7.3.1 Fixed Frequency Peak Current-Mode Controlled Step-Down Regulator The following operating description of the LM43602 will refer to the Functional Block Diagram and to the waveforms in Figure 25. The LM43602 is a step-down Buck regulator with both high-side (HS) switch and lowside (LS) switch (synchronous rectifier) integrated. The LM43602 supplies a regulated output voltage by turning on the HS and LS NMOS switches with controlled ON time. During the HS switch ON time, the SW pin voltage VSW swings up to approximately VIN, and the inductor current iL increases with a linear slope (VIN - VOUT) / L. When the HS switch is turned off by the control logic, the LS switch is turned on after a anti-shoot-through dead time. Inductor current discharges through the LS switch with a slope of -VOUT / L. The control parameter of buck converters are defined as Duty Cycle D = tON / TSW, where tON is the HS switch ON time and TSW is the switching period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal Buck converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN. VSW D = tON / TSW SW Voltage VIN tOFF tON 0 t -VD1 Inductor Current iL TSW ILPK IOUT ûiL t 0 Figure 25. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM) The LM43602 synchronous Buck converter employs peak current mode control topology. A voltage feedback loop is used to get accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak inductor current is sensed from the HS switch and compared to the peak current to control the ON time of the HS switch. The voltage feedback loop is internally compensated, which allows for fewer external components, makes it easy to design, and provides stable operation with almost any combination of output capacitors. The regulator operates with fixed switching frequency in Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). At very light load, the LM43602 will operate in PFM to maintain high efficiency and the switching frequency will decrease with reduced load current. 7.3.2 Light Load Operation DCM operation is employed in the LM43602 when the inductor current valley reaches zero. The LM43602 will be in DCM when load current is less than half of the peak-to-peak inductor current ripple in CCM. In DCM, the LS switch is turned off when the inductor current reaches zero. Switching loss is reduced by turning off the LS FET at zero current and the conduction loss is lowered by not allowing negative current conduction. Power conversion efficiency is higher in DCM than CCM under the same conditions. In DCM, the HS switch ON time will reduce with lower load current. When either the minimum HS switch ON time (tON-MIN) or the minimum peak inductor current (IPEAK-MIN) is reached, the switching frequency will decrease to maintain regulation. At this point, the LM43602 operates in PFM. In PFM, switching frequency is decreased by the control loop when load current reduces to maintain output voltage regulation. Switching loss is further reduced in PFM operation due to less frequent switching actions. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 13 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com Feature Description (continued) In PFM operation, a small positive DC offset is required at the output voltage to activate the PFM detector. The lower the frequency in PFM, the more DC offset is needed at VOUT. Please refer to the Typical Characteristics for typical DC offset at very light load. If the DC offset on VOUT is not acceptable for a given application, a static load at output is recommended to reduce or eliminate the offset. Lowering values of the feedback divider RFBT and RFBB can also serve as a static load. In conditions with low VIN and/or high frequency, the LM43602 may not enter PFM mode if the output voltage cannot be charged up to provide the trigger to activate the PFM detector. Once the LM43602 is operating in PFM mode at higher VIN, it will remain in PFM operation when VIN is reduced 7.3.3 Adjustable Output Voltage The voltage regulation loop in the LM43602 regulates output voltage by maintaining the voltage on FB pin ( VFB) to be the same as the internal REF voltage (VREF). A resistor divider pair is needed to program the ratio from output voltage VOUT to VFB. The resistor divider is connected from the VOUT of the LM43602 to ground with the mid-point connecting to the FB pin. VOUT RFBT FB RFBB Figure 26. Output Voltage Setting The voltage reference system produces a precise voltage reference over temperature. The internal REF voltage is 1.011 V typically. To program the output voltage of the LM43602 to be a certain value VOUT, RFBB can be calculated with a selected RFBT by VFB RFBB RFBT VOUT VFB (1) The choice of the RFBT depends on the application. RFBT in the range from 10 kΩ to 100 kΩ is recommended for most applications. A lower RFBT value can be used if static loading is desired to reduce VOUT offset in PFM operation. Lower RFBT will reduce efficiency at very light load. Less static current goes through a larger RFBT and might be more desirable when light load efficiency is critical. But RFBT larger than 1 MΩ is not recommended because it makes the feedback path more susceptible to noise. Larger RFBT value requires more carefully designed feedback path on the PCB. The tolerance and temperature variation of the resistor dividers affect the output voltage regulation. It is recommended to use divider resistors with 1% tolerance or better and temperature coefficient of 100 ppm or lower. If the resistor divider is not connected properly, output voltage cannot be regulated since the feedback loop is broken. If the FB pin is shorted to ground, the output voltage will be driven close to VIN, since the regulator sees very low voltage on the FB pin and tries to regulator it up. The load connected to the output could be damaged under such a condition. Do not short FB pin to ground when the LM43602 is enabled. It is important to route the feedback trace away from the noisy area of the PCB. For more layout recommendations, please refer to the Layout section. 7.3.4 Enable (EN) Voltage on the EN pin (VEN) controls the ON or OFF operation of the LM43602. Applying a voltage less than 0.4 V to the EN input shuts down the operation of the LM43602. In shutdown mode the quiescent current drops to typically 1.2 µA at VIN = 12 V. The internal LDO output voltage VCC is turned on when VEN is higher than 1.2 V. The LM43602 switching action and output regulation are enabled when VEN is greater than 2.1 V (typical). The LM43602 supplies regulated output voltage when enabled and output current up to 2 A. The EN pin is an input and cannot be open circuit or floating. The simplest way to enable the operation of the LM43602 is to connect the EN pin to VIN pins directly. This allows self-start-up of the LM43602 when VIN is within the operation range. 14 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 Feature Description (continued) Many applications will benefit from the employment of an enable divider RENT and RENB in Figure 27 to establish a precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such as a battery. An external logic signal can also be used to drive EN input for system sequencing and protection. VIN RENT ENABLE RENB Figure 27. System UVLO By Enable Dividers 7.3.5 VCC, UVLO and BIAS The LM43602 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The nominal voltage for VCC is 3.2 V. The VCC pin is the output of the LDO must be properly bypassed. A high quality ceramic capacitor with 2.2 µF to 10 µF capacitance and 6.3 V or higher rated voltage should be placed as close as possible to VCC and grounded to the exposed PAD and ground pins. The VCC output pin should not be loaded, left floating, or shorted to ground during operation. Shorting VCC to ground during operation may cause damage to the LM43602. Under voltage lockout (UVLO) prevents the LM43602 from operating until the VCC voltage exceeds 3.15 V (typical). The VCC UVLO threshold has 575 mV of hysteresis (typically) to prevent undesired shuting down due to temperary VIN droops. The internal LDO has two inputs: primary from VIN and secondary from BIAS input. The BIAS input powers the LDO when VBIAS is higher than the change-over threshold. Power loss of an LDO is calculated by ILDO * (VIN-LDO VOUT-LDO). The higher the difference between the input and output voltages of the LDO, the more power loss occur to supply the same output current. The BIAS input is designed to reduce the difference of the input and output voltages of the LDO to reduce power loss and improve LM43602 efficiency, especially at light load. It is recommended to tie the BIAS pin to VOUT when VOUT ≥ 3.3 V. The BIAS pin should be grounded in applications with VOUT less than 3.3 V. BIAS input can also come from an external voltage source, if available, to reduce power loss. When used, a 1 µF to 10 µF high quality ceramic capacitor is recommended to bypass the BIAS pin to ground. 7.3.6 Soft-Start and Voltage Tracking (SS/TRK) The LM43602 has a flexible and easy to use start up rate control pin: SS/TRK. Soft-start feature is to prevent inrush current impacting the LM43602 and its supply when power is first applied. Soft-start is achieved by slowly ramping up the target regulation voltage when the device is first enabled or powered up. The simplest way to use the part is to leave the SS/TRK pin open circuit or floating. The LM43602 will employ the internal soft-start control ramp and start up to the regulated output voltage in 4.1 ms typically. In applications with a large amount of output capacitors, or higher VOUT, or other special requirements the softstart time can be extended by connecting an external capacitor CSS from SS/TRK pin to AGND. Extended softstart time further reduces the supply current needed to charge up output capacitors and supply any output loading. An internal current source (ISSC = 2.2 µA) charges CSS and generates a ramp from 0 V to VFB to control the ramp-up rate of the output voltage. For a desired soft start time tSS, the capacitance for CSS can be found by CSS ISSC u t SS (2) The LM43602 is capable of start up into prebiased output conditions. When the inductor current reaches zero, the LS switch will be turned off to avoid negative current conduction. This operation mode is also called diode emulation mode. It is built-in by the DCM operation in light loads. With prebiased output voltage, the LM43602 will wait until the soft-start ramp allows regulation above the prebiased voltage and then follow the soft-start ramp to regulation level. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 15 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com Feature Description (continued) When an external voltage ramp is applied to the SS/TRK pin, the LM43602 FB voltage follows the ramp if the ramp magnitude is lower than the internal soft-start ramp. A resistor divider pair can be used on the external control ramp to the SS/TRK pin to program the tracking rate of the output voltage. The final voltage seen by the SS/TRK pin should not fall below 1.2 V to avoid abnormal operation. EXT RAMP RTRT SS/TRK RTRB Figure 28. Soft Start Tracking External Ramp VOUT tracked to external voltage ramps has options of ramping up slower or faster than the internal voltage ramp. VFB always follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin. Figure 29 shows the case when VOUT ramps slower than the internal ramp, while Figure 30 shows when VOUT ramps faster than the internal ramp. Faster start up time may result in inductor current tripping current protection during startup. Use with special care. Enable Internal SS Ramp Ext Tracking Signal to SS pin VOUT Figure 29. Tracking with Longer Start-up Time Than The Internal Ramp Enable Internal SS Ramp Ext Tracking Signal to SS pin VOUT Figure 30. Tracking with Shorter Start-up Time Than The Internal Ramp 7.3.7 Switching Frequency (RT) and Synchronization (SYNC) The switching frequency of the LM43602 can be programmed by the impedance RT from the RT pin to ground. The frequency is inversely proportional to the RT resistance. The RT pin can be left floating and the LM43602 will operate at 500 kHz default switching frequency. The RT pin is not designed to be shorted to ground. For a desired frequency, typical RT resistance can be found by Equation 3. Table 1 gives typical RT values with a given FS. RT(kΩ) = 40200 / Freq (kHz) - 0.6 16 (3) Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 Feature Description (continued) 250 RT Resistance (kŸ) 200 150 100 50 0 0 500 1000 1500 2000 Switching Frequency (kHz) 2500 C008 Figure 31. RT vs Frequency Curve Table 1. Typical Frequency Setting RT Resistance FS (kHz) RT (kΩ) 200 200 350 115 500 78.7 750 53.6 1000 39.2 1500 26.1 2000 19.6 2200 17.8 The LM43602 switching action can also be synchronized to an external clock from 200 kHz to 2.2 MHz. Connect an external clock to the SYNC pin, with proper high speed termination, to avoid ringing. The SYNC pin should be grounded if not used. SYNC EXT CLOCK RTERM Figure 32. Frequency Synchronization The recommendations for the external clock include: high level no lower than 2 V, low level no higher than 0.4 V, duty cycle between 10% and 90% and both positive and negative pulse width no shorter than 80 ns. When the external clock fails at logic high or low, the LM43602 will switch at the frequency programmed by the RT resistor after a time-out period. It is recommended to connect a resistor RT to the RT pin such that the internal oscillator frequency is the same as the target clock frequency when the LM43602 is synchronized to an external clock. This allows the regulator to continue operating at approximately the same switching frequency if the external clock fails. The choice of switching frequency is usually a compromise between conversion efficiency and the size of the circuit. Lower switching frequency implies reduced switching losses (including gate charge losses, switch transition losses, etc.) and usually results in higher overall efficiency. However, higher switching frequency allows use of smaller LC output filters and hence a more compact design. Lower inductance also helps transient response (higher large signal slew rate of inductor current), and reduces the DCR loss. The optimal switching frequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis. It is related to the input voltage, output voltage, most frequent load current level(s), external component choices, and circuit size requirement. The choice of switching frequency may also be limited if an operating condition triggers TON-MIN or TOFF-MIN. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 17 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com Feature Description (continued) 7.3.8 Minimum ON-time, Minimum OFF-time and Frequency Foldback at Drop-Out Conditions Minimum ON-time, TON-MIN, is the smallest duration of time that the HS switch can be on. TON-MIN is typically 125 ns in the LM43602. Minimum OFF-time, TOFF-MIN, is the smallest duration that the HS switch can be off. TOFF-MIN is typically 200 ns in the LM43602. In CCM operation, TON-MIN and TOFF-MIN limits the voltage conversion range given a selected switching frequency. The minimum duty cycle allowed is DMIN = TON-MIN × FS (4) And the maximum duty cycle allowed is DMAX = 1 - TOFF-MIN × FS (5) Given fixed TON-MIN and TOFF-MIN, the higher the switching frequency the narrower the range of the allowed duty cycle. In the LM43602, frequency foldback scheme is employed to extend the maximum duty cycle when TOFF-MIN is reached. The switching frequency will decrease once longer duty cycle is needed under low VIN conditions. The switching frequency can be decreased to approximately 1/10 of the programmed frequency by RT or the synchronization clock. Such wide range of frequency foldback allows the LM43602 output voltage stays in regulation with much lower supply voltage VIN. This leads to a lower effective drop-out voltage. Please refer to Typical Characteristics for more details. Given a output voltage, the choice of the switching frequency affects the allowed input voltage range, solution size and efficiency. The maximum operatable supply voltage can be found by VIN-MAX = VOUT / (FS * TON-MIN ) (6) At lower supply voltage, the switching frequency will decrease once TOFF-MIN is tripped. The minimum VIN without frequency foldback can be approximated by VIN-MIN = VOUT / (1 - FS * TOFF-MIN ) (7) Taking considerations of power losses in the system with heavy load operation, VIN-MIN is higher than the result calculated in Equation 7 . With frequency foldback, VIN-MIN is lowered by decreased FS. Frequency (Hz) 1000000 100000 0.1A 0.5A 1A 1.5A 2A 10000 5.00 5.20 5.40 5.60 5.80 6.00 6.20 6.40 6.60 6.80 7.00 VIN (V) C007 Figure 33. VOUT = 5 V Fs = 500 kHz Frequency Foldback at Dropout 7.3.9 Internal Compensation and CFF The LM43602 is internally compensated with RC = 400 kΩ and CC = 50 pF as shown in Functional Block Diagram. The internal compensation is designed such that the loop response is stable over the entire operating frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can be low with all ceramic capacitors. An external feed-forward cap CFF is recommended to be placed in parallel with the top resistor divider RFBT for optimum transient performance. 18 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 Feature Description (continued) VOUT RFBT CFF FB RFBB Figure 34. Feed-forward Capacitor for Loop Compensation The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the cross over frequency of the control loop to boost phase margin. The zero frequency can be found by fZ-CFF = 1 / ( 2π × RFBT × CFF ). (8) An additional pole is also introduced with CFF at the frequency of fP-CFF = 1 / ( 2π × CFF × ( RFBT // RFBB )). (9) The CFF should be selected such that the bandwidth of the control loop without the CFF is centered between fZ-CFF and fP-CFF. The zero fZ-CFF adds phase boost at the crossover frequency and improves transient response. The pole fP-CFF helps maintaining proper gain margin at frequency beyond the crossover. Designs with different combinations of output capacitors need different CFF. Different types of capacitors have different Equivalent Series Resistance (ESR). Ceramic capacitors have the smallest ESR and need the most CFF. Electrolytic capacitors have much larger ESR and the ESR zero frequency fZ-ESR = 1 / ( 2π × ESR × COUT) (10) would be low enough to boost the phase up around the crossover frequency. Designs using mostly electrolytic capacitors at the output may not need any CFF. The CFF creates a time constant with RFBT that couples in the attenuated output voltage ripple to the FB node. If the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. It could also couple too much transient voltage deviation and falsely trip PGOOD thresholds. Therefore, CFF should be calculated based on output capacitors used in the system. At cold temperatures, the value of CFF might change based on the tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB node. To avoid this, more capacitance can be added to the output or the value of CFF can be reduced. Please refer to the Detailed Design Procedure for the calculation of CFF. 7.3.10 Bootstrap Voltage (BOOT) The driver of the HS switch requires a bias voltage higher than VIN when the HS switch is ON. The capacitor connected between CBOOT and SW pins works as a charge pump to boost voltage on the CBOOT pin to (VSW + VCC). The boot diode is integrated on the LM43602 die to minimize Bill-Of-Material (BOM). A synchronous switch is also integrated in parallel with the boot diode to reduce voltage drop on CBOOT. A high quality ceramic 0.47 µF 6.3 V or higher capacitor is recommended for CBOOT. 7.3.11 Power Good (PGOOD) The LM43602 has a built in power-good flag shown on PGOOD pin to indicate whether the output voltage is within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails or fault protection. The PGOOD pin is an open-drain output that requires a pull-up resistor to an appropriate DC voltage. Voltage seen by the PGOOD pin should never exceed 12 V. A Resistor divider pair can be used to divide voltage down from a higher potential. A typical range of pull-up resistor value is 10 kΩ to 100 kΩ. When the FB voltage is within the power-good band, +4% above and -7% below the internal reference VREF typically, the PGOOD switch will be turned off and the PGOOD voltage will be pulled up to the voltage level defined by the pull up resistor or divider. When the FB voltage is outside of the tolerance band, +10% above or -13% below VREF typically, the PGOOD switch will be turned on and the PGOOD pin voltage will be pulled low to indicate power bad. Both rising and falling edges of the power-good flag have a built-in 220 µs (typical) deglitch delay. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 19 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com Feature Description (continued) 7.3.12 Over Current and Short Circuit Protection The LM43602 is protected from over-current conditions by cycle-by-cycle current limiting on both peak and valley of the inductor current. Hiccup mode will be activated if a fault condition persists to prevent over heating. High-side MOSFET over-current protection is implemented by the nature of the Peak Current Mode control. The HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. Please refer to Functional Block Diagram for more details. The peak current of the HS switch is limited by the maximum EA output voltage minus the slope compensation at every switching cycle. The slope compensation magnitude at the peak current is proportional to the duty cycle. When the LS switch is turned on, the current going through it is also sensed and monitored. The LS switch will not be turned OFF at the end of a switching cycle if its current is above the LS current limit ILS-LIMIT. The LS switch will be kept ON so that inductor current keeps ramping down, until the inductor current ramps below the LS current limit. Then the LS switch will be turned OFF and the HS switch will be turned on after a dead time. If the current of the LS switch is higher than the LS current limit for 32 consecutive cycles and the power-good flag is low, hiccup current protection mode will be activated. In hiccup mode, the regulator will be shutdown and kept off for 5.5 ms typically before the LM43602 tries to start again. If over-current or short-circuit fault condition still exist, hiccup will repeat until the fault condition is removed. Hiccup mode reduces power dissipation under severe over-current conditions, prevents over heating and potential damage to the device. Hiccup is only activated when power-good flag is low. Under non-severe over-current conditions when VOUT has not fallen outside of the PGOOD tolerance band, the LM43602 will reduce the switching frequency and keep the inductor current valley clamped at the LS current limit level. This operation mode allows slight over current operation during load transients without tripping hiccup. If power-good flag becomes low, hiccup operation will start after LS current limit is tripped 32 consecutive cycles. 7.3.13 Thermal Shutdown Thermal shutdown is a built-in self protection to limit junction temperature and prevent damages due to over heating. Thermal shutdown turns off the device when the junction temperature exceeds 160°C typically to prevent further power dissipation and temperature rise. Junction temperature will reduce after thermal shutdown. The LM43602 will attempt to restart when the junction temperature drops to 150°C. 7.4 Device Functional Modes 7.4.1 Shutdown Mode The EN pin provides electrical ON and OFF control for the LM43602. When VEN is below 0.4 V, the device is in shutdown mode. Both the internal LDO and the switching regulator are off. In shutdown mode the quiescent current drops to 2.3 µA typically with VIN = 24 V. The LM43602 also employs under voltage lock out protection. If VCC voltage is below the UVLO level, the output of the regulator will be turned off. 7.4.2 Stand-by Mode The internal LDO has a lower enable threshold than the regulator. When VEN is above 1.2 V and below the precision enable falling threshold (1.8 V typically), the internal LDO regulates the VCC voltage at 3.2 V. The precision enable circuitry is turned on once VCC is above the UVLO threshold. The switching action and voltage regulation are not enabled unless VEN rises above the precision enable threshold (2.1 V typically). 7.4.3 Active Mode The LM43602 is in Active Mode when VEN is above the precision enable threshold and VCC is above its UVLO level. The simplest way to enable the LM43602 is to connect the EN pin to VIN. This allows self start-up of the LM43602 when the input voltage is in the operation range: 3.5 V to 36 V. Please refer to Enable (EN) and VCC, UVLO and BIAS for details on setting these operating levels. In Active Mode, depending on the load current, the LM43602 will be in one of four modes: 1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the peak-to-peak inductor current ripple; 20 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 Device Functional Modes (continued) 2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of the peak-to-peak inductor current ripple in CCM operation; 3. Pulse Frequency Modulation (PFM) when switching frequency is decreased at very light load; 4. Fold-back mode when switching frequency is decreased to maintain output regulation at lower supply voltage VIN. 7.4.4 CCM Mode Constant Current Mode (CCM) operation is employed in the LM43602 when the load current is higher than half of the peak-to-peak inductor current. In CCM peration, the frequency of operation is fixed unless the the minimum HS switch ON-time (TON_MIN) or OFF-time (TOFF_MIN) is exceeded. Output voltage ripple will be at a minimum in this mode and the maximum output current of 2 A can be supplied by the LM43602. 7.4.5 Light Load Operation When the load current is lower than half of the peak-to-peak inductor current in CCM, the LM43602 will operate in Discontinuous Conduction Mode (DCM), also known as Diode Emulation Mode (DEM). In DCM operation, the LS FET is turned off when the inductor current drops to 0 A to improve efficiency. Both switching losses and conduction losses are reduced in DCM, comparing to forced PWM operation at light load. At even lighter current loads, Pulse Frequency Mode (PFM) is activated to maintain high efficiency operation. When the HS switch ON-time reduces to TON_MIN or peak inductor current reduces to its minimum IPEAK-MIN, the switching frequency will reduce to maintain proper regulation. Efficiency is greatly improved by reducing switching and gate drive losses. Frequency (Hz) 1000000 100000 10000 1000 0.001 8V 12V 24V 36V 0.01 0.1 Current (A) 1 C007 Figure 35. VOUT = 5 V Fs = 500 kHz Pulse Frequency Mode Operation 7.4.6 Self-Bias Mode For highest efficiency of operation, it is recommended that the BIAS pin be connected directly to VOUT when VOUT ≥ 3.3 V. In this Self-Bias Mode of operation, the difference between the input and output voltages of the internal LDO are reduced and therefore the total efficiency of the LM43602 is improved. These efficiency gains are more evident during light load operation. During this mode of operation, the LM43602 operates with a minimum quiescent current of 27 µA (typical). Please refer to VCC, UVLO and BIAS for more details. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 21 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com 8 Applications and Implementation 8.1 Application Information The LM43602 is a step down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 2 A. The following design procedure can be used to select components for the LM43602. Alternately, the WEBENCH® software may be used to generate complete designs. When generating a design, the WEBENCH® software utilizes iterative design procedure and accesses comprehensive databases of components. Please go to ti.com for more details. This section presents a simplified discussion of the design process. 8.2 Typical Applications The LM43602 only requires a few external components to convert from a wide voltage range of supply to a fixed output voltage. Figure 36 shows a basic schematic when BIAS is connected to VOUT and this is recommended for VOUT ≥ 3.3 V. For VOUT < 3.3 V, BIAS should be connected to ground, as shown in Figure 37. L VIN VIN CIN VOUT SW LM43602 ENABLE CBOOT COUT CBIAS CFF CBOOT BIAS PGOOD SS/TRK RT RFBT FB SYNC VCC AGND PGND RFBB CVCC Figure 36. LM43602 Basic Schematic for VOUT ≥ 3.3 V, tie BIAS to VOUT L VIN VIN CIN VOUT SW LM43602 CBOOT COUT CBOOT ENABLE PGOOD BIAS CFF SS/TRK RT RFBT FB SYNC VCC AGND PGND CVCC RFBB Figure 37. LM43602 Basic Schematic for VOUT < 3.3 V, tie BIAS to ground The LM43602 also integrates a full list of optional features to aid system design requirements such as: precision enable, VCC UVLO, programmable soft-start, output voltage tracking, programmable switching frequency, clock synchronization and power-good indication. Each application can select the features for a more comprehensive design. A schematic with all features utilized is shown in Figure 38. 22 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 Typical Applications (continued) L VIN RENT VOUT SW VIN COUT LM43602 CIN ENABLE RENB RFBT CBOOT CBOOT FB VCC CFF RFBB CVCC SS/TRK CSS RT BIAS RT CBIAS SYNC PGOOD RPG RSYNC AGND Tie BIAS to PGND when VOUT < 3.3V PGND Figure 38. LM43602 Schematic with All Features The external components have to fulfill the needs of the application, but also the stability criteria of the device's control loop. The LM43602 is optimized to work within a range of external components. The LC output filter's inductance and capacitance have to be considered in conjunction, creating a double pole, responsible for the corner frequency of the converter (see Output Filter And Loop Stability section). Table 2 can be used to simplify the output filter component selection. Table 2. L, COUT and CFF Typical Values (1) (2) (3) (4) (5) FS (kHz) VOUT (V) L (µH) (1) 200 1 8.2 560 none 200 100 500 1 3.3 470 none 80.6 or open 100 1000 1 1.5 220 none 39.2 100 2200 1 0.68 150 none 17.8 100 200 3.3 18 250 56 200 432 COUT (µF) (2) CFF (pF) (3) (4) RT (kΩ) RFBB (kΩ) 500 3.3 6.8 150 47 80.6 or open 432 1000 3.3 4.7 100 33 39.2 432 2200 3.3 1.8 47 22 17.8 432 200 5 22 200 68 200 249 500 5 10 100 47 80.6 or open 249 1000 5 4.7 47 47 39.2 249 2200 5 2.2 33 33 17.8 249 See note (5) 200 12 68 68 200 90.9 500 12 27 47 68 80.6 or open 90.9 1000 12 15 33 47 39.2 90.9 (5) 200 24 68 68 See note 200 43.2 500 24 27 47 See note (5) 80.6 or open 43.2 1000 24 15 33 See note (5) 39.2 43.2 (3) (4) Inductance value is calculated based on typical VIN value of 12V. All the COUT values are after derating. Add more when using ceramics RFBT = 0 Ω for VOUT = 1 V. RFBT = 1 MΩ for all other VOUT setting. For designs with RFBT other than 1 MΩ, please adjust CFF such that (CFF × RFBT) is unchanged and adjust RFBB such that (RFBT / RFBB) is unchanged. High ESR COUT will give enough phase boost and CFF not needed. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 23 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com Typical Applications (continued) 8.2.1 Design Requirements Detailed design procedure is described based on a design example. For this design example, use the parameters listed in Table 3 as the input parameters. Table 3. Design Example Parameters DESIGN PARAMETER VALUE Input voltage VIN 12 V typical, range from 3.5 V to 36 V Output voltage VOUT 3.3 V Input ripple voltage 400 mV Output ripple voltage 30 mV Output current rating 2A Operating frequency 500 kHz Soft-start time 10 ms 8.2.2 Detailed Design Procedure 8.2.2.1 Custom Design With WEBENCH® Tools Click here to create a custom design using the LM43602 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 8.2.2.2 Output Voltage Set-Point The output voltage of the LM43602 device is externally adjustable using a resistor divider network. The divider network is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. The following equation is used to determine the output voltage of the converter: VFB RFBB RFBT VOUT VFB (11) Choose the value of the RFBT to be 1 MΩ to minimize quiescent current to improve light load efficiency in this application. With the desired output voltage set to be 3.3 V and the VFB = 1.011 V, the RFBB value can then be calculated using Equation 11. The formula yields a value of 434.78 kΩ. Choose the closest available value of 432 kΩ for the RFBB. Please refer to Adjustable Output Voltage for more details. 8.2.2.3 Switching Frequency The default switching frequency of the LM43602 device is set at 500 kHz when RT pin is open circuit. The switching frequency is selected to be 500 kHz in this application for one less passive components. If other frequency is desired, use Equation 12 to calculate the required value for RT. RT(kΩ) = 40200 / Freq (kHz) - 0.6 (12) For 500 kHz, the calculated RT is 79.8 kΩ and standard value 80.6 kΩ can also be used to set the switching frequency at 500 kHz. 24 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 8.2.2.4 Input Capacitors The LM43602 device requires high frequency input decoupling capacitor(s) and a bulk input capacitor, depending on the application. The typical recommended value for the high frequency decoupling capacitor is 4.7 µF to 10 µF. A high-quality ceramic type X5R or X7R with sufficiency voltage rating is recommended. The voltage rating must be greater than the maximum input voltage. To compensate the derating of ceramic capactors, a voltage rating of twice the maximum input voltage is recommended. Additionally, some bulk capacitance can be required, especially if the LM43602 circuit is not located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to the voltage spiking due to the lead inductance of the cable or trace. The value for this capacitor is not critical but must be rated to handle the maximum input voltage including ripple. For this design, a 10 µF, X7R dielectric capacitor rated for 100 V is used for the input decoupling capacitor. The equivalent series resistance (ESR) is approximately 3 mΩ, and the current-rating is 3 A. Include a capacitor with a value of 0.1 µF for high-frequency filtering and place it as close as possible to the device pins. NOTE DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will have a strong influence on the final effective capacitance. Therefore the right capacitor value has to be chosen carefully. Package size and voltage rating in combination with dielectric material are responsible for differences between the rated capacitor value and the effective capacitance. 8.2.2.5 Inductor Selection The first criterion for selecting an output inductor is the inductance itself. In most buck converters, this value is based on the desired peak-to-peak ripple current, ΔiL, that flows in the inductor along with the DC load current. As with switching frequency, the selection of the inductor is a tradeoff between size and cost. Higher inductance gives lower ripple current and hence lower output voltage ripple with the same output capacitors. Lower inductance could result in smaller, less expensive component. An inductance that gives a ripple current of 20% to 40% of the 2 A at the typical supply voltage is a good starting point. ΔIL = (1/5 to 2/5) x IOUT. The peak-to-peak inductor current ripple can be found by Equation 13 and the range of inductance can be found by Equation 14 with the typical input voltage used as VIN. 'iL (VIN VOUT ) u D L u FS (13) (VIN VOUT ) u D (V VOUT ) u D d L d IN 0.4 u FS u IL MAX 0.2 u FS u IL MAX (14) D is the duty cycle of the converter which in a buck converter can be approximated as D = VIN/VOUT, assuming no loss power conversion. By calculating in terms of amperes, volts, and megahertz, the inductance value will come out in micro henries. The inductor ripple current ratio is defined by: 'iL r IOUT (15) The second criterion is the inductor saturation current rating. The inductor should be rated to handle the maximum load current plus the ripple current: IL-PEAK = ILOAD-MAX + ΔiL/ 2 (16) The LM43602 has both valley current limit and peak current limit. During an instantaneous short, the peak inductor current can be high due to a momentary increase in duty cycle. The inductor current rating should be higher than the HS current limit. It is advised to select an inductor with a larger core saturation margin and preferably a softer roll off of the inductance value over load current. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 25 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com In general, it is preferable to choose lower inductance in switching power supplies, because it usually corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low of an inductance can generate too large of an inductor current ripple such that over current protection at the full load could be falsely triggered. It also generates more conduction loss, since the RMS current is slightly higher relative that with lower current ripple at the same DC current. Larger inductor current ripple also implies larger output voltage ripple with the same output capacitors. With peak current mode control, it is not recommended to have too small of an inductor current ripple. A larger peak current ripple improves the comparator signal to noise ratio. Once the inductance is determined, the type of inductor must be selected. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. The ‘hard’ saturation results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! For the design example, a standard 6.8 μH inductor from Wurth, Coiltronics, or Vishay can be used for the 3.3 V output with plenty of current rating margin. 8.2.2.6 Output Capacitor Selection The device is designed to be used with a wide variety of LC filters. It is generally desired to use as little output capacitance as possible to keep cost and size down. The output capacitor (s), COUT, should be chosen with care since it directly affects the steady state output voltage ripple, loop stability and the voltage over/undershoot during load current transients. The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the Equivalent Series Resistance (ESR) of the output capacitors: ΔVOUT-ESR =ΔiL×ESR (17) The other is caused by the inductor current ripple charging and discharging the output capacitors: ΔVOUT-C =ΔiL/ ( 8 × FS × COUT ) (18) The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of the two peaks. Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation in the presence of large current steps and fast slew rates. When a fast large load transient happens, output capacitors provide the required charge before the inductor current can slew to the appropriate level. The initial output voltage step is equal to the load current step multiplied by the ESR. VOUT continues to droop until the control loop response increases or decreases the inductor current to supply the load. To maintain a small over- or undershoot during a transient, small ESR and large capacitance are desired. But these also come with higher cost and size. Thus, the motivation is to seek a fast control loop response to reduce the output voltage deviation. For a given input and output requirement, the following inequality gives an approximation for an absolute minimum output cap required: COUT ! ª§ r 2 · 1 u «¨ u (1 Dc) ¸ ¨ ¸ (FS u r u 'VOUT / IOUT ) ¬«© 12 ¹ º Dc u (1 r) » ¼» (19) Along with this for the same requirement, the max ESR should be calculated as per the following inequality ESR Dc 1 u ( 0.5) FS u COUT r (20) where r = Ripple ratio of the inductor ripple current (ΔIL / IOUT) ΔVOUT = Target output voltage undershoot D’ = 1 – Duty cycle FS = Switching Frequency 26 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 IOUT = Load Current A general guide line for COUT range is that COUT should be larger than the minimum required output capacitance calculated by Equation 19, and smaller than 10 times the minimum required output capacitance or 1 mF. In applications with VOUT less than 3.3 V, it is critical that low ESR output capacitors are selected. This will limit potential output voltage overshoots as the input voltage falls below the device normal operating range. To optimize the transient behavior a feed-forward capacitor could be added in parallel with the upper feedback resistor. For this design example, three 47 µF,10 V, X7R ceramic capacitors are used in parallel. 8.2.2.7 Feed-Forward Capacitor The LM43602 is internally compensated and the internal R-C values are 400 kΩ and 50 pF respectively. Depending on the VOUT and frequency FS, if the output capacitor COUT is dominated by low ESR (ceramic types) capacitors, it could result in low phase margin. To improve the phase boost an external feedforward capacitor CFF can be added in parallel with RFBT. CFF is chosen such that phase margin is boosted at the crossover frequency without CFF. A simple estimation for the crossover frequency without CFF (fx) is shown in Equation 21, assuming COUT has very small ESR. fx 4.35 VOUT u COUT (21) The following equation for CFF was tested: CFF 1 1 u 2Sfx RFBT u (RFBT / /RFBB ) (22) This equation indicates that the crossover frequency is geometrically centered on the zero and pole frequencies caused by the CFF capacitor. For designs with higher ESR, CFF is not neeed when COUT has very high ESR and CFF calculated from Equation 22 should be reduced with medium ESR. Table 2 can be used as a quick starting point. For the application in this design example, a 100 pF COG capacitor is selected. 8.2.2.8 Bootstrap Capacitors Every LM43602 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor is 0.47 μF and rated at 6.3 V or higher. The bootstrap capacitor is located between the SW pin and the CBOOT pin. The bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature stability. 8.2.2.9 VCC Capacitor The VCC pin is the output of an internal LDO for LM43602. The input for this LDO comes from either VIN or BIAS (please refer to Functional Block Diagram for LM43602). To insure stability of the part, place a minimum of 2.2 µF, 10 V capacitor from this pin to ground. 8.2.2.10 BIAS Capacitors For an output voltage of 3.3 V and greater, the BIAS pin can be connected to the output in order to increase light load efficiency. This pin is an input for the VCC LDO. When BIAS is not connected, the input for the VCC LDO will be internally connected into VIN. Since this is an LDO, the voltage differences between the input and output will affect the efficiency of the LDO. If necessary, a capacitor with a value of 1 μF can be added close to the BIAS pin as an input capacitor for the LDO. 8.2.2.11 Soft-Start Capacitors The user can left the SS/TRK pin floating and the LM43602 will implement a soft start time of 4.1 ms typically. In order to use an external soft start capacitor, the capacitor should be sized such that the soft start time will be longer than 4.1 ms. Use the following equation in order to calculate the soft start capacitor value: CSS ISSC u t SS (23) Where, Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 27 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com CSS = Soft start capacitor value (µF) ISS = Soft start charging current (µA) tSS = Desired soft start time (s) For the desired soft start time of 10 ms and soft start charging current of 2.0 µA, the equation above yield a soft start capacitor value of 0.020 µF. 8.2.2.12 Under Voltage Lockout Set-Point The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. RENT is connected between VIN and the EN pin of the LM43602 device. RENB is connected between the EN pin and the GND pin. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. The following equation can be used to determine the VIN (UVLO) level. VIN-UVLO-RISING = VENH × (RENB + RENT) / RENB (24) The EN rising threshold (VENH) for LM43602 is set to be 2.2 V (typical). Choose the value of RENB to be 1 MΩ to minimize input current from the supply. If the desired VIN UVLO level is at 5.0 V, then the value of RENT can be calculated using the equation below: RENT = (VIN-UVLO-RISING / VENH -1) × RENB (25) The above equation yields a value of 1.27 MΩ. The resulting falling UVLO threshold, equals 4.3 V, can be calculated by below equation, where EN falling threshold (VENL) is 1.9 V (typical). VIN-UVLO-FALLING = VENL × (RENB + RENT) / RENB (26) 8.2.2.13 PGOOD A typical pull-up resistor value is 10 kΩ to 100 kΩ from PGOOD pin to a voltage no higher than 12 V. If it is desired to pull up PGOOD pin to a voltage higher than 12 V, a resistor can be added from PGOOD pin to ground to divide the voltage seen by the PGOOD pin to a value no higher than 12 V. 28 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 8.2.3 Application Performance Curves Unless otherwise specified, VIN = 12V, VOUT = 3.3 V, FS = 500 kHz. Please refer to Application Performance Curves for Bill of materials for each VOUT and FS combination. 100 90 6.8µH VIN 3.3VOUT SW 4.7 µF LM43602 CBOOT FB ENABLE SS/TRK 0.47µF 120µF VCC 100pF 1MŸ 432kŸ 2.2µF Efficiency (%) VIN RT 80 70 60 5VIN BIAS SYNC 50 PGOOD AGND 12VIN PGND 24VIN 40 0 0.5 1 VOUT = 3.3 V FS = 500 kHz VOUT = 3.3 V Figure 39. BOM for VOUT = 3.3 V FS = 500 kHz 100 100 90 90 80 80 70 60 FS = 500 kHz 70 60 5VIN 50 5VIN 50 12VIN 12VIN 24VIN 40 0.001 0.01 0.1 VOUT = 3.3 V 24VIN 40 0.001 1 Current (A) 0.01 FS = 500 kHz VOUT = 3.3 V 3 12VIN C001 FS = 500 kHz 5VIN 12VIN 2.5 24VIN Power Dissipation (W) Power Dissipation (W) 1 Figure 42. Efficiency at 85°C 5VIN 2.5 0.1 Current (A) C001 Figure 41. Efficiency at Room Temperature 3 2 C001 Figure 40. Efficiency at Room Temperature Efficiency (%) Efficiency (%) 1.5 Current (A) C001 2 1.5 1 0.5 24VIN 2 1.5 1 0.5 0 0 0 0.5 1 1.5 2 Current (A) VOUT = 3.3 V 0 0.5 FS = 500 kHz 1 1.5 2 Current (A) C001 VOUT = 3.3 V Figure 43. Power Loss at Room Temperature FS = 500 kHz C001 VIN = 24 V Figure 44. Power Loss at 85°C Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 29 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com Unless otherwise specified, VIN = 12V, VOUT = 3.3 V, FS = 500 kHz. Please refer to Application Performance Curves for Bill of materials for each VOUT and FS combination. 1000000 3.5 FREQUENCY (Hz) 3.4 VOUT (V) 3.3 3.2 0.1A 0.5A 3.1 1A 100000 0.1A 0.5A 10000 1A 1.5A 1.5A 3.0 2A 2A 1000 2.9 3.5 3.7 3.9 4.1 4.3 3.5 4.5 VIN (V) 3.7 3.9 VOUT = 3.3 V 4.1 FS = 500 kHz 4.5 C007 VOUT = 3.3 V Figure 45. Dropout Voltage FS = 500 kHz Figure 46. Frequency vs VIN 1000000 3.40 5VIN 3.38 12VIN 3.36 24VIN 3.34 100000 VOUT (V) FREQUENCY (Hz) 4.3 VIN (V) C007 5VIN 8VIN 12VIN 24VIN 10000 1000 0.001 0.01 0.1 3.30 3.28 3.26 3.24 3.22 3.20 0.001 1 Current (A) 3.32 0.01 VOUT = 3.3 V 0.1 1 Current (A) C007 FS = 500 kHz C001 VOUT = 3.3 V Figure 47. Frequency vs Load FS = 500 kHz Figure 48. Regulation Curve 3.0 2.5 VOUT (100 mV/DIV) Current (A) IOUT (0.5 A/DIV) 2.0 1.5 1.0 12VIN 18VIN 0.5 24VIN 0.0 Time (100µs/DIV) 65 75 85 95 105 Ambient Temperature (deg C) VOUT = 3.3 V FS = 500 kHz VIN =12 V Figure 49. Load Transient 30 VOUT = 3.3 V 115 125 C007 FS = 500 kHz Figure 50. Derating Curve Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 Unless otherwise specified, VIN = 12V, VOUT = 3.3 V, FS = 500 kHz. Please refer to Application Performance Curves for Bill of materials for each VOUT and FS combination. 100 90 10µH VIN 5VOUT SW 4.7 µF LM43602 CBOOT FB ENABLE SS/TRK 0.47µF 100µF VCC 100pF 1MŸ 249kŸ 2.2µF Efficiency (%) VIN RT 80 70 60 12VIN BIAS SYNC 50 PGOOD AGND 24VIN PGND 40 0 0.5 1 VOUT = 5 V FS = 500 kHz VOUT = 5 V Figure 51. BOM for VOUT = 5 V FS = 500 kHz FS = 500 kHz 100 100 90 90 80 80 70 60 70 60 12VIN 12VIN 50 50 24VIN 40 0.001 0.01 0.1 VOUT = 5 V 24VIN 40 0.001 1 Current (A) 0.01 0.1 1 Current (A) C001 FS = 500 kHz VOUT = 5 V Figure 53. Efficiency at Room Temperature C001 FS = 500 kHz Figure 54. Efficiency at 85°C Ambient Temperature 3 3 12VIN 2.5 12VIN 2.5 24VIN Power Dissipaton (W) Power Dissipation (W) 2 C001 Figure 52. Efficiency at Room Temperature Efficiency (%) Efficiency (%) 1.5 Current (A) C001 2 1.5 1 0.5 24VIN 2 1.5 1 0.5 0 0 0 0.5 1 Current (A) VOUT = 5 V 1.5 2 0 FS = 500 kHz VOUT = 5 V Figure 55. Power Dissipation at Room Temperature 0.5 1 1.5 Current (A) C001 2 C001 FS = 500 kHz Figure 56. Power Dissipation at 85C Ambient Temperature Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 31 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com Unless otherwise specified, VIN = 12V, VOUT = 3.3 V, FS = 500 kHz. Please refer to Application Performance Curves for Bill of materials for each VOUT and FS combination. 1000000 5.4 5.2 Frequency (Hz) VOUT (V) 5.0 4.8 4.6 0.1A 0.5A 1A 1.5A 2A 4.4 4.2 VIN (V) 0.1A 0.5A 1A 1.5A 4.0 5.00 5.20 5.40 5.60 5.80 6.00 6.20 6.40 6.60 6.80 7.00 VOUT = 5 V 100000 2A 10000 5.00 5.20 5.40 5.60 5.80 6.00 6.20 6.40 6.60 6.80 7.00 VIN (V) C007 FS = 500 kHz VOUT = 5 V Figure 57. Dropout Voltage C007 FS = 500 kHz Figure 58. Frequency vs VIN 1000000 5.25 8VIN 5.20 12VIN 24VIN 5.10 100000 VOUT (V) Frequency (Hz) 5.15 10000 0.01 0.1 VOUT = 5 V 4.95 4.85 4.80 4.75 0.001 1 Current (A) 5.00 4.90 8V 12V 24V 36V 1000 0.001 5.05 0.01 0.1 1 Current (A) C007 FS = 500 kHz VOUT = 5 V Figure 59. Frequency vs Load C004 FS = 500 kHz Figure 60. Regulation Curve 3.0 2.5 VOUT (100 mV/DIV) Current (A) IOUT (0.5 A/DIV) 2.0 1.5 1.0 12VIN 18VIN 24VIN 28VIN 0.5 0.0 Time (100µs/div) 65 75 85 95 105 Ambient Temperature (deg C) VOUT = 5 V FS = 1 MHz VIN = 12V VOUT = 5 V Figure 61. Load Transient 0.1A to 1A 32 Submit Documentation Feedback 115 125 C007 FS = 500 kHz Figure 62. Derating Curve Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 9 Power Supply Recommendations The LM43602 is designed to operate from an input voltage supply range between 3.5 V and 60 V. This input supply should be well regulated and able to withstand maximum input current and maintain a stable voltage. The resistance of the input supply rail should be low enough that an input current transient does not cause a high enough drop at the LM43602 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is located more than a few inches from the LM43602 additional bulk capacitance may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47 µF or 100 µF electrolytic capacitor is a typical choice. 10 Layout The performance of any switching converter depends as much upon the layout of the PCB as the component selection. The following guidelines will help users design a PCB with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI. 10.1 Layout Guidelines 1. Place ceramic high frequency bypass CIN as close as possible to the LM43602 VIN and PGND pins. Grounding for both the input and output capacitors should consist of localized top side planes that connect to the PGND pins and PAD. 2. Place bypass capacitors for VCC and BIAS close to the pins and ground the bypass capacitors to device ground. 3. Minimize trace length to the FB pin net. Both feedback resistors, RFBT and RFBB should be located close to the FB pin. Place Cff directly in parallel with RFBT. If VOUT accuracy at the load is important, make sure VOUT sense is made at the load. Route VOUT sense path away from noisy nodes and preferably through a layer on the other side of a shieldig layer. 4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path. 5. Have a single point ground connection to the plane. The ground connections for the feedback, soft-start, and enable components should be routed to the ground plane. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. 6. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the input or output paths of the converter and maximizes efficiency. 7. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125°C. 10.1.1 Compact Layout for EMI Reduction Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger area covered by the path of a pulsing current, the more EMI is generated. The key to minimize radiated EMI is to identify pulsing current path and minimize the area of the path. In Buck converters,the pulsing current path is from the VIN side of the input capacitors to HS switch, to the LS switch, and then return to the ground of the input capacitors, as shown in Figure 63. BUCK CONVERTER VIN VIN SW L CIN VOUT COUT PGND High di/dt current PGND Figure 63. Buck Converter High Δi/Δt Path Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 33 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com Layout Guidelines (continued) High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the key to EMI reduction. The SW pin connecting to the inductor should be as short as possible, and just wide enough to carry the load current without excessive heating. Short, thick traces or copper pours (shapes) should be used for high current condution path to minimize parasitic resistance. The output capacitors should be place close to the VOUT end of the inductor and closely grounded to PGND pin and exposed PAD. The bypass capacitors on VCC and BIAS pins should be placed as close as possible to the pins respectively and closely grounded to PGND and the exposed PAD. 10.1.2 Ground Plane and Thermal Considerations It is recommended to use one of the middle layers as a solid ground plane. Ground plane provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. The AGND and PGND pins should be connected to the ground plane using vias right next to the bypass capacitors. PGND pins are connected to the source of the internal LS switch. They should be connected directly to the grounds of the input and output capacitors. The PGND net contains noise at switching frequency and may bounce due to load variations. PGND trace, as well as PVIN and SW traces, should be constrained to one side of the ground plane. The other side of the ground plane contains much less noise and should be used for sensitive routes. It is recommended to provide adequate device heat sinking by utilizing the PAD of the IC as the primary thermal path. Use a minimum 4 by 4 array of 10 mil thermal vias to connect the PAD to the system ground plane heat sink. The vias should be evenly distributed under the PAD. Use as much copper as possible for system ground plane on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top one, 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enough copper thickness provides low current conduction impedance, proper shielding and lower thermal resistance. The thermal characteristics of the LM46002 are specified using the parameter RθJA, which characterize the junction temperature of the silicon to the ambient temperature in a specific system. Although the value of θJA is dependant on many variables, it still can be used to approximate the operating junction temperature of the device. To obtain an estimate of the device junction temperature, one may use the following relationship: TJ = PD× θJA + TA (27) where TJ = Junction temperature in °C PD = VIN × IIN × (1 − Efficiency) − 1.1 x IOUT x DCR DCR = Inductor DC parasitic resistance in Ω θJA = Junction-to-ambient thermal resistance of the device in °C/W TA = Ambient temperature in °C. The maximum operating junction temperature of the LM43602 is 125°C. θJA is highly related to PCB size and layout, as well as enviromental factors such as heat sinking and air flow. Figure 64 shows measured results of RθJA with different copper area on a 2-layer board and a 4-layer board. 34 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 Layout Guidelines (continued) 50.0 1W @ 0fpm - 2 layer 2W @ 0fpm - 2 layer 45.0 1W @ 0fpm - 4 layer 2W @ 0fpm - 4 layer ,JA (ƒC/W) 40.0 35.0 30.0 25.0 20.0 20mm x 20mm 30mm x 30mm 40mm x 40mm Copper Area 50mm x 50mm C007 Figure 64. RθJA vs Copper Area 2 oz Copper on Outer Layers and 1oz Copper on Inner Layers 10.1.3 Feedback Resistors To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and CFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high impedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces the trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace from VOUT to the resistor divider can be long if short path is not available. If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so will correct for voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to the feedback resistor divider should be routed away from the SW node path and the inductor to avoid contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most important when high-value resistors are used to set the output voltage. This provides further shielding for the voltage feedback path from EMI noises. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 35 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com 10.2 Layout Example TO LOAD + VOUT sense point is away from inductor and past COUT VOUT VOUT distribution point is away from inductor and past COUT COUT As much copper area as possible, for better thermal performance L GND Place bypass caps close to terminals CVCC Ground bypass caps to DAP 1 SW 2 CBOOT 3 14 VIN VCC 4 13 VIN BIAS 5 12 EN SYNC 6 11 SS/TRK RT 7 10 AGND PGOOD 8 9 Thermal Vias under DAP PAD (17) CBIAS 16 PGND 15 PGND + CBOOT SW CIN VIN Place ceramic bypass caps close to VIN and PGND terminals RFBB FB RFBT CFF Route VOUT sense trace away from SW and VIN nodes. Preferably shielded in an alternative layer GND Plane As much copper area as possible, for better thermal performance Figure 65. LM43602 Board Layout Recommendations 36 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Custom Design With WEBENCH® Tools Click here to create a custom design using the LM43602 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: • LM43602 EVM User's Guide ( • Using New Thermal Metrics applications report (SBVA025). • Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor (SLVA289). • Simple Success with Conducted EMI for DC-DC Converters (SNVA489). • AN-1149 Layout Guidelines for Switching Power Supplies SNVA021 • AN-1229 Simple Switcher PCB Layout Guidelines SNVA054 • Constructing Your Power Supply- Layout Considerations SLUP230 • Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x SNVA721 • AN-2020 Thermal Design By Insight, Not Hindsight SNVA419 • AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages SNVA183 • Semiconductor and IC Package Thermal Metrics SPRA953 • Thermal Design made Simple with LM43603 and LM43602 SNVA719 • PowerPAD™ Thermally Enhanced Package SLMA002 • PowerPAD Made Easy SLMA004 • Using New Thermal Metrics SBVA025 11.3 Related Links Table 4. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LM43603 Click here Click here Click here Click here Click here Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 37 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com 11.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.5 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.6 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.7 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.8 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 38 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 PACKAGE OUTLINE DSU0016A VSON - 1 mm max height SCALE 3.000 PLASTIC SMALL OUTLINE - NO LEAD 4.1 3.9 A B PIN 1 INDEX AREA 5.1 4.9 (0.08) (0.05) SECTION A-A SECTION A-A SCALE 30.000 TYPICAL 1 MAX C SEATING PLANE 0.05 0.00 0.08 C 2.45±0.1 EXPOSED THERMAL PAD (0.2) TYP 8 9 A 2X 3.5 A 4.35±0.1 1 16 14X 0.5 16X PIN 1 ID (OPTIONAL) 0.5 16X 0.3 0.3 0.2 0.1 0.05 C A C B 4222160/A 09/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 39 LM43602 SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 www.ti.com EXAMPLE BOARD LAYOUT DSU0016A VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (2.45) 4X (0.975) 16X (0.6) 1 16 16X (0.25) 14X (0.5) 6X (0.705) (4.35) (R0.05) TYP 2X (1.925) 8 9 SYMM ( 0.2) VIA TYP (3.8) LAND PATTERN EXAMPLE SCALE:15X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4222160/A 09/2015 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com 40 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 LM43602 www.ti.com SNVSA36C – APRIL 2014 – REVISED OCTOBER 2017 EXAMPLE STENCIL DESIGN DSU0016A VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM METAL TYP 6X (0.64) 16X (0.6) 1 16 16X (0.25) 4X (1.41) 14X (0.5) (R0.05) TYP 6X (1.21) 8 9 6X (1.08) (3.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 74% PRINTED SOLDER COVERAGE BY AREA SCALE:20X 4222160/A 09/2015 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: LM43602 41 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LM43602DSUR ACTIVE SON DSU 16 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 LM43602 LM43602DSUT ACTIVE SON DSU 16 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 LM43602 LM43602PWP ACTIVE HTSSOP PWP 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LM43602 LM43602PWPR ACTIVE HTSSOP PWP 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LM43602 LM43602PWPT ACTIVE HTSSOP PWP 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LM43602 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
LM43602DSUT 价格&库存

很抱歉,暂时无法提供与“LM43602DSUT”相匹配的价格&库存,您可以联系我们找货

免费人工找货
LM43602DSUT
  •  国内价格 香港价格
  • 250+24.26059250+3.00952
  • 500+23.37938500+2.90020
  • 750+23.23795750+2.88266

库存:430