LM4946
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LM4946
SNAS335E – JANUARY 2006 – REVISED AUGUST 2007
Output Capacitor-Less Audio Subsystem with
Programmable TI 3D
Check for Samples: LM4946
FEATURES
1
•
•
•
2
•
•
•
•
•
•
•
2
I C/SPI Control Interface
I2C/SPI Programmable TI 3D Audio
I2C/SPI Controlled 32 Step Digital Volume
Control (-54dB to +18dB)
Three Independent Volume Channels (Left,
Right, Mono)
Eight Distinct Output Modes
WQFN and DSBGA Surface Mount Packaging
“Click and Pop” Suppression Circuitry
Thermal Shutdown Protection
Low Shutdown Current (0.02uA, typ)
RF Immunity Topology
APPLICATIONS
•
•
Mobile Phones
PDAs
KEY SPECIFICATIONS
•
•
•
•
THD+N at 1kHz, 540mW into 8Ω BTL (3.3V)
1.0% (typ)
THD+N at 1kHz, 35mW into 32Ω SE (3.3V) 1.0%
(typ)
Single Supply Operation (VDD) 2.7 to 5.5V
I2C/SPI Single Supply Operation
– WQFN 2.2 to 5.5V
– DSBGA 1.7 to 5.5V
DESCRIPTION
The LM4946 is an audio power amplifier capable of
delivering 540mW of continuous average power into a
mono 8Ω bridged-tied load (BTL) with 1% THD+N,
35mW per channel of continuous average power into
stereo 32Ω single-ended (SE) loads with 1% THD+N,
or an output capacitor-less (OCL) configuration with
identical specifications as the SE configuration, from
a 3.3V power supply.
The LM4946 has three input channels: one pair for a
two-channel stereo signal and the third for a
differential single-channel mono input. The LM4946
features a 32-step digital volume control and eight
distinct output modes. The digital volume control, 3D
enhancement, and output modes (mono/SE/OCL) are
programmed through a two-wire I2C or a three-wire
SPI compatible interface that allows flexibility in
routing and mixing audio channels.
The LM4946 is designed for cellular phone, PDA, and
other portable handheld applications. It delivers high
quality output power from a surface-mount package
and requires only seven external components in the
OCL mode (two additional components in SE mode).
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
LM4946
SNAS335E – JANUARY 2006 – REVISED AUGUST 2007
www.ti.com
Typical Application
V
DD
1 PF
0.1 PF ceramic
+
CS1
CS2
Handsfree
Speaker
C IN 4
MONO_IN+
MONO +
+
+
1 PF
Volume Control
-54dB to +18dB
-6dB
C IN 3
8:
-
MONO -
+
1 PF
MONO_IN-
6dB
Mixer
C IN 2
AUDIO
Volume Control
-54dB to +18dB
+
INPUT
R OUT
and
R IN
0.22 PF
0dB
32:
Output
Mode
V OC
Select
3D
C IN1
L IN
AUDIO
L OUT
Volume Control
-54dB to +18dB
+
INPUT
32:
0dB
0.22 PF
CSPI_VDD
I 2 C/SPI
Bias
LHP3D2
Bypass
R HP3D2
Interface
I 2 CSPI_SEL
R HP3D1
SCL
ID_ENB
B
+
C
SDA
L HP3D1
I2
2.2 PF
GND
C 3DL C 3DR
Figure 1. Typical Audio Amplifier Application Circuit-Output Capacitor-less
VDD
1 PF
0.1 PF
ceramic
+
CS1
C IN 4
MONO_IN+
-6 dB
C IN 3
MONO +
Volume Control
-54 dB to +18 dB
6 dB
8:
-
MONO-
+
Mixer
AUDIO
RIN
+
INPUT
R OUT
and
Volume Control
-54 dB to +18 dB
0.22 PF
0 dB
Output
VOC
Select
3D
+
INPUT
L OUT
Volume Control
-54 dB to +18 dB
0 dB
CO
+
LIN
32:
100 PF
Mode
CIN 1
AUDIO
CO
+
CIN 2
32:
100 PF
0.22 PF
I 2CSPI_VDD
CB
SDA
I 2C/SPI
SCL
Bias
Bypass
2.2 PF
RHP3D2
RHP3D1
LHP3D1
I 2CSPI_SEL
LHP3D2
Interface
ID_ENB
+
1 PF
MONO_IN-
Handsfree
Speaker
+
+
1 PF
CS2
GND
C 3DL
C 3DR
Figure 2. Typical Audio Amplifier Application Circuit-Single Ended
2
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19
21
20
22
23
24
Connection Diagram
15
5
14
6
13
11
12
4
10
16
9
17
3
8
18
7
1
2
Figure 3. 24 Lead WQFN Package (Top View)
1
2
3
4
5
A
VOC
VDD
GND
ROUT
LOUT
B
RHP3D2
LHP3D2
LIN
I2CSPI_VDD
RIN
C
MONO_IN-
MONO_IN+
BYPASS
SCL
SDA
D
GND
RHP3D1
VDD
ID_ENB
GND
E
LHP3D1
MONO-
VDD
MONO+
I2CSPI_SEL
Figure 4. 25 Bump DSBGA Package (Top View)
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LM4946
SNAS335E – JANUARY 2006 – REVISED AUGUST 2007
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PIN DESCRIPTIONS
Pin Number (WQFN)
Name
Description
1
B2
LHP3D2
2
A1
VOC
Center Amplifier Output
3
A2
VDD
Voltage Supply
4
A3
GND
Ground
5
A4
ROUT
Right Headphone Output
6
A5
LOUT
Left Headphone Output
7
B4
I2CSPI_VDD
8
B5
RIN
Right Input Channel
9
B3
LIN
Left Input Channel
10
C5
SDA
Data
11
C4
SCL
Clock
12
D5
GND
Ground
13
D4
ID_ENB
14
4
Bump (DSBGA)
2
Left Headphone 3D Input 1
I2C or SPI Interface Voltage Supply
Address Identification/Enable Bar
I2C or SPI Select
E5
I CSPI_SEL
15
E4
MONO+
16
D3
VDD
17
E2
MONO-
Loudspeaker Output Negative
Loudspeaker Output Positive
Voltage Supply
18
E1
LHP3D1
Left Headphone 3D Input 2
19
D2
RHP3D1
Right Headphone 3D Input 1
20
D1
GND
21
C3
BYPASS
22
C1
MONO_IN-
Loudspeaker Negative Input
23
C2
MONO_IN+
Loudspeaker Positive Input
24
B1
RHP3D2
E3
VDD
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Ground
Half-Supply Bypass
Right Headphone 3D Input 2
Voltage Supply
Copyright © 2006–2007, Texas Instruments Incorporated
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SNAS335E – JANUARY 2006 – REVISED AUGUST 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Supply Voltage
6.0V
Storage Temperature
−65°C to +150°C
Input Voltage
−0.3 to VDD +0.3
ESD Susceptibility
(3)
2.0kV
ESD Machine model (4)
200V
Junction Temperature
150°C
Soldering Information
Vapor Phase (60 sec.)
215°C
Infrared (15 sec.)
Thermal Resistance (5)
(1)
(2)
(3)
(4)
(5)
220°C
θJA (typ) - RTW0024A
46°C/W
θJA (typ) - YFQ0025
49°C/W
Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Human body model, 100pF discharged through a 1.5kΩ resistor.
Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then
discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50Ω).
The given θJA for an LM4946SQ mounted on a demonstration board with a 9in2 area of 1oz printed circuit board copper ground plane.
Operating Ratings
−40°C to 85°C
Temperature Range
2.7V ≤ VDD ≤ 5.5V
Supply Voltage (VDD)
Supply Voltage (I2C/SPI) (1)
I2CSPI_VDD ≤ VDD
2
WQFN
2.2V ≤ I CSPI_VDD ≤ 5.5V
DSBGA
1.7V ≤ I2CSPI_VDD ≤ 5.5V
(1)
Refer to this table.
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LM4946
SNAS335E – JANUARY 2006 – REVISED AUGUST 2007
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Electrical Characteristics 3.3V (1) (2)
The following specifications apply for VDD = 3.3V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified.
Symbol
Parameter
Conditions
LM4946
Typical
IDD
Supply Current
ISD
Shutdown Current
VOS
Output Offset Voltage
PO
Output Power
THD+N
Total Harmonic Distortion + Noise
(4)
Limits
(5)
Units
(Limits) (3)
Output Modes 2, 4, 6
VIN = 0V; No load,
SE Headphone
3.25
mA
Output Modes 1, 3, 5, 7
VIN = 0V; No load,
SE Headphone
5.65
mA
Output Modes 2, 4, 6
VIN = 0V; No load,
OCL Headphone
4
Output Modes 1, 3, 5,
VIN = 0V; No load,
OCL Headphone
5
6.5
mA (max)
mA
Output Modes 7
VIN = 0V; No load,
OCL Headphone
6.5
10.5
mA (max)
Output Mode 0
µA (max)
0.02
1
VIN = 0V, Mode 7
Mono
12
50
VIN = 0V, Mode 7
Headphones (Note 11)
3
15
MONO OUT; RL = 8Ω
THD+N = 1%; f = 1kHz, BTL, Mode 1
540
500
mW (min)
ROUT and LOUT; RL = 32Ω
THD+N = 1%; f = 1kHz, SE, Mode 4
35
30
mW (min)
mV (max)
MONOOUT
f = 1kHz
POUT = 250mW; RL = 8Ω, BTL, Mode 1
0.05
%
ROUT and LOUT
f = 1kHz
POUT = 12mW; RL = 32Ω, SE, Mode 4
0.015
%
Speaker; Mode 1
17
μV
Speaker; Mode 3, 7
27
μV
Speaker; Mode 5
33
μV
Headphone; SE, Mode 2
8
μV
Headphone; SE, Mode 4, 7
8
μV
Headphone; SE, Mode 6
12
μV
Headphone; OCL, Mode 2
8
μV
Headphone; OCL, Mode 4, 7
9
μV
Headphone; OCL, Mode 6
12
μV
A-weighted,
inputs terminated to GND, output referred
NOUT
(1)
(2)
(3)
(4)
(5)
6
Output Noise
Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to the ground pin, unless otherwise specified.
Datasheet min/max specifications are specified by design, test, or statistical analysis.
Typical specifications are specified at +25°C and represent the most likely parametric norm.
Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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Electrical Characteristics 3.3V(1)(2) (continued)
The following specifications apply for VDD = 3.3V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified.
Symbol
Parameter
Conditions
LM4946
Typical
Power Supply Rejection Ratio
MONOOUT
Power Supply Rejection Ratio
ROUT and LOUT
BTL, Output Mode 1
76
dB
BTL, Output Mode 3, 7
65
dB
BTL, Output Mode 5
63
dB
SE, Output Mode 2
78
dB
SE, Output Mode 4,7
82
dB
SE, Output Mode 6
78
dB
OCL, Output Mode 2
84
dB
OCL, Output Mode 4, 7
78
dB
OCL, Output Mode 6
77
dB
±0.2
HP(SE) Mute Attenuation
MONO_IN Input Impedance
RIN and LIN Input Impedance
Common-Mode Rejection Ratio
Crosstalk
Wake-Up Time from Shutdown
dB
Maximum attenuation
-54
–56
–52
Maximum gain
18
17.4
18.6
dB (min)
dB (max)
Output Mode 1, 3, 5
96
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
Digital Volume Control Range
TWU
Units
(Limits) (3)
VRIPPLE = 200mVPP; f = 217Hz, RL = 8Ω
CB = 2.2µF, BTL
All audio inputs terminated to GND;
output referred
Volume Control Step Size Error
XTALK
Limits
(5)
VRIPPLE = 200mVPP; f = 217Hz, RL = 32Ω
CB = 2.2µF,
All audio inputs terminated to GND
output referred
PSRR
CMRR
(4)
dB (max)
dB (min)
dB
Maximum gain setting
12.5
10
15
Maximum attenuation setting
110
90
130
f = 217Hz, VCM = 1Vpp,
Mode 1, BTL, RL = 8Ω
61
f = 217Hz, VCM = 1Vpp,
Mode 2, RL = 32Ω
66
Headphone; PO = 12mW
f = 1kHz, OCL, Mode 4
–54
Headphone; PO = 12mW
f = 1kHz, SE, Mode 4
–72
CB = 2.2μF, OCL
100
ms
CB = 2.2μF, SE
135
ms
dB
dB
dB
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Electrical Characteristics 5.0V (1) (2)
The following specifications apply for VDD = 5.0V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified.
Symbol
Parameter
Conditions
LM4946
Typical
IDD
Supply Current
ISD
Shutdown Current
VOS
Output Offset Voltage
PO
Output Power
THD+N
Total Harmonic Distortion + Noise
(4)
Limits
(5)
Units
(Limits) (3)
Output Modes 2, 4, 6
VIN = 0V; No load
SE Headphone
3.8
mA
Output Modes 1, 3, 5, 7
VIN = 0V; No Load,
SE Headphone
6.6
mA
Output Modes 2, 4, 6
VIN = 0V; No load,
OCL Headphone
4.6
mA
Output Modes 1, 3, 5
VIN = 0V; No Load,
OCL Headphone
6
mA
Output Modes 7
VIN = 0V; No Load,
OCL Headphone
7.4
mA
Output Mode 0
0.05
µA
VIN = 0V, Mode 7
Mono
12
VIN = 0V, Mode 7
Headphones
3
mV
MONOOUT; RL = 8Ω
THD+N = 1%; f = 1kHz, BTL, Mode 1
1.3
W
ROUT and LOUT; RL = 32Ω
THD+N = 1%; f = 1kHz, SE, Mode 4
85
mW
MONOOUT, f = 1kHz
POUT = 500mW; RL = 8Ω, BTL, Mode 1
0.05
%
ROUT and LOUT, f = 1kHz
POUT = 30mW; RL = 32Ω, SE, Mode 4
0.012
%
Speaker; Mode 1
17
μV
Speaker; Mode 3, 7
27
μV
Speaker; Mode 5
33
μV
Headphone; SE, Mode 2
8
μV
Headphone; SE, Mode 4, 7
8
μV
Headphone; SE, Mode 6
12
μV
Headphone; OCL, Mode 2
8
μV
Headphone; OCL, Mode 4, 7
9
μV
Headphone; OCL, Mode 6
12
μV
BTL, Output Mode 1
69
dB
BTL, Output Mode 3, 7
60
dB
BTL, Output Mode 5
58
dB
A-weighted,
inputs terminated to GND, output referred
NOUT
PSRR
(1)
(2)
(3)
(4)
(5)
8
Output Noise
Power Supply rejection Ratio
MONOOUT
VRIPPLE = 200mVPP; f = 217Hz, RL = 8Ω
CB = 2.2µF, BTL
All audio inputs terminated to GND;
output referred
Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to the ground pin, unless otherwise specified.
Datasheet min/max specifications are specified by design, test, or statistical analysis.
Typical specifications are specified at +25°C and represent the most likely parametric norm.
Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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Electrical Characteristics 5.0V(1)(2) (continued)
The following specifications apply for VDD = 5.0V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified.
Symbol
Parameter
Conditions
LM4946
Typical
(4)
Limits
Units
(Limits) (3)
(5)
VRIPPLE = 200mVPP; f = 217Hz, RL = 32Ω
CB = 2.2µF, BTL
All audio inputs terminated to GND;
output referred
PSRR
Power Supply Rejection Ratio
ROUT and LOUT
SE, Output Mode 2
75
dB
SE, Output Mode 4,7
75
dB
SE, Output Mode 6
72
dB
OCL, Output Mode 2
75
dB
OCL, Output Mode 4, 7
79
dB
OCL, Output Mode 6
72
dB
Maximum attenuation
-54
-56
-52
dB (max)
dB (min)
Maximum gain
18
17.4
18.6
dB (min)
dB (max)
Output Mode 1, 3, 5
96
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
Digital Volume Control Range
HP(SE) Mute Attenuation
MONO_IN Input Impedance
RIN and LIN Input Impedance
CMRR
XTALK
TWU
Common-Mode Rejection Ratio
Crosstalk
Wake-Up Time from Shutdown
dB
Maximum gain setting
12.5
10
15
Maximum attenuation setting
110
90
130
f = 217Hz, VCM = 1Vpp, 0dB gain
Mode 1, BTL, RL = 8Ω
61
f = 217Hz, VCM = 1Vpp, 0dB gain
Mode 2, RL = 32Ω
66
Headphone; PO = 30mW, OCL, Mode 4
–55
Headphone; PO = 30mW, SE, Mode 4
–72
dB
CB = 2.2μF, OCL
135
ms
CB = 2.2μF, SE
180
ms
dB
dB
I2C/SPI WQFN/DSBGA (1) (2)
The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 2.2V ≤ I2CSPI_VDD ≤ 5.5V, unless otherwise specified.
Symbol
Parameter
Conditions
LM4946 (3)
Typical (5)
t1
I2C Clock Period
2
Limits (6)
(2)
Units
(Limits) (4)
2.5
µs (min)
t2
I C Data Setup Time
100
ns (min)
t3
I2C Data Stable Time
0
ns (min)
t4
Start Condition Time
100
ns (min)
t5
Stop Condition Time
100
ns (min)
t6
I2C Data Hold Time
100
ns (min)
fSPI
Maximum SPI Frequency
1000
kHz (max)
tEL
SPI ENB High Time
100
ns (min)
tDS
SPI Data Setup Time
100
ns (min)
tES
SPI ENB Setup Time
100
ns (min)
(1)
(2)
(3)
(4)
(5)
(6)
Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to the ground pin, unless otherwise specified.
For LM4946 WQFN package, revised specification goes into effect starting with date code 79. Existing specification is per datasheet rev
1.0
Datasheet min/max specifications are specified by design, test, or statistical analysis.
Typical specifications are specified at +25°C and represent the most likely parametric norm.
Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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I2C/SPI WQFN/DSBGA(1)(2) (continued)
The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 2.2V ≤ I2CSPI_VDD ≤ 5.5V, unless otherwise specified.
Symbol
Parameter
LM4946 (3)
Conditions
Typical
(5)
Limits
(6) (2)
Units
(Limits) (4)
tDH
SPI Data Hold Time
100
ns (min)
tEH
SPI Enable Hold Time
100
ns (min)
tCL
SPI Clock Low Time
500
ns (min)
tCH
SPI Clock High Time
500
ns (min)
V (min)
V (max)
VIH
I C/SPI Input Voltage High
0.7xI2CSPI
VDD
VIL
I2C/SPI Input Voltage Low
0.3xI2CSPI
VDD
2
I2C/SPI DSBGA only (1) (2)
The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 1.7V ≤ I2CSPI_VDD ≤ 2.2V, unless otherwise specified.
Symbol
Parameter
Conditions
LM4946
Typical
(4)
Limits
(5) (2)
Units
(Limits) (3)
t1
I2C Clock Period
2.5
µs (min)
t2
I2C Data Setup Time
250
ns (min)
2
t3
I C Data Stable Time
0
ns (min)
t4
Start Condition Time
250
ns (min)
t5
Stop Condition Time
250
ns (min)
2
t6
I C Data Hold Time
250
ns (min)
fSPI
Maximum SPI Frequency
250
kHz (max)
tEL
SPI ENB High Time
250
ns (min)
tDS
SPI Data Setup Time
250
ns (min)
tES
SPI ENB Setup Time
250
ns (min)
tDH
SPI Data Hold Time
250
ns (min)
tEH
SPI Enable Hold Time
250
ns (min)
tCL
SPI Clock Low Time
500
ns (min)
tCH
SPI Clock High Time
500
ns (min)
V (min)
V (max)
VIH
I2C/SPI Input Voltage High
0.7xI2CSPI
VDD
VIL
I2C/SPI Input Voltage Low
0.25 xI2CSPI
VDD
(1)
(2)
(3)
(4)
(5)
10
Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
Some performance characteristics may degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to the ground pin, unless otherwise specified.
Datasheet min/max specifications are specified by design, test, or statistical analysis.
Typical specifications are specified at +25°C and represent the most likely parametric norm.
Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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Typical Performance Characteristics
10
THD+N vs Frequency
VDD = 3.3V, RL = 8Ω, PO = 250mW
Mode 1, BTL, BW = 80kHz
THD+N vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Mode 4, 7, OCL, BW = 80kHz
10
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
0.001
20
200
2k
20k
0.001
20
FREQUENCY (Hz)
THD+N vs
Frequency VDD = 3.3V, RL = 32Ω, PO = 12mW
Mode 6, OCL, BW = 80kHz
10
20k
THD+N vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Mode 4, 7, SE, BW = 80kHz
10
1
1
THD+N (%)
THD+N (%)
2k
FREQUENCY (Hz)
Figure 6.
Figure 5.
0.1
0.01
0.1
0.01
0.001
20
200
2k
20k
0.001
20
200
2k
FREQUENCY (Hz)
Figure 7.
FREQUENCY (Hz)
THD+N vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Mode 6, SE, BW = 80kHz
THD+N vs Frequency
VDD = 3.3V, RL = 8Ω, PO = 250mW
Mode 5, BTL, BW = 80kHz
10
10
1
1
0.1
0.1
0.01
0.01
0.001
20
20k
Figure 8.
THD+N (%)
THD+N (%)
200
200
2k
20k
0.001
20
200
2k
20k
FREQUENCY (Hz)
Figure 10.
FREQUENCY (Hz)
Figure 9.
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Typical Performance Characteristics (continued)
10
10
1
1
THD+N (%)
THD+N (%)
THD+N vs Frequency
VDD = 5V, RL = 8Ω, PO = 500mW
Mode 1, BTL, BW = 80kHz
0.1
10
0.1
0.01
0.01
0.001
20
200
2k
20k
0.001
20
THD+N vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
Mode 4, 7, SE, BW = 80kHz
THD+N vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
Mode 6, OCL, BW = 80kHz
1
THD+N (%)
THD+N (%)
0.1
0.01
200
2k
20k
0.001
20
200
2k
FREQUENCY (Hz)
Figure 13.
FREQUENCY (Hz)
THD+N vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
Mode 6, SE, BW = 80kHz
THD+N vs Frequency
VDD = 5V, RL = 8Ω, PO = 500mW
Mode 5, BTL
20k
Figure 14.
10
10
1
1
THD+N (%)
THD+N (%)
20k
10
0.01
0.1
0.1
0.01
0.01
200
2k
20k
0.001
20
200
2k
20k
FREQUENCY (Hz)
Figure 16.
FREQUENCY (Hz)
Figure 15.
12
2k
FREQUENCY (Hz)
Figure 12.
0.1
0.001
20
200
FREQUENCY (Hz)
Figure 11.
1
0.001
20
THD+N vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
Mode 4, 7, OCL, BW = 80kHz
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Typical Performance Characteristics (continued)
THD+N vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Mode 2, OCL
THD+N vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Mode 2, SE, BW = 80kHz
10
10
THD+N (%)
THD+N (%)
1
0.1
1
0.01
0.001
20
200
2k
0.1
20
20k
2k
FREQUENCY (Hz)
Figure 17.
Figure 18.
THD+N vs Frequency
VDD = 3.3V, RL = 8Ω, PO = 250mW
Mode 3, BTL
THD+N vs Output Power
VDD = 3.3V, RL = 8Ω, f = 1kHz
Mode 1, BTL
20k
10
10
1
THD+N (%)
THD+N (%)
200
FREQUENCY (Hz)
1
0.1
0.1
20
200
2k
0.01
10
20k
100
1000
OUTPUT POWER (mW)
Figure 19.
Figure 20.
THD+N vs Output Power
VDD = 3.3V, RL = 8Ω, f = 1kHz
Mode 5, BTL
THD+N vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz
Mode 4, 7, OCL
10
10
1
1
THD+N (%)
THD+N (%)
FREQUENCY (Hz)
0.1
0.01
10
0.1
100
1000
OUTPUT POWER (mW)
0.01
1
10
100
OUTPUT POWER (mW)
Figure 21.
Figure 22.
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Typical Performance Characteristics (continued)
THD+N vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz
Mode 6, SE
10
10
1
1
THD+N (%)
THD+N (%)
THD+N vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz
Mode 4, 7, SE
0.1
0.1
0.01
0.01
1
10
100
1
10
OUTPUT POWER (mW)
Figure 23.
Figure 24.
THD+N vs Output Power
VDD = 5V, RL = 8Ω, f = 1kHz
Mode 1, BTL
THD+N vs Output Power
VDD = 5V, RL = 8Ω, f = 1kHz
Mode 5, BTL
10
10
1
1
0.1
0.1
0.01
20
50
100
200
500
1k
0.01
20
2k
50
100
200
500
1k
2k
OUTPUT POWER (mW)
Figure 25.
Figure 26.
THD+N vs Output Power
VDD = 5V, RL = 32Ω, f = 1kHz
Mode 4, 7, OCL
THD+N vs Output Power
VDD = 5V, RL = 32Ω, f = 1kHz
Mode 4, 7, SE
10
10
1
1
THD+N (%)
THD+N (%)
OUTPUT POWER (mW)
0.1
0.1
0.01
0.01
0.001
0.001
2
5
10
20
50
100
200
2
5
10
20
50
100
200
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 27.
14
100
THD+N (%)
THD+N (%)
OUTPUT POWER (mW)
Figure 28.
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Typical Performance Characteristics (continued)
THD+N vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz
Mode 6, Mono Input, OCL
10
10
1
1
THD+N (%)
THD+N (%)
THD+N vs Output Power
VDD = 5V, RL = 32Ω, f = 1kHz
Mode 6, SE
0.1
0.1
0.01
0.001
0.01
2
5
10
20
50
100
200
1
OUTPUT POWER (mW)
10
100
OUTPUT POWER (mW)
Figure 29.
Figure 30.
THD+N vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz
Mode 6, Stereo Input, OCL
THD+N vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz
Mode 2, OCL
10
10
1
THD+N (%)
THD+N (%)
1
0.1
0.1
0.01
0.01
1
10
1
100
10
100
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 31.
Figure 32.
THD+N vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz
Mode 2, SE
THD+N vs Output Power
VDD = 3.3V, RL = 8Ω, f = 1kHz
Mode 3, BTL
10
10
THD+N (%)
THD+N (%)
1
1
0.1
0.01
1
10
100
0.1
0.01
0.1
OUTPUT POWER (mW)
OUTPUT POWER (W)
Figure 33.
Figure 34.
1
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Typical Performance Characteristics (continued)
-10
-20
-20
-30
-30
-40
-40
-50
-60
-70
-50
-60
-70
-80
-80
-90
-100
20
PSRR vs Frequency
VDD = 3.3V, 0dB
Mode 4, 7, SE
0
-10
PSRR (dB)
PSRR (dB)
0
PSRR vs Frequency
VDD = 3.3V, 0dB
Mode 4, 7, OCL
-90
200
2k
-100
20
20k
200
2k
20k
FREQUENCY (Hz)
Figure 36.
PSRR vs Frequency
VDD = 3.3V, 0dB
Mode 6, OCL
PSRR vs Frequency
VDD = 3.3V, 0dB
Mode 6, SE
0
0
-10
-10
-20
-20
-30
-30
PSRR (dB)
PSRR (dB)
FREQUENCY (Hz)
Figure 35.
-40
-50
-60
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
200
2k
-100
20
20k
Figure 37.
Figure 38.
PSRR vs Frequency
VDD = 3.3V, 6dB
Mode 1, BTL
PSRR vs Frequency
VDD = 3.3V, RL = 8Ω
Mode 3, 7, BTL
0
0
-10
-10
-20
-20
-30
-30
PSRR (dB)
PSRR (dB)
2k
-40
-50
-60
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
20
200
2k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
20k
FREQUENCY (Hz)
200
2k
20k
FREQUENCY (Hz)
Figure 39.
16
200
Figure 40.
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Typical Performance Characteristics (continued)
PSRR vs Frequency
VDD = 3.3V, RL = 8Ω
Mode 2, SE
0
-10
-20
-20
-30
-30
PSRR (dB)
0
-10
-40
-50
-60
-40
-50
-60
-70
-70
-80
-80
-90
-90
-100
20
-100
20
200
2k
20k
Figure 42.
PSRR vs Frequency
VDD = 3.3V, 6dB
Mode 5, BTL
PSRR vs Supply Voltage
RL = 8Ω, 217Hz
Mode 1, BTL
0
-10
-20
-20
-30
-30
-40
-40
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
200
2k
-100
3.0
20k
3.5
FREQUENCY (Hz)
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
Figure 43.
Figure 44.
PSRR vs Supply Voltage
RL = 32Ω, 217Hz
Mode 4, OCL
PSRR vs Supply Voltage
RL = 32Ω, 217Hz
Mode 4, SE
0
0
-10
-10
-20
-20
-30
-30
-40
-40
PSRR (dB)
PSRR (dB)
20k
Figure 41.
0
-50
-60
-50
-60
-70
-70
-80
-80
-90
-90
-100
3.0
2k
FREQUENCY (Hz)
-10
-100
20
200
FREQUENCY (Hz)
PSRR (dB)
PSRR (dB)
PSRR (dB)
PSRR vs Frequency
VDD = 3.3V, RL = 32Ω
Mode 2, OCL
3.5
4.0
4.5
5.0
5.5
6.0
-100
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 45.
Figure 46.
5.5
6.0
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Typical Performance Characteristics (continued)
Power Dissipation vs Output Power
VDD = 3.3V, RL = 32Ω
f = 1kHz, Mode 2, 4, 6, SE
100
Power Dissipation vs Output Power
VDD = 5V, RL = 8Ω
f = 1kHz, Mode 1, 3, 5, BTL
700
POWER DISSIPATION (mW)
POWER DISSIPATION (mW)
90
80
70
60
50
40
30
20
10
0
600
500
400
300
200
100
0
0
10
20
30
40
0
50
200
Power Dissipation vs Output Power
VDD = 3.3V, RL = 8Ω, f = 1kHz,
Modes 1, 3, 5, BTL
350
300
POWER DISSIPATION (mW)
POWER DISSIPATION (mW)
Power Dissipation vs Output Power
VDD = 5V, RL = 32Ω
f = 1kHz, Mode 2, 4, 6, OCL
200
150
100
50
250
200
150
100
50
0
0
20
40
60
80
100
0
50
100
OUTPUT POWER (mW)
150
200
250
300
350
OUTPUT POWER (mW)
Figure 49.
Figure 50.
Power Dissipation vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz,
Modes 2, 4, 6, OCL
Power Dissipation vs Output Power
VDD = 3.3V, RL = 8Ω, f = 1kHz,
Mode 7, OCL
250
POWER DISSIPATION (mW)
250
200
POWER DISSIPATION (mW)
1000 1200
Figure 48.
0
150
100
50
0
10
20
30
40
50
200
150
100
50
0
0
10
20
30
40
50
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Figure 51.
18
800
Figure 47.
250
0
600
OuUTPUT POWER (mW)
OUTPUT POWER (mW)
300
400
Figure 52.
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Typical Performance Characteristics (continued)
Crosstalk vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Right-Left, Mode 4, OCL
0
90
-10
80
-20
70
-30
CROSSTALK (dB)
POWER DISSIPATION (mW)
100
Power Dissipation vs Output Power
VDD = 3.3V, RL = 32Ω, f = 1kHz,
Mode 7, SE
60
50
40
30
-40
50
Right to Left
-60
Left to Right
-70
20
-80
10
-90
0
-100
0
10
20
30
40
50
20
Figure 54.
Crosstalk vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
Left-Right, Mode 4, OCL
Crosstalk vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW
Mode 4, SE
0
0
-10
-20
-20
-30
-30
CROSSTALK (dB)
CROSSTALK (dB)
Figure 53.
-10
-40
Right to Left
Left to Right
-60
-70
50
-60
-90
-90
-100
200
2k
Left to Right
-70
-80
20
20k
-40
-80
-100
2k
FREQUENCY (Hz)
OUTPUT POWER (mW)
50
200
20k
Right to Left
20
FREQUENCY (Hz)
200
2k
20k
FREQUENCY (Hz)
Figure 55.
Figure 56.
Crosstalk vs Frequency
VDD = 5V, RL = 32Ω, PO = 30mW
Mode 4, SE
Supply Current vs Supply Voltage
No Load, Mode 7
0
12
-10
10
SUPPLY CURRENT (mA)
CROSSTALK (dB)
-20
-30
-40
50
-60
-70
Right to Left
-80
6
4
2
Left to Right
-90
8
0
-100
20
200
2k
20k
FREQUENCY (Hz)
3
4
5
6
SUPPLY VOLTAGE (V)
Figure 57.
Figure 58.
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Typical Performance Characteristics (continued)
12
Supply Current vs Supply Voltage
VDD = 3.3V, No Load, Modes 1, 3, 5
10
SUPPLY CURRENT (mA)
10
SUPPLY CURRENT (mA)
Supply Current vs Supply Voltage
No Load, Modes 2, 4, 6
12
8
6
4
8
6
4
2
2
0
0
3
4
5
3
6
4
6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 59.
2.5
5
Figure 60.
Output Power vs Supply Voltage
RL = 8Ω, f = 1kHz, Mono, Mode 1
160
Output Power vs Supply Voltage
RL = 32Ω, f = 1kHz, OCL, Mode 4
OUTPUT POWER (W)
OUTPUT POWER (mW)
140
2.0
THD+N = 10%
1.5
1.0
THD+N = 1%
120
THD+N = 10%
100
80
60
THD+N = 1%
40
0.5
20
0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
3.5
4.0
4.5
5.0
5.5
6.0
VOLTAGE SUPPLY (V)
VOLTAGE SUPPLY (V)
Figure 61.
20
0
3.0
Figure 62.
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APPLICATION INFORMATION
I2C PIN DESCRIPTION
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ID_ENB: This is the address select input pin.
I2CSPI_SEL: This is tied LOW for I2C mode.
I2C COMPATIBLE INTERFACE
The LM4946 uses a serial bus which conforms to the I2C protocol to control the chip's functions with two wires:
clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The
maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4946.
The I2C address for the LM4946 is determined using the ID_ENB pin. The LM4946's two possible I2C chip
addresses are of the form 111110X10 (binary), where X1 = 0, if ID_ENB is logic LOW; and X1 = 1, if ID_ENB is
logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM4946's chip address can
be changed to avoid any possible address conflicts.
The bus format for the I2C interface is shown in Figure 63. The bus format diagram is broken up into six major
sections:
1. The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will
alert all devices attached to the I2C bus to check the incoming address against their own address.
2. The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the
clock. Each address bit must be stable while the clock level is HIGH.
For I2C interface operation, the I2CSPI_SEL pin needs to be tied LOW (and tied high for SPI operation).
3. After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up
resistor). Then the master sends an acknowledge clock pulse. If the LM4946 has received the address
correctly, then it holds the data line LOW during the clock pulse. If the data line is not held LOW during the
acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM4946.
4. The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is
stable HIGH.
5. After the data byte is sent, the master must check for another acknowledge to see if the LM4946 received
the data.
If the master has more data bytes to send to the LM4946, then the master can repeat the previous two steps
until all data bytes have been sent.
6. The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is
HIGH. The data line should be held HIGH when not in use.
I2C INTERFACE POWER SUPPLY PIN (I2CSPI_VDD)
The LM4946's I2C interface is powered up through the I2CSPI_VDD pin. The LM4946's I2C interface operates at a
voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This
is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.
Figure 63. I2C Bus Format
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Figure 64. I2C Timing Diagram
SPI DESCRIPTION
(For 2.2V ≤ I2CSPI_VDD ≤ 5.5V, see I2C/SPI WQFN/DSBGA for more information).
0. I2CSPI_SEL: This pin is tied HIGH for SPI mode.
1. The data bits are transmitted with the MSB first.
2. The maximum clock rate is 1MHz for the CLK pin.
3. CLK must remain HIGH for at least 500ns (tCH ) after the rising edge of CLK, and CLK must remain LOW for at
least 500ns (tCL) after the falling edge of CLK.
4. The serial data bits are sampled at the rising edge of CLK. Any transition on DATA must occur at least 100ns
(tDS) before the rising edge of CLK. Also, any transition on DATA must occur at least 100ns (tDH) after the rising
edge of CLK and stabilize before the next rising edge of CLK.
5.ID_ENB should be LOW only during serial data transmission.
6. ID_ENB must be LOW at least 100ns (tES ) before the first rising edge of CLK, and ID_ENB has to remain
LOW at least 100ns (tEH) after the eighth rising edge of CLK.
7. If ID_ENB remains HIGH for more than 100ns before all 8 bits are transmitted then the data latch will be
aborted.
8. If ID_ENB is LOW for more than 8 CLK pulses then only the first 8 data bits will be latched and activated when
ID_ENB transitions to logic-high.
9. ID_ENB must remain HIGH for at least 100ns (tEL ) to latch in the data.
10. Coincidental rising or falling edges of CLK and ID_ENB are not allowed. If CLK is to be held HIGH after the
data transmission, the falling edge of CLK must occur at least 100ns (tCS) before ID_ENB transitions to LOW for
the next set of data.
ID_ENB
tCS
tES
tCH
tCL
tEH
tEL
CLK
tDS
DATA
tDH
Data 7
Data 6
Data 1
Data 0
Figure 65. SPI Timing Diagram
22
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Table 1. Chip Address
A7
A6
A5
A4
A3
A2
A1
A0
Chip Address
1
1
1
1
1
0
EC (1)
0
ID_ENB = 0
1
1
1
1
1
0
0
0
ID_ENB = 1
1
1
1
1
1
0
1
0
(1)
EC — Externally Controlled
Table 2. Control Registers (1)
D7
D6
D5
D4
D3
D2
D1
D0
Mode Control
0
0
0
0
OCL
MC2
MC1
MC0
Programmable 3D
0
1
0
0
N3D3
N3D2
N3D1
N3D0
Mono Volume Control
1
0
0
MVC4
MVC3
MVC2
MVC1
MVC0
Left Volume Control
1
1
0
LVC4
LVC3
LVC2
LVC1
LVC0
Right Volume Control
1
1
1
RVC4
RVC3
RVC2
RVC1
RVC0
(1)
Bits MVC0 — MVC4 control 32 step volume control for MONO input
Bits LVC0 — LVC4 control 32 step volume control for LEFT input
Bits RVC0 — RVC4 control 32 step volume control for RIGHT input
Bits MC0 — MC2 control 8 distinct modes
Bits N3D3, N3D2, N3D1, N3D0 control programmable 3D function
N3D0 turns the 3D function ON (N3D0 = 1) or OFF (N3D0 = 0), and N3D1 = 0 provides a “wider” aural effect or N3D1 = 1 a “narrower”
aural effect
Bit OCL selects between SE with output capacitor (OCL = 0) or SE without output capacitors (OCL = 1). Default is OCL = 0
Table 3. Programmable TI 3D Audio
N3D3
N3D2
Low
0
0
Medium
0
1
High
1
0
Maximum
1
1
Table 4. Output Mode Selection (1)
Output Mode
Number
MC2
MC1
MC0
Handsfree Speaker Output
Right HP Output
Left HP Output
0
0
0
0
SD
SD
SD
1
0
0
1
GP X P
MUTE
MUTE
2
0
1
0
SD
GP X P/2
GP X P/2
3
0
1
1
2 X (GL X L + GR X R)
MUTE
MUTE
4
1
0
0
SD
GR X R
GL X L
5
1
0
1
2 X (GL X L + GR X R) + GP
XP
MUTE
MUTE
6
1
1
0
SD
GR X R + GP X P/2
GL X L + GP X P/2
7
1
1
1
2 X (GR X R + GL X L)
GR X R
GL X L
(1)
On initial POWER ON, the default mode is 000
P = Phone-in (Mono)
R = RIN
L = LIN
SD = Shutdown
MUTE = Mute Mode
GP = Phone In (Mono) volume control gain
GR = Right stereo volume control gain
GL = Left stereo volume control gain
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Table 5. Volume Control Table (1)
(1)
Volume Step
xVC4
xVC3
xVC2
xVC1
xVC0
Gain,dB
1
0
0
0
0
0
–54.00
2
0
0
0
0
1
–46.50
3
0
0
0
1
0
–40.50
4
0
0
0
1
1
–34.50
5
0
0
1
0
0
–30.00
6
0
0
1
0
1
–27.00
7
0
0
1
1
0
–24.00
8
0
0
1
1
1
–21.00
9
0
1
0
0
0
–18.00
10
0
1
0
0
1
–15.00
11
0
1
0
1
0
–13.50
12
0
1
0
1
1
–12.00
13
0
1
1
0
0
–10.50
14
0
1
1
0
1
–9.00
15
0
1
1
1
0
–7.50
16
0
1
1
1
1
–6.00
17
1
0
0
0
0
–4.50
18
1
0
0
0
1
–3.00
19
1
0
0
1
0
–1.50
20
1
0
0
1
1
0.00
21
1
0
1
0
0
1.50
22
1
0
1
0
1
3.00
23
1
0
1
1
0
4.50
24
1
0
1
1
1
6.00
25
1
1
0
0
0
7.50
26
1
1
0
0
1
9.00
27
1
1
0
1
0
10.50
28
1
1
0
1
1
12.00
29
1
1
1
0
0
13.50
30
1
1
1
0
1
15.00
31
1
1
1
1
0
16.50
32
1
1
1
1
1
18.00
x = M, L, or R
Gain / Attenuation is from input to output
TI 3D ENHANCEMENT
The LM4946 features a stereo headphone, 3D audio enhancement effect that widens the perceived soundstage
from a stereo audio signal. The 3D audio enhancement creates a perceived spatial effect optimized for stereo
headphone listening. The LM4946 can be programmed for a “narrow” or “wide” soundstage perception. The
narrow soundstage has a more focused approaching sound direction, while the wide soundstage has a spatial,
theater-like effect. Within each of these two modes, four discrete levels of 3D effect that can be programmed:
low, medium, high, and maximum (Table 2, Table 3), each level with an ever increasing aural effect, respectively.
The difference between each level is 3dB.
The external capacitors, shown in Figure 66, are required to enable the 3D effect. The value of the capacitors set
the cutoff frequency of the 3D effect, as shown by Equation 1 and Equation 2. Note that the internal 20kΩ
resistor is nominal.
24
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20 k: (internal resistor)
C3DL
RHP3D2
RHP3D1
LHP3D2
LHP3D1
LM4946
C3DR
Figure 66. External 3D Effect Capacitors
f3DL(-3dB) = 1 / 2π * 20kΩ * C3DL
f3DR(-3dB) = 1 / 2π * 20kΩ * C3DR
(1)
(2)
Optional resistors R3DL and R3DR can also be added (Figure 67) to affect the -3dB frequency and 3D magnitude.
20 k: (internal resistor)
RHP3D2
RHP3D1
LHP3D2
LHP3D1
LM4946
C3DL
C3DR
R3DL
R3DR
Figure 67. External RC Network with Optional R3DL and R3DR Resistors
f3DL(-3dB) = 1 / 2π * (20kΩ + R3DL) * C3DL
f3DR(-3dB) = 1 / 2π * 20kΩ + R3DR) * C3DR
(3)
(4)
ΔAV (change in AC gain) = 1 / 1 + M, where M represents some ratio of the nominal internal resistor, 20kΩ (see
example below).
f3dB (3D) = 1 / 2π (1 + M)(20kΩ * C3D)
CEquivalent (new) = C3D / 1 + M
(5)
(6)
Table 6. Pole Locations
R3D (kΩ)
(optional)
C3D (nF)
M
ΔAV (dB)
f-3dB (3D)
(Hz)
0
68
0
0
117
1
68
0.05
–0.4
5
68
0.25
–1.9
10
68
0.50
20
68
1.00
Value of C3D
to keep same
pole location
(nF)
new Pole
Location
(Hz)
111
64.8
117
94
54.4
117
–3.5
78
45.3
117
–6.0
59
34.0
117
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PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 8Ω LOAD
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load
impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and
wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes
a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω
trace resistance reduces the output power dissipated by an 8Ω load from 158.3mW to 156.4mW. The problem of
decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load
dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide
as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output
voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output
signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the
same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps
maintain full output voltage swing.
BRIDGE CONFIGURATION EXPLANATION
The LM4946 drives a load, such as a speaker, connected between outputs, MONO+ and MONO-.
This results in both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage
of this phase difference, a load is placed between MONO- and MONO+ and driven differentially (commonly
referred to as ”bridge mode”). This results in a differential or BTL gain of:
AVD = 2(Rf / Ri) = 2
(7)
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single
amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the singleended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces
four times the output power when compared to a single-ended amplifier under the same conditions. This increase
in attainable output power assumes that the amplifier is not current limited and that the output signal is not
clipped.
Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by
biasing MONO- and MONO+ outputs at half-supply. This eliminates the coupling capacitor that single supply,
single-ended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration
forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power
dissipation and may permanently damage loads such as speakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power
dissipation. The LM4946 has a pair of bridged-tied amplifiers driving a handsfree speaker, MONO. The maximum
internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From Equation 8,
assuming a 5V power supply and an 8Ω load, the maximum MONO power dissipation is 634mW.
PDMAX-SPKROUT = 4(VDD)2/ (2π2 RL): Bridge Mode
(8)
The LM4946 also has a pair of single-ended amplifiers driving stereo headphones, ROUT and LOUT. The maximum
internal power dissipation for ROUT and LOUT is given by Equation 9 and Equation 10. From Equation 9 and
Equation 10, assuming a 5V power supply and a 32Ω load, the maximum power dissipation for LOUT and ROUT is
40mW, or 80mW total.
PDMAX-LOUT = (VDD)2 / (2π2 RL): Single-ended Mode
PDMAX-ROUT = (VDD)2 / (2π2 RL): Single-ended Mode
(9)
(10)
The maximum internal power dissipation of the LM4946 occurs when all three amplifiers pairs are simultaneously
on; and is given by Equation 11.
PDMAX-TOTAL = PDMAX-SPKROUT + PDMAX-LOUT + PDMAX-ROUT
(11)
The maximum power dissipation point given by Equation 11 must not exceed the power dissipation given by
Equation 12:
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PDMAX = (TJMAX - TA) / θJA
(12)
The LM4946's TJMAX = 150°C. In the SQ package, the LM4946's θJA is 46°C/W. At any given ambient
temperature TA, use Equation 12 to find the maximum internal power dissipation supported by the IC packaging.
Rearranging Equation 12 and substituting PDMAX-TOTAL for PDMAX' results in Equation 13. This equation gives the
maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4946's
maximum junction temperature.
TA = TJMAX - PDMAX-TOTAL θJA
(13)
For a typical application with a 5V power supply and an 8Ω load, the maximum ambient temperature that allows
maximum mono power dissipation without exceeding the maximum junction temperature is approximately 121°C
for the SQ package.
TJMAX = PDMAX-TOTAL θJA + TA
(14)
Equation 14 gives the maximum junction temperature TJMAX. If the result violates the LM4946's 150°C, reduce
the maximum junction temperature by reducing the power supply voltage or increasing the load resistance.
Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are
allowed as output power or duty cycle decreases. If the result of Equation 11 is greater than that of Equation 12,
then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these
measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional
copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins.
External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation.
When adding a heat sink, the θJA is the sum of θJC, θCS, and θSA. (θJC is the junction-to-case thermal impedance,
θCS is the case-to-sink thermal impedance, and θSA is the sink-to-ambient thermal impedance). Refer to the
Typical Performance Characteristics curves for power dissipation information at lower output power levels.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 1µF in parallel with a 0.1µF filter capacitors to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 1.0µF tantalum bypass capacitor and a parallel
0.1µF ceramic capacitor connected between the LM4946's supply pin and ground. Keep the length of leads and
traces that connect capacitors between the LM4946's power supply pin and ground as short as possible.
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value input coupling capacitor (Ci in Figure 1 & Figure 2).
A high value capacitor can be expensive and may compromise space efficiency in portable designs. In many
cases, however, the speakers used in portable systems, whether internal or external, have little ability to
reproduce signals below 150Hz. Applications using speakers with this limited frequency response reap little
improvement by using large input capacitor.
The internal input resistor (Ri), minimum 10kΩ, and the input capacitor (Ci) produce a high pass filter cutoff
frequency that is found using Equation 15.
fc = 1 / (2πRiCi)
(15)
As an example when using a speaker with a low frequency limit of 150Hz, Ci, using Equation 15 is 0.106µF. The
0.22µF Ci shown in Figure 1 allows the LM4946 to drive high efficiency, full range speaker whose response
extends below 40Hz.
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Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor
connected to the BYPASS pin. Since CB determines how fast the LM4946 settles to quiescent operation, its
value is critical when minimizing turn-on pops. The slower the LM4946's outputs ramp to their quiescent DC
voltage (nominally VDD/2), the smaller the turn-on pop. Choosing CB equal to 2.2µF along with a small value of Ci
(in the range of 0.1µF to 0.33µF), produces a click-less and pop-less shutdown function. As discussed above,
choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value
should be in the range of 7 to 10 times the value of Ci. This ensures that output transients are eliminated when
power is first applied or the LM4946 resumes operation after shutdown.
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Demo Board Schematic Diagram
External I2CSPI_VDD
2
3
LM4946SQ
I2CSPI_SEL
MONO_IN+
CIN4
MONO_IN+
MONO
MONO+
MONO-
1 PF polarized
CIN3
MONO_IN1 PF polarized
RIGHT_IN
RIN
GND
LEFT_IN
LIN
GND
RIN
I2CSPI_VDD
VDD
VDD
CBYPASS
CIN2
RIN
0.22 PF polarized
CIN1
GND
GND
MONO+
LIN
0.22 PF polarized
MONOLOUT
ROUT
LHP3D1
LHP3D2
VOC
RHP3D1
RHP3D2
GND
ID_ENB
MONO_IN-
10
14
23
8
7
16
3
J1
SCL
CI2CSPI_Supply
1 PF Polarized
VDD
SDA
VDD
VDD
GND
I2CSPI_SEL
I2CSPI_VDD
CSUPPLY2
0.10 PF ceramic
CSUPPLY1
1 PF Polarized
I2CSPI Header
I2CSPI_VDD
MONO_IN+
SDA/DATA
RIN
J2
I2CSPI_VDD
VDD
1
VDD
2
VDD
3
1
2
SPI Mode = 1 - 2
I2C Mode = 2 - 3
SDA
SCL/CLOCK
SCL
ID_ENB
ADDR/ID_ENB
I2CSPI_SEL
3
NO CONNECT
GND
21
4
J3
CBYPASS
2.2 PF Polarized
J4
ROUT
20
Speaker
ROUT PIN2
1
2
SDA
LIN
1
2
SCL
9
11
1
2
LIN
1
2
15
STEREO HEADPHONE JACK
1
1
17
COL
6
2
COR
5
100 PF Polarized
R3DL
18
0:
1
2
100 PF Polarized
0 Farads
C3DL1
68 nF ceramic
1
R3DR
0:
24
2
0 Farads
C3DR1
68 nF ceramic
C3DR2
0 Farads ceramic
22
3
1
2
VOC
LOUT PIN2
SLEEVE
1
3
2
J5
12
13
LOUT
C3DL2
0 Farads ceramic
VOC
19
2
3
SLEEVE 3
1
ID_ENB
2
MONO_IN3
1
2
3
VOC
1
2
1
2
VOC
LOUT-PIN2
3
J7
ROUT_PIN2
3
J6
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REVISION HISTORY
Rev
Date
Description
1.0
01/23/06
Initial release.
1.1
03/05/07
Added the YFQ0025XXX package.
1.2
03/13/07
Edited the 25–pin DSBGA connection
diagram.
1.3
04/24/07
Added the I2C/SPI (1.7V 2.2V ) table.
1.4
04/26/07
Added the numerical values for the X1,
X2, and X3 in the Physical Dimension
section.
1.5
05/02/07
Text edits. Added the YFQ package.
1.6
05/15/07
Added the TM board schematic and
input some text edits.
1.7
05/16/07
More text edits.
1.8
06/06/07
Added Note 11 and more text edits.
1.9
07/31/07
Edited the 5.0V EC table (MONO_IN
Input Impedance and Rin/Lin Input
Impedance).
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM4946SQ/NOPB
ACTIVE
WQFN
RTW
24
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
L4946SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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