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LM5001, LM5001-Q1
SNVS484H – JANUARY 2007 – REVISED JULY 2015
LM5001x High-Voltage Switch-Mode Regulator
1 Features
3 Description
•
•
•
The LM5001 high-voltage switch-mode regulator
features all of the functions necessary to implement
efficient high-voltage Boost, Flyback, SEPIC and
Forward converters, using few external components.
This easy-to-use regulator integrates a 75-V NChannel MOSFET with a 1-A peak current limit.
Current mode control provides inherently simple loop
compensation and line-voltage feed-forward for
superior rejection of input transients. The switching
frequency is set with a single resistor and is
programmable up to 1.5 MHz. The oscillator can also
be synchronized to an external clock. Additional
protection features include: current limit, thermal
shutdown, undervoltage lockout and remote
shutdown capability.
1
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified (TJ = –40°C to 125°C)
Integrated 75-V N-Channel MOSFET
Ultra-Wide Input Voltage Range from
3.1 V to 75 V
Integrated High Voltage Bias Regulator
Adjustable Output Voltage
1.5% Output Voltage Accuracy
Current Mode Control with Selectable
Compensation
Wide Bandwidth Error Amplifier
Integrated Current Sensing and Limiting
Integrated Slope Compensation
85% Maximum Duty Cycle Limit
Single Resistor Oscillator Programming
Oscillator Synchronization Capability
Enable / Undervoltage Lockout (UVLO) Pin
Thermal Shutdown
Device Information(1)
DEVICE NAME
LM5001
LM5001Q1
•
BODY SIZE
4.9 mm x 3.91 mm
WSON (8)
4 mm x 4 mm
SOIC (8)
4.9 mm x 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
PACKAGE
SOIC (8)
DC-DC Power Supplies for Industrial,
Communications, and Automotive Applications
Boost, Flyback, SEPIC and Forward Converter
Topologies
+12V to +36V
+48V
VIN
SW
COMP
EN
LM5001
FB
VCC
RT
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5001, LM5001-Q1
SNVS484H – JANUARY 2007 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
4
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics .............................................
Detailed Description .............................................. 8
7.1 Overview .................................................................. 8
7.2 Functional Block Diagram ........................................ 8
7.3 Feature Description .................................................. 9
8
Applications and Implementation ...................... 11
8.1 Application Information............................................ 11
8.2 Typical Applications ................................................ 14
9
Layout ................................................................... 18
9.1 Layout Guidelines ................................................... 18
10 Device and Documentation Support ................. 19
10.1
10.2
10.3
10.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
11 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
Changes from Revision G (April 2014) to Revision H
•
Page
Changed to match the new ESD table ................................................................................................................................... 4
Changes from Revision F (March 2013) to Revision G
•
Page
Added LM5001-Q1 option to Electrical Characteristics table ................................................................................................. 5
Changes from Revision E (March 2013) to Revision F
Page
•
Added availability of LM5001-Q1 option ................................................................................................................................ 1
•
Changed to new TI standard: Added Handling Ratings table and the Device and Documentation Support section. ........... 1
2
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SNVS484H – JANUARY 2007 – REVISED JULY 2015
5 Pin Configuration and Functions
SOIC (D) 8 Pins
Top View
SW
1
8
EN
VIN
2
7
COMP
VCC
3
6
FB
GND
4
5
RT
WSON (NGT) 8 Pins
Top View
COMP
1
EN
2
8 FB
7 RT
EP
SW
3
6 GND
VIN
4
5 VCC
Pin Functions
PIN
SOIC
WSON
1
3
2
4
NAME
TYPE
DESCRIPTION
SW
Switch pin
The drain terminal of the internal power MOSFET.
VIN
Input supply pin
Nominal operating range: 3.1 V to 75 V.
3
5
VCC
Bias regulator output, or input for external
bias supply
VCC tracks VIN up to 6.9 V. Above VIN = 6.9 V, VCC is
regulated to 6.9 V. A 0.47-µF or greater ceramic decoupling
capacitor is required. An external voltage (7 V – 12 V) can
be applied to this pin which disables the internal VCC
regulator to reduce internal power dissipation and improve
converter efficiency.
4
6
GND
Ground
Internal reference for the regulator control functions and the
power MOSFET current sense resistor connection.
5
7
RT
Oscillator frequency programming and
optional synchronization pulse input
The internal oscillator is set with a resistor, between this pin
and the GND pin. The recommended frequency range is 50
KHz to 1.5 MHz. The RT pin can accept synchronization
pulses from an external clock. A 100-pF capacitor is
recommended for coupling the synchronizing clock to the
RT pin.
6
8
FB
Feedback input from the regulated output
voltage
This pin is connected to the inverting input of the internal
error amplifier. The 1.26-V reference is internally connected
to the non-inverting input of the error amplifier.
Open drain output of the internal error
amplifier
The loop compensation network should be connected
between the COMP pin and the FB pin. COMP pull-up is
provided by an internal 5-kΩ resistor which may be used to
bias an opto-coupler transistor (while FB is grounded) for
isolated ground applications.
Enable / Undervoltage Lock-Out /
Shutdown input
An external voltage divider can be used to set the line
undervoltage lockout threshold. If the EN pin is left
unconnected, a 6-µA pull-up current source pulls the EN pin
high to enable the regulator.
Exposed Pad, WSON only
Exposed metal pad on the underside of the package with a
resistive connection to pin 6. It is recommended to connect
this pad to the PC board ground plane in order to improve
heat dissipation.
7
8
NA
1
2
EP
COMP
EN
EP
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SNVS484H – JANUARY 2007 – REVISED JULY 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
VIN to GND
SW to GND (Steady State)
–0.3
VCC, EN to GND
COMP, FB, RT to GND
–0.3
Maximum Junction Temperature
Storage Temperature Range, Tstg
-65
MAX
UNIT
76
V
76
V
14
V
7
V
150
°C
150
°C
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
VIN
Operating Junction Temperature
NOM
MAX
UNIT
3.1
75
V
−40
125
°C
6.4 Thermal Information
LM5001-Q1
THERMAL METRIC
SOIC
LM5001
SOIC
WSON
UNIT
(8 PINS)
RθJA
Junction-to-ambient thermal resistance
140
140
40
RθJCtop
Junction-to-case (top) thermal resistance
32
32
4.5
°C/W
6.5 Electrical Characteristics
Minimum and Maximum limits are ensured through test, design, or statistical correlation, over the junction temperature (TJ)
range of –40°C to +125°C. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for
reference purposes only. VVIN = 10 V, RRT = 48.7 kΩ unless otherwise stated (1).
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
7.15
UNIT
Startup Regulator
VVCC-REG
VCC Regulator Output
6.55
6.85
VCC Current Limit
VVCC = 6 V
15
20
VCC UVLO Threshold
VVCC increasing
2.6
2.8
VCC Undervoltage Hysteresis
IQ
(1)
4
V
mA
3
0.1
V
Bias Current (IIN)
VFB = 1.5 V
3.1
4.5
mA
Shutdown Current (IIN)
VEN = 0V
95
130
µA
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate TI’s Average Outgoing Quality Level (AOQL).
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Electrical Characteristics (continued)
Minimum and Maximum limits are ensured through test, design, or statistical correlation, over the junction temperature (TJ)
range of –40°C to +125°C. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for
reference purposes only. VVIN = 10 V, RRT = 48.7 kΩ unless otherwise stated(1).
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VEN increasing
0.25
0.45
0.65
VEN increasing
1.2
1.26
UNIT
EN Thresholds
EN Shutdown Threshold
EN Shutdown Hysteresis
0.1
EN Standby Threshold
EN Standby Hysteresis
1.32
V
0.1
EN Current Source
6
µA
MOSFET Characteristics
MOSFET RDS(ON) plus
Current Sense Resistance
LM5001
LM5001-Q1
ID = 0.5 A
MOSFET Leakage Current
VSW = 75 V
MOSFET Gate Charge
VVCC = 6.9 V
490
800
490
880
0.05
5
4.5
mΩ
µA
nC
Current Limit
ILIM
Cycle by Cycle Current Limit
0.8
Cycle by Cycle Current Limit Delay
1.0
1.2
A
100
200
ns
Oscillator
FSW1
Frequency1
RRT = 48.7 kΩ
225
260
295
FSW2
Frequency2
RRT = 15.8 kΩ
660
780
900
VRT-SYNC
SYNC Threshold
2.2
2.6
3.2
SYNC Pulse Width Minimum
VRT > VRT-SYNC + 0.5 V
15
KHz
V
ns
PWM Comparator
Maximum Duty Cycle
VCOMP-OS
80%
85%
Min On-time
VCOMP > VCOMP-OS
35
Min On-time
VCOMP < VCOMP-OS
0
COMP to PWM Comparator Offset
90%
ns
0.9
1.30
1.55
V
1.241
1.260
1.279
V
Error Amplifier
VFB-REF
Internal reference
VFB = VCOMP
Feedback Reference Voltage
FB Bias Current
10
nA
DC Gain
72
dB
COMP Sink Current
VCOMP = 250 mV
2.5
COMP Short Circuit Current
VFB = 0, VCOMP = 0
0.9
1.2
1.5
COMP Open Circuit Voltage
VFB = 0
4.8
5.5
6.2
COMP to SW Delay
Unity Gain Bandwidth
mA
V
50
ns
3
MHz
Thermal Shutdown
TSD
Thermal Shutdown Threshold
165
Thermal Shutdown Hysteresis
20
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°C
5
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SNVS484H – JANUARY 2007 – REVISED JULY 2015
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6.6 Typical Characteristics
6
Figure 1. Efficiency, Boost Converter
Figure 2. VFB vs Temperature
Figure 3. IQ (Non-Switching) vs VIN
Figure 4. VCC vs VIN
Figure 5. RDS(ON) vs VCC
Figure 6. RDS(ON) vs Temperature
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Typical Characteristics (continued)
Figure 7. ILIM vs VCC
Figure 8. ILIM vs VCC vs Temperature
Figure 9. FSW vs RRT
Figure 10. FSW vs Temperature
Figure 11. FSW vs VCC
Figure 12. IEN vs VVIN vs Temperature
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LM5001, LM5001-Q1
SNVS484H – JANUARY 2007 – REVISED JULY 2015
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7 Detailed Description
7.1 Overview
The LM5001 high voltage switching regulator features all the functions necessary to implement an efficient boost,
flyback, SEPIC or forward current mode power converter. The operation can be best understood by referring to
the block diagram. At the start of each cycle, the oscillator sets the driver logic and turns on the power MOSFET
to conduct current through the inductor or transformer. The peak current in the MOSFET is controlled by the
voltage at the COMP pin. The COMP voltage increases with larger loads and decrease with smaller loads. This
voltage is compared with the sum of a voltage proportional to the power MOSFET current and an internally
generated Slope Compensation ramp. Slope Compensation is used in current mode PWM architectures to
eliminate sub-harmonic current oscillation that occurs with static duty cycles greater than 50%. When the
summed signal exceeds the COMP voltage, the PWM comparator resets the driver logic, turning off the power
MOSFET. The driver logic is then set by the oscillator at the end of the switching cycle to initiate the next power
period.
The LM5001 has dedicated protection circuitry to protect the IC from abnormal operating conditions. Cycle-bycycle current limiting prevents the power MOSFET current from exceeding 1 A. This feature can also be used to
soft-start the regulator. Thermal Shutdown circuitry holds the driver logic in reset when the die temperature
reaches 165°C, and returns to normal operation when the die temperature drops by approximately 20°C. The EN
pin can be used as an input voltage undervoltage lockout (UVLO) during start-up to prevent operation with less
than the minimum desired input voltage.
7.2 Functional Block Diagram
HV-LDO
VIN
VCC
+6.9V
6 PA
Disable
0.45V
EN
+
-
REFERENCE +5V
GENERATOR
1.26V
Disable
SHUTDOWN
+
1.26V
STANDBY
+
VCC 2.8V
UVLO
+
-
ENABLE
THERMAL
STANDBY
(165oC)
ENABLE
RT
OSCILLATOR
WITH
SYNC
CAPABILITY
SW
CLK
MAX DUTY
VCC
ENABLE
RAMP
SLOPE COMP RAMP
450 mV
DRIVER
0
RAMP
+
CS
× 0.7
+5V
CLK
1.26V
S
5k
+
-
FB
Q
PWM
R
1.3V
1.5V
-
COMP
CS
ENABLE
8
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CURRENT
LIMIT
Av = 30
CS
+
-
+
CLK
(Leading Edge Blanking)
CURRENT
SENSE
50 m:
GND
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7.3 Feature Description
7.3.1 High-Voltage VCC Regulator
The LM5001 VCC Low Drop Out (LDO) regulator allows the LM5001 to operate at the lowest possible input
voltage. The VCC pin voltage is very nearly equal to the input voltage from 2.8 V up to approximately 6.9 V. As
the input voltage continues to increase, the VCC pin voltage is regulated at the 6.9 V set-point. The total input
operating range of the VCC LDO regulator is 3.1 V to 75 V.
The output of the VCC regulator is current limited to 20 mA. During power up, the VCC regulator supplies current
into the required decoupling capacitor (0.47 µF or greater ceramic capacitor) at the VCC pin. When the voltage at
the VCC pin exceeds the VCC UVLO threshold of 2.8 V and the EN pin is greater than 1.26 V the PWM
controller is enabled and switching begins. The controller remains enabled until VCC falls below 2.7 V or the EN
pin falls below 1.16 V.
An auxiliary supply voltage can be applied to the VCC pin to reduce the IC power dissipation. If the auxiliary
voltage is greater than 6.9 V, the internal regulator essentially shuts off, and internal power dissipation decreases
by the VIN voltage times the operating current. The overall converter efficiency improves if the VIN voltage is
much higher than the auxiliary voltage. The externally applied VCC voltage should not exceed 14 V. The VCC
regulator series pass MOSFET includes a body diode (Functional Block Diagram ) between VCC and VIN that
should not be forward biased in normal operation. Therefore, the auxiliary VCC voltage should never exceed the
VIN voltage.
In high voltage applications extra care should be taken to ensure the VIN pin does not exceed the absolute
maximum voltage rating of 76 V. Voltage ringing on the VIN line during line transients that exceeds the Absolute
Maximum Ratings damages the IC. Both careful PC board layout and the use of quality bypass capacitors
located close to the VIN and GND pins are essential.
7.3.2 Oscillator
A single external resistor connected between RT and GND pins sets the LM5001 oscillator frequency. To set a
desired oscillator frequency (FSW), the necessary value for the RT resistor can be calculated from:
9
RT = 13.1 x 10 x
1
- 83 ns
FSW
(1)
The tolerance of the external resistor and the frequency tolerance indicated in the Electrical Characteristics must
be taken into account when determining the worst case frequency range.
7.3.3 External Synchronization
The LM5001 can be synchronized to the rising edge of an external clock. The external clock must have a higher
frequency than the free running oscillator frequency set by the RT resistor. The clock signal should be coupled
through a 100 pF capacitor into the RT pin. A peak voltage level greater than 2.6 V at the RT pin is required for
detection of the sync pulse. The DC voltage across the RT resistor is internally regulated at 1.5 V. The negative
portion of the AC voltage of the synchronizing clock is clamped to this 1.5 V by an amplifier inside the LM5001
with ~100 Ω output impedance. Therefore, the AC pulse superimposed on the RT resistor must have positive
pulse amplitude of 1.1 V or greater to successfully synchronize the oscillator. The sync pulse width measured at
the RT pin should have a duration greater than 15 ns and less than 5% of the switching period. The sync pulse
rising edge initiates the internal CLK signal rising edge, which turns off the power MOSFET. The RT resistor is
always required, whether the oscillator is free running or externally synchronized. The RT resistor should be
located very close to the device and connected directly to the RT and GND pins of the LM5001.
7.3.4 Enable / Standby
The LM5001 contains a dual level Enable circuit. When the EN pin voltage is below 450 mV, the IC is in a low
current shutdown mode with the VCC LDO disabled. When the EN pin voltage is raised above the shutdown
threshold but below the 1.26 V standby threshold, the VCC LDO regulator is enabled, while the remainder of the
IC is disabled. When the EN pin voltage is raised above the 1.26 V standby threshold, all functions are enabled
and normal operation begins. An internal 6 µA current source pulls up the EN pin to activate the IC when the EN
pin is left disconnected.
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Feature Description (continued)
An external set-point resistor divider from VIN to GND can be used to determine the minimum operating input
range of the regulator. The divider must be designed such that the EN pin exceeds the 1.26 V standby threshold
when VIN is in the desired operating range. The internal 6 µA current source should be included when
determining the resistor values. The shutdown and standby thresholds have 100 mV hysteresis to prevent noise
from toggling between modes. When the VIN voltage is below 3.5 VDC during start-up and the operating
temperature is below –20°C, the EN pin should have a pull-up resistor provides 2 µA or greater current. The EN
pin is internally protected by a 6 V Zener diode through a 1 kΩ resistor. The enabling voltage may exceed the
Zener voltage, however the Zener current should be limited to less than 4 mA.
7.3.5 Error Amplifier and PWM Comparator
An internal high gain error amplifier generates an error signal proportional to the difference between the
regulated output voltage and an internal precision reference. The output of the error amplifier is connected to the
COMP pin allowing the user to add loop compensation, typically a Type II network, as illustrated in Figure 13.
This network creates a low frequency pole that rolls off the high DC gain of the amplifier, which is necessary to
accurately regulate the output voltage. FDC_POLE is the closed loop unity gain (0 dB) frequency of this pole. A zero
provides phase boost near the closed loop unity gain frequency, and a high frequency pole attenuates switching
noise. The PWM comparator compares the current sense signal from the current sense amplifier to the error
amplifier output voltage at the COMP pin.
FDC_POLE =
FZERO =
VOUT
FPOLE =
R1
1
2S x R1 x(C1 + C2)
1
2S x R2 xC2
1
§ C1 xC2
2S x R2 x ¨
¨ C1 + C2
©
5V
·
¸¸
¹
1.26V
PWM
5k
FB
1.3V
C1
COMP
R2
RFEEDBACK
C2
LM5001
Figure 13. Type II Compensator
When isolation between primary and secondary circuits is required, the Error Amplifier is usually disabled by
connecting the FB pin to GND. This allows the COMP pin to be driven directly by the collector of an opto-coupler.
In isolated designs the external error amplifier is located on the secondary circuit and drives the opto-coupler
LED. The compensation network is connected to the secondary side error amplifier. An example of an isolated
regulator with an opto-coupler is shown in Figure 19.
7.3.6 Current Amplifier and Slope Compensation
The LM5001 employs peak current mode control which also provides a cycle-by-cycle over current protection
feature. An internal 50 mΩ current sense resistor measures the current in the power MOSFET source. The sense
resistor voltage is amplified 30 times to provide a 1.5 V/A signal into the current limit comparator. Current limiting
is initiated if the internal current limit comparator input exceeds the 1.5 V threshold, corresponding to 1 A. When
the current limit comparator is triggered, the SW output pin immediately switches to a high impedance state.
10
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Feature Description (continued)
The current sense signal is reduced to a scale factor of 1.05 V/A for the PWM comparator signal. The signal is
then summed with a 450 mV peak slope compensation ramp. The combined signal provides the PWM
comparator with a control signal that reaches 1.5 V when the MOSFET current is 1 A. For duty cycles greater
than 50%, current mode control circuits are subject to sub-harmonic oscillation (alternating between short and
long PWM pulses every other cycle). Adding a fixed slope voltage ramp signal (slope compensation) to the
current sense signal prevents this oscillation. The 450 mV ramp (zero volts when the power MOSFET turns on,
and 450 mV at the end of the PWM clock cycle) adds a fixed slope to the current sense ramp to prevent
oscillation.
To prevent erratic operation at low duty cycle, a leading edge blanking circuit attenuates the current sense signal
when the power MOSFET is turned on. When the MOSFET is initially turned on, current spikes from the power
MOSFET drain-source and gate-source capacitances flow through the current sense resistor. These transient
currents normally cease within 50 ns with proper selection of rectifier diodes and proper PC board layout.
7.3.7 Thermal Protection
Internal Thermal Shutdown circuitry is provided to protect the IC in the event the maximum junction temperature
is exceeded. When the 165°C junction temperature threshold is reached, the regulator is forced into a low power
standby state, disabling all functions except the VCC regulator. Thermal hysteresis allows the IC to cool down
before it is re-enabled. Note that since the VCC regulator remains functional during this period, the soft-start
circuit shown in Figure 17 should be augmented if soft-start from Thermal Shutdown state is required.
7.3.8 Power MOSFET
The LM5001 switching regulator includes an N-Channel MOSFET with 440-mΩ on-resistance. The on-resistance
of the LM5001 MOSFET varies with temperature as shown in the Typical Characteristics graph. The typical total
gate charge for the MOSFET is 4.5 nC which is supplied from the VCC pin when the MOSFET is turned on.
8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
This information is intended to provide guidelines for the power supply designer using the LM5001.
8.1.1 VIN
The voltage applied to the VIN pin can vary within the range of 3.1 V to 75 V. The current into the VIN pin
depends primarily on the gate charge of the power MOSFET, the switching frequency, and any external load on
the VCC pin. It is recommended the filter shown in Figure 14 be used to suppress transients which may occur at
the input supply. This is particularly important when VIN is operated close to the maximum operating rating of the
LM5001.
When power is applied and the VIN voltage exceeds 2.8 V with the EN pin voltage greater than 0.45 V, the VCC
regulator is enabled, supplying current into the external capacitor connected to the VCC pin. When the VIN
voltage is between 2.8 V and 6.9 V, the VCC voltage is approximately equal to the VIN voltage. When the
voltage on the VCC pin exceeds 6.9 V, the VCC pin voltage is regulated at 6.9 V. In typical flyback applications,
an auxiliary transformer winding is connected through a diode to the VCC pin. This winding must raise the VCC
voltage above 6.9 V to shut off the internal start-up regulator. The current requirements from this winding are
relatively small, typically less than 20 mA. If the VIN voltage is much higher than the auxiliary voltage, the
auxiliary winding significantly improves conversion efficiency. It also reduces the power dissipation within the
LM5001. The externally applied VCC voltage should never exceed 14 V. Also the applied VCC should never
exceed the VIN voltage to avoid reverse current through the internal VCC to VIN diode shown in the LM5001
block diagram.
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Application Information (continued)
VPWR
10
VIN
LM5001
0.1 PF
Figure 14. Input Transient Protection
8.1.2 SW Pin
Attention must be given to the PC board layout for the SW pin which connects to the power MOSFET drain.
Energy can be stored in parasitic inductance and capacitance which cause switching spikes that negatively effect
efficiency, and conducted and radiated emissions. These connections should be as short as possible to reduce
inductance and as wide as possible to reduce resistance. The loop area, defined by the SW and GND pin
connections, the transformer or inductor terminals, and their respective return paths, should be minimized.
8.1.3 EN / UVLO Voltage Divider Selection
Two dedicated comparators connected to the EN pin are used to detect under-voltage and shutdown conditions.
When the EN pin voltage is below 0.45 V, the controller is in a low current shutdown mode where the VIN current
is reduced to 95 µA. For an EN pin voltage greater than 0.45 V but less than 1.26 V the controller is in standby
mode, with all internal circuits operational, but the PWM gate driver signal is blocked. Once the EN pin voltage is
greater than 1.26 V, the controller is fully enabled. Two external resistors can be used to program the minimum
operational voltage for the power converter as shown in Figure 15. When the EN pin voltage falls below the 1.26
V threshold, an internal 100 mV threshold hysteresis prevents noise from toggling the state, so the voltage must
be reduced to 1.16 V to transition to standby. Resistance values for R1 and R2 can be determined from
Equation 2 and Equation 3:
VPWR - 1.26V
R1 =
R2 =
IDIVIDER
(2)
1.26V
IDIVIDER + 6 PA
(3)
where VPWR is the desired turn-on voltage and IDIVIDER is an arbitrary current through R1 and R2.
For example, if the LM5001 is to be enabled when VPWR reaches 16 V, IDIVIDER could be chosen as 501 µA which
would set R1 to 29.4 kΩ and R2 to 2.49 kΩ. The voltage at the EN pin should not exceed 10 V unless the current
into the 6 V protection Zener diode is limited below 4 mA. The EN pin voltage should not exceed 14 V at any
time. Be sure to check both the power and voltage rating (some 0603 resistors are rated as low as 50 V) for the
selected R1 resistor.
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Application Information (continued)
VPWR
LM5001
VIN
6 PA
R1
1.26V
Disable PWM Controller
EN
0.45V
R2
Disable VCC Regulator
Figure 15. Basic EN (UVLO) Configuration
Remote configuration of the controller’s operational modes can be accomplished with open drain device(s)
connected to the EN pin as shown in Figure 16. A MOSFET or an NPN transistor connected to the EN pin can
force the regulator into the low power ‘off’ state. Adding a PN diode in the drain (or collector) provides the offset
to achieve the standby state. The advantage of standby is that the VCC LDO is not disabled and external
circuitry powered by VCC remains functional.
LM5001
VPWR
R1
1.26V
STANDBY
EN
STANDBY
OFF
R2
0.45V
OFF
Figure 16. Remote Standby and Disable Control
8.1.4 Soft-Start
Soft-start (SS) can be implemented with an external capacitor connected to COMP through a diode as shown in
Figure 17. The COMP discharge MOSFET conducts during Shutdown and Standby modes to keep the COMP
voltage below the PWM offset (1.3 V), which inhibits PWM pulses. The error amplifier attempts to raise the
COMP voltage after the EN pin exceeds the 1.26-V standby threshold. Because the error amplifier output can
only sink current, the internal COMP pull-up resistor (~5 kΩ) supplies the charging current to the SS capacitor.
The SS capacitor causes the COMP voltage to gradually increase, until the output voltage achieves regulation
and FB assumes control of the COMP and the PWM duty cycle. The SS capacitor continues charging through a
large resistance, RSS, preventing the SS circuit from interfering with the normal error amplifier function. During
shutdown, the VCC diode discharges the SS capacitor.
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Application Information (continued)
VCC
5V
VOUT
1.26V
PWM
5k
FB
1.3V
COMP
SHUTDOWN
& STANDBY
RSS
SOFT-START
CAPACITOR
LM5001
Figure 17. Soft-Start
8.2 Typical Applications
Figure 18, Figure 19, Figure 20, Figure 21, and Figure 22 present examples of a Non-Isolated Flyback, Isolated
Flyback, Boost, 24-V SEPIC and a 12-V Automotive range SEPIC converters utilizing the LM5001 switching
regulator.
8.2.1 Non-Isolated Flyback
The Non-Isolated Flyback converter (Figure 18) utilizes the internal voltage reference for the regulation setpoint.
The output is 5 V at 1 A while the input voltage can vary from 16 V to 42 V. The switching frequency is set to 250
kHz. An auxiliary winding on transformer (T1) provides 7.5 V to power the LM5001 when the output is in
regulation. This disables the internal high voltage VCC LDO regulator and improves efficiency. The input undervoltage threshold is 13.9 V. The converter can be shut down by driving the EN input below 1.26 V with an opencollector or open-drain transistor. An external synchronizing frequency can be applied to the SYNC input. An
optional soft-start circuit is connected to the COMP pin input. When power is applied, the soft-start capacitor (C7)
is discharged and limits the voltage applied to the PWM comparator by the internal error amplifier. The internal
~5 kΩ COMP pull-up resistor charges the soft-start capacitor until regulation is achieved. The VCC pull-up
resistor (R7) continues to charge C7 so that the soft-start circuit will not affect the compensation network in
normal operation. If the output capacitance is small, the soft-start circuit can be adjusted to limit the power-on
output voltage overshoot. If the output capacitance is sufficiently large, no soft-start circuit is needed because the
LM5001 gradually charges the output capacitor by current limiting at approximately 1 A (ILIM) until regulation is
achieved.
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Typical Applications (continued)
T1
VCC
VIN = 16V ± 42V
D1
LPRI = 160 PH
8:3:2
D2
VOUT = 5V
C1
4.7 PF
IOUT = 1A
C4
100 PF
C5
220 pF
R1
60.4k
EN
R2
6.04k
C2
100 pF
R3
52.3k
C6
4700 pF
LM5001
VIN
EN
RT
GND
SW
COMP
FB
VCC
R5
10.2k
R4
13.0k
VCC
C3
1 PF
R6
3.40k
R7
100k
C7
10 PF
SYNC
Figure 18. Non-Isolated Flyback
8.2.2 Isolated Flyback
The Isolated Flyback converter (Figure 19) utilizes a 2.5 V voltage reference (LM431) located on the isolated
secondary side for the regulation setpoint. The LM5001 internal error amplifier is disabled by grounding the FB
pin. The LM431 controls the current through the opto-coupler LED, which sets the COMP pin voltage. The R4
and C3 network boosts the phase response of the opto-coupler to increase the loop bandwidth. The output is 5 V
at 1 A and the input voltage ranges from 16 V to 42 V. The switching frequency is set to 250 kHz.
T1
VCC
VIN = 16V ± 42V
D1
LPRI = 160 éH
8:3:2
D2
VOUT = 5V
C1
4.7 éF
R6
47
C4
1 éF
R2
6.04k
R3
52.3k
VIN
EN
RT
GND
LM5001
R1
60.4k
SW
COMP
FB
VCC
VCC
C2
1 éF
R5
560
C6
100éF
R7
10k
R4
249
C3
1 éF
C5
0.1 PF
LM431
R8
4.99k
IOUT = 1A
R9
2.20k
R10
2.20k
Figure 19. Isolated Flyback
8.2.3 Boost
The Boost converter (Figure 20) utilizes the internal voltage reference for the regulation setpoint. The output is 48
V at 150 mA, while the input voltage can vary from 16 V to 36 V. The switching frequency is set to 250 kHz. The
internal VCC regulator provides 6.9 V bias power, since there isn’t a simple method for creating an auxiliary
voltage with the boost topology. Note that the boost topology does not provide output short-circuit protection
because the power MOSFET cannot interrupt the path between the input and the output.
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Typical Applications (continued)
L1
100 PH
VIN = 16V ± 36V
D2
VOUT = 48V
IOUT = 150mA
C1
4.7 éF
C3
10éF
R1
60.4k
R3
52.3k
C4
2200 pF
LM5001
R2
6.04k
VIN
EN
RT
GND
SW
COMP
FB
VCC
R4
73.2k
R5
54.9k
R6
1.47k
C2
1 éF
Figure 20. Boost
8.2.4 24-V SEPIC
The 24-V SEPIC converter (Figure 21) utilizes the internal voltage reference for the regulation setpoint. The
output is 24 V at 250 mA while the input voltage can vary from 16 V to 48 V. The switching frequency is set to
250 kHz. The internal VCC regulator provides 6.9 V bias power for the LM5001. An auxiliary voltage can be
created by adding a winding on L2 and a diode into the VCC pin.
L1
470 PH
VIN = 16V ± 48V
C3
10 PF
C1
4.7 éF
D2
VOUT = 24V
IOUT = 250 mA
L2
470 PH
C4
150 pF
R1
60.4k
R3
52.3k
VIN
EN
RT
GND
C5
0.015 PF
LM5001
R2
6.04k
C6
22éF
SW
COMP
FB
VCC
R4
11.5k
R5
11.5k
R6
634
C2
1 PF
Figure 21. 24-V SEPIC
8.2.5 12-V Automotive SEPIC
The 12-V Automotive SEPIC converter (Figure 22) utilizes the internal bandgap voltage reference for the
regulation setpoint. The output is 12 V at 50 mA while the input voltage can vary from 3.1 V to 60 V. The output
current rating can be increased if the minimum VIN voltage requirement is increased. The switching frequency is
set to 750 kHz. The internal VCC regulator provides 6.9 V bias power for the LM5001. The output voltage can be
used as an auxiliary voltage if the nominal VIN voltage is greater than 12 V by adding a diode from the output
into the VCC pin. In this configuration, the minimum input voltage must be greater than 12 V to prevent the
internal VCC to VIN diode from conducting. If the applied VCC voltage exceeds the minimum VIN voltage, then
an external blocking diode is required between the VIN pin and the power source to block current flow from VCC
to the input supply.
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Typical Applications (continued)
L1
100 PH
VIN = 3.1V ± 60V
C3
4.7 PF
C1
2.2 éF
D2
L2
100 PH
VOUT = 12V
IOUT = 50 mA
C6
22 éF
C4
150 pF
R1
15.8k
C5
0.015 PF
LM5001
NC
VIN
EN
RT
GND
SW
COMP
FB
VCC
R2
11.5k
C2
1 PF
R3
11.5k
R4
1.33k
Figure 22. 12-V SEPIC
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9 Layout
9.1 Layout Guidelines
The LM5001 Current Sense and PWM comparators are very fast and may respond to short duration noise
pulses. The components at the SW, COMP, EN and the RT pins should be as physically close as possible to the
IC, thereby minimizing noise pickup on the PC board tracks.
The SW output pin of the LM5001 should have a short, wide conductor to the power path inductors, transformers
and capacitors in order to minimize parasitic inductance that reduces efficiency and increases conducted and
radiated noise. Ceramic decoupling capacitors are recommended between the VIN pin to the GND pin and
between the VCC pin to the GND pin. Use short, direct connections to avoid clock jitter due to ground voltage
differentials. Small package surface mount X7R or X5R capacitors are preferred for high frequency performance
and limited variation over temperature and applied voltage.
If an application using the LM5001 produces high junction temperatures during normal operation, multiple vias
from the GND pin to a PC board ground plane helps conduct heat away from the IC. Judicious positioning of the
PC board within the end product, along with use of any available air flow helps reduce the junction temperatures.
If using forced air cooling, avoid placing the LM5001 in the airflow shadow of large components, such as input
capacitors, inductors or transformers.
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10 Device and Documentation Support
10.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LM5001
Click here
Click here
Click here
Click here
Click here
LM5001-Q1
Click here
Click here
Click here
Click here
Click here
10.2 Trademarks
All trademarks are the property of their respective owners.
10.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM5001IDQ1
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L5001
IDQ1
LM5001IDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L5001
IDQ1
LM5001MA
NRND
SOIC
D
8
95
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
-40 to 125
L5001
MA
LM5001MA/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L5001
MA
LM5001MAX/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L5001
MA
LM5001SD/NOPB
ACTIVE
WSON
NGT
8
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM5001
LM5001SDE/NOPB
ACTIVE
WSON
NGT
8
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM5001
LM5001SDX/NOPB
ACTIVE
WSON
NGT
8
4500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM5001
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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