LM5006EVAL/NOPB

User's Guide SNVA434A – February 2011 – Revised April 2013 AN-2050 LM5006 Evaluation Board 1 Introduction The LM5006EVAL evaluation board provides the design engineer with a fully functional buck regulator, employing the constant on-time (COT) operating principle. This evaluation board provides a 5V output over an input range of 6V to 75V. The circuit delivers load currents to 500 mA, with current limit set at a nominal 1 Amp. The board’s specification are: • Input Voltage: 6V to 75V • Output Voltage: 5V • Maximum load current: 500 mA • Minimum load current: 0A • Current Limit: 1 Amp (nominal) • Measured Efficiency: 94.75% (VIN = 6V, IOUT = 100 mA) • Nominal Switching Frequency: 200 kHz • Size: 2.6 in. × 1.6 in. 2 Theory of Operation Refer to the evaluation board schematic in Figure 1. When the circuit is in regulation, the buck switch is on each cycle for a time determined by R1 and VIN according to the equation: -10 ton = 1.25 x 10 x (R1 + 500:) + 30 ns VIN - 0.5V (1) The on-time of this evaluation board ranges from ≊4.38 µs at VIN = 6V, to ≊351 ns at VIN = 75V. The ontime varies inversely with VIN to maintain a nearly constant switching frequency. At the end of each ontime the Minimum Off-Timer ensures the buck switch is off for at least 260 ns. In normal operation, the offtime is much longer. During the off-time, the load current is supplied by the output capacitor (C2). When the output voltage falls sufficiently that the voltage at FB is below 2.5V, the regulation comparator initiates a new on-time period. For stable, fixed frequency operation, a minimum of 25 mV of ripple is required at FB to switch the regulation comparator. Refer to the LM5006 data sheet for a more detailed block diagram, and a complete description of the various functional blocks. All trademarks are the property of their respective owners. SNVA434A – February 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated AN-2050 LM5006 Evaluation Board 1 Evaluation Board Schematic 3 www.ti.com Evaluation Board Schematic 6V to 75V Input VIN C1 2.2 PF GND VCC VIN C5 0.1 PF LM5006 R1 191 k: TP1 SD BST C3 1 PF 0.01 PF R9 0: SW R2 200 k: R4 100 k: TP3 STATUS R3 59 k: 36.5 k: LG C9 1000 pF 5V R8 UV TP2 UVO VOUT L1 82 PH C4 RT/SD SW Scope TP4 Q1 C6 3300 pF C7 0.1 PF C8 R5 3.01 k: FB R6 3.01 k: RTN UVO R7 0: C2 15 PF VOUT Scope TP5 GND Figure 1. Complete Evaluation Board Schematic (As Supplied) 4 Board Layout and Probing Figure 2 shows the placement of the circuit components. The following should be kept in mind when the board is powered: • When operating at high input voltage and high load current, forced air flow may be necessary. • The LM5006 may be hot to the touch when operating at high input voltage and high load current. • Use CAUTION when probing the circuit at high input voltages to prevent injury, as well as possible damage to the circuit. • At maximum load current, the wire size and length used to connect the load becomes important. Ensure there is not a significant drop in the wires between this evaluation board and the load. 5 Board Connection/Start-up The input connections are made to the J1 connector. The load is connected to the J2 (OUT) and J3 (GND) terminals. Ensure the wires are adequately sized for the intended load current. Before start-up a voltmeter should be connected to the input terminals, and to the output terminals. The load current should be monitored with an ammeter or a current probe. It is recommended that the input voltage be increased gradually to 6V, at which time the output voltage should be 5V. If the output voltage is correct with 6V at VIN, then increase the input voltage as desired and proceed with evaluating the circuit. DO NOT EXCEED 75V AT VIN. 2 AN-2050 LM5006 Evaluation Board SNVA434A – February 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Board Connection/Start-up www.ti.com LM5006 EVALUATION BOARD (c) 2010 J2 OUT SD C6 C7 R2 R3 TP4 TP5 U1 Q1 R1 GND R6 TP1 R8 C9 C3 C4 D1 J1 L1 R9 C2 J3 GND 980600447-002 C1 TP2 UVO R7 IN TP3 STATUS R5 C8 MADE IN U.S. S/N Figure 2. Evaluation Board - Top Side SNVA434A – February 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated AN-2050 LM5006 Evaluation Board 3 Output Ripple Control 6 www.ti.com Output Ripple Control The LM5006 requires a minimum of 25 mVp-p ripple at the FB pin, in phase with the switching waveform at the SW pin, for proper operation. The required ripple can be supplied from ripple at VOUT, through the feedback resistors as described in Option A.. Option B and Option C provide lower output ripple with one or two additional components. 6.1 Option A: Lowest Cost Configuration In this configuration, Figure 3, R7 is installed in series with the output capacitance (C2). Since ≥25 mVp-p are required at the FB pin, R7 must be chosen to generate ≥50 mVp-p at VOUT, knowing that the minimum ripple current in this circuit is ≊51 mAp-p at minimum VIN. Using 1Ω for R7, the ripple at VOUT ranges from ≊51 mVp-p to ≊280 mVp-p over the input voltage range. If the application can accept this ripple level, this is the most economical solution. See Figure 11. R8, C6, C7, and C8 are not used in this configuration. VCC LM5006 C3 1 PF BST 0.01 PF C4 VOUT L1 82 PH SW LG 5V R7 1: Q1 R5 3.01 k: C2 15 PF FB GND RTN R6 3.01k: Figure 3. Lowest Cost Configuration 4 AN-2050 LM5006 Evaluation Board SNVA434A – February 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Output Ripple Control www.ti.com 6.2 Option B: Reduced Ripple Configuration This configuration, Figure 4, generates less ripple at VOUT than Option A, by the addition of one capacitor (C8) across R5. Since the output ripple is passed by C8 to the FB pin with little or no attenuation, R7 can be reduced so the minimum ripple at VOUT is ≊25 mVp-p. The minimum value for Cff is calculated from: C8 ! 3 x tON (max) (R5//R6) (2) where: tON(max) is the maximum on-time (at minimum VIN) R5//R6 is the parallel equivalent of the feedback resistors The ripple at VOUT ranges from 28 mVp-p to 159 mVp-p over the input voltage range. See Figure 11. VCC LM5006 C3 1 PF BST 0.01 PF C4 L1 82 PH SW 5V Q1 LG C8 0.01 PF R5 3.01 k: FB RTN VOUT R6 3.01k: R7 0.56: C2 15 PF GND Figure 4. Reduced Ripple Configuration SNVA434A – February 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated AN-2050 LM5006 Evaluation Board 5 Output Ripple Control 6.3 www.ti.com Option C: Minimum Ripple Configuration To obtain minimum ripple at VOUT, Figure 5, R7 is set to 0Ω, and R8, C6, and C7 are added to generate the required ripple for the FB pin. In this configuration, the output ripple is determined primarily by the characteristics of the output capacitance and the inductor’s ripple current. See Figure 11. The ripple voltage required by the FB pin is generated by R8, and C6 since the SW pin switches from 0.1V to VIN, and the right end of C6 is a virtual ground. The values for R8 and C6 are chosen to generate a 30-100 mVp-p triangle waveform at their junction. That triangle wave is then coupled to the FB pin through C7. The following procedure is used to calculate values for R8, C6 and C7: 1) Calculate the voltage VA: VA = VOUT – (VSW x (1 – (VOUT/VIN))) (3) where: VSW is the absolute value of the voltage at the SW pin during the off-time (typically 0.1V with Q1) VIN is the minimum input voltage For this circuit, VA calculates to 4.98V. This is the approximate DC voltage at the R8/C6 junction, and is used in the next equation. 2) Calculate the R8 × C6 product: R8 x C6 = (VIN ± VA) x tON ÂV (4) where: tON is the maximum on-time VIN is the minimum input voltage ΔV is the desired ripple amplitude at the R8/C6 junction, 40 mVp-p for this example R8 x C6 = (6V - 4.98V) x 4.38 Ps -4 = 1.12 x 10 0.04 (5) R8 and C6 are then chosen from standard value components to satisfy the above product. Typically C6 is 3000 to 10000 pF, and R8 is 10 kΩ to 300 kΩ. C7 is chosen large compared to C6, typically 0.1 µF. The ripple at VOUT is typically less than 10 mVp-p. See Figure 11. VCC C3 1 PF LM5006 BST 0.01 PF C4 SW VOUT L1 82 PH 5V R8 C6 3300 pF R5 C7 3.01 0.1 PF k: 36.5 k: LG FB Q1 R7 0: C2 15 PF GND RTN R6 3.01 k: Figure 5. Minimum Output Ripple Configuration 6 AN-2050 LM5006 Evaluation Board SNVA434A – February 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated LG (Low Side Gate) Output www.ti.com 7 LG (Low Side Gate) Output As supplied, this evaluation board employs synchronous rectification by using an N-Channel MOSFET (Q1) in place of a more traditional flyback diode. This board accepts any device in a SOT-23 package, such as a Vishay Si2328. The LG output pin switches between approximately 7.5V (the VCC voltage) and ground. The LG output is capable of sourcing 250 mA, and sinking 300 mA. An external gate driver is not needed if the selected MOSFET has a total gate charge of less than 10 nC. Use of a synchronous rectifier generally results in higher circuit efficiency due to the lower voltage drop across the MOSFET as compared to a diode. See Figure 6. Another advantage of using a synchronous rectifier is that the circuit remains in continuous conduction mode, providing a relatively constant switching frequency, for all values of load current, including zero. If a flyback diode is used, the switching frequency decreases significantly at low values of load current when the circuit changes to discontinuous conduction mode. If a flyback diode is preferred over a synchronous rectifier, remove Q1 and install a diode at the pads labeled D1. This board accepts devices such as the DFLS1100 from Diodes Inc. Figure 6. Efficiency Comparison at 200 kHz SNVA434A – February 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated AN-2050 LM5006 Evaluation Board 7 Under-Voltage Detector 8 www.ti.com Under-Voltage Detector The Under Voltage Detector can be used to monitor the input voltage, or any other system voltage as long as the voltage at the UV pin does not exceed its maximum rating. On this evaluation board the input voltage is monitored via resistors R2 and R3. An appropriate pull-up voltage less than 10 volts must be connected to test point TP2-UVO on this evaluation board. R4 is the pull-up resistor for the UVO output. The under-voltage status can then be monitored at the TP3-Status test point. On this evaluation board the UVO output switches low when the input voltage exceeds 12V, and it switches high when the input voltage is less than 11V. If it is desired to change the thresholds, the equations for determining the resistor values are: R2 = R3 = VUVH - VUVL 5 µA VUV(HYS) = 5 µA (6) R2 x 2.5V VUVL ± 2.5V (7) Where: VUVH is the upper threshold at VIN VUVL is the lower threshold. The threshold at the UV pin is 2.5V. The UVO output is high when the VCC voltage is below its UVLO threshold, or when the LM5006 is shutdown by grounding the TP1-SD test point, regardless of the voltage at the UV pin. 9 Monitor the Inductor Current The inductor’s current can be monitored or viewed on a scope with a current probe. Remove R9, and install an appropriate current loop across the two large pads where R9 was located. In this way the inductor’s ripple current and peak current can be accurately determined. 10 Multiple Outputs Multiple outputs can be produced by replacing the inductor (L1) with a transformer, and using a MOSFET (Q1) for synchronous rectification. The synchronous rectification is required to ensure the circuit is in continuous conduction mode at all values of the main output’s load current. This ensures the secondary output voltages are correct at all times. In Figure 7, a second isolated output is provided at VOUT2. Its regulation depends on the relative output voltages, current levels at the both outputs, and the design of the transformer L1. The two outputs can be isolated, or share a common ground. Figure 8 shows a circuit that provides a regulated 12V output, and two secondary 5V outputs. VOUT2 and VOUT3 can be isolated from VOUT1 and from each other, or share ground connections, depending on the application. 8 AN-2050 LM5006 Evaluation Board SNVA434A – February 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Multiple Outputs www.ti.com Input VIN VIN C1 GND VCC LM5006 C5 VOUT2 BST RT C4 RT/SD SHUT DOWN C3 SW VOUT1 L1 RUV2 Q1 UV LG R3 RFB2 RUV1 C2 FB RUVO GND UVO UV STATUS RFB1 RTN Figure 7. Generate a Secondary Output VOUT3 5V 500: 22 PF Input VIN VIN 2.2 PF GND 0.1 PF LM5006 BST 182 k: RT/SD SHUT DOWN VCC 5V 500: SW 43.2 k: VOUT1 L1 Q1 LG 22 PF 0.01 PF 200 k: UV 51 k: 0.1 PF 3300 pF 13 k: 1 k: 12V 22 PF GND FB 100 k: UV STATUS VOUT2 1 PF UVO RTN 3.4 k: Figure 8. Generate Three Outputs SNVA434A – February 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated AN-2050 LM5006 Evaluation Board 9 Scope Probe Adapters 11 www.ti.com Scope Probe Adapters Scope probe adapters are provided on this evaluation board for monitoring the waveform at the SW pin, and at the circuit’s output (VOUT), without using the probe’s ground lead which can pick up noise from the switching waveforms. 12 Bill of Materials Table 1. Bill of Materials 10 Item Description Mfg., Part Number Package Value C1 Ceramic Capacitor TDK C3225X7R2A225M 1210 2.2 µF, 100V C2 Ceramic Capacitor TDK C3225X7R1C156M 1210 15 µF, 16V C3 Ceramic Capacitor TDK C1608X7R1C105K 0603 1 µF, 16V C4 Ceramic Capacitor TDK C1608X7R2A103K 0603 0.01 µF, 100V C5 Ceramic Capacitor TDK C2012X7R2A104M 0805 0.1 µF, 100V C6 Ceramic Capacitor TDK C1608X7R2A332K 0603 3300 pF, 100V C7 Ceramic Capacitor TDK C2012X7R2A104M 0805 0.1 µF, 100V C8 Unpopulated C9 Ceramic Capacitor TDK C1608X7R2A102K 0805 1000 pF, 100V L1 Inductor Coiltronics DR74-820-R or Wurth Electronics 744771182 Q1 N-Channel MOSFET Vishay Si2328DS SOT-23 100V, 1.5A R1 Resistor Vishay CRCW0603191KF 0603 191kΩ R2 Resistor Vishay CRCW0603200KF 0603 200kΩ R3 Resistor Vishay CRCW060359KOF 0603 59 kΩ R4 Resistor Vishay CRCW0603100KF 0603 100 kΩ R5 Resistor Vishay CRCW06033KO1F 0603 3.01 kΩ R6 Resistor Vishay CRCW06033KO1F 0603 3.01 kΩ R7 Resistor Vishay CRCW06030000Z 0603 0Ω jumper R8 Resistor Vishay CRCW060336K5F 0603 36.5 kΩ R9 Resistor Vishay CRCW06030000Z 0603 0Ω jumper U1 Switching Regulator LM5006 VSSOP-10 AN-2050 LM5006 Evaluation Board 82 uH,1A SNVA434A – February 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Circuit Performance www.ti.com 13 Circuit Performance Figure 9. Efficiency vs Load Current Figure 10. Efficiency vs Input Voltage Figure 11. Output Voltage Ripple Figure 12. Switching Frequency vs. Input Voltage SNVA434A – February 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated AN-2050 LM5006 Evaluation Board 11 Circuit Performance www.ti.com Figure 13. Current Limit vs Input Voltage Figure 14. Line Regulation Figure 15. Load Regulation 12 AN-2050 LM5006 Evaluation Board SNVA434A – February 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Typical Waveforms www.ti.com 14 Typical Waveforms Trace 1 = SW Pin Trace 2 = VOUT Trace 4 = Inductor Current Vin = 12V, Iout = 200 mA Figure 16. Typical Waveforms 15 PC Board Layout Figure 17. Board Silkscreen SNVA434A – February 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated AN-2050 LM5006 Evaluation Board 13 PC Board Layout www.ti.com Figure 18. Board Top Layer Figure 19. Board Bottom Layer (Viewed from Top) 14 AN-2050 LM5006 Evaluation Board SNVA434A – February 2011 – Revised April 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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