LM5010AEVAL/NOPB

User's Guide SNVA137A – December 2005 – Revised April 2013 AN-1423 LM5010A Evaluation Board 1 Introduction The LM5010AEVAL evaluation board provides the design engineer with a fully functional buck regulator, employing the constant on-time (COT) operating principle. This evaluation board provides a 5V output over an input range of 6V - 75V. The circuit delivers load currents to 1A, with current limit set at ≊1.3A. The board is populated with all external components except R6 and C9-C11. These components provide options for reducing output ripple as described later in this document. The board’s specification are: • Input Voltage: 6V to 75V • Output Voltage: 5V • Maximum load current: 1.0A • Minimum load current: 0A • Current Limit: 1.3A • Measured Efficiency: 94.75% (VIN = 6V, IOUT = 200 mA) • Nominal Switching Frequency: 200 kHz • Size: 2.25 in. x 0.88 in. x 0.47 in J3 OUT2 C9 C10 C8 U1 C6 C3 LM5010A BUCK EVALUATION L1 C7 BOARD NATIONAL C 2005 P / N 55101 2686-001 REV A SEMICONDUCTOR OUT1 D1 S/N R4 R1 IN GND R5 R6 R3 C11 C2 R2 C5 C1 C4 GND J1 Figure 1. Evaluation Board - Top Side 2 Theory of Operation The evaluation board schematic in Figure 3 contains a simplified block diagram of the LM5010A, LM5010A-Q1 High-Voltage 1-A Step-Down Switching Regulator Data Sheet (SNVS376). When the circuit is in regulation, the buck switch is on each cycle for a time determined by R1 and VIN according to Equation 1: tON = 1.18 x 10-10 x (R1 + 1.4k) (VIN - 1.4V) + 67 ns (1) All trademarks are the property of their respective owners. SNVA137A – December 2005 – Revised April 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated AN-1423 LM5010A Evaluation Board 1 Board Layout and Probing www.ti.com The on-time of this evaluation board ranges from ≊5000 ns at VIN = 6V, to ≊380 ns at VIN = 75V. The ontime varies inversely with VIN to maintain a nearly constant switching frequency. At the end of each ontime the Minimum Off-Timer ensures the buck switch is off for at least 260 ns. In normal operation, the offtime is much longer. During the off-time, the output capacitor (C7) is discharged by the load current. When the output voltage falls sufficiently that the voltage at FB is below 2.5V, the regulation comparator initiates a new on-time period. For stable, fixed frequency operation, ≊25 mV of ripple is required at FB to switch the regulation comparator. For a more detailed block diagram and a complete description of the various functional blocks, see the LM5010A, LM5010A-Q1 High-Voltage 1-A Step-Down Switching Regulator Data Sheet (SNVS376). 3 Board Layout and Probing Figure 1 shows the placement of the circuit components. The following should be kept in mind when the board is powered: • When operating at high input voltage and high load current, forced air flow is necessary. • The LM5010A, and the diode D1 will be hot to the touch when operating at high input voltage and high load current. • Use CAUTION when probing the circuit at high input voltages to prevent injury, as well as possible damage to the circuit. • At maximum load current (1A), the wire size and length used to connect the load becomes important. Ensure there is not a significant drop in the wires between this evaluation board and the load. 4 Board Connection/Start-up The input connections are made to the J1 connector. The load is normally connected to the OUT1 and GND terminals of the J3 connector. Ensure the wires are adequately sized for the intended load current. Before start-up a voltmeter should be connected to the input terminals, and to the output terminals. The load current should be monitored with an ammeter or a current probe. It is recommended that the input voltage be increased gradually to 6V, at which time the output voltage should be 5V. If the output voltage is correct with 6V at VIN, then increase the input voltage as desired and proceed with evaluating the circuit. 5 Reducing Output Ripple The LM5010A requires a minimum of 25 mVp-p ripple at the FB pin, in phase with the switching waveform at the SW pin, for proper operation. In the basic application circuit shown in the device-specific data sheet, C8 is not included. The required ripple at FB is derived from the ripple at VOUT1, which is generated by the inductor’s ripple current passing through R4 and the ESR of capacitor C7. Since the ripple voltage at VOUT1 is attenuated by the R2/R3 feedback divider, a minimum of 50 mVp-p is required at VOUT1. If this ripple level is acceptable for the intended application, C8 can be removed from this evaluation board, and R4 increased to 1.5Ω. In that case, the minimum ripple amplitude (≊55 mVp-p) occurs at minimum Vin (6V), and increases to ≊340 mVp-p at Vin = 75V, as shown in Figure 6. If a low ripple output is desired, three alternatives are described in Section 5.1, Section 5.2, and Section 5.3. 5.1 Option A: Ripple Reduction This EVB is supplied with C8 installed, and R4 = 0.68Ω, providing a relatively low ripple output at VOUT1 since C8 couples the output ripple directly to FB without attenuation. The ripple amplitude at VOUT1 ranges from 30mVp-p to 170 mVp-p (see Figure 6) as Vin is varied over its range. The minimum value for C8 is calculated from: C8 = tON(max) (R2//R3) (2) where, tON(max) is the maximum on-time at minimum Vin, and R2//R3 is the equivalent parallel value of R2 and R3. For this evaluation board, tON(max) is approximately 5000 ns, and R2//R3 = 500Ω, resulting in a minimum value of 0.01 µF for C8. 2 AN-1423 LM5010A Evaluation Board SNVA137A – December 2005 – Revised April 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Reducing Output Ripple www.ti.com 5.2 Option B: Ripple Reduction Add R6, C9, C10, replace R4 with zero ohms, and leave C8 and C11 positions open. Since the SW pin switches from -1V to VIN, and the right end of C9 is a virtual ground, R6 and C9 are chosen to generate a 30-40 mVp-p triangle wave at their junction. That triangle wave is coupled to the FB pin through C10. To calculate the values for R6, C9, and C10, use the following procedure, using the minimum input voltage for Vin: Calculate the voltage VA: VA = VOUT - (VSW x (1 - (VOUT/Vin))) (3) where, VSW is the absolute value of the voltage at the SW pin during the off-time (typically 1V), and Vin is the minimum input voltage. For this circuit, VA calculates to 4.83V. This is the DC voltage at the R6/C9 junction, and is used in Equation 4. Calculate the R6•C9 product: R6 ‡ C9 = (Vin - VA) x tON 'V (4) where, tON is the on-time at minimum Vin (≊5 µs), and ΔV is the desired ripple amplitude at the R6/C9 junction, 30mV for this example. R6 ‡ C9 = (6V ± 4.83V) x 5 Ps 0.03V = 1.95 x 10-4 (5) R6 and C9 are then chosen from standard value components to satisfy the above product. For example, C9 can be 1000 pF, requiring R6 to be 195 kΩ. C10 is chosen to be 0.01 µF, large compared to C9. R2 and R3 are increased to 5 kΩ each to reduce the loading on the signal provided through C10. The resulting circuit is: LM5010A BST 3 0.022 PF L1 C6 100 PH SW 5V 2 D1 ISEN 4 R6 195k C10 0.01 PF C9 1000 pF VOUT1 R2 5k FB 9 6 RTN SGND 5 R3 5k R4 0 C7 22 PF Gnd Figure 2. Low Ripple Output Using R6, C9, C10 The resulting ripple at VOUT1 ranges from 5 mVp-p at Vin = 6V, to 18 mVp-p at Vin = 75V, and varies slightly with load current, see Figure 6. These values are valid only for continuous conduction mode (load current is between 120 mA and 1.3A). If the load current is reduced below 120 mA such that the circuit operates in discontinuous conduction mode the VOUT1 ripple ranges from ≊40 mVp-p to ≊100 mVp-p. If the circuit is operated in current limit mode the ripple ranges from ≊100 mVp-p to ≊300 mVp-p. 5.3 Option C: Ripple Reduction Connect the load to VOUT2 (leave R4 in). The ripple at this output varies from ≊3 mVp-p to ≊7.5 mVp-p over the input voltage range, see Figure 6. However, the load regulation is not as good at VOUT2 as at VOUT1 due to the presence of R4. This alternative may be preferred for applications where the load current is relatively constant. SNVA137A – December 2005 – Revised April 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated AN-1423 LM5010A Evaluation Board 3 Increasing the Current Limit 6 www.ti.com Increasing the Current Limit The evaluation board current limit activates at a load current of ≊1.3A. If it is desired to increase the current limit for a particular application, R5 must be added to the board. To determine the appropriate value for this resistor, see the LM5010A, LM5010A-Q1 High-Voltage 1-A Step-Down Switching Regulator Data Sheet (SNVS376). 7 Minimum Load Current The LM5010A requires a minimum load current of ≊500 µA to ensure the boost capacitor (C6) is recharged sufficiently during each off-time. In this evaluation board, the minimum load current is provided by the feedback resistor (R2, R3), allowing the board’s minimum load current at VOUT1 (or VOUT2) to be specified at zero. 6 V - 75V Vin C1 2.2 PF C2 2.2 PF LM5010A VIN 13 C3 Minimum Off Timer On Timer R1 200k 0.1 PF VCC 12 VIN Gnd C5 0.022 PF RON/SD 11 SS 10 FB 9 C4 0. 47 PF BST 3 C6 0.022 PF L1 100 PH SW 2 Logic 2.5V 5V D1 R6 ISEN 4 R5 Regulation Comparator 6 RTN C10 C8 001 . PF SGND 5 VOUT1 C9 C11 R2 1.0k R4 0.68 VOUT2 R3 1.0k C7 22 PF Gnd Figure 3. Evaluation Board Schematic Table 1. Bill of Materials (BOM) Item Description Mfg., Part Number Package Value C1, 2 Ceramic Capacitor TDK C4532X7R2A225M 1812 2.2 µF, 100V C3 Ceramic Capacitor TDK C2012X7R2A104M 0805 0.1 µF, 100V C4 Ceramic Capacitor TDK C2012X7R1C474M 0805 0.47 µF, 16V C5, 6 Ceramic Capacitor TDK C2012X7R1C223M 0805 0.022 µF, 16V C7 Ceramic Capacitor TDK C4532X7R1E226M 1812 22 µF, 25V C8 Ceramic Capacitor TDK C2012X7R1C103M 0805 0.01 µF, 16V C9 Unpopulated C10 Unpopulated C11 Unpopulated D1 Schottky Diode Central Semi CMSH2-100 SMB 100V, 2A L1 Power Inductor TDK SLF12575T-101M1R9, or 12.5 mm x 12.5 mm 100 µH, 1.9A R1 Resistor CRCW08052003F 0805 200 kΩ R2, 3 Resistor CRCW08051001F 0805 1.00 kΩ R4 Resistor ERJ-6RQFR68V (Panasonic) 0805 0.68 Ω Cooper Bussmann DR125-101 R5 Unpopulated R6 U1 4 Unpopulated Switching Regulator AN-1423 LM5010A Evaluation Board Texas Instruments LM5010 HTSSOP - 14 SNVA137A – December 2005 – Revised April 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Minimum Load Current www.ti.com 100 VIN = 6V EFFICIENCY (%) 90 80 10V 70 20V 40V 60 75V 60V 50 0 50 200 400 600 800 1000 LOAD CURRENT (mA) Figure 4. Efficiency vs Load Current 100 Load Current = 200 mA EFFICIENCY (%) 90 Load Current = 1000 mA 80 70 60 Load Current = 50 mA 50 0 6 20 40 60 75 VIN (V) Figure 5. Efficiency vs VIN 400 Load Current = 200 mA RIPPLE @ VOUT1 (mVp-p) R6, C8-C11 Not Installed R4 = 1.5: 300 200 C8 = 0.01 PF, R4 = 0.68: 100 R6 = 195 k:, C9 = 1 nF, R4 = 0 C10 = 0.01 PF Ripple @ VOUT2 0 0 6 20 40 60 75 VIN (V) Figure 6. Voltage Ripple at VOUT1, VOUT2 SNVA137A – December 2005 – Revised April 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated AN-1423 LM5010A Evaluation Board 5 PCB Layout 8 www.ti.com PCB Layout Figure 7. Board Silkscreen Figure 8. Board Top Layer Figure 9. Board Bottom Layer (viewed from top) 6 AN-1423 LM5010A Evaluation Board SNVA137A – December 2005 – Revised April 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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