LM5026EVAL/NOPB

User's Guide SNVA117A – September 2005 – Revised May 2013 AN-1387 LM5026 Evaluation Board 1 Introduction The performance of the evaluation board is as follows: • Input range: 36V to 78V • Output voltage: 3.3V • Output current: 0 to 30A • Measured efficiency: 90% at 30A, 92.5% at 15A • Frequency of operation: 230kHz • Board size: 2.3 x 2.4 x 0.5 inches • Load Regulation: 1% • Line Regulation: 0.1% • Line UVLO, Hiccup Current Limit The printed circuit board consists of 4 layers of 3 ounce copper on FR4 material with a total thickness of 0.050 inches. Soldermask has been omitted from some areas to facilitate cooling. The unit is designed for continuous operation at rated load at < 40°C and a minimum airflow of 200 CFM. 2 Theory of Operation Power converters based on the Forward topology offer high efficiency and good power handling capability in applications up to several hundred Watts. The operation of the transformer in a forward topology does not inherently self-reset each power switching cycle, a mechanism to reset the transformer is required. The active clamp reset mechanism is presently finding extensive use in medium level power converters in the 50 to 200W range. The Forward converter is derived from the Buck topology family, employing a single modulating power switch. The main difference between the topologies are, the Forward topology employs a transformer to provide input / output ground isolation and a step down or step up function. Each cycle, the main primary switch turns on and applies the input voltage across the primary winding, which has 12 turns. The transformer secondary has 2 turns, leading to a 6:1 step-down of the input voltage. For an output voltage of 3.3V the required duty cycle (D) of the main switch must vary from approximately 65% (low line) to 25% (high line). The clamp capacitor along with the reset switch reverse biases the transformer primary each cycle when the main switch turns off. This reverse voltage resets the transformer. The clamp capacitor voltage is Vin / (1-D). The secondary rectification employs self-driven synchronous rectification to maintain high efficiency and ease of drive. Feedback from the output is processed by an amplifier and reference, generating an error voltage, which is coupled back to the primary side control through an optocoupler. The COMP input to the LM5026 greatly increases the achievable loop bandwidth. The capacitance effect (and associated pole) of the optocoupler is greatly reduced by holding the voltage across the optocoupler constant. The LM5026 current mode controller pulse width modulates the error signal with a ramp signal derived from the transformer primary. A standard “type II” (pole-zero-pole) is used as a compensation network. The LM5026 provides a controlled delay necessary for the reset switch. The evaluation board can be synchronized to an external clock with a recommended frequency range of 230 to 300KHz. All trademarks are the property of their respective owners. SNVA117A – September 2005 – Revised May 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated AN-1387 LM5026 Evaluation Board 1 Powering and Loading Considerations www.ti.com VIN 36 - 78V VOUT 3.3V T1 CS VCC CS LM5026 VIN UVLO OUT_A TIME RES RT OUT_B ERROR AMP and ISOLATION REF COMP SYNC DCL SS PGND AGND SYNC I/O Figure 1. Schematic 3 Powering and Loading Considerations When applying power to the LM5026 evaluation board certain precautions need to be followed. A misconnection can damage the assembly. 4 Proper Connections When operated at low input voltages the evaluation board can draw up to 3.5A of current at full load. The maximum rated output current is 30A. Be sure to choose the correct connector and wire size when attaching the source supply and the load. Monitor the current into and out of the evaluation board. Monitor the voltage directly at the output terminals of the evaluation board. The voltage drop across the load connecting wires will give inaccurate measurements, this is especially true for accurate efficiency measurements. 5 Source Power The evaluation board can be viewed as a constant power load. At low input line voltage (36V) the input current can reach 3.5A, while at high input line voltage (78V) the input current will be approximately 1.5A. Therefore to fully test the LM5026 evaluation board a DC power supply capable of at least 80V and 4A is required. The power supply must have adjustments for both voltage and current. The power supply and cabling must present a low impedance to the evaluation board. Insufficient cabling or a high impedance power supply will droop during power supply application with the evaluation board inrush current. If large enough, this droop will cause a chattering condition upon power up. This chattering condition is an interaction with the evaluation board undervoltage lockout, the cabling impedance and the inrush current. 2 AN-1387 LM5026 Evaluation Board SNVA117A – September 2005 – Revised May 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Loading www.ti.com 6 Loading An appropriate electronic load, with specified operation down to 3.0V minimum, is desirable. The resistance of a maximum load is 0.11Ω. The high output current requires thick cables! If resistor banks are used there are certain precautions to be taken. The wattage and current ratings must be adequate for a 30A, 100W supply. Monitor both current and voltage at all times. Ensure there is sufficient cooling provided for the load. 7 Air Flow Full power loading should never be attempted without providing the specified 200 CFM of air flow over the evaluation board. A stand-alone fan should be provided. 8 Powering Up Using the provided shutdown pin will allow powering up the source supply with the current level set low. It is suggested that the load be kept low during the first power up. Set the current limit of the source supply to provide about 1.5 times the wattage of the load. As you remove the connection from the shutdown pin to ground, immediately check for 3.3 volts at the output. A most common occurrence, that will prove unnerving, is when the current limit set on the source supply is insufficient for the load. The result is similar to having the high source impedance referred to earlier. The interaction of the source supply folding back and the evaluation board going into undervoltage shutdown will start an oscillation, or chatter, that may have undesirable consequences. A quick efficiency check is the best way to confirm that everything is operating properly. If something is amiss you can be reasonably sure that it will affect the efficiency adversely. Few parameters can be incorrect in a switching power supply without creating losses and potentially damaging heat. 9 Over Current Protection The evaluation board is configured with hiccup over-current protection. In the event of an output overload (approximately 33A) the unit will discharge the softstart capacitor, which disables the power stage. After a delay the softstart is released. The shutdown, delay and slow recharge time of the softstart capacitor protects the unit, especially during short circuit event where the stress is highest. Scope 80 Volt, 5 Amp Power Supply with Current Meter Volt-meter - Evaluation Board + IN Volt-meter Current-meter + ON/OFF (SHUTDOWN) OUT 200 Watt, 60 Amp Electronic Load - + Jumper Figure 2. Typical Evaluation Setup 10 Performance Characteristics 10.1 Turn-On Waveforms When applying power to the LM5026 evaluation board a certain sequence of events occurs. Soft-start capacitor values and other components allow for a minimal output voltage for a short time until the feedback loop can stabilize without overshoot. Figure 3 shows the output voltage during a typical start-up with a 48V input and a load of 5A. There is no overshoot during startup. SNVA117A – September 2005 – Revised May 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated AN-1387 LM5026 Evaluation Board 3 Performance Characteristics www.ti.com 10.2 Output Ripple Waveforms Figure 4 shows the transient response for a load of change from 5A to 25A. The upper trace shows minimal output voltage droop and overshoot during the sudden change in output current shown by the lower trace. Figure 5 shows typical output ripple seen directly across the output capacitor, for an input voltage of 48V and a load of 30A. This waveform is typical of most loads and input voltages. Figure 6 and Figure 7 show the drain voltage of Q1 with a 25A load. Figure 6 represents an input voltage of 38V and Figure 7 represents an input voltage of 78V. Figure 8 shows the gate voltages of the synchronous rectifiers. The drive from the main power transformer is delayed slightly at turn-on by a resistor interacting with the gate capacitance. This provides improved switching transitions for optimum efficiency. The difference in drive voltage is inherent in the topology and varies with line voltage. 1 Conditions: Input Voltage = 48VDC Output Current = 5A Trace 1: Output Voltage Volts/div = 1V Horizontal Resolution = 1msec/div Figure 3. Output Voltage Conditions: Input Voltage = 48VDC Output Current = 5A to 25A Trace 1: Output Voltage Volts/div = 0.5V Trace 2: Output Current, Amps/div = 5A Horizontal Resolution = 1msec/div Figure 4. Transient Response 1 1 Conditions: Input Voltage = 48VDC Output Current = 30A Bandwidth Limit = 25MHz Trace 1: Output Ripple Voltage Volts/div = 50mV Horizontal Resolution = 2µs/div Figure 5. Typical Output Ripple 4 AN-1387 LM5026 Evaluation Board Conditions: Input Voltage = 38VDC Output Current = 25A Trace 1: Q1 drain voltage Volts/div = 20V Horizontal Resolution = 1µs/div Figure 6. Drain Voltage of Q1 SNVA117A – September 2005 – Revised May 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Performance Characteristics www.ti.com 1 2 1 Conditions: Input Voltage = 78VDC Output Current = 25A Trace 1: Q1 drain voltage Volts/div = 20V Horizontal Resolution = 1µs/div Figure 7. Drain Voltage of Q1 Conditions: Input Voltage = 48VDC Output Current = 5A Synchronous rectifier, Q3 gate Volts/div = 5V Trace 1: Synchronous rectifier, Q3 gate Volts/div = 5V Trace 2: Synchronous rectifier, Q5 gate Volts/div = 5V Horizontal Resolution = 1µs/div Figure 8. Gate Voltages SNVA117A – September 2005 – Revised May 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated AN-1387 LM5026 Evaluation Board 5 Application Circuit 11 www.ti.com Application Circuit Figure 9. Application Circuit: Input 36 to 78V, Output 3.3V, 30A 6 AN-1387 LM5026 Evaluation Board SNVA117A – September 2005 – Revised May 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Layout and Bill of Materials (BOM) www.ti.com 12 Layout and Bill of Materials (BOM) The Bill of Materials is shown in Table 1 and includes the manufacturer and part number. The layers of the printed circuit board (PCB) are shown in top down order. The view is from the top down except for the bottom silkscreen, which is shown viewed from the bottom. The scale is approximately X1.5. The printed circuit board consists of 4 layers of 3 ounce copper on FR4 material with a total thickness of 0.050 inches. Table 1. Bill of Materials (BOM) QTY DESIGNATOR PART NUMBER DESCRIPTION VALUE 4 C1-C4 C4532X7R2A225M CAPACITOR, CER, TDK 2.2µ, 100V 1 C5 C4532X7R3A103K CAPACITOR, CER, TDK 0.01µ, 1000V 2 C6,C15 C3216X7R2E104K CAPACITOR, CER, TDK 0.1µ, 250V 1 C7 C4532X7R1E156M CAPACITOR, CER, TDK 15µ, 25V 1 C8 C2012X7R2A103K CAPACITOR, CER, TDK 0.01µ, 100V 3 C9,C30,C33 C2012X7R2A102K CAPACITOR, CER, TDK 1000p, 100V 4 C10,C14,C28, C31 C2012X7R1H104K CAPACITOR, CER, TDK 0.1µ, 50V 2 C11, C12 C2012X7R1H473K CAPACITOR, CER, TDK 0.047µ, 50V 2 C13,C18 C1206C104K5RAC CAPACITOR, CER, KEMET 0.1µ, 50V 3 C16, C17, C29 C0805C471J5GAC CAPACITOR, CER, KEMET 470p, 50V 2 C19,C20 T520D337M006AS4350 CAPACITOR,TANT,KEMET 330µ, 6.3V 3 C21,C22,C23 C4532X7S0G686M CAPACITOR, CER, TDK 68µ, 4V C24, C25 OPEN NOT USED 1 C26 C0805C101J5GAC CAPACITOR, CER, KEMET 100p, 50V 1 C27 C1206C333K5RAC CAPACITOR, CER, KEMET 0.033µ, 50V 1 C32 C0805C330J5GAC CAPACITOR, CER, KEMET 33p, 50V 7 D1- D7 CMPD2838 DIODE, SIGNAL, CENTRAL 1 D8 CMPD7000 DIODE, SIGNAL, CENTRAL 1 D9 CMR1U-02 DIODE, 200V, CENTRAL 1 L1 SLF10145T-5R6M3R2 INPUT CHOKE, TDK 5.6µH, 3.5A 1 L2 B0358-C CHOKE with AUX, COILCRAFT 2µH, 33A 1 Q1 SI7846DP N-FET, SILICONIX 150V, 50m 1 Q2 ZVP2120GTA P-FET, ZETEX 200V, 20 4 Q3 - Q6 SI7866DP FET, SILICONIX 20V, 3m 4 R1, R22, R24, R28 CRCW120610R0F RESISTOR 10Ω R2, R13, R25 OPEN NOT USED 2 R3, R4 CRCW120615R0F RESISTOR 15Ω 1 R5 CRCW12062000F RESISTOR 200Ω 1 R6 CRCW120649R9F RESISTOR 49.9Ω 1 R7 CRCW12061003F RESISTOR 100kΩ 1 R8 CRCW12063831F RESISTOR 3.83kΩ 2 R9, R15 CRCW12061001F RESISTOR 1kΩ 1 R10 CRCW12062212F RESISTOR 22.1kΩ 1 R11 CRCW12063921F RESISTOR 3.92kΩ 1 R12 CRCW12061652F RESISTOR 16.5kΩ 5 R14,R18,R19,R29,R3 3,R35 CRCW12061002F RESISTOR 10kΩ 2 R16, R17 CRCW12065R60F RESISTOR 5.6Ω 2 R20, R21 CRCW2512100J RESISTOR 10Ω, 1W 1 R23 CRCW12061000F RESISTOR 100Ω 1 R26 CRCW12062492F RESISTOR 24.9kΩ 1 R27 CRCW12061502F RESISTOR 15kΩ SNVA117A – September 2005 – Revised May 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated AN-1387 LM5026 Evaluation Board 7 PCB Layouts www.ti.com Table 1. Bill of Materials (BOM) (continued) QTY DESIGNATOR PART NUMBER DESCRIPTION VALUE 3 R30, R31, R34 CRCW12064991F RESISTOR 4.99kΩ 1 R32 CRCW12062002F RESISTOR 20kΩ 1 T1 P8208T CURRENT XFR, PULSE ENG 100:01 1 T2 B0357-B POWER XFR, COILCRAFT 12:02 1 U1 LM5026 CONTROLLER, Texas Instruments 1 U2 MOCD207M OPTO-COUPLER, QT OPTO 1 U3 LM6132 OPAMP, Texas Instruments 1 U4 LM4041 REFERENCE, Texas Instruments 13 PCB Layouts Figure 10. 8 AN-1387 LM5026 Evaluation Board SNVA117A – September 2005 – Revised May 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated PCB Layouts www.ti.com Figure 11. Figure 12. SNVA117A – September 2005 – Revised May 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated AN-1387 LM5026 Evaluation Board 9 PCB Layouts www.ti.com Figure 13. Figure 14. 10 AN-1387 LM5026 Evaluation Board SNVA117A – September 2005 – Revised May 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated PCB Layouts www.ti.com Figure 15. SNVA117A – September 2005 – Revised May 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated AN-1387 LM5026 Evaluation Board 11 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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