LM5036
SNVSB14C – APRIL 2018 – REVISED OCTOBER 2021
LM5036 Half-Bridge PWM Controller with Integrated Auxiliary Bias Supply
isolated power applications. It contains all the features
necessary to implement half-bridge power converters,
using voltage-mode control, with input voltage feedforward. This controller is intended to operate on
the primary side of an isolated converter with DC
input voltage up to 100 V. The controller includes
features that improve power density and reliability
while reducing system cost:
• An integrated fly-buck converter as auxiliary bias
supply. Provides bias power for both primary and
secondary circuits, with a minimum of external
components.
• Fully regulated pre-bias start-up. Eliminates output
voltage over-shoot or dips even when starting into
a pre-charged output capacitor.
• Enhanced cycle-by-cycle peak current limit with
pulse matching. The controller limits both positive
and negative current. Pulse matching ensures
equal pulse width for low and high side devices,
to avoid transformer saturation. Output current limit
is approximately constant across the full range of
input voltage.
1 Features
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High integration controller for small form factor,
high-density DC-DC power converters
Integrated 100-V, 100-mA auxiliary bias supply
Fully regulated pre-biased start-up
Enhanced cycle-by-cycle current limiting with pulse
matching for low and high primary FETs
Optimized maximum duty cycle for primary-side
FETs
Voltage-mode control with input voltage feedforward
100-V high-voltage start-up regulator
Configurable latch, OVP operation
Integrated 100-V, 2-A MOSFET drivers for primaryside FETs
Programmable dead-time between primary-side
and synchronous rectifier (SR) FETs
Create a custom design using the LM5036 with
the Excel Calculator Tool or WEBENCH® Power
Designer
2 Applications
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Device Information
Telecom and data communication isolated power
supplies
Industrial power supplies and factory automation
Test, measurement equipment
PACKAGE(1)
PART NUMBER
LM5036
(1)
WQFN (28)
BODY SIZE (NOM)
5.00 mm × 5.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
The LM5036 PWM controller, with integrated auxiliary
bias supply, offers high power density for industrial
13 VIN
VIN
BST_AUX 15
VAUX2
SW_AUX 14
28 UVLO
VAUX1
VCC 17
24 RAMP
1
RES
6
RON
7
ON_OFF
FB_AUX 12
BST 21
VCC
VIN
SR1
VIN
VO
HSG 22
8
SS
11
RD2
10 RD1
SW
23
LSG 18
SR2
AGND
VCS+
16 PGND
VCS±
2
SGND
VAUX2
REF
SR1 20
5
RT
VIN
SR1
VO
Isolated
Driver
SR2 19
SR2
VFB
VAUX2
VCS+
25 CS_POS
VCS±
26 CS_NEG
27 CS_SET
REF
4
COMP
3
SSSR
9
+
VREF
VAUX2
VAUX2
+
TH
Simplified Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5036
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SNVSB14C – APRIL 2018 – REVISED OCTOBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................7
6.5 Electrical Characteristics.............................................7
6.6 Switching Characteristics..........................................10
6.7 Typical Characteristics.............................................. 11
7 Detailed Description......................................................13
7.1 Overview................................................................... 13
7.2 Functional Block Diagram......................................... 14
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................41
8 Application and Implementation.................................. 42
8.1 Application Information............................................. 42
8.2 Typical Application.................................................... 42
9 Power Supply Recommendations................................57
10 Layout...........................................................................58
10.1 Layout Guidelines................................................... 58
10.2 Layout Example...................................................... 58
11 Device and Documentation Support..........................60
11.1 Device Support........................................................60
11.2 Documentation Support.......................................... 60
11.3 Support Resources................................................. 60
11.4 Trademarks............................................................. 60
11.5 Electrostatic Discharge Caution.............................. 60
11.6 Glossary.................................................................. 60
12 Mechanical, Packaging, and Orderable
Information.................................................................... 61
4 Revision History
Changes from Revision B (April 2019) to Revision C (October 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated footnote to standard language............................................................................................................. 7
• Deleted minimum and maximum peak value of current source for slope compensation (ISLOPE) specifications.
Updated typical from 54 µA to 36 µA. Removed table note (1) from this parameter.......................................... 7
• Changed typical peak current (ISO_PRI) specification from 1.5 A to 1 A ............................................................. 7
• Changed minimum BST_AUX undervoltage threshold (VBST_AUX(UVLO) ) specification from 2.1 V to 3.5 V ......7
• Changed typical BST_AUX undervoltage threshold (VBST_AUX(UVLO) ) specification from 2.8 V to 5.0 V .......... 7
• Changed maximum BST_AUX undervoltage threshold (VBST_AUX(UVLO) ) specification from 3.6 V to 6.5 V .....7
• Changed typical peak current source value references from "1.5 A" to "1 A" in Section 7.3.6 ........................17
Changes from Revision A (June 2018) to Revision B (April 2019)
Page
• Added minimum recommended values for RD1 and RD2 ..................................................................................6
• Changed minimum recommended input voltage from 18V to 16V. ....................................................................6
• Added current limit parameters KCBC1, VCSOFFSET and IBiasOffset .......................................................................7
• Changed typical value of ISLOPE from 50-µA to 54-µA........................................................................................7
• Added parameter names for some items that had none: IOVL, VSSSecEn, VSSREn, tCSLSG, tCSBLK, VRESTh2,
VRESTh3 VRTReg, VRTSync,ICOSsrEn, IAUX(LIM) ........................................................................................................ 7
• Changed parameter name VRES to VRESTh1 ...................................................................................................... 7
• Changed parameter name VPWM-OS to IPWM-OS .................................................................................................7
• Changed parameter VAUX_UVLO maximum value from 16.6V to 16V. ................................................................ 7
• Changed parameter name HC_BLK_TH to VHC_BLK_TH .................................................................................... 7
• Added new parameters AUX SUPPLY CURRENT LIMIT: tCSBLKA, tAUX(LIM), τAuxSns .........................................7
• Added new conditions in Switching Characteristics for tON ............................................................................. 10
• Added Reference to the Calculator tool............................................................................................................13
• Changed Positive and negative current limit shown to be affected by LEB signal. ......................................... 14
• Added reference to operation from voltages above 100V. Values replaced with parameter names. ...............15
• Added reference to table of device functional modes.......................................................................................15
• Changed Parameter name VREF to VREFSec to avoid confusion with primary reference voltage...................... 16
• Changed Implied minimum value of tD from 0-ns to 30-ns............................................................................... 18
• Added note that minimum value of RD1/RD2 resistors should not be less that 5-kΩ ......................................18
• Added pre-biased start-up process is handled automatically by LM5036 ....................................................... 21
2
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SNVSB14C – APRIL 2018 – REVISED OCTOBER 2021
Changed values to parameter names. VREF changed to VREFSec, TH changed to VTHSec .............................. 21
Changed values to parameter names. ICOMP is graphed instead of VCOMP. ....................................................21
Changed VCOMP to ICOMP. ................................................................................................................................21
Changed and expanded Section: 'Enhanced Cycle-by-Cycle Current Limiting with Pulse Matching'.............. 24
Changed and expanded Section: 'Reverse Current Protection'. ..................................................................... 28
Added Section: 'CBC Threshold Accuracy'.......................................................................................................29
Changed values to parameter names. .............................................................................................................31
Changed Section: 'ON_OFF Pin' to 'Over-Voltage / Latch (ON_OFF Pin)'. Values replaced by parameter
names. ............................................................................................................................................................. 33
Changed Section: 'Constant On-Time Control' to 'Auxiliary Constant On-Time Control'.................................. 34
Changed Section: 'On-Time Generator' to 'Auxiliary On-Time Generator'........................................................35
Added method to calculate peak Auxiliary transformer current. External schottky recommended to improve
Auxiliary efficiency during ASYNCH mode. ..................................................................................................... 36
Deleted Section: 'Ripple Configuration Types'..................................................................................................38
Added Section: 'Auxiliary Ripple Configuration and Control'. .......................................................................... 39
Changed values to parameter names. .............................................................................................................41
Changed C26 from 330-pF to 47-pF, R29 from 165-kΩ to 220-kΩ. Added D11............................................... 42
Changed voltage targets for auxiliary output voltage from 12.6 V / 9 V to 11.9 V / 8.5 V. ............................... 43
Added reference to Excel Calculator Tool. .......................................................................................................43
Added restriction on use of TL431 to implement secondary side error amplifier.............................................. 44
Added reference to Power Stage Designer Tool. .............................................................................................44
Changed values to parameter names. RUV1 andRUV2 replace R1 and R2. .......................................................45
Changed Section: 'ON_OFF Pin Voltage Divider Selection' to 'Over Voltage / Latch (ON_OFF Pin) Voltage
Divider Selection'. ............................................................................................................................................ 46
Added new Section: 'Half-Bridge Power Stage Design' ...................................................................................47
Changed and expanded Section:'Current Limit' .............................................................................................. 48
Changed calculation of Auxiliary transformer inductance. ...............................................................................52
Changed calculated value for RON resistor. ..................................................................................................... 53
Changed calculated value of Auxiliary primary output capacitor value. ...........................................................54
Changed calculation of secondary output capacitor. Now uses ripple peak amplitude not peak-to-peak
amplitude. ........................................................................................................................................................ 54
Changed calculation of Auxiliary Feedback component values. ......................................................................54
Changed expression for ICOMP to fix error. .......................................................................................................55
Changed layout diagram to include external schottky diode connected between PGND and SW_AUX pins. ....
58
Changes from Revision * (April 2018) to Revision A (June 2018)
Page
• Changed marketing status from Advance Information to initial release. ............................................................1
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HSG
SW
RAMP
CS_POS
CS_NEG
CS_SET
UVLO
5 Pin Configuration and Functions
RES
1
28 27 26 25 24 23 22
21
BST
AGND
2
20
SR1
COMP
3
19
SR2
18
LSG
29
Thermal Pad
RT
5
17
VCC
RON
6
16
PGND
ON_OFF
7
BST_AUX
SW_AUX
VIN
FB_AUX
15
10 11 12 13 14
RD2
9
RD1
8
SSSR
4
SS
REF
Figure 5-1. RJB Package, 28-Pin WQFN (Top View)
Table 5-1. Pin Functions
PIN
4
TYPE(1)
DESCRIPTION
NAME
NO.
AGND
2
G
Analog ground
BST
21
I
Half-bridge high-side gate drive bootstrap
BST_AUX
15
I
Auxiliary supply high-side gate drive bootstrap
COMP
3
I
Control current input to half-bridge PWM comparator
CS_NEG
26
I
Current sense amplifier negative input terminal
CS_POS
25
I
Current sense amplifier positive input terminal
CS_SET
27
I
Current limit setting
FB_AUX
12
I
Auxiliary supply output voltage feedback
HSG
22
O
Half-bridge high-side MOSFET output driver
LSG
18
O
Half-bridge low-side MOSFET output driver
ON_OFF
7
I
Configurable for over voltage protection (OVP) or latch mode
PGND
16
G
Power ground
RAMP
24
I
RAMP signal input to half-bridge PWM comparator
RD1
10
I
Synchronous rectifier trailing-edge delay
RD2
11
I
Synchronous rectifier leading-edge delay
REF
4
O
5-V reference regulator output
RES
1
I
Hiccup mode restart timer
RON
6
I
Auxiliary supply on-time control
RT/SYNC
5
I
Oscillator frequency control or external clock synchronization
SR1
20
O
Synchronous rectifier PWM control output
SR2
19
O
Synchronous rectifier PWM control output
SS
8
I
Soft-start input
SSSR
9
I
Synchronous rectifier soft-start input
SW
23
I
Half-bridge switch node
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Table 5-1. Pin Functions (continued)
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
SW_AUX
14
I
Auxiliary supply switch node
UVLO
28
I
Input undervoltage lockout
VCC
17
I
Bias supply
VIN
13
I
Input voltage
Pad
29
G
Exposed thermal pad
(1)
I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VIN to GND
SW/SW_AUX to GND
MIN
MAX
UNIT
-0.3
105
V
-5
105
V
BST TO SW, BST_AUX TO SW_AUX
-0.3
16
V
HSG to SW
-0.3
16
V
LSG to GND
-0.3
16
V
SR1/SR2 to GND
-0.3
5
V
VCC to GND
-0.3
16
V
RT, UVLO, ON/OFF, RON, RAMP, RES, FB_AUX, CS_POS, CS_NEG, CS_SET to GND
-0.3
5
V
COMP to GND
-0.3
COMP Input Current
Junction Temperature
Storage Temperature, Tstg
(1)
-55
V
10
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
±2000
Charged device model (CDM), per JEDEC specificationJESD22C101, all pins(2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
6
NOM
MAX
UNIT
VIN
Input voltage
16
100
V
External VCC
Supply Voltage
8.5
14
V
RDx
RD1, RD2 Resistor value
TJ
Junction Temperature
5
–40
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kΩ
125
°C
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6.4 Thermal Information
LM5036
THERMAL METRIC
(1)
RJB (WQFN)
UNIT
28 PINS
RΘJA
Junction-to-ambient thermal resistance
29.9
°C/W
RΘJC(top)
Junction-to-case (top) thermal resistance
18.2
°C/W
RΘJB
Junction-to-board thermal resistance
10.4
°C/W
ΨJT
Junction-to-top characterization parameter
0.2
°C/W
ΨJB
Junction-to-board characterization parameter
10.3
°C/W
RΘJC(bot)
Junction-to-case (bottom) thermal resistance
1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
MIN and MAX limits apply the junction temperature range of –40°C ≤ TJ ≤ 125°C. Unless otherwise specified, the following
conditions apply: VIN = 48 V, RT = 25 kΩ, RD1 = RD2 = 20 kΩ, RON = 100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5
V, ON_OFF = 0 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
START-UP REGULATOR
VCC
VCC voltage
ICC = 10 mA
7.5
7.8
8.1
V
ICC (Lim)
Vcc current limit
VCC = 6 V, VIN = 20 V
69
81
94
mA
ICC(ext)
Vcc supply current
Supply current into Vcc from an
externally applied source. VCC = 9 V,
FB_AUX = 0 V
6.6
9
11
mA
VCC(reg)
Vcc load regulation
ICC from 0 to 50 mA
31
49
73
mV
VCC(UV)
Vcc undervoltage threshold
Positive going Vcc
7.4
7.7
8.0
V
Negative going Vcc
6.1
6.3
6.7
V
VIN = 20 V, VUVLO = 0 V, RON = 100 kΩ
276
580
670
µA
VIN = 100 V, VUVLO = 0 V, RON = 100 kΩ
299
600
717
µA
VCC = 9 V, applied externally, FB_AUX
> 2 V, SS = 0 V, RON = 100 kΩ
180
234
304
µA
4.85
5
5.15
V
VIN shutdown current
VIN start-up regulator leakage
VOLTAGE REFERENCE REGULATOR (REF PIN)
VREF
REF voltage
IREF = 0 mA
VREF(REG)
REF load regulation
IREF = 0 to 25 mA
24
37
57
mV
IREF(LIM)
REF current limit
VREF = 4.5 V, VIN = 20 V
28
39
47
mA
VREF(UV)
REF undervoltage threshold
Positive going VREF
Hysteresis
4.3
4.5
4.7
V
0.16
0.26
0.37
V
1.205
1.25
1.305
V
15
20
24
µA
0.34
0.38
0.41
V
90
135
175
mV
1.18
1.25
1.32
V
40
50
60
µA
17
20
24
µA
UNDERVOLTAGE LOCK OUT AND SHUTDOWN (UVLO PIN)
VUVLO
UVLO threshold
IUVLO
UVLO Hysteresis current
VSD
Internal startup regulator enable
threshold
SS = 0 V, FB_AUX = 2.5 V
Hysteresis
OVER-VOLTAGE/LATCH (ON_OFF PIN)
VON_OFF
ON_OFF threshold
IOVL
ON_OFF hysteresis current
SOFT-START (SS PIN, SSSR PIN)
ISS
SS charge current
SS = 0 V
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MIN and MAX limits apply the junction temperature range of –40°C ≤ TJ ≤ 125°C. Unless otherwise specified, the following
conditions apply: VIN = 48 V, RT = 25 kΩ, RD1 = RD2 = 20 kΩ, RON = 100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5
V, ON_OFF = 0 V.
PARAMETER
VSSSecEn
SS threshold to enable SSSR
charge current
SS output low voltage
TEST CONDITIONS
MIN
TYP
MAX
ICOMP < 800 µA
1.93
2.06
2.2
V
Sinking 100 µA
30
48
57
mV
SS threshold to disable switching
ISSSR
865
1000
1198
mV
SSSR charge current
SS > 2 V, ICOMP < 800 µA
17
20
24
µA
SSSR output low voltage
Sinking 100 µA
30
38.7
49
mV
0.65
1.17
1.67
V
V
SSSR threshold to enable SR
freewheeling pulse
VSSREn
UNIT
CURRENT SENSE (CS_POS, CS_NEG, and CS_SET PIN)
VLIM
Current limit setting voltage
0.72
0.75
0.77
Ratio of internal negative to
positive current limit threshold
0.3
0.58
0.9
tCSLSG
CS to gate driver output delay
60
85
122
ns
tCSBLK
CS leading-edge blanking
33
53
76
ns
KCBC1 (1)
VLIM x (K2a X K10b - K10a)
At CBC trip threshold
7.28
7.51
7.81
V
VCSOffset
(1)
VCS_POS - VCS_NEG
At CBC trip threshold
-0.63
-0.02
0.32
mV
IBiasOffset (1)
IBiasPOS - IBiasNEG
At CBC trip threshold
-0.67
0.02
0.29
µA
ISLOPE
Peak value of current source for
slope compensation
36
µA
REVERSE CURRENT PROTECTION
N
Number of switching periods to
reset negative over-current event
counter
SR_CTR_TH
SSSR threshold to reset SSSR
cap clamp event counter
4
4.8
4.94
5.1
V
HICCUP MODE (RES PIN)
RRES
RES pulldown resistance
24
36
55
Ω
VRESTh1
RES hiccup threshold
Termination of hiccup timer
0.90
1
1.04
V
VRESTh3
RES upper counter threshold
3.91
4
4.07
V
VRESTh2
RES lower counter threshold
1.95
2
2.04
V
IRES-SRC1
Charge current source1
VRES < 1 V, CBC active
12
15
18
µA
IRES-SRC2
Charge current source2
1 V < VRES< 4 V
25
30
36
µA
IRES-DIS1
Discharge current source1
CBC not active
3.2
5
5.5
µA
IRES-DIS2
Discharge current source2
2 V < VRES < 4 V
2.5
5
7.5
µA
5.26
5.5
5.66
V
3.9
6.0
9.1
Ω
HICCUP MODE BLANKING
VHC_BLK_TH
SSSR threshold to disable the
hiccup blanking
VOLTAGE FEED-FORWARD (RAMP PIN)
RAMP sink impednace (clocked)
OSCILLATOR (RT PIN)
fSW1
Frequency (half oscillator
frequency)
RT = 25 kΩ
185
200
215
kHz
fSW2
Frequency (half oscillator
frequency)
RT = 10 kΩ
420
480
540
kHz
VRTReg
DC level
1.85
2
2.06
V
VRTSync
RT sync threshold
2.8
3
3.3
V
SYNCHRONOUS RECTIFIER TIMING CONTROL (RD1 and RD2 PINS)
8
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MIN and MAX limits apply the junction temperature range of –40°C ≤ TJ ≤ 125°C. Unless otherwise specified, the following
conditions apply: VIN = 48 V, RT = 25 kΩ, RD1 = RD2 = 20 kΩ, RON = 100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5
V, ON_OFF = 0 V.
PARAMETER
t1
TEST CONDITIONS
MIN
TYP
MAX
UNIT
94
123
157
ns
RD1 = 100 kΩ
213
278
350
ns
RD2 = 20 kΩ
60
79
102
ns
RD2 = 100 kΩ
188
250
315
ns
47
65
87
ns
596
800
1063
µA
SR trailing edge delay SR turn-off
RD1 = 20 kΩ
to primary switch turn-on
t2
SR leading edge delay primary
switch turn-off to SR turn-on
tclk
Pulse width of the clock
COMP PIN
IPWM-OS
COMP current to RAMP offset
RAMP = 0 V
VSS-OS
SS to RAMP offset
RAMP = 0 V
0.86
1
1.15
V
COMP current to RAMP gain
delta RAMP/delta ICOMP
1895
2400
2936
Ω
SS to RAMP gain
delta SS/delta RAMP
0.574
0.646
0.74
COMP current for SSSR charge
curent enable
SS > 2 V
600
750
900
µA
100
120
150
ns
0
%
ICOSsrEn
COMP to gate driver output delay
Minimum duty cycle
ICOMP = 1 mA
BOOST (BST PIN)
VBST(UV)
BST under-voltage threshold
VBST - VSW rising
Hysteresis
3.2
4.137
5.6
V
0.37
0.481
0.65
V
LSG, HSG GATE DRIVERS
VOL_PRI
VOH_PRI
Low-state output voltage
IHSG/LSG = 100 mA
0.1
0.3
0.41
V
High-state output voltage
IHSG/LSG = 100 mA, VOHL_PRI = VCC VLSG, VOHH_PRI = VBST - VHSG
0
0.38
1
V
Rise Time
C-load =1000 pF
2
8
12
ns
2
10
14
ns
Fall Time
C-load =1000 pF
ISO_PRI
Peak Source Current
VHSG/LSG = 0V
1
A
ISI_PRI
Peak Sink Current
VHSG/LSG = VCC
2
A
SR1, SR2 GATE DRIVERS
VOL_SR
Low-state output voltage
ISR1/SR2 = 10 mA
VOH_SR
High-state output voltage
ISR1/SR2 = 10 mA, VOH_SR = VREF - VSR
0.12
V
0.313
V
Rise Time
C-load = 1000 pF
25
Fall Time
C-load = 1000 pF
4
45
65
ns
10
16
ns
ISO_SR
Peak Source Current
VSR = 0 V
ISI_SR
Peak Sink Current
VSR = VREF
0.05
0.09
0.14
A
0.1
0.2
0.4
A
HALF BRIDGE THERMAL SHUTDOWN
TSD
Thermal Shutdown Temp
Thermal Shutdown Hysteresis
150
°C
25
°C
AUX SUPPLY SWITCH CHARACTERISTICS
Buck Switch RDS(ON)
ITEST= 60 mA
3.0
5.2
7.5
Ω
Synchronous Switch RDS(ON)
ITEST= 60 mA
1.2
2.8
4.5
Ω
3.5
5.0
6.5
V
AUX SUPPLY UNDERVOLTAGE LOCKOUT
VBST_AUX(UV)
BST_AUX undervoltage threshold VBST_AUX - VSW_AUX rising
VAUX_UVLO
AUX supply UVLO input voltage
rising threshold
12.2
15
16.0
V
AUX supply UVLO input voltage
falling threshold
7.9
11.2
12.7
V
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MIN and MAX limits apply the junction temperature range of –40°C ≤ TJ ≤ 125°C. Unless otherwise specified, the following
conditions apply: VIN = 48 V, RT = 25 kΩ, RD1 = RD2 = 20 kΩ, RON = 100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5
V, ON_OFF = 0 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUX SUPPLY REGULATION
VAUX-OFF
OFF-State AUX Voltage
Regulation Level
1.26
1.4
1.53
V
VAUX-ON
ON-State AUX Voltage
Regulation Level
0.95
1
1.04
V
150
200
250
mA
AUX SUPPLY CURRENT LIMIT
IAUX(LIM)
AUX Supply Current Limit
Threshold
tCSBLKA
Current limit comparator blanking
period measured from start of tON
period (1)
tAUX(LIM)
Delay from Comparator
Threshold to upper MOSFET
turn-OFF (1)
τAuxSns
Aux Current Limit Parasitic Filter
time constant (1)
50
ns
116
ns
41
ns
AUX Supply Thermal Shutdown
Temp
160
°C
AUX Supply Thermal Shutdown
Hysteresis
28
°C
AUX SUPPLY THERMAL SHUTDOWN
TSD_AUX
(1)
Specified by design. Not production tested.
6.6 Switching Characteristics
MIN and MAX limits apply the junction temperature range –40°C ≤ TJ ≤ 125°C. Unless otherwise specified, the following
conditions apply: VIN = 48 V, RT = 25 kΩ, RD1 = RD2 = 20 kΩ, RON =100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5
V, ON_OFF = 0 V.
PARAMETER
tON
AUX SUPPLY ON-TIME
TEST CONDITIONS
VIN = 32 V, RON = 100 kΩ
MIN
TYP
MAX
UNIT
240
330
440
ns
tON
AUX SUPPLY
ON-TIME(1)
VIN=54 V, RON = 250 kΩ
493
ns
tON
AUX SUPPLY ON-TIME(1)
VIN=75V, RON = 250 kΩ
370
ns
tOFF(MIN)
AUX SUPPLY MINIMUM OFFTIME
FB_AUX = 0 V
(1)
10
69
103
136
ns
Specified by design. Not production tested.
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6.7 Typical Characteristics
100%
95%
VCC Supply Voltage (V)
90%
85%
Efficiency
80%
75%
70%
65%
60%
VIN = 36 V
VIN = 48 V
VIN = 75 V
55%
50%
0
1
2
3
4
5
Load Current (A)
fSW = 200 kHz
6
7
8
8
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
10
20
D001
VO = 12 V
30
40
50
60
70
VCC Supply Current (mV)
80
90
100
D002
Figure 6-2. VCC Load Regulation
8
325
300
275
250
225
200
175
150
125
100
75
50
25
0
7
VCC and REF Voltage
Input Start-Up Regulator
Leakage Current (PA)
Figure 6-1. Application Board Efficiency vs Load
Current
5
4
3
2
1
9
19
29
39
49
59
69
Input Voltage (V)
79
89
VCC
REF
0
99
2
D003
Figure 6-3. Input Leakage Current of Start-up
Regulator vs Input Voltage
4
6
8
10
12
14
Input Voltage (V)
16
18
20
D004
Figure 6-4. VCC and REF Voltage vs Input Voltage
2100
300
275
1800
250
1500
225
1200
200
Time (ms)
Oscillator Frequency (kHz)
6
900
RD1 = 20 k:, T1
RD1 = 100 k:, T1
175
RD2 = 20 k:, T2
RD2 = 100 k:, T2
150
125
600
100
300
75
0
0
5
10
15
20
25
30
35
RT Timing Resistance (k:)
40
45
50
50
-40
-25
D001
Figure 6-5. Oscillator Frequency vs RT Timing
Resistance
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
D006
Figure 6-6. Dead Time vs Temperature
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300
775
275
770
CS_SET Pin Voltage (mV)
250
225
Time (ns)
200
175
150
125
100
75
50
T1
T2
25
750
745
740
735
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
D001
Figure 6-8. CS_SET Pin Voltage vs Temperature
210
AUX Supply Current Limit (mA)
1000
COMP Pin Current to Ramp Offset (PA)
755
725
-40
10
20
30
40
50
60
70
80
90 100
RD1 = RD2 Dead-Time Programming Resistance (k:) D007
Figure 6-7. Dead Time vs Programming Resistance
900
800
700
600
-40
760
730
0
0
765
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
205
200
195
190
185
180
-40
-25
-10
5
D009
Figure 6-9. COMP Pin to 1-V RAMP Offset vs
Temperature
20 35 50 65
Temperature (qC)
80
95
110 125
D010
Figure 6-10. Auxiliary Supply Current Limit vs
Temperature
5.5
5
4.5
REF Voltage (V)
4
3.5
3
2.5
2
1.5
1
0.5
0
0
5
10
15
20
25
30
35
REF Current (mA)
40
45
50
D011
Figure 6-11. REF Load Regulation
12
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7 Detailed Description
7.1 Overview
The LM5036 device is a highly-integrated, half-bridge PWM controller with integrated auxiliary bias supply. It
provides a high power-density solution for telecom, datacom and industrial power converters. The device has all
of the features necessary to implement a power converter that uses half-bridge topology. The device employs
voltage-mode control and includes input voltage feed-forward to improve performance. This device operates on
the primary side of an isolated DC-DC power converter with input voltage up to 100-V.
The soft-start function provides a fully regulated and monotonic rise of output voltage, even when the converter
energizes into a pre-biased load. The device uses an enhanced cycle-by-cycle (CBC) current limit. This function
matches the pulse to maintain the voltage balance of the half-bridge capacitor divider. This method ensures flux
balance of the transformer during CBC operation. The input voltage compensation function helps to minimize the
variation of the current limit level across the entire input voltage range.
The LM5036 device has these other features:
•
•
•
•
•
•
•
•
•
•
•
•
configurable latch protection
configurable overvoltage protection (OVP)
optimized maximum duty cycle operation for the primary MOSFETs
integrated half-bridge MOSFET gate drivers
programmable dead-time between the primary MOSFETs and synchronous rectifiers
auxiliary supply synchronous and asynchronous mode transition
5-V synchronous rectifier PWM outputs
programmable line undervoltage lockout (UVLO)
hiccup mode overcurrent protection (OCP)
reverse current protection
a 2-MHz capable oscillator with synchronization capability
two-level thermal shutdown protection
An Excel Calculator Tool is provided to ease the process of creating custom designs using this controller. This
tool calculates values for all the external components required by the controller to meet a given specification. It
also generates many key parameters of the power stage including, for example, the turns ratio of the half-bridge
transformer. The tool generates graphs predicting, for a given set of current limit components, how the output
current limit will vary with input voltage. Maximum flexibility is offered by calculating suggested values for most
components, but allowing the user to input values of their own choice.
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7.2 Functional Block Diagram
VCC
VIN 13
RES 1
RON 6
RES
IAUX
REF
REF
Regulator
IAUX_LIM
RON
VAUX_UVLO
+
VIN
±
+
15 BST_AUX
TEMP
20 µA
1.25 V
AUX OTP
RON
+
COT
Timers
VIN
50 µA
AUX
Supply
Control
Logic,
Driver
Logic,
Dead
Time,
Protection
Logic
+
160°C
ON_OFF 7
IAUX
HB OFF
+
1.25 V
AUX
OFF
VCC UV
REF UV
VCC UV
REF UV
2
8
AUX
OCP
VIN
350 mV
SS
ILIM
One-Shot
Start-Up Regulator
UVLO 28
AGND
VCC
+
Hiccup Mode
150°C OTP
HB OFF
UVLO VAUX_UVLO (15-V typical) and VCC and REF are above the respective
UV thresholds. When the soft-start capacitor is below VSSSecEn (2.06-V typical), the auxiliary supply will produce
the off-state voltage on the primary (VAUX1-OFF) and secondary side (VAUX2-OFF), as shown in Figure 7-9.
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The off-state auxiliary output voltage level present on the secondary side VAUX2-OFF is above the threshold
VTHSec, which activates a reset circuit that discharges the output voltage reference VREFSec. This ensures that
the opto-coupler is producing a 0% duty-cycle command. When UVLO exceeds VUVLO (1.25-V typical) and VCC
and REF are above the respective UV thresholds, the soft-start capacitor starts to charge. The auxiliary supply
will produce the on-state voltage level when the soft-start capacitor reaches VSSSecEn.
VAUX_UVLO
VIN
VUVLO
VSD
UVLO
VAUX2-OFF
VTHSec
VAUX2-ON
VAUX2
VSSSecEn
VSS-OS
SS
Prebias
Voltage
VO
VREFSec
ICOSsrEn
ICOMP
Soft-Start of SR
SR
SYNC Mode Freewheeling
Pulse
VSSREn
SSSR
t1
t2
t3
Figure 7-9. Pre-biased Start-Up Waveform
The secondary side reset circuit will now be disabled because VAUX2-ON < VTHSec, and the output voltage
reference is released. The reference capacitor soft-starts the output voltage under full regulation. By modulation
22
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of the auxiliary output voltage, the communication between the primary and secondary side is established
without the need of any additional opto-coupler.
Due to the introduced programmable soft-start delay (before SS capacitor reaches VSSSecEn), the duty cycle is
controlled by the feedback control loop at all times without being interfered by the SS capacitor voltage (because
VCOMP < V SS). When the reference voltage exceeds the pre-bias voltage at the output, the ICOMP starts to fall as
the secondary side error amplifier demands increased power. As ICOMP falls the internal VCOMP voltage will rise
and when it exceeds VSS-OS, which corresponds to zero duty cycle, the duty cycle of the primary FETs starts to
increase. Once the ICOMP current falls below ICOSsrEn the device starts to charge SSSR capacitor with current
ISSSR (20-µA typical).
Main
Clk
Delayed
Clk
LSG
HSG
SR1
SR2
VSSREn
SSSR
Figure 7-10. PWM Timing During Startup Process
7.3.9.2 Synchronous Rectifier (SR) Soft-Start Process
Until SSSR capacitor reaches VSSREn (1-V typical), the controller operates at SR synchronization (SYNC) mode
where the SR pulses are synchronized to the respective primary FET pulses, as shown in Figure 7-10. This
helps to reduce the conduction loss of the SRs. In addition, due to the fact that the SRs only conduct during
power transfer phase, there is no risk of reverse current in SYNC mode. Since the pulse width of SRs gradually
increases, the output voltage disturbance due to the difference in the voltage drop between the body diode and
the on resistance of the SRs is prevented.
Once the SSSR capacitor crosses the VSSREn, the LM5036 device begins the soft-start of the SRs freewheeling
period (highlighted in gray in Figure 7-10) where the SRs may sink current from the output if they are engaged
prematurely. The VSSREn offset on the SSSR pin is intended to provide additional delay which ensures that
the primary duty cycle ramps up to a point where the output voltage is in-regulation, thereby avoiding reverse
current when the SRs are engaged. The SR soft-start follows a leading-edge modulation technique such that
the leading-edge of the SR pulse is soft-started as opposed to the trailing-edge modulation of the primary FETs.
As shown in Figure 7-10, SR1 and SR2 are turned on simultaneously with a narrow pulse-width during the
freewheeling period. At the end of the freewheel period, that is, at the rising edge of the main CLK, the SR in
phase with the next power transfer cycle remains on while the SR out of phase with it is turned off. The in-phase
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SR remains on throughout the power transfer cycle and at the end of it, both the primary FET and the in-phase
SR are turned off simultaneously. At the end of the soft-start, the SR pulses will become complementary to the
respective primary FETs, as shown in Figure 7-6.
7.3.10 Zero Duty Cycle Operation
The zero duty cycle detection ensures that there is no excessive reverse current when the primary duty cycle
is zero. In that case, the SSSR capacitor would be clamped to ground and therefore SRs will be turned off (SR
SYNC mode). Normal operation will resume (SSSR capacitor start to charge) as soon as the load is applied. It
should be noted about a special application scenario where there is a low output capacitance value. During the
start-up under no load condition, the output capacitor acts like a load. With small output capacitor the converter
might get stuck in zero duty until load is applied.
7.3.11 Enhanced Cycle-by-Cycle Current Limiting with Pulse Matching
Figure 7-11 illustrates the half-bridge converter with low-side current sensing using a sense resistor.
VIN
SR1
VO
HSG
SW
LSG
SR2
SGND
VCS+
PGND
VCS±
PGND
Figure 7-11. Half-Bridge Converter with Low-Side Current Sensing
In LM5036 device, current limiting for the half-bridge converter is accomplished with three pins, including
CS_SET, CS_POS and CS_ NEG pins, as shown in Figure 7-12. The current sense circuit limits positive
current flowing from input to output and also negative current flowing from output to input. An input voltage
compensation function helps to minimize the variation of effective output current limit across the range of input
voltage. A pulse matching function is automatically implemented when the peak current limit circuit is active. This
function matches the pulse width on the high and low primary FETs to maintain voltage balance of the half-bridge
capacitor divider. This method ensures flux balance of the transformer during peak current limit operation.
24
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VIN
IPRI
R2
ISLOPE
R1
VCS
CF
RCS
CS_POS
K10a
+
Amp
1/K10b
R3
K2a
CS_NEG
PGND
POS_OCP
ICS_SET
RLIM
AGND
+
CBC
1/K2b
CS_SET
+
±
NEG
+
NEG_OCP
VLIM
AGND
Figure 7-12. Block Diagram of the Current Limiting Function
CS_SET pin is used to set the internal current limit threshold with an external resistor RLIM according to Equation
7.
ICS _SET =
VLIM
RLIM
(7)
where
•
VLIM (0.75-V typical) is the internal current limit setting voltage.
The CS_POS pin is driven by a signal representative of the current flowing through the low-side FET of the
half-bridge converter. The current sense voltage at CS_POS pin (equal to CS_NEG pin voltage) is converted
to a current sense signal through R3 which is then sensed, scaled and compared against the internal current
limit thresholds. In order to blank the leading-edge transient noise seen when the low-side FET is turned
on, the current sense signal is blanked for tCSBLK after LSG is turned on. If the magnitude of the noise
spike is excessive, an additional filter capacitor CF may be added to form an RC filter with R1 to reduce the
high-frequency noise spike. Both the leading-edge blanking and RC filter help to prevent false triggering of CBC
current limiting operation.
In order to achieve bi-directional current sensing, an internal offset current (K10a x ICS_SET), is injected to the
CS_POS pin. This offset allows positive internal thresholds on the CBC and NEG comparators that correspond
to effective ICS_SET and -ICS_SET / 2 thresholds at the input.
When the current sense signal (IR3 x 1 / K10b) reaches the positive threshold (K2a x ICS_SET), CBC current limiting
operation is activated. The controller essentially operates in peak current mode control, with the voltage loop
open, during the CBC operation. A common issue with peak current mode control is sub-harmonic oscillation.
This occurs when the effective duty cycle is greater than 50%. A common solution for sub-harmonic oscillation is
to add slope compensation. The slope of the compensation ramp must be set to at least one half the downslope
of the output inductor current transformed to the primary side across the current sense resistor. To eliminate
sub-harmonic oscillation after one switching cycle, the slope compensation must be equal to the downslope of
the output inductor current. This is known as deadbeat control. In LM5036, the slope compensation signal is a
saw-tooth current signal ramping up from 0 to ISLOPE at the oscillator frequency (twice the switching frequency of
each primary FET).
However, another issue will arise after slope compensation is added. The current limit level varies with the input
voltage, as illustrated in Figure 7-13. Because the slope compensation magnitude is different at different input
voltages, the actual current limit level varies with input voltage for a given internal current limit threshold.
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ICS_SET x 20
ISLOPE x Dmax
IO / NPS
ICS_SET x 20
ISLOPE x Dmin
VCS / R1
VIN(min) / R2
ICS_SET x 10
VCS / R1
IO / NPS
VIN(max) / R2
ICS_SET x 10
ICS_SET x 5
ICS_SET x 5
time
time
Figure 7-13. Current Sense and Current Limit Waveforms
A new feature, input voltage compensation, is provided by LM5036. By adding an extra signal, which is a
function of input voltage, on top of the current sense signal and the slope compensation signal, variation of the
current limit level can be minimized over the entire input voltage range. The CS_POS pin voltage at time t, after
the rising edge of LSG, is expressed by Equation 8:
v CS _ POS t
v CS t
§
R1 u ¨ ICS _ SET u K10a
¨
©
v CS t
v CS _ POS t
VIN
§
VIN
R1 u ¨ ICS _ SET u K10a
R2
©
R1
1
R2
v CS _ POS t
R2
·
ISLOPE u t u fOSC ¸
¸
¹
(8)
·
ISLOPE u t u fOSC ¸
¹
(9)
At the trip threshold, of the CBC comparator, both its inputs are at the same potential. In this case the voltage on
the CS_NEG pin is expressed by Equation 10.
vCS _ NEG
v CS _ POS t
ICS _ SET u K 2a u K10b u R3
(10)
v CS _ NEG
(11)
For a given duty cycle (D) the current sense threshold voltage that will just trigger the CBC comparator can be
determined by combining Equation 9, Equation 10 and Equation 11.
vCS _ CBCTh
§
§
§ 1
R1 u ¨ ICS _ SET u ¨ K 2a u K10b u R3 ¨
¨
¨
© R1
©
©
·
1 ·
¸ K10a ¸¸
R2 ¹
¹
VIN
R2
·
ISLOPE u D ¸
¸
¹
(12)
Now if we assume:
26
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1
R3
1
R1
K10a
K 2a
D
NPS
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1
R2
K10b
10
2
tON u fOSC
2 u VO
u NPS
VIN
NP
NS
(13)
Equation 12 simplifies to Equation 14.
v CS _ CBCTh
§K
R1 u ¨ CBC1
© RLIM
VIN
R2
ISLOPE u
·
2 u VO
u NPS ¸
VIN
¹
Where
K CBC1
VLIM u K 2a u K10b
K10a
(14)
Section 8.2.2.11 gives an example design process for calculating the CBC external resistor values. The Excel
Calculator Tool can also be used to assist in the process of selecting these resistor values.
LM5036 ensures flux balance of the main transformer during CBC operation. The duty cycles of the two primary
FETs are always matched. If the low-side FET is terminated due to a current limit event, a matched duty cycle
will be applied to the high-side FET during the next half switching period, regardless of the current condition. The
matched duty cycles ensure voltage-second balance of the transformer which prevents transformer saturation.
The pulse matching operation is illustrated in Figure 7-14. When the current limit is reached during the low-side
phase, a FLAG signal goes high. The RAMP signal is sampled at the rising edge of the FLAG signal and then
held through the next half switching period for the high-side phase. When the high-side phase RAMP signal
rises above the sampled value, the high-side PWM pulse is turned off so that the duty cycle are matched for
both phases. In the meantime, the hiccup restart capacitor is charged with a current source IRES-SRC1 (15-µA
typical) during CBC operation. The pulse matching feature is handled automatically by the LM5036 controller
and requires no action from the designer.
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Delayed
CLK
Current Limit
Sensed
Current
S&H
Ramp
Flag
LSG
HSG
Figure 7-14. Pulse Matching Operation
7.3.12 Reverse Current Protection
In addition to the CBC current limit, a negative current limit, which is set to be half of the positive current limit
as shown in Figure 7-15. This is used to prevent excessive reverse current which could cause significant output
voltage dip and potentially damage the power converter. When the negative current limit is exceeded twice, the
SSSR capacitor will be clamped to ground so the controller enters the SR SYNC mode where the SR pulses are
synchronized to the respective primary FET pulses. Therefore, the SR freewheeling pulses are turned off. The
negative current limit event counter will be reset if the number of negative current limit events detected within
four switching periods is less than two.
1/K2b
+
CS_SET
RLIM
AGND
INEG_LIM
+
±
Negative
SSSR Cap
Current Limit
Clamp Event
Event Counter Clamping
Counter
NEG_OCP
SSSR cap
Hiccup Mode ON
When Counter = 8
VLIM
AGND
Figure 7-15. Reverse Current Protection Circuit
At the trip threshold of the NEG comparator both inputs are at the same potential. In this case the voltage on the
CS_NEG pin is expressed by Equation 15.
28
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vCS _ NEG
ICS _ SET u
1
u K10b u R3
K 2b
(15)
The voltage across the CS resistor at the trip threshold of the NEG comparator can therefore be determined by
combining Equation 9, Equation 11 and Equation 15.
v CS _ NEGTh
§K
R1 u ¨ CBC2
© RLIM
VIN
R2
·
ISLOPE u tCSBLK u fosc ¸
¹
Where :
K 2b 2
§ 1
VLIM u ¨
u K10b
© K 2b
K CBC2
·
K10a ¸
¹
(16)
Notice that the inductor current has its most negative value at the start of the LSG on period. The NEG
comparator trip will occur immediately after the blanking period (tCSBLK) has expired.
The Excel Calculator Tool predicts both the positive and negative output current limit levels as a function of input
voltage for a given set of resistor values.
7.3.13 CBC Threshold Accuracy
The CBC current limit amplifier deployed within LM5036 is a precise component. In common with all such
devices the input bias currents and input offset voltage will lead to small variations in the current trip threshold
between parts and across temperature.
VIN
R2
ISLOPE
VCSOffset
K10a
+
R1
VCS
CF
RCS
±
IPRI
IBiasPOS
CS_POS
+
Amp
K2a
CS_NEG
PGND
+
CBC
POS_OCP
ICS_SET
RLIM
AGND
1/K10b
IBiasNEG
R3
1/K2b
+
±
CS_SET
NEG
+
NEG_OCP
VLIM
AGND
Figure 7-16. Diagram of Current Limiting Function with Error Terms Shown in Red
At its trip threshold the two inputs of the CBC comparator must be equal. At this condition the voltage on the
CS_NEG pin is given by Equation 17.
v CS _ NEG
§ VLIM
u K 2a u K10b
¨
© RLIM
·
IBiasNEG ¸ u R3
¹
(17)
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The voltage drop across the ideal amplifier input must be zero. The voltage of the CS_POS pin, at the trip
threshold can be expressed as follows:
vCS _ POS
vCS _ NEG
vCSOffset
vCS _ POS
vCS _ CBCTh
(18)
§ VLIM
u K10a IBiasPOS D u ISLOPE
¨
© RLIM
VIN
vCS _ POS ·
¸ u R1
R2
¹
(19)
Combining Equation 17, Equation 18 and Equation 19 and re-arranging gives an expression for the voltage
across the current sense resistor at the trip threshold Equation 20.
v CS _ CBCTh
Where :
IBiasOffset
§K
R1 u ¨ CBC1 IBiasOffset
© RLIM
v CSOffset
R3
D u ISLOPE
VIN ·
¸
R2 ¹
IBiasPOS IBiasNEG
(20)
Hence, for a given set of external component values, the variation in current trip threshold across parts and
temperature can be found using data supplied in the Electrical Tables.
A short delay will exist (tCSLSG), after the CBC comparator inputs reach their trip threshold, before the LSG falling
edge. During this delay the primary current will continue to ramp, giving rise to a further error in the apparent trip
threshold. The peak primary current flowing when the low side MOSFET switches OFF (IPriCBC), is expressed by
Equation 21.
IPr iCBC
VCS _ CBCTh
RCS
§1 § V
tCSLSG u ¨ u ¨ IN
¨ 2 ¨ LMag
©
©
VIN
LO u NPS
2
·
·
VO
¸
¸
¸ LO u NPS ¸
¹
¹
(21)
The output current at which the primary peak current threshold is reached is expressed by Equation 22.
ILIM
ª
NPS u «IPr iCBC
¬
'ILO
NPS
º
'ILMag »
¼
(22)
ΔILO is the amplitude of ripple current in the output inductor and is expressed in Equation 23.
'ILO
VO u (1 D)
2 u LO u fOSC
(23)
ΔILMag is the amplitude of ripple current in the magnetising inductor and is expressed in Equation 24.
'ILMag
30
VIN
D
u
2 2 u LMag u fOSC
NPS u VO
2 u LMag u fOSC
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Combining Equation 22, Equation 23 and Equation 24 gives an expression for output current limit as a function
of primary current limit threshold Equation 25.
ILIM
ª
NPS u «IPr iCBC
«¬
VO u NPS º
»
2 u LMag u fOSC »¼
VO u 1 D
2 u LO u fOSC u NPS
(25)
The Excel Calculator Tool can be used to evaluate the tolerance of output current limit.
7.3.14 Hiccup Mode Protection
A block diagram of the hiccup mode function is shown in Figure 7-17. Both the repetitive CBC and negative
current limit events will trigger hiccup mode operation in LM5036 device.
Continuous
CBC
SSSR Cap
Clamp Event
Counter
Hiccup
Mode
Timer
and
Logic
RES
Reset
SSSR
TH
+
Hiccup
Blank
+
VRES
SSSR
1V
Figure 7-17. Hiccup Mode Circuitry
The device charges the hiccup restart capacitor with a current source IRES-SRC1 (15-µA typical) during CBC
operation. The hiccup mode is activated when VRES exceeds 1 V. During hiccup mode operation, the SS and
SSSR capacitors are fully discharged and the half-bridge converter remains off for a period of time (tHIC) before a
new soft-start sequence is initiated.
4V
2V
1V
tCBC
SS
tHIC
Figure 7-18. Hiccup Mode Activated By Continuous CBC Operation
Use Equation 26 to calculate the duration of CBC operation before entering the hiccup mode.
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tCBC
CRES u 1 V
IRES SRC1
(26)
where
•
CRES is the value of the hiccup capacitor
After the RES pin reaches 1.0-V, current source IRES-SRC1 (15-μA typical) is turned off and current source
IRES-SRC2 (30-μA typical) is turned on which charges the RES capacitor to 4-V. Then current source IRES-DIS2
(5-μA typical) is enabled which discharges the RES capacitor to 2-V.
Use Equation 27 to calculate the hiccup mode off-time.
tHIC
CRES u 2 V u 8
IRES DIS2
CRES u 2 V u 8 1 V
IRES
SRC2
(27)
In addition to the repetitive CBC current limit condition, the device also enters hiccup mode if the SSSR capacitor
is clamped for eight times due to repetitive negative current limit condition. The operating pattern of the hiccup
mode activated by the negative current limit is similar to that activated by CBC current limit. The only difference
is that at the beginning of the hiccup mode operation the RES capacitor is charged with current source IRES-SRC2
when activated by negative current limit as illustrated in Figure 7-19 whereas the RES capacitor is charged with
current source IRES-SRC1 when activated by CBC current limit condition.
4V
2V
0V
Counter (1)
tHIC
(1) SSSR capacitor clamp event counter
Figure 7-19. Hiccup Mode Activated By Repetitive Negative OCP Condition
Once the hiccup off-timer expires, the SSSR capacitor clamp event counter will be reset. If SSSR capacitor gets
clamped for less than eight times before the SSSR capacitor voltage is fully ramped up to its maximum value,
the SSSR capacitor clamp event counter will also be reset. This is because the fact that SSSR capacitor voltage
is able to fully ramp up to its maximum value indicates that repetitive negative current limit condition no longer
exists.
7.3.15 Hiccup Mode Blanking
In some application scenarios such as high output capacitance and/or heavy load, there can be excessive
inrush current during the start-up process. This would trigger CBC current limit which in turn activates the hiccup
mode operation, thereby causing the converter to keep attempting to restart. In LM5036 device, a hiccup mode
blanking circuitry is implemented to disable the hiccup mode operation during the start-up. The hiccup capacitor
is clamped to ground until the SSSR capacitor voltage rises above the hiccup blank threshold VHC_BLK_TH (5.5-V
typical).
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7.3.16 Over-Temperature Protection (OTP)
Two-level internal thermal shutdown circuitry is implemented in LM5036 device to protect the integrated circuit
should its maximum rated junction temperature be exceeded. When the internal temperature is above the
lower-level threshold of 150°C, the half-bridge converter is turned off and thereby the SS and SSSR capacitors
are fully discharged.
Typically, the internal temperature should drop after the main half-bridge converter is turned off. However, if the
temperature continues to rise above the higher-level threshold of 160°C, the auxiliary supply will be disabled in
order to prevent the device from catastrophic failure due to accidental device overheating . Note that the internal
VCC and REF bias regulators still remain active during thermal shutdown to provide the bias power for the
external house-keeping circuitry.
7.3.17 Over-Voltage / Latch (ON_OFF Pin)
The ON_OFF pin can be configured as a latch pin or OVP pin. In the latch configuration, the half-bridge
converter remains off even after the faults are cleared. A new soft-start sequence will not be initiated until the
latch is reset. One latch configuration is illustrated in Figure 7-20 where a large latch resistor RL (for example, 50
kΩ) and a diode are tied to the ON_OFF pin.
REF
IOVL
VIN
ON_OFF
ROV1
VON_OFF
REF UV
+
ROV2
RL
Hiccup Mode
VCC UV
HB OFF
150°C OTP
UVLO < 1.25 V
(LATCH RESET)
UVLO < 1.25 V
Figure 7-20. ON/OFF Pin Latch Function
When any of the faults is detected including OVP, hiccup mode OCP and 150 °C OTP, the ON_OFF pin current
source, IOVL (50-µA typical), is activated, that raises the ON_OFF pin voltage quickly. As a result, the latch diode
is reverse biased. The current source IOVL remains active even if the fault is cleared because the ON_OFF pin
voltage is latched above VON_OFF (1.25-V typical). To reset the latch operation, simply pulling down the UVLO
pin voltage below VON_OFF disables the current source and thus the ON_OFF pin voltage falls quickly. A new
soft-start sequence will be initiated as soon as the latch is reset and the faults are cleared.
Use Equation 28 to design the external voltage divider in latch mode.
VIN _ L
§ VON _ OFF VF
¨
ROV2
©
VON _ OFF ·
¸ u ROV1 VON _ OFF
RL
¹
VF
(28)
where
•
•
VF is the forward voltage drop of the latch diode
VIN_L is the desired input voltage latch threshold, and RL is the latch resistor.
Note that the current source IOVL does not provide any hysteresis when ON_OFF pin is configured in latch mode.
The ON_OFF pin can also be configured as an OVP pin as shown in Figure 7-21. In this configuration, the
external voltage divider should be designed such that the ON_OFF pin voltage is greater than VON_OFF when an
over-voltage condition occurs.
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REF
IOVL
VIN
ROV1
VON_OFF
ON_OFF
REF UV
+
ROV2
Hiccup Mode
VCC UV
HB_OFF
150°C OTP
UVLO < 1.25 V
UVLO < 1.25 V
AGND
Figure 7-21. ON/OFF Pin Configured as OVP Pin
The OVP hysteresis is accomplished with the IOVL current source. When the ON_OFF pin voltage exceeds
VON_OFF, the IOVL current source is activated which quickly raises the voltage at the pin. The half-bridge
converter is turned off and the SS and SSSR capacitors are fully discharged. When the ON_OFF pin voltage
falls below VON_OFF, the current source is deactivated causing the voltage at the pin to quickly fall followed by
a new soft-start sequence. In addition to the OVP fault, hiccup mode and internal 150-°C thermal shutdown
faults will also cause the half-bridge converter to turn off. Once the faults are cleared, a new soft-start sequence
automatically begins. Because the hiccup mode or 150-°C thermal shutdown fault also activates the current
source, it is important to make sure that the ON_OFF pin voltage doesn't rise above VON_OFF when the input
voltage is high, which otherwise would lead to latch operation. Avoid this scenario by selecting a proper voltage
divider.
Use Equation 29 and Equation 30 to select the voltage divider for the OVP configuration.
ROV1
VHYS(OVP)
IOVL
(29)
where
•
VHYS(OVP) is the OVP hysteresis
ROV2
VON _ OFF u ROV1
VIN(OFF)
VON _ OFF
(30)
where
•
VIN(OFF) is the OVP rising threshold
7.3.18 Auxiliary Constant On-Time Control
Figure 7-22 shows a block diagram of the constant on-time (COT) controlled fly-buck converter. The LM5036
device integrates an N-channel high-side MOSFET and associated high-voltage gate driver. The gate driver
circuit works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A 0.01-µF
ceramic capacitor connected between the BST_AUX pin and SW_AUX pin provides the voltage to the driver
during the on-time. During each off-time, the SW_AUX pin is at approximately 0-V, and the bootstrap capacitor
charges from VCC through the internal diode. The minimum off-timer ensures a minimum time in each cycle
to recharge the bootstrap capacitor. The LM5036 device also provides an internal N-channel SR MOSFET and
associated driver. This MOSFET provides a path for the inductor current to flow when the high-side MOSFET is
turned off.
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The integrated auxiliary supply employs constant on-time (COT) hysteretic control which provides excellent
transient response and ease of use. The control principle is based on a comparator and a one-shot on-timer,
with the output voltage feedback (FB_AUX) compared to an internal reference. If the feedback voltage is below
the reference the internal buck switch is switched on for the one-shot timer period, which is a function of the
input voltage and the on-time resistor (RON). Following the on-time the switch remains off until the FB_AUX
voltage falls below the reference, and the forced minimum off-time has expired. When the feedback voltage falls
below the reference and the minimum off-time one-shot period expires, the high-side buck switch is then turned
on for another on-time one-shot period. This will continue until regulation is achieved.
VCC
VCC
BST_AUX
VIN
PWMA
SW_AUX
VAUX2
Constant
On-Time
(COT)
Control
Logic
VCC
VAUX1
PWMB
FB_AUX
+
REF_AUX
Figure 7-22. COT Controlled Fly-Buck Auxiliary Supply Circuitry
In a fly-buck converter, the low-side SR MOSFET is on when the high-side switch is off. The inductor current
ramps up when the high-side switch is on and ramps down when the low-side switch is on.
The switching frequency remains relatively constant with load and line variations. Use Equation 31 to calculate
the switching frequency of the auxiliary supply.
fSW _AUX =
VAUX1
9 × 10F11 × RON
(31)
where
•
VAUX1 is the primary output voltage of the auxiliary supply.
Two external resistor values set the value of VAUX1. This regulation of the output voltage depends on ripple
voltage at the feedback input, requiring a minimum amount of ESR for the output capacitor (CAUX1). A minimum
of 25-mV of ripple voltage at the feedback pin is required for stable operation of the auxiliary supply. The Section
7.3.22 section describes auxiliary ripple circuit configuration.
7.3.19 Auxiliary On-Time Generator
The on-time for the auxiliary supply is determined by the resistor RON, and is inversely proportional to the input
voltage, resulting in a nearly constant switching frequency as the input voltage is varied over its entire range.
Figure 7-23 shows the block diagram for the on-time generator.
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VIN
AUX RAMP
tON
AUX RAMP
RESET
RON
PWMA
RON
PWMB
Figure 7-23. On-Time Generator
Time
Figure 7-24. Constant On-Time Control Waveform
A current source, which is a function of the input voltage and the RON resistor value, charges a capacitor. The
capacitor voltage ramps up linearly and gets reset when it reaches the threshold.
Use Equation 32 to calculate the on time tON of the high-side switch.
t ON =
9 × 10F11 × R ON
VIN
(32)
7.3.20 Auxiliary Supply Current Limiting
The LM5036 controller contains an intelligent current limit off-timer for the auxiliary supply. If the current in
the high-side switch exceeds IAUX(LIM) (200-mA typical), both the high-side MOSFET and the low-side SR are
immediately turned off, and a non-resetable off-timer is initiated. The length of the off-time is a function of the
FB_AUX pin voltage and the input voltage VIN. As an example, when VFB_AUX = 0 V and VIN = 48 V, a maximum
off-time is set to 16 µs. This condition occurs when the output is shorted, and during the initial phase of start-up.
This amount of time ensures safe short-circuit operation up to the maximum input voltage of 100 V.
In cases of overload where the FB_AUX voltage is above zero volts (not a short circuit) the current limit off-time
is reduced. Reducing the off-time during less severe overloads reduces the amount of foldback, recovery time,
and start-up time. The current limit off-time is calculated from Equation 33.
tOFF (ILIM ) =
(0.07 × VIN )
Js
VFB_AUX + 0.2 V
(33)
Because the current limit protection feature of the auxiliary supply is peak limited, the maximum average output
is less than the peak.
To prevent excessive reverse current during the off-time of the current limit, the auxiliary supply operates in
asynchronous (ASYNC) mode where the low-side SR is turned off during current limit operation. The body
diode of the internal low-side MOSFET (QB) incurs significant power loss during asynchronous operation. TI
recommends adding an external schottky diode (DFW) between the PGND and SW_AUX pins to ensure robust
and efficient current limit operation. This schottky diode is particularly important when operating from high input
voltage. Use an external schottky diode (DFW) that is rated to carry the maximum auxiliary current and block the
maximum input voltage (VIN(max)).
For high density designs it is desirable to use an auxiliary transformer with low magnetising inductance and
saturation current. The peak magnetising current flowing in the auxiliary transformer can exceed IAUX(LIM) due
to delays in the peak current detection and comparator circuit. The actual peak magnetising current reached
is a function of the maximum slope of the transformer magnetising current. This behavior depends upon both
maximum input voltage VIN(max) and magnetising inductance value. The method outlined below allows designers
to estimate the peak magnetising current that will flow in the Aux transformer (ILPk).
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As illustrated in Figure 7-25, it is convenient to model the internal current sense circuit as a simple RC time
constant, τAuxSns (41-ns typical), that delays the sensed current signal presented to the OCP comparator input.
There is a further delay tAUX(LIM) (116-ns typical), after the comparator input reaches its trip threshold before the
OCPb fault flag is set. The controller applies this extended off time, tOFF(ILIM), only if the OCPb fault flag is set
before the COT (tON) period ends. Equation 34 is an expression for the sensed and delayed magnetising current
inductor signal applied to the non-inverting input of the OCP comparator.
VIN
IQA(t)
QA
WAuxSns
PWMA
ILPk
ILAux(t)
+
IAUX(LIM)
ILInit
IAuxSns(t)
tAUX(LIM)
OCPb
IQA(t)
IAUX(LIM)
±
SW_AUX
VAUX2
IAuxSns(t)
QB
tAUX(LIM)
PWMB
tON
DFW
VAUX1
PGND
PGND
PGND
Figure 7-25. Aux Current Limit Circuit Model
IAuxSns (t)
ILInit
mAux u W AuxSns
t
§
W AuxSns
¨
u 1 e
¨¨
©
·
¸ m
Aux u t
¸¸
¹
(34)
where
•
•
mAux is the slope of Aux transformer magnetising inductor current during QA on period
τAuxSns is the time constant of the internal current sensing circuit feeding the OCP comparator
Maximum peak current occurs when the magnetising inductor current slope has its highest value. This peak
occurs at start-up, or when a short circuit is applied across the VAUX1 output, while operating from maximum
input voltage (VIN(max)). The maximum inductor current slope is given by Equation 35.
mAux
VIN(max)
L AUX
(35)
where
•
LAUX is the magnetising inductance of the Aux transformer
For a use case where the inductor current slope is fixed at its maximum value (mAux), the highest peak current
occurs when the inductor current at the start of the pulse (ILInit) is just high enough to trip the OCPb flag before
the COT period (tON) expires. After this trip occurrs, the controller applies the extended OFF period (tOFF(ILIM))
to reduce the inductor current for subsequent pulses. This condition is given in Equation 36 and is shown
graphically in Figure 7-25
IAuxSns tON
t AUX(LIM)
IAUX(LIM)
(36)
where
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•
tAUX(LIM) is the time delay between comparator input threshold being achieved and the OCPb flag set
Combining Equation 34 and Equation 36 determines the initial inductor current for a pulse containing the highest
peak current Equation 37.
IAUX(LIM)
ILInit
mAux u tON
t AUX(LIM)
mAux u W AuxSns
tON t AUX(LIM)
W AuxSns
1 e
(37)
Equation 38 uses the COT period in Equation 37 for the maximum input voltage.
tON
K ON u RON
VIN(max)
(38)
where
•
KON (9 × 10–11 typical) is an internal constant that defines the COT period for a given VIN and RON
Having calculated ILInit the estimated peak inductor current is given by Equation 39.
ILPk
ILInit
mAux u tON
(39)
Use this method to ensure that the operation does not exceed the Aux transformer saturation current under
transient or fault conditions. This method assumes fixed transformer magnetising inductance. The method
provides only a reasonable accuracy if the transformer magnetising inductance has not fallen significantly at the
predicted peak current.
To avoid excessive peak magnetising current during transient or fault events, ensure that the COT period (tON)
is longer than the response time of the peak current protection circuit. Equation 40 expresses it as a minimum
required value for RON .
RON t
W AuxSns
t AUX(LIM) u 1.2
KON
u VIN(max)
VIN(max) u 2.09 k:
(40)
7.3.21 Auxiliary Primary Output Capacitor Ripple
Equation 41 describes the output ripple voltage amplitude for a buck converter. This equation may be used if
there is no secondary winding or if the current supplied by VAUX2 is small compared with that supplied by VAUX1
(IAUX1>>IAUX2). Equation 41 neglects capacitor ESR and therefore calculates only the capacitive component of
output voltage ripple.
'VAUX1Cap
38
'IL(AUX)
2 u fSW _ AUX u CAUX1
(41)
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IL_PRI/IL_SEC
IAUX1 + N2/N1 × IAUX2
(1)
(2)
0A
IL_PRI
IL_SEC
Time
Figure 7-26. Auxiliary Transformer Current Waveform for CAUX1 Ripple Calculation
Figure 7-26 shows the flybuck primary and secondary winding current waveforms I L_PRI and IL_SEC. The reflected
secondary winding current adds to the primary winding current during the off-time of the high-side switch. Due to
this increased current, the output voltage ripple is not the same as in a conventional buck converter. In this case
the average current flowing into CAUX1 during the tON period is the reflected secondary current. Hence Equation
42 can be used to calculate ΔVAUX1Cap, the voltage ripple across the primary side capacitor, for the more typical
case when the secondary current cannot be neglected. Notice that Equation 42 neglects capacitor ESR and
therefore calculates only the capacitive component of ripple voltage amplitude.
N2
ut
N1 ON(max)
2 u C AUX1
IAUX2 u
'VAUX1Cap
(42)
7.3.22 Auxiliary Ripple Configuration and Control
The voltage ripple across the output capacitor CAUX1 is made up of two components:
•
•
Resistive ripple appears across the equivalent series resistance (ESR) of the output capacitor. This
component of ripple is in phase with the inductor current and is 90° delayed compared with the applied
PWM signal.
Capacitive ripple appears across the ideal capacitor. This component of ripple is 90° delayed compared with
the inductor current ripple and 180° delayed compared with the applied PWM signal.
With COT control, the on-time of the high-side FET is terminated by an on-timer, and the off-time is terminated
when the feedback voltage VFB_AUX falls below the reference voltage (VAUX-ON). For a buck topology this type of
hysteretic control provides stable operation if these two conditions are met:
• Output voltage ripple is dominated by the resistive ESR component. The resistive ripple amplitude must be
approximately five times the capacitive ripple amplitude to guarantee stable operation.
• Output voltage ripple amplitude present at the FB_AUX pin must be greater than noise coupled onto this pin
from other sources. For an output voltage ripple amplitude of 25 mV at the FB_AUX pin ensures that other
sources of noise coupled to the pin can be assumed small
Aux transformer magnetising inductor ripple current amplitude is expressed by Equation 43.
'IL(AUX)
VAUX1 §
1
u¨
¨
2 u L AUX © fSW _ AUX
·
tON ¸
¸
¹
K ON u RON §
VAUX1 ·
u ¨1
¸
2 u L AUX
VIN ¹
©
(43)
For a buck converter the capacitive component of output voltage ripple amplitude is expressed by Equation 41.
The resistive component of output ripple voltage amplitude is expressed by Equation 44.
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'VAUX1Re s
'IL(AUX) u REsr
(44)
Our condition for stable operation requires that Equation 45 and Equation 46 are both satisfied.
'VAUX1Re s t 5 u 'VAUX1Cap
(45)
'VAUX1Re s t 25 mV
(46)
The method outlined above allows us to calculate the resistance (REsr) that must be present in series with the
output capacitor (CAUX1) to provide stable operation of a buck converter. This simple method has disadvantages
of high output voltage ripple amplitude and high dissipation in the series resistor REsr. The method is also not
ideal for a flybuck topology, especially if most of the load current is drawn from the secondary winding. In this
case much of the magnetising inductor current flows into the secondary output capacitor (CAUX2) and not the
primary output capacitor (CAUX1) during the low-side FET conduction period (tOFF). The circuit of Figure 7-27
provides a better solution that is well suited to the flybuck topology. A series branch Rr – Cr is connected
across LAUX. The controller applies the same PWM voltage across this series branch as appears across LAUX.
Assuming most of the PWM voltage is dropped across Rr, the voltage across Cr has the almost the same shape
and phase as the inductor current. The voltage ripple across Cr can be used to substitute the voltage across
RESR and thus provide stable operation without the need for high output ripple and dissipation. By coupling this
capacitor voltage signal directly to the FB_AUX pin we can achieve the same result as a large ESR resistor, but
without the penalty of dissipation and high output voltage ripple amplitude. The method is suitable for a flybuck
topology, since the down-slope of the magnetising current is synthesised, across Cr, and therefore available on
the primary side to couple onto the FB_AUX pin.
LAUX
SW_AUX
Rr
VAUX1
Cr
Cac
RFB1
CAUX1
FB_AUX
RFB2
PGND
PGND
PGND
Figure 7-27. Minimum Ripple Configuration
The impedance of the capacitor generating the synthesised inductor current ripple signal, at the Aux switching
frequency (fSW_AUX), must be low compared with the impedance of the RFBx divider network.
Cr !
R
RFB2
3
u FB1
2 u S u fSW _ AUX RFB1 u RFB2
(47)
The synthesised inductor ripple, generated across Cr, is added to the ripple across the output capacitor (CAUX1).
The resultant signal is coupled to the FB_AUX pin via capacitor Cac. The value of series resistor Rr is chosen to
ensure the synthesised resistive ripple amplitude satisfies Equation 45 giving Equation 48.
Rr d
40
§
K ON u RON
VAUX1 ·
u ¨1
¸
¨
10 u Cr u 'VAUX1Cap ©
VIN(min) ¸¹
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Capacitor Cac couples the ripple signal directly onto the FB_AUX pin. Ensure that the value of this capacitor is
at least five times greater than the value of Cr. This ratio ensures minimum attenuation and phase shift of the
coupled ripple signal.
Cac t 5 u Cr
(49)
7.3.23 Asynchronous Mode Operation of Auxiliary Supply
In LM5036 device, there are two conditions where the auxiliary supply will enter asynchronous (ASYNC) mode
operation where the low-side SR is turned off and only its body diode is allowed to conduct. The first condition
is when the half-bridge converter is turned off (Refer to the Section 7.4 section). This helps to reduce the power
consumption of the auxiliary supply at light loads. As described in the Section 7.3.20 section, the auxiliary
supply will also be forced to operate at ASYNC mode during current limit operation to prevent excessive reverse
current.
7.4 Device Functional Modes
The functional modes of the device are summarized in the following table. Faults include hiccup mode OCP,
OVP, and 150°C OTP.
Table 7-1. Device Functional Modes
CRITERIA
VCC AND REF
REGULATORS
AUXILIARY
SUPPLY
HALF-BRIDGE
CONVERTER
UVLO < VSD
OFF
OFF
OFF
( VSD < UVLO < VUVLO) & (VIN <
VAUX_UVLO)
ON
OFF
OFF
( VSD < UVLO < VUVLO) & (VCC & REF >
UV) & (VIN > VAUX_UVLO)
ON
ON at ASYNC
Mode
OFF
(UVLO > VUVLO) & (VIN > VAUX_UVLO) &
(VCC & REF > UV) & No Faults
ON
ON at SYNC Mode
ON
(UVLO > VUVLO) & (VIN > VAUX_UVLO) &
(VCC & REF > UV) & Any Faults
ON
ON at ASYNC
Mode
OFF
(VCC & REF > UV) & (VIN > VAUX_UVLO)
& AUX Current Limit
ON
ON at ASYNC
Mode
NA
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The LM5036 device is a highly integrated half-bridge PWM controller that contains all the features necessary
for implementing the half-bridge topology power converters using voltage-mode control with input voltage feedforward. The device targets isolated DC-DC converter applications with input voltage of up to 100 VDC.
8.2 Typical Application
The following schematic shows an example of an isolated half-bridge DC-DC converter controlled by LM5036
device. The operating input voltage range is 36-V to 75-V, and the output voltage is 12-V. The maximum load
current is 8-A and the output current limit is configured to be 10-A.
D10
VIN
L1
VIN
TP1
HSG
RM7/ILP
3.3
4:3:3
T1
1
TxOut
3
131-5031-00
1
C4
2.2µF
SGND
5,6,
7,8
C8
6.8µF
6.8µF
LSG
C11
47µF
6
Q2
C12
47µF
C14
470µF
C13
47µF
C15
0.1µF
12V/10A
R37
3.3
TP2
SGND
TxOut
SGND
RCS
Q3
C9
470pF
0.005
7,8
5,6,
J2
5,6,
7,8
PGND
C7
J3
4.7µH
2
R5
100k
TP5
L2
5 TxOut
TP9
Q5
Q4
5,6,
7,8
C3
2.2µF
J7
Q1
R36
7,8
5,6,
C2
220pF
C1
2.2µF
Prebias source
2
3
4
5
C6
5,6,
7,8
6.8µF
C5
1,2,3
36V - 75V DC Input
6.8µF
SW
C42
100µF
1.21k
100V
R4
100k
TP4
R39
VIN_PIN
470nH
1,2,3
J1
Q6
TP6
C10
470pF
TP7
R38
4.99
1,2,3
1,2,3
R33
4.99
1,2,3
NT1
1,2,3
VCS+
J5
PGND
R6
100
Add shunt on J5
Net-Tie
TP8
PGND
AGND
SGND
SGND
SGND
SGND
SGND
RESET
SGND
TP3
U1
D3
RC
VIN_PIN
100V
C16
0.1µF
13
VIN
BST_AUX
15
16
PGND
SW_AUX
14
SW_AUX
VIN
R32
105k
R30
PGND
100k
R31
4.02k
C44
1000pF
28
UVLO
24
RAMP
D9
VCC
17
FB_AUX
12
R24
46.4k C34
D11
100V
VAUX1
J4
R27
40.2k
220k
AGND
D1
45V
R34
6.81k
24.9k
R29
Add shunt on J6
J6
D2
150µH
R26
715
C39
R25
49.9k
C40
BST
21
HSG
22
5
RT
6
RON
7
ON/OFF
8
SS
9
R11
20.0k 10
R35
40.2k
11
R2
VCS+
23
LSG
18
1.96M
R1 576
SR1
20
SR2
19
RD1
RD2
25
26
27
CS_POS
CS_NEG
CS_SET
PGND
RLIM
56.2k
A1
A2
A3
A4
A1
A2
A3
A4
AGND
SGND
PGND
1
U2
4
7
LSG
4
C29
COMP
0.1µF 0.1µF
VCCI
VCCI
2
INA
5
DISABLE
REF
R10
3
R9
VDDA
13
VOUTA
12
5.11k
VSSA
11
C21
0.47µF
SGND
U5
C20
1000pF
10.0k
NC
LM4040BIM3-2.5/NOPB
C28
1µF
SGND
SGND
C30
6
3
C41
1
29
DT
VDDB
INB
GND
10
VOUTB
9
VSSB
8
Q7B
C27
1µF
10k
PGND
SGND
R18
1.15k
R19
10k
PGND
LM5036RJBR
MMDT3946-7-F
R20
UCC21225ANPL
2
V+
V-
R8
6.65k
30V
4
LM8261M5
3
AGND
U4
SW
REF
EP
0.01µF
0.01µF
0.1µF
R3
576
C26
47pF
VAUX2
D6
VX
C25
SGND
C46
0.1µF
REF
SSSR
6800pF
VX
4.7V
C22
R23
1.00k
HSG
0.018uF
VIN
AGND
SW
C18
R12
R16
240
D8
C36
1µF
PGND
PGND
0.047µF
C38
1000pF
RES
SGND
VAUX2
100V
R22
7.50k
C17
1500pF
R14
150k
5
1
R28
3
220pF
2
C45
560pF
R21
2.2k
C31
1µF
D4
VAUX1
2
1000pF
C35
0.1µF
45V
C43 0.068µF
Add shunt on J4
R7
25.5k
4
11.8k
C32
2.2µF
100V
L3
1
AGND
VIN
R13
511
30V
D7
C19
C33
0.01µF
R17
C37
AGND
VAUX2
D5
10k
9.1V
2200pF
SGND
RESET
PGND
C24
0.01µF
Q7A
MMDT3946-7-F
C23
0.1µF
U3
4
1
3
2
R15
SGND
1.82k
PS2811-1-M-A
Figure 8-1. Evaluation Board Schematic
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8.2.1 Design Requirements
PARAMETER
VALUE
VIN
Input voltage
VO
Output voltage
IO (max)
Maximum load current
8A
ILIM
Output current limit
10 A
η
Peak efficiency
94.4 %
Efficiency at VIN = 48 V and IO = 8 A
93.5 %
VAUX1-OFF
Off-state auxiliary output voltage
11.9 V
VAUX1-ON
On-state auxiliary output voltage
8.5 V
Load regulation
0.2%
Line regulation
0.1%
Line UVLO rising threshold
34 V
Line UVLO falling threshold
32 V
Line OVP rising threshold
80 V
Line OVP falling threshold
78 V
Latch threshold
80 V
IAUX(max)
36 V to 75 V
12 V
Maximum load current for auxiliary supply
100 mA
8.2.2 Detailed Design Procedure
The Excel Calculator Tool can be used to assist with selecting both power stage and controller setup
components.
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5036 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Input Transient Protection
The voltage applied to the VIN pin of LM5036 device serves as the input voltage for the internal VCC startup
regulator and auxiliary supply. In typical applications, the VIN pin voltage is the same as the input voltage for the
main half-bridge converter. The recommended range of the VIN pin voltage is 18-V to 100-V. Figure 8-2 shows
the recommended filter to suppress transients that may occur at the input supply. This suppression is particularly
important when the input voltage rises to a level near the maximum recommended operating rating (100-V) of
the LM5036 device.
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VIN
50 Ÿ
VIN
0.1 PF
PGND
Figure 8-2. Input Transient Protection
8.2.2.3 Level-Shift Detection Circuit
An example implementation of the VAUX2 level-shift detection circuit is shown in Figure 8-3. The zener voltage
must be between the off-state and on-state level of VAUX2. When VAUX2 is above the zener voltage, both Q1A
and Q1B are turned on and therefore the reference output voltage VREFSec is clamped to ground. Once VAUX2
falls below the zener voltage, both Q1A and Q1B are turned off, and the reference is released.
Designers who wish to benefit from the fully regulated pre-biased startup feature of LM5036 must use separate
voltage reference and error amplifier devices. Popular combined error amplifier and voltage reference devices,
such as TL431, can be used only when the fully regulated pre-biased startup feature is not required.
Assistance with half-bridge voltage control loop design may be obtained using the Power Stage Designer™ tool.
1.15 k
VREFSec
Q1B
MMDT3946-7-F
VAUX2
10 k
10 k
10 k
Q1A
MMDT3946-7-F
0.01 …F
0.1 …F
GND
Figure 8-3. Secondary Auxiliary Voltage Level-Shift Detection Circuit
8.2.2.4 Applications with VIN > 100-V
For applications where the input voltage exceeds 100-V, all of the 100V-rated internal circuit blocks, including
VCC start-up regulator, auxiliary supply and half-bridge gate drivers, need to be bypassed, or powered from a
reduced voltage. In this case, VIN pin can be powered from an external start-up regulator, as shown in Figure
8-4. If pre-biased start-up is required the integrated flybuck aux circuit should be used from the reduced VIN pin
voltage to supply the secondary control circuit. If pre-biased start-up is not required, the bias supply VAUX1, can
be derived from an external auxiliary supply. An external gate driver with higher voltage rating should be used to
drive the half bridge.
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VIN
VIN
VCC
VAUX1
PGND
PGND
Figure 8-4. External Start-Up Regulator
8.2.2.5 Applications without Pre-Biased Start-Up Requirement
For applications where the pre-biased startup is not required, the level-shift detection circuit described in the
Section 7.3.9 section is not necessary. Without the level-shift detection circuit, the reference voltage on the
secondary side would be released as soon as the secondary bias is established. The external VCC bias supply
can be derived from the integrated auxiliary supply or an auxiliary winding of the main transformer.
8.2.2.6 UVLO Voltage Divider Selection
As described in Section 7.3.2 , two external resistors can be used to program the minimum operating voltage
for the power converter, as shown Figure 8-5. When the UVLO pin voltage falls below VUVLO (1.25-V typical),
an internal current sink IUVLO (20-µA typical) is enabled to lower the voltage at the UVLO pin, thus providing
threshold hysteresis. Resistance values for RUV1 and RUV2 can be determined from Equation 50 and Equation
51.
RUV1
HHYS(UVLO)
IUVLO
(50)
where
•
VHYS(UVLO) is the UVLO hysteresis
RUV2
VIN(on)
VUVLO u RUV1
VUVLO IUVLO u RUV1
(51)
where
•
VIN(on) is the input voltage above which the main converter will start to operate.
Figure 8-6 illustrates one way to configure a latch reset operation by pulling the UVLO pin voltage below VUVLO.
The diode voltage drop must be between 0.35 V and 1.25 V. The controller can be forced to enter shutdown
mode by pulling UVLO pin to GND.
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VIN
RUV1
VIN
RUV1
VUVLO
UVLO
+
UVLO
IUVLO
RUV2
VUVLO
+
IUVLO
LATCH
RESET
RUV2
AGND
VSD
+
Figure 8-5. UVLO Configuration
Figure 8-6. Latch Reset
8.2.2.7 Over Voltage, Latch (ON_OFF Pin) Voltage Divider Selection
As described in Section 7.3.17, the ON_OFF pin can be configured as a latch pin or an OVP pin. Figure 7-20
shows the latch configuration. The ON_OFF pin is latched when the pin voltage reaches IOVL × RL when any of
the internal faults is detected. The latch diode is reverse-biased during latch operation. Select the latch resistor
RL value such that IOVL × RL > VON_OFF. This design example uses an RL value of 49.9 kΩ. If the latch threshold
is 80 V, use an ROV1 value of 40 kΩ, and use an ROV2 value of 710 Ω.
If the ON_OFF pin is configured as an OVP pin, two resistors can be used to program the maximum operating
input voltage for the half-bridge converter, as illustrated in Figure 7-21. When the ON_OFF pin voltage rises
above the VON_OFF threshold, an internal current source IOVL is enabled to raise the ON_OFF pin voltage, thus
providing the threshold hysteresis. Use Equation 29 and Equation 30 to determine resistance values for ROV1
and ROV2. If the LM5036 controller is to be disabled when VIN rises above 80 V and enabled when it falls below
78 V. Use an ROV1 value of 40-kΩ, and an ROV2 value of 635-Ω. The ON_OFF pin can also be used for external
thermal protection with a thermistor.
8.2.2.8 SS Capacitor
The soft-start delay tD(SS) , which is the time it takes for the soft-start capacitor to rise from 0 V to VSSSecEn
(2.06-V typical), can be programmed with the SS capacitor value according to Equation 52
CSS
ISS u tD(SS)
VSS Sec En
(52)
where
•
ISS (20-µA typical) is the current source of the soft-start pin
8.2.2.9 SSSR Capacitor
The SSSR capacitor value determines the rate at which the pulse width of the SRs of the half-bridge converter
increases. To achieve a monotonic start-up for the output voltage, the optimum SSSR capacitor value satisfies
the following two conditions:
• Ensure the SR soft-start sequence is completed before the controller reaches the regulation set-point of the
output voltage.
• With a lower control loop bandwidth, the primary-side duty cycle tends to increase at a slower rate. in order to
prevent excessive reverse current, reduce the ramp-up speed of the SSSR capacitor voltage accordingly.
A general rule is to maintain the control loop bandwidth of the half-bridge converter above 1 kHz. With a slow
control loop bandwidth, the output voltage needs to drop at least 25% from the regulation set-point during
the restart time period where the SS pin voltage rises from 0 V to VSSSecEn (2.06-V typical) and then the
secondary-side reference VREF rises to 75% of regulation set-point. To satisfy the first condition above, maintain
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the rise time of the SSSR capacitor voltage to less than 25% of the rise time of the output voltage, as described
in Equation 53.
CSSSR <
ISSSR × 25% × t RAMP
5V
(53)
where
•
ISSSR (20-µA typical) is the current source of the SSSR pin. tRAMP is the ramp-up time of the output voltage.
Use the SSSR capacitor value calculated from Equation 53 as a starting point. Fine-tuning may be needed
based on the actual control loop design and other specific design requirements such as pre-bias conditions and
loading profile.
8.2.2.10 Half-Bridge Power Stage Design
For a PWM operating frequency of 400kHz applied to the output inductor the oscillator frequency of LM5036
must also be set to 400kHz. The value of resistor RT is obtained using Equation 54.
RT
1
fOSC u 1u 10
10
25 k:
(54)
Maximum effective duty cycle that can be applied to the output inductor is Equation 55.
DMAX
1 tCLK u fOSC
0.974
(55)
Maximum transformer turns ratio that will deliver the required output voltage from minimum input voltage is given
by Equation 56.
NPS(max)
DMAX u VIN(min)
1.46
2 u VO
(56)
For our example design we will opt for a planar transformer with 4 primary turns and 3 secondary turns. The
turns are located in an un-gapped RM7/ILP ferrite core made of 3C95 material. This core has an inductance
factor AL = 4.4-µH/turn2. Hence the actual turns ratio (NPS) and magnetising inductance (LMag) are given by
Equation 57 and Equation 58.
NPS
LMag
NP
NS
4
3
NP2 u AL
(57)
70.4 PH
(58)
Maximum inductor current ripple will occur at maximum input voltage. The output inductor value LO will be
selected to limit inductor current ripple amplitude to 20-% of the maximum output current ILIM
LO
VO u 1 DMIN
20% u 2 u ILIM u fOSC
4.3 PH
(59)
Hence a catalog part with an inductance of 4.7-µH, capable of carrying the full output current, and with a
saturation current of more that 120-% of ILIM, is selected.
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LO
4.7 PH
(60)
8.2.2.11 Current Limit
Section 7.3.11 describes the CBC current limiting functionality in detail. Figure 8-7 illustrates the current limiting
block diagram of the LM5036 controller. These are the five resistors associated with the current limiting function
of the half-bridge converter:
•
•
•
•
•
RCS
R3
R2
RLIM
R1
Because R3 is equal to the equivalent resistance of R1 and R2 as given by Equation 13, there are four unknown
resistor values to be determined.
VIN
IPRI
R2
ISLOPE
R1
CF
RCS
VCS
CS_POS
K10a
+
Amp
1/K10b
R3
K2a
CS_NEG
PGND
POS_OCP
ICS_SET
RLIM
AGND
+
CBC
1/K2b
CS_SET
+
±
NEG
+
NEG_OCP
VLIM
AGND
Figure 8-7. Current Limiting Block
The value of current sense resistor RCS is determined based on the maximum power consumption requirement.
Typically, the current sense resistor should consume less than 0.5% of the input power of the converter at the
worst case scenario. The sense resistor conducts every alternate current pulse flowing in the primary winding.
The power dissipated in the sense resistor is determined by Equation 61.
PCS
IPr i _ RMS2
2
u RCS
(61)
The RMS current flowing in the primary winding may be calculated using Equation 62.
IPr i _ RMS
2
§
IO
1 § 'IPr i · ·¸
u D u ¨1
u¨
¸
NPS
¨ 3 © IO ¹ ¸
©
¹
Where :
'IPr i
48
'ILO
NPS
'ILMag
§1 D ·
VO
u¨
¸
2 u LO u NPS © fOSC ¹
VIN
D
u
4 u LMag fOSC
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Maximum loss in the current sense resistor will occur while maximum output current (ILIM) is delivered from
minimum input voltage (VIN(min)). Evaluating Equation 62 gives Equation 63.
IPr i _ RMS
7.07A
(63)
To achieve our target of dissipating less than 0.5% of maximum output power the current sense resistor must
satisfy Equation 64.
RCS
0.5% u VO u ILIM u
2
IPr i _ RMS2
0.024 :
(64)
In our example design the current sense resistor value selected is given in Equation 65.
RCS
5 m:
(65)
HSG
tON
LSG
tOFF
tOFF
VIN
VSW
VIN/2
tON
ILO/Nps
IO/Nps
4ILO/NPS
4IPri
4ILO/NPS
4IPri
ILMag
0
4ILMag
4ILMag
Ipri
Figure 8-8. Main Converter Operating Waveforms
The resistor R1 is used to set the slope compensation magnitude. In LM5036 device, the slope of the
compensation ramp is given by Equation 66. To eliminate sub-harmonic oscillation, set mC to at least one-half
the down-slope of output inductor current transformed to the primary side across the current sense resistor,
as given by Equation 67 and Equation 68. To damp the sub-harmonic oscillation after one cycle, mC must be
set equal to one times the down-slope of the output inductor current. This configuration is known as deadbeat
control. In LM5036 controller, the slope compensation signal is a saw-tooth current waveform of magnitude
ISLOPE at the oscillator frequency (twice the switching frequency).
mC
ISLOPE u fOSC u R1
(66)
where
•
•
mC is the slope of the compensation ramp
ISLOPE is the amplitude of the saw-tooth current signal used for slope compensation
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VO
1
u
u RCS
LO NPS
mL
9.57
mV
Ps
(67)
where
•
•
•
•
•
•
mL is the down-slope of the output inductor current transformed to the primary side
NP is the number of turns for the primary winding of the main transformer
NS is the number of turns for the secondary winding of the main transformer
VO is the output voltage of the half-bridge converter
LO is the output inductor value of the half-bridge converter
RCS is the current sense resistor value
1
mC > × mL
(68)
2
Substituting Equation 66 and Equation 67 into Equation 68 gives an expression for the minimum value for
resistor R1 to avoid sub-harmonic oscillation.
R1 !
1 VO
1
1
u
u
u RCS u
2 LO NPS
ISLOPE u fOSC
221 :
(69)
Doubling this value ensures deadbeat control. For this example design, the value given in Equation 70 are
selected
R1
576 :
(70)
Values have now been selected for both RCS and R1. Values for RLIM and R2 are yet to be determined. These
values define the peak current limit threshold and how this level varies with input voltage. Equation 20, Equation
21 and Equation 25 define the relationship between peak primary current limit and maximum output current. For
this design example ignore IBiasOffset and V CSOffset, because these parameters have only a small effect on output
current limit. Setting these parameters to zero calculates Equation 71, Equation 72 and Equation 73.
IO VIN,RLIM,R2
ª
NPS u «IPr iCBC VIN,RLIM,R2
¬«
IPr iCBC VIN,RLIM,R2
VCS _ CBCTh (VIN,RLIM,R2 )
RCS
VO
u 1 D
2 u LO u fOSC u NPS
§1 § V
tCSLSG u ¨ u ¨ IN
¨ 2 ¨ LMag
©
©
§K
VCS _ CBCTh (VIN,RLIM,R2 ) R1 u ¨ CBC1 ISLOPE u D
© RLIM
VIN ·
¸
R2 ¹
VO u NPS º
»
2 u LMag u fOSC ¼»
VIN
LO u NPS
2
·
VO ·
¸
¸
¸ LO u NPS ¸
¹
¹
(71)
(72)
(73)
The output current limit varies with input voltage. This design example limits the output current to ILIM at the
extremes of input voltage giving Equation 74 and Equation 75. This value limits the spread of output current limit
across the range of input voltage.
50
IO VIN(min) ,RLIM,R 2
ILIM
IO VIN(max) ,RLIM ,R 2
ILIM
(74)
(75)
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Solving Equation 74 and Equation 75 simultaneously yields values for resistors RLIM and R2.
R2
RLIM
1
§ 1
tCSLSG
RCS
u
u¨
2
R1 u NPS ©¨ LMag
·
¸
2¸
LO u NPS ¹
1
§ VO2
R
1
u CS
¨¨
VIN(min) u VIN(max) © LO u fOSC R1
·
ISLOPE u 2 u VO u NPS ¸
¸
¹
2.32 M:
(76)
KCBC1
RCS ª ILIM
u«
R1 « NPS
¬
§ 2 u VO u NPS ·
VO
u ¨1
¸
2 u LO u NPS u fOSC ¨©
VIN(min) ¹¸
VO u NPS
2 u LMag u fOSC
tCSLSG ª VIN(min)
u«
NPS
¬« 2 u LMag
VIN(min)
2 u LO u NPS2
VO º º
2 u VO u NPS
u
»» I
LO u NPS ¼» » SLOPE
VIN(min)
¼
VIN(min)
55.2 k:
R2
(77)
Having determined values for R1 and R2, the value of resistor R3 is fixed by Equation 13.
The selected values for R2 and RLIM are given in Equation 78. Figure 8-9 presents the measured output current
limit vs input voltage for the circuit presented in Figure 8-1. Figure 8-9 also presents the output current limit
vs line for the same circuit predicted by Equation 71, Equation 72 and Equation 73. There is good agreement
between measured and predicted results.
R2
RLIM
1.96 M:
56.2 k:
(78)
10.2
ILIM Calculated
ILIM Measured
Output Current Limit (A)
10.1
10
9.9
9.8
9.7
9.6
9.5
9.4
9.3
36
41
46
51
56
61
Input Voltage (V)
66
71
76
D002
Figure 8-9. Main Converter Measured vs Predicted Output Current Limit
If the magnitude of the leading-edge spike is excessive, add an additional filter capacitor CF to form an RC filter
with R1, to reduce the high-frequency noise spike. Both the leading-edge blanking (tCSBLK) and the RC filter help
to prevent false triggering of the CBC current limiting operation.
The circuit connected to the CS_POS pin may be approximated by the simplified circuit shown in Figure 8-10.
IPri(t)
IPri(t) x RCS
R1
CS_POS
VCF(t)
RCS
CF
PGND
Figure 8-10. CS_POS Filter Circuit Model and Waveform
The voltage across the current sense resistor during the conduction period of the low-side MOSFET is
represented by Equation 79.
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IPr i t u RCS
IP0
m u t u RCS
(79)
Where IP0 is the primary current at the start of the on period of the lower switch, and m is the slope of the
primary current during the on period.
IO
NPS
IP0
m
'ILMag
§ VIN(max)
¨
© 2 u NPS
'ILO
NPS
(80)
·
1
VO ¸ u
L
u
¹ O NPS
VIN(max)
2 u LMag
(81)
The voltage across capacitor CF for the circuit shown is expressed by Equation 82.
VCF t
t ·
ª
º
§
CF uR1 ¸
«
»
¨
RCS u IP0 m u CF u R1 u 1 e
mut
«
»
¨¨
¸¸
«¬
©
¹
¼»
(82)
Let us assume that the on period of the lower switch is more than four times longer than the time constant made
up of CF and R1. In this case the exponential term of Equation 82 tends to zero and the voltage across capacitor
CF at the end of the tON period may be expressed by Equation 83.
VCF tON
RCS u >IP0
m u CF u R1 m u tON @
(83)
Comparing Equation 79 and Equation 83 shows that capacitor CF introduces an error in the sensed peak current
given by Equation 84.
ErrCF
VCS tON VCF tON
ILIM
u RCS
NPS
m u CF u R1
ILIM
NPS
ª§ VIN(max)
Ǭ
«¬© 2 u NPS
·
1
VO ¸ u
¹ LO u NPS
ILIM
NPS
VIN(max) º
» u CF u R1
2 u LMag »¼
(84)
Hence, to ensure the error introduced by the filter capacitor is less than 2%, the value of capacitor CF should not
exceed the value given by Equation 85.
CF d
0.02 u ILIM
ª§ VIN(max)
Ǭ
«¬© 2 u NPS
·
1
VO ¸ u
¹ LO u NPS
VIN(max) º
» u R1 u NPS
2 u LMag »¼
84 pF
(85)
The Excel Calculator Tool can be used to facilitate the process of calculating all the external CBC component
values.
8.2.2.12 Auxiliary Transformer
A coupled inductor or a flyback-type transformer is required for this fly-buck topology auxiliary supply. Energy is
transferred from primary to secondary when the low-side SR MOSFET is conducting.
The transformer turns ratio is selected based on the ratio of the primary output voltage to the secondary output
voltage. In this design example, the two outputs are set to be equal and a 1:1 turns ratio transformer is selected,
i.e., N2/N1 = 1. The primary output voltage is normally selected based on the input voltage range such that the
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duty cycle of the converter does not exceed 50% at the minimum input voltage. This condition is satisfied if
VAUX1 < VIN(min) / 2.
Use Equation 86 to calculate the maximum inductor current ripple amplitude ΔIL (AUX) that can be tolerated
without exceeding the peak current limit threshold IAUX(LIM) (200-mA typical) of the high-side switch,
'IL(AUX)
§
N2 ·
¨ IAUX(LIM) IAUX1 IAUX2 u
¸
N1 ¹
©
(86)
where
•
IAUX1 is the primary output current, and IAUX2 is the secondary output current of the auxiliary supply,
respectively.
In this design example, the maximum total output current IAUX(max) of the auxiliary supply referred to the primary
side is 100-mA, as given by Equation 87.
IAUX (max ) = IAUX1 + IAUX2 ×
N2
= 0.1 A
N1
(87)
Therefore, ΔIL(AUX) = 0.1-A. Use Equation 88 to calculate the minimum inductor value for the auxiliary supply.
L AUX t
KON u RON §
VAUX1 ·
u ¨1
¸
2 u 'IL(AUX) ¨©
VIN(max) ¸¹
88 PH
(88)
Select a higher value of 150-µH to ensure the high-side switch current doesn’t exceed the minimum peak current
limit threshold.
8.2.2.13 Auxiliary Feedback Resistors
The two feedback resistors are selected to set the primary output voltage VAUX1 of the auxiliary supply. The
internal reference for the off-state and on-state auxiliary output voltage levels are VAUX-OFF (1.4-V typical) and
VAUX-ON (1-V typical). The feedback resistors are calculated such that both of the off-state and on-state auxiliary
output voltage fall into the recommended operating range (8.5-V to 14-V). In this design example, the off-state
and on-state auxiliary output voltages are set to 11.9-V and 8.5-V, respectively. RFB2 is selected to be 1-kΩ and
RFB1 is calculated to be 7.5-kΩ according to Equation 89. Note that it is the valley of the output voltage that is
regulated at the reference value. Therefore the average output voltage is greater than the reference value due to
the ripple injected to the feedback node.
VAUX1
ON
VAUX
ON
§
RFB1 ·
u ¨1
¸
© RFB2 ¹
(89)
8.2.2.14 RON Resistor
Use Equation 31 to calculate the value of RON required to achieve the desired switching frequency for the
auxiliary supply. Make sure that the calculated RON value is greater than the minimum value required by
Equation 40. For this design example where on-state VAUX1 is 8.5-V and target fSW_AUX is 500-kHz, the
calculated value of RON is 189-kΩ. The minimum recommended value calculated using Equation 40 is 209-kΩ.
A standard value of 220-kΩ is selected to satisfy this minimum RON requirement giving and actual switching
frequency (fSW_AUX) of 430-kHz.
8.2.2.15 VIN Pin Capacitor
Place the required bypass capacitor close to the VIN pin of the LM5036 device. Ensure that the capacitance is
large enough to limit the ripple of the VIN pin voltage to a desired level. Use Equation 90 to calculate the value of
CIN required to meet the ripple voltage ∆VIN requirement.
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CIN R
IAUX :max ;
4 × fSW _AUX × ¿VIN
(90)
Choosing a value of 0.5-V for ∆VIN yields a minimum CIN value of 0.12-µF. Select the standard value of 0.1-µF
for this design. Ensure that the voltage rating of the input capacitor is greater than the maximum input voltage
under all conditions.
8.2.2.16 Auxiliary Primary Output Capacitor
The output capacitor value (CAUX1), needed to achieve our target output ripple amplitude (ΔVAUX1Cap = 25-mV),
may be calculated using Equation 94.Highest ripple voltage will be observed if all the Aux current is drawn
from VAUX2 (IAUX2=IAUX(max)). In this case a capacitor value of 1.1-µF is required to limit capacitive ripple voltage
amplitude to 25-mV. A standard 1-µF, 25-V capacitor is selected for this design.
8.2.2.17 Auxiliary Secondary Output Capacitor
A simplified waveform for the secondary winding current IL_SEC is shown in Figure 8-11.
IL_SEC
IAUX2
0A
Time
Figure 8-11. Auxiliary Transformer Secondary Winding Current Waveforms for CAUX2 Ripple Calculation
The secondary output current IAUX2 is sourced by CAUX2 during on-time of the high-side switch, tON. Ignoring the
current transition times in the secondary winding, the secondary output capacitor ripple voltage amplitude can be
calculated using Equation 91.
'VAUX2Cap
IAUX2 u tON(max)
2 u C AUX2
(91)
For a 1:1 auxiliary transformer turns ratio, the primary and secondary voltage ripple equations are identical.
Therefore, CAUX2 is chosen to be equal to CAUX1 (1 µF) to achieve comparable ripple voltages on the primary
and secondary outputs.
8.2.2.18 Auxiliary Feedback Ripple Circuit
The auxiliary feedback ripple circuit employed is presented in Figure 7-27. Having selected appropriate values
for RON in Section 8.2.2.14 and RFBx in Section 8.2.2.13, the value of Cr required can be calculated using
Equation 47. For our design we have opted to use a standard value Cr = 1-nF.
Cr !
R
RFB2
3
u FB1
2 u S u fSW _ AUX RFB1 u RFB2
1.3 nF
(92)
Based on our target output ripple specification a value for the primary output capacitor (CAUX1 = 1-µF) was
chosen in Section 8.2.2.16. The primary output ripple voltage VAUX1Cap can be calculated using Equation 94.
54
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Since the value of VAUX1Cap is already greater than 25-mV there is no danger that we will fail to meet the
requirement of Equation 46. Hence the value of Rr needed to ensure stable operation is calculated using
Equation 48. For our design example a value of 46.4-kΩ has been selected.
Rr d
§
K ON u RON
VAUX1 ·
u ¨1
¸
10 u Cr u 'VAUX1Cap ¨©
VIN(min) ¸¹
55 k:
(93)
The minimum value of Cac is determined using Equation 49. The precise value of this component is not very
critical and for our design example we selected a convenient value of Cac = 100-nF.
Cac t 5 u Cr
5 nF
(94)
8.2.2.19 Auxiliary Secondary Diode
Use Equation 95 to calculate the reverse voltage across secondary rectifier of the auxiliary supply when the
high-side switch is on.
VD =
N2
× VIN(max )
N1
(95)
For a maximum input voltage of 75-V and the 1:1 turns ratio of this design, select a schottky diode with a rating
of 75-V or higher.
8.2.2.20 VCC Diode
A diode must be connected between the primary output VAUX1 and the VCC pin. When VAUX1 is more than one
diode voltage drop greater than the internal VCC voltage, the VCC bias current is supplied from VAUX1. This
results in reduced power losses in the internal VCC regulator, especially at high input voltage.
8.2.2.21 Opto-Coupler Interface
Figure 8-12 illustrates the opto-coupler interface for the main feedback control loop. The primary side of the
opto-coupler is biased with VREF voltage from LM5036 device. ROPTO should be selected such that with the
minimum error amplifier output, the comp current flowing into the COMP pin of the device is greater than IPWM-OS
(800-µA typical) which corresponds to zero duty cycle, as given by Equation 96.
Vb
VREF
COMP
ROPTO
VO
Ve
+
VREFSec
SGND
Figure 8-12. Opto-Coupler Interface
ICOMP
Vb
Vf Ve
u CTR
Ropto
(96)
where
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•
•
•
•
•
•
Vb is the bias supply for the error amplifier and opto-coupler on the secondary side
Vf is the diode forward voltage drop of the opto-coupler LED
Ve is the error amplifier output
CTR is the current transfer ratio of the opto-coupler
ICOMP is the comp current flowing into the COMP pin
VREF (5-V typical) is the reference of LM5036 device
8.2.2.22 Full-Bridge Converter Applications
While LM5036 device is optimized for half-bridge applications, it can also be used for full-bridge applications.
External gate drivers are needed to support an additional pair of FETs in full-bridge configuration. In addition,
a DC-blocking capacitor is required to ensure voltage-second balance of the main transformer with the voltagemode control of LM5036 device. Only one phase current information is needed for current protection in the
full-bridge applications.
8.2.3 Application Curves
100%
95%
90%
Efficiency
85%
80%
75%
70%
65%
60%
VIN = 36 V
VIN = 48 V
VIN = 75 V
55%
50%
0
1
2
3
4
5
Load Current (A)
fSW = 200-kHz
VO= 12 V
Figure 8-13. Efficiency
6
7
8
D001
VIN = 48-V
IO = 8-A
VO = 12-V
Figure 8-14. Steady State Operation Waveform
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9 Power Supply Recommendations
The power converter controlled by LM5036 device can have considerable current level. Care should be
taken that components with the correct current rating are chosen. This includes magnetic components, power
MOSFETS and diodes, connectors and wire sizes. Input and output capacitors should have the correct ripple
current rating.
The recommended maximum input voltage for the VIN pin of LM5036 device is 100-V. The recommended
voltage for the VCC pin is between 8.5-V and 14-V. Both VCC pin and REF pin must be locally decoupled with
a ceramic capacitor. The recommended range of values is 0.47-µF to 10-µF for VCC pin, and 0.1-µF to 10-µF
for REF pin. To reduce the power consumption of the internal VCC regulator, an external bias supply can be
connected to VCC pin through a diode.
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10 Layout
10.1 Layout Guidelines
•
The two ground planes (AGND and PGND) of LM5036 device should be tied together with a short and
direct connection to avoid jitter due to relative ground bounce. The connection point could be at the negative
terminal of the input power supply.
•
The VIN, VCC, REF pin capacitors, and CS_NEG resistor should be tied to PGND plane. UVLO, ON_OFF,
RT, RON, RD1 and RD2 resistors, RAMP, RES, SS and SSSR capacitors, and the thermal pad should all be
tied to AGND plane.
•
SW and SW_AUX are switching nodes which switch rapidly between VIN and GND every cycle which are
sources of high dv/dt noise. Therefore, large SW/SW_AUX node area should be avoided.
•
The differential current sense signals at CS_POS and CS_NEG pins should be routed in parallel and close to
each other to minimize the common-mode noise.
•
The area of the loop formed by the main feedback control signal traces (COMP and REF) should be
minimized in order to reduce the noise pick up. This can be accomplished by placing the COMP and REF
signal traces on top of each other in adjacent PCB layers. In addition, the main feedback control signal traces
should be routed away from the SW_AUX switching node to avoid high dv/dt noise coupling.
•
The gate drive outputs (LSG and HSG) should have short and direct paths to the power MOSFETs to
minimize parasitic inductance in the gate driving loop.
•
The VCC and REF decoupling capacitors should be placed close to their respective pins with short trace
inductance. Low ESR and ESL ceramic capacitors are recommended for the boot-strap, VCC and the REF
capacitors.
•
A decoupling capacitor should be placed close to the IC, directly across VIN and PGND pins. The
connections to these two pins should be direct to minimize the loop area which carries switching currents.
•
The boot-strap capacitors required for the high-side gate drivers of the half-bridge converter and auxiliary
supply should be located close to the IC and connected directly to the BST/BST_AUX and SW/SW_AUX
pins.
•
The area of the switching loop of the power stage consisting of input capacitor, capacitive divider,
transformer, and the primary MOSFETs should be minimized.
10.2 Layout Example
See Figure 10-1 for an example layout that matches the schematic of Figure 8-1.
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Figure 10-1. LM5036 PCB Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5036 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
11.2.1.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
60
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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17-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM5036RJBR
ACTIVE
WQFN
RJB
28
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LM5036
LM5036RJBT
ACTIVE
WQFN
RJB
28
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LM5036
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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