LM5109A
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SNVS412A – APRIL 2006 – REVISED MARCH 2013
LM5109A High Voltage 1A Peak Half Bridge Gate Driver
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FEATURES
DESCRIPTION
•
The LM5109A is a cost effective, high voltage gate
driver designed to drive both the high-side and the
low-side N-Channel MOSFETs in a synchronous
buck or a half bridge configuration. The floating highside driver is capable of working with rail voltages up
to 90V. The outputs are independently controlled with
TTL compatible input thresholds. The robust level
shift technology operates at high speed while
consuming low power and providing clean level
transitions from the control input logic to the high-side
gate driver. Under-voltage lockout is provided on both
the low-side and the high-side power rails. The
device is available in the SOIC and the thermally
enhanced WSON packages.
1
2
•
•
•
•
•
•
•
•
•
Drives Both a High-Side and Low-Side NChannel MOSFET
1A peak Output Current (1.0A Sink / 1.0A
Source)
Independent TTL Compatible Inputs
Bootstrap Supply Voltage to 108V DC
Fast Propagation Times (30 ns Typical)
Drives 1000 pF Load with 15ns Rise and Fall
Times
Excellent Propagation Delay Matching (2 ns
Typical)
Supply Rail Under-Voltage Lockout
Low Power Consumption
Pin Compatible with ISL6700
TYPICAL APPLICATIONS
•
•
•
•
Package
•
•
SOIC
WSON-8 (4 mm x 4 mm)
Current Fed Push-Pull Converters
Half and Full Bridge Power Converters
Solid State Motor Drives
Two Switch Forward Power Converters
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LM5109A
SNVS412A – APRIL 2006 – REVISED MARCH 2013
www.ti.com
Simplified Block Diagram
VDD
HV
HB
HO
DRIVER
LEVEL
SHIFT
UVLO
HS
HI
VDD
UVLO
LO
DRIVER
LI
VSS
Connection Diagrams
VDD
1
8
HB
VDD
1
8
HB
HI
2
7
HO
HI
2
7
HO
LI
3
6
HS
LI
3
6
HS
VSS
4
5
LO
VSS
4
5
LO
Figure 1. 8-Lead SOIC
See D Package
Figure 2. 8-Lead WSON
See NGT0008A Package
PIN DESCRIPTIONS
Pin #
(1)
2
NAME
DESCRIPTION
APPLICATION INFORMATION
SOIC
WSON (1)
1
1
VDD
Positive gate drive supply
Locally decouple to VSS using low ESR/ESL capacitor located as
close to IC as possible.
2
2
HI
High side control input
The HI input is compatible with TTL input thresholds. Unused HI input
should be tied to ground and not left open
3
3
LI
Low side control input
The LI input is compatible with TTL input thresholds. Unused LI input
should be tied to ground and not left open.
4
4
VSS
Ground reference
All signals are referenced to this ground.
5
5
LO
Low side gate driver output
Connect to the gate of the low-side N- MOS device.
6
6
HS
High side source connection
Connect to the negative terminal of the bootstrap capacitor and to the
source of the high-side N-MOS device.
7
7
HO
High side gate driver output
Connect to the gate of the high-side N-MOS device.
For WSON package it is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PCB
and the ground plane should extend out from underneath the package to improve heat dissipation.
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PIN DESCRIPTIONS (continued)
Pin #
SOIC
WSON (1)
8
8
NAME
HB
DESCRIPTION
High side gate driver positive
supply rail
APPLICATION INFORMATION
Connect the positive terminal of the bootstrap capacitor to HB and
the negative terminal of the bootstrap capacitor to HS. The bootstrap
capacitor should be placed as close to IC as possible.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
VDD to VSS
–0.3V to 18V
HB to HS
−0.3V to 18V
−0.3V to VDD + 0.3V
LI or HI to VSS
LO to VSS
−0.3V to VDD + 0.3V
HO to VSS
VHS − 0.3V to VHB + 0.3V
HS to VSS (3)
−5V to 90V
HB to VSS
108V
Junction Temperature
–40°C to 150°C
Storage Temperature Range
−55°C to 150°C
ESD Rating HBM
(1)
(2)
(3)
(4)
(4)
1.5 kV
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see the Electrical Characteristics .
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed –1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15V. For example, if
VDD = 10V, the negative transients at HS must not exceed –5V.
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.
Recommended Operating Conditions
VDD
8V to 14V
HS (1)
−1V to 90V
HB
VHS + 8V to VHS + 14V
HS Slew Rate
< 50 V/ns
−40°C to 125°C
Junction Temperature
(1)
In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed –1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15V. For example, if
VDD = 10V, the negative transients at HS must not exceed –5V.
Electrical Characteristics
Specifications in standard typeface are for TJ = 25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (1).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
0.3
0.6
mA
Supply Currents
IDD
VDD quiescent current
LI = HI = 0V
IDDO
VDD operating current
f = 500 kHz
1.8
2.9
mA
IHB
Total HB quiescent current
LI = HI = 0V
0.06
0.2
mA
IHBO
Total HB operating current
f = 500 kHz
1.4
2.8
mA
(1)
Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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Electrical Characteristics (continued)
Specifications in standard typeface are for TJ = 25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO(1).
TYP
MAX
UNIT
IHBS
SYMBOL
HB to VSS current, quiescent
PARAMETER
VHS = VHB = 90V
CONDITIONS
MIN
0.1
10
µA
IHBSO
HB to VSS current, operating
f = 500 kHz
0.5
mA
Input Pins LI and HI
VIL
Low-level input voltage threshold
VIH
High-level input voltage threshold
RI
Input pulldown resistance
0.8
1.8
V
1.8
2.2
V
100
200
500
kΩ
VDDR = VDD – VSS
6.0
6.7
7.4
V
VHBR = VHB – VHS
5.7
Under-Voltage Protection
VDDR
VDD rising threshold
VDDH
VDD threshold hysteresis
VHBR
HB rising threshold
VHBH
HB threshold hysteresis
0.5
V
6.6
7.1
V
0.4
V
LO Gate Driver
VOLL
Low-level output voltage
ILO = 100 mA, VOHL = VLO – VSS
0.38
0.65
V
VOHL
High-level output voltage
ILO = −100 mA, VOHL = VDD – VLO
0.72
1.20
V
IOHL
Peak pullup current
VLO = 0V
1.0
A
IOLL
Peak pulldown current
VLO = 12V
1.0
A
HO Gate Driver
VOLH
Low-level output voltage
IHO = 100 mA, VOLH = VHO – VHS
0.38
0.65
V
VOHH
High-level output voltage
IHO = −100 mA, VOHH = VHB – VHO
0.72
1.20
V
IOHH
Peak pullup current
VHO = 0V
1.0
A
IOLH
Peak pulldown current
VHO = 12V
1.0
A
SOIC (2) (3)
160
WSON (2) (3)
40
Thermal Resistance
θJA
(2)
(3)
Junction to ambient
°C/W
4-layer board with Cu finished thicknesses 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm
ground and power planes embedded in PCB. See Application Note AN-1187.
The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions.
Switching Characteristics
Specifications in standard typeface are for TJ = 25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
LM5109A
tLPHL
Lower turn-off propagation delay
(LI falling to LO falling)
30
56
ns
tHPHL
Upper turn-off propagation delay
(HI falling to HO falling)
30
56
ns
tLPLH
Lower turn-on propagation delay
(LI rising to LO rising)
32
56
ns
tHPLH
Upper turn-on propagation delay
(HI rising to HO rising)
32
56
ns
tMON
Delay matching: lower turn-on and upper
turn-off
2
15
ns
tMOFF
Delay matching: lower turn-off and upper
turn-on
2
15
ns
tRC, tFC
Either output rise or fall time
15
-
ns
tPW
Minimum input pulse width that changes
the output
4
CL = 1000 pF
50
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ns
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Typical Performance Characteristics
VDD Operating Current vs Frequency
100
HB Operating Current vs Frequency
100
VDD = VHB = 12V
VDD = VHB = 12V
VSS = VHS = 0V
VSS = VHS = 0V
10
10
IDDO (mA)
CL = 2200 pF
IDDO (mA)
CL = 1000 pF
CL = 1000 pF
CL = 4400 pF
CL = 2200 pF
CL = 4400 pF
1
1
CL = 0 pF
0.1
CL = 0 pF
CL = 470 pF
CL = 470 pF
0.1
0.01
1
10
100
1000
1
10
FREQUENCY (kHz)
100
1000
FREQUENCY (kHz)
Figure 3.
Figure 4.
Operating Current vs Temperature
Quiescent Current vs Temperature
0.45
2.2
0.40
IDDO
0.35
CL = 0 pF
f = 500 kHz
1.8
IDD, IHB (mA)
IDDO, IHBO (mA)
2.0
VDD = VHB = 12V
1.6
VSS = VHS = 0V
1.4
IHBO
IDDO
0.30
0.25 LI = HI = 0V
VDD = VHB = 12V
0.20
VSS = VHS = 0V
0.15
0.10
1.2
IHBO
0.05
0.00
-40 -25 -10 5 20 35 50 65 80 95 110 125
1.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (oC)
TEMPERATURE (°C)
Figure 5.
Figure 6.
Quiescent Current vs Voltage
Propagation Delay vs Temperature
600
44
CL = 0 pF
VDD = VHB
VDD = VHB = 12V
CURRENT (PA)
VSS= VHS = 0V
PROPAGATION DELAY (ns)
500
LI = HI = 0V
IDD
400
300
200
IHB
100
0
8
10
12
14
16
18
40
tLPHL
tHPHL
VSS = VHS = 0V
36
turn off
32
tHPLH
28
24
tLPLH
turn on
20
-40 -25 -10 5 20 35 50 65 80 95 110 125
VDD, VHB (V)
TEMPERATURE (oC)
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
LO and HO High Level Output Voltage
vs Temperature
LO and HO Low Level Output Voltage
vs Temperature
0.6
1.6
Output Current : -100 mA
VSS = VHS = 0V
Output Current : -100 mA
1.4
VSS = VHS = 0V
0.5
1.2
VDD = VHB = 8V
1.0
VOL (V)
VOH (V)
VDD = VHB = 8V
0.8
0.4
VDD = VHB = 12V
0.6
VDD = VHB = 12V
0.4
0.2
0.3
VDD = VHB = 16V
VDD = VHB = 16V
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
0.2
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9.
Figure 10.
Undervoltage Rising Thresholds vs Temperature
THRESHOLD (V)
6.9
VDDR = VDD - VSS
0.48
VHBR = VHB - VHS
0.46
HYSTERESIS (V)
7.0
Undervoltage Hysteresis vs Temperature
0.50
6.8
VDDR
6.7
VHBR
6.6
VDDH
0.44
0.42
0.40
0.38
VHBH
0.36
6.5
0.34
6.4
0.32
0.30
-40 -25 -10 5 20 35 50 65 80 95 110 125
6.3
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (oC)
TEMPERATURE (oC)
Figure 11.
Figure 12.
Input Thresholds vs Temperature
Input Thresholds vs Supply Voltage
1.92
VDD = 12V
1.95
INPUT THRESHOLD VOLTAGE (V)
INPUT THRESHOLD VOLTAGE (V)
2.00
VSS = 0V
Rising
1.90
1.85
Falling
1.80
1.75
1.91
1.89
1.88
1.87
1.86
1.85
Falling
1.84
1.83
1.82
1.81
1.70
1.80
-40 -25 -10 5 20 35 50 65 80 95 110 125
8
9
10
11
12
13
14
15
16
VDD (V)
o
TEMPERATURE ( C)
Figure 13.
6
Rising
1.90
Figure 14.
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SNVS412A – APRIL 2006 – REVISED MARCH 2013
Timing Diagram
LI
LI
HI
tHPLH
tLPLH
HI
tHPHL
tLPHL
LO
LO
HO
HO
tMON
tMOFF
Figure 15.
Layout Considerations
Optimum performance of high and low-side gate drivers cannot be achieved without taking due considerations
during circuit board layout. The following points are emphasized:
1. Low ESR / ESL capacitors must be connected close to the IC between VDD and VSS pins and between HB
and HS pins to support high peak currents being drawn from VDD and HB during the turn-on of the external
MOSFETs.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a
good quality ceramic capacitor must be connected between the MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between
the top MOSFET source and the of the bottom MOSFET drain (synchronous rectifier) must be minimized.
4. Grounding considerations:
– The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gates to a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminals of the MOSFETs. The gate driver should be placed as close
as possible to the MOSFETs.
– The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap
diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The
bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground
referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak
current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.
HS Transient Voltages Below Ground
The HS node will always be clamped by the body diode of the lower external FET. In some situations, board
resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS
node can swing below ground provided:
1. HS must always be at a lower potential than HO. Pulling HO more than –0.3V below HS can activate
parasitic transistors resulting in excessive current flow from the HB supply, possibly resulting in damage to
the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed
externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must
be placed as close to the IC pins as possible in order to be effective.
2. HB to HS operating voltage should be 15V or less. Hence, if the HS pin transient voltage is –5V, VDD should
be ideally limited to 10V to keep HB to HS below 15V.
3. Low ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation. The
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capacitor should be located at the leads of the IC to minimize series inductance. The peak currents from LO
and HO can be quite large. Any series inductances with the bypass capacitor will cause voltage ringing at the
leads of the IC which must be avoided for reliable operation.
8
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SNVS412A – APRIL 2006 – REVISED MARCH 2013
REVISION HISTORY
Changes from Original (March 2013) to Revision A
•
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 7
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
LM5109AMA
ACTIVE
SOIC
D
8
LM5109AMA/NOPB
ACTIVE
SOIC
D
8
LM5109AMAX
ACTIVE
SOIC
D
8
LM5109AMAX/NOPB
ACTIVE
SOIC
D
8
LM5109ASD
ACTIVE
WSON
NGT
LM5109ASD/NOPB
ACTIVE
WSON
LM5109ASDX
ACTIVE
LM5109ASDX/NOPB
ACTIVE
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
TBD
Call TI
Call TI
-40 to 125
L5109
AMA
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5109
AMA
TBD
Call TI
Call TI
-40 to 125
L5109
AMA
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5109
AMA
8
1000
TBD
Call TI
Call TI
-40 to 125
5109ASD
NGT
8
1000
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 125
5109ASD
WSON
NGT
8
TBD
Call TI
Call TI
-40 to 125
5109ASD
WSON
NGT
8
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 125
5109ASD
95
4500
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Sep-2013
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM5109AMAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM5109ASD
WSON
NGT
8
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM5109ASD/NOPB
WSON
NGT
8
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
LM5109ASDX/NOPB
WSON
NGT
8
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5109AMAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM5109ASD
WSON
NGT
8
1000
210.0
185.0
35.0
LM5109ASD/NOPB
WSON
NGT
8
1000
210.0
185.0
35.0
LM5109ASDX/NOPB
WSON
NGT
8
4500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
NGT0008A
SDC08A (Rev A)
www.ti.com
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Applications
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Amplifiers
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www.ti.com/communications
Data Converters
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Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
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www.ti.com/consumer-apps
DSP
dsp.ti.com
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www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
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Interface
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Medical
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Logic
logic.ti.com
Security
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Power Mgmt
power.ti.com
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www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
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