LM5115EVAL

User's Guide SNVA107A – April 2005 – Revised April 2013 AN–1368 LM5115/5025A Evaluation Board 1 Introduction The LM5115/LM5025A evaluation board provides the design engineer with a secondary side post regulated (SSPR) output from an existing Active Clamp Forward topology. Information on the LM5025A active clamp evaluation board can be found in AN-1345 LM5025A Evaluation Board User's Guide (SNVA097). Note that other types of isolated power converters (for example, push-pull, half-bridge, and full-bridge) can be used in the place of the LM5025A active clamp forward converter to drive the LM5115 AC evaluation board. The evaluation board specifications are: • Input voltage: 36V to 72V, 48V nominal on LM5025A • Output voltage Main: 3.3V nominal • Output current Main: 0 to 30A • Current limit Main: ≊30A • Output voltage Secondary: 2V • Output current Secondary: 0 to 9A • Current limit Secondary: ≊9A • Measured efficiency on secondary only: 98% at 36V, Iload = 1A, 93% at 48V, Iload = 4A • Load regulation: 2mV change from 1A-7A, 36V < Vin < 72V • Size: 2.0 × 1.125 × 0.375 inches The printed circuit board consists of 4 layers of 2 oz copper on FR4 material, with a thickness of 0.050 in. It is designed for continuous operation at rated load with a minimum airflow of 200 LFPM. 2 Theory of Operation The LM5115 controller contains all of the features necessary to implement multiple output power converters utilizing the Secondary Side Post Regulation (SSPR) technique. The SSPR technique develops a highly efficient and well regulated auxiliary output from the secondary side switching waveform of an isolated power converter. Synchronization of the LM5115 comes from the main pulsed signal of the transformer secondary winding. Resistor R2 and R4 sense the pulsing signal to form an internal synchronization signal and an internal current to charge the RAMP of the LM5115. The LM5115 controls the buck power stage with leading edge pulse width modulation (PWM) to hold off the high side driver until the necessary volt*seconds is established for regulation. Representative waveforms are shown in Section 10. Bias to the part comes from a rectified pulse signal. Note that the pulse signals vary from 6Vpp to 12Vpp, with Vin varying from 36V to 72V, respectively. Therefore, the VCC regulator will not regulate at 7V until the peak to peak voltage is slightly higher than 7.5V (accounting for the diode drop to the bias). The intention was to show that with non-regulation on VCC the LM5115 is still capable of providing the secondary voltage of 2V from the main 3.3V. Adaptive deadtime control delays the top and bottom drivers to avoid shoot through currents (Figure 7 and Figure 8). All trademarks are the property of their respective owners. SNVA107A – April 2005 – Revised April 2013 Submit Documentation Feedback AN–1368 LM5115/5025A Evaluation Board Copyright © 2005–2013, Texas Instruments Incorporated 1 Board Layout and Probing 3 www.ti.com Board Layout and Probing Figure 1, Figure 2, and Figure 3 show the board layout, main components, and critical probe points for testing the LM5115 AC mode evaluation board in conjunction with the LM5025A board. The following notes should be considered prior to applying power to the board: 1. Main input power (36V to 72V) is applied to points J1 and J4 of the LM5025A board, connected to VIN and GND, respectively. 2. The main current carrying components (LM5115 board: L1, Q1, and Q2; LM5025A board L2, Q3-Q6) will be hot to the touch at maximum load current. USE CAUTION. When operating at load currents in excess of 5A, the use of a fan to provide forced air flow is necessary. 3. The diameter and length of the wire used to connect the load is important. To ensure that there is not a significant voltage drop in the wires, a minimum of 14 gauge wire is recommended. NATIONAL SEMICONDUCTOR LM5115 AC EVALUATION BOARD L1 P/N 551012239-001 R10 Q1 + D4 G Connect to 5025 Main Transformer Secondary Winding J1 to J7 and J2 to J10 S G J1 (+) D + R7 R8 R9 D J3 (+) S - C3 R1 D2 C C GND C2 C7 C11 GND U1 C1 C13 C5 R4 R2 D1 +OUTPUT- R5 C - +OUT +OUT Q2 C12 J2 (-) J4 (-) C4 R13 R12 C8 Top Side Bottom Side Figure 1. LM5115 Evaluation Board 2 AN–1368 LM5115/5025A Evaluation Board Copyright © 2005–2013, Texas Instruments Incorporated SNVA107A – April 2005 – Revised April 2013 Submit Documentation Feedback Board Layout and Probing www.ti.com NATIONAL SEMICONDUCTOR P/N 551012240-001 REV C LM5025A EVALUATION BOARD L1 IN(+) J1 C19 D3 OUT(+) J9 J8 C11 R11 C22 L2 3.3V +OUTPUT- 36V to 72V -INPUT+ J2 T2 J3 J6 C21 T1 U4 R14 R9 C9 R8 D4 J4 C10 C8 U2 R12 IN(-) U1 C31 C32 R18 OUT(-) R35 U3 R15 C14 J5 R36 C20 R32 R30 R28 C12 C33 R2 R13 TP1 VCC C13 R33 TP4 SB C29 Figure 2. LM5025A Evaluation Board Top Side C1 R1 IN(+) C2 C17 J10 S D5 R10 S G Q5 J7 R22 Q2 R17 D R20 D C23 G Q6 S D2 D S G C25 Q1 R16 C5 C6 OUT(-) R27 R3 R7 Cut C27 D8 R4 C7 R31 R26 C16 C24 C15 3.3V -OUTPUT+ C18 D26 36V to 72V -INPUT+ G R24 C4 S R19 Q3 G R25 D Q4 C3 D R21 R23 OUT(+) IN(-) R5 R34 D7 O ohm C30 Figure 3. LM5025A Evaluation Board Bottom Side SNVA107A – April 2005 – Revised April 2013 Submit Documentation Feedback AN–1368 LM5115/5025A Evaluation Board Copyright © 2005–2013, Texas Instruments Incorporated 3 Board Connections/Start-Up 4 www.ti.com Board Connections/Start-Up The input power connections are made to terminals J1 (+) and J4 (-) of the LM5025A evaluation board. The input source must be capable of supplying the load on both the output of the LM5025A board and LM5115 board. The input to the LM5115 is supplied by the secondary winding of the LM5025A board. J7 (LM5025A) connects to J1 (LM5115) and J10 (LM5025A) connects to J2 (LM5115) (see Figure 1, Figure 2, and Figure 3). The main load is connected to terminals J9 (+) and J5 (-) for the LM5025. Terminals J3 (+) and J4 (-) are the load connections for the LM5115. Before start-up, a voltmeter should be connected to the input terminals and to the output terminals. The input current should be monitored with an ammeter or a current probe. Soft-start provided by the LM5115 will insure that the output rises with a smooth turn on without overshoot (Figure 12). The LM5115 evaluation board will operate in the continuous conduction mode even with a light or no load (Figure 4). 5 Performance LM5115 Secondary Side Post Regulator Performance of the LM5115 evaluation board can be seen in the following figures: 1. Power Conversion Efficiency (Figure 5 and Figure 6) 2. Gate Delays (Figure 7 and Figure 8) 3. Short circuit response (Figure 9) 4. Step Load Response (Figure 10 and Figure 11) 5. Startup and Shutdown Response (Figure 12 and Figure 13) 6. Ripple Voltage (Figure 14) 7. Load Regulation (Figure 15) 8. Secondary Closed Loop Frequency Response (Figure 16) 6 VCC The LM5115 produces a LDO 7V regulated output (VCC) that can supply up to 40mA of DC current. The VCC regulator supplies power for the high current gate drive for the low side MOSFET and the bootstrap capacitor of the high side MOSFET driver. 7 Current Limit Operation Inductor current is sensed through the parallel resistances of R7, R8, and R9. The resistor values are designed for a current limit of ~9A. Current limiting occurs when the delta voltage across the sense resistor exceeds 45mV causing the current sense amplifier to pull down the combined CO and COMP pins. Pulling COMP low reduces the width of pulses to the high side driver, limiting the output current of the converter. After reaching the current limit, the voltage feedback causes the COMP pin to rise and turn on the high side driver until the inductor current again reaches the ~9A current limit threshold. (Figure 9). The parallel resistance also serves to inject the inductor current into the LM5115 feedback loop. Injecting a signal proportional to the instantaneous inductor current into a voltage mode controller improves the control loop stability and bandwidth. Current injection, which is a form of average current mode control, eliminates the lead R-C network in the feedback path that is normally required with voltage mode control. This not only simplifies the compensation but also reduces sensitivity to output noise that could pass through the lead network to the error amplifier. In cases where a noisy current sense is present, adding a low pass filter to the input of CS and VOUT can help restore a cleaner waveform (Figure 24 , R16 and C10). Care must be taken not to have a large RC time constant to avoid instability. 4 AN–1368 LM5115/5025A Evaluation Board Copyright © 2005–2013, Texas Instruments Incorporated SNVA107A – April 2005 – Revised April 2013 Submit Documentation Feedback Foldback Current Limit www.ti.com 8 Foldback Current Limit Current limit foldback can be implemented with the following components: R17, R18, C10, D5, and R16 (see Figure 24). At nominal output voltage (VOUT > 3V) D5 is reversed biased and the current limit threshold is still ~45mV. At lower output voltage the resistor divider network along with the forward biased diode (D5) will increase the voltage across R16. In order to reach the 45mV current limit threshold, the voltage across the sense resistor (R7-R9) is reduced due to the increase in voltage across R16. Thus, the current limit is reduced providing current limit foldback. The resistor divider sets the voltage when current limit foldback kicks in and R16 sets the amount of current limit foldback. A most common occurrence, that will prove unnerving, is when the current limit set on the source supply is insufficient for the load. The result is similar to having the high source impedance referred to earlier. The interaction of the source supply folding back and the UUT going into undervoltage shutdown will start an oscillation, or chatter, that may have highly undesirable consequences. 9 Optional DC Buck LM5115 can also be configured as a DC buck regulator. Information for the DC board can be found in LM5115 Secondary Side Post Regulator/Synchronous Buck Controller (SNVS343). 10 Typical Performance Characteristics 90 CH1 80 2 CH2 3 EFFICIENCY (%) CH3 VIN = 36V 70 1 VIN = 72V 60 50 VIN = 48V 40 30 20 4 10 CH4 VIN = 48V, Secondary output load = open CH1 = Main Phase Signal (5V/Div). CH2 = RAMP (1V/Div). CH3 = Secondary Switch Signal (5V/Div). CH4 = Inductor Current Secondary (2A/Div). Horizontal Resolution = 2 Ps/Div. Figure 4. Representative Waveform SNVA107A – April 2005 – Revised April 2013 Submit Documentation Feedback 0 0 1 2 3 4 5 6 7 LOAD (A) Figure 5. System Efficiency vs. Load Current and VIN AN–1368 LM5115/5025A Evaluation Board Copyright © 2005–2013, Texas Instruments Incorporated 5 Typical Performance Characteristics www.ti.com 100 98 VIN = 36V CH2 EFFICIENCY (%) 96 94 VIN = 48V CH1 92 90 VIN = 72V 88 86 1&2 84 82 0 1 2 3 4 5 6 7 VIN = 48V; LM5115 Load = 5.0A CH1 = Lo Side Sw Gate Drive, 2V/Div. CH2 = Hi Side Sw Gate Drive, 2V/Div. Horizontal Resolution = 100 ns/Div. LOAD (A) Figure 6. Adjusted Efficiency on Secondary Side vs. Load Current and VIN Figure 7. Gate Turn-on Delay CH2 CH1 CH1 CH3 CH2 1&2 VIN = 48V; LM5115 Load = 5.0A CH1 = Lo Side Sw Gate Drive, 2V/Div. CH2 = Hi Side Sw Gate Drive, 2V/Div. Horizontal Resolution = 100 ns/Div. Figure 8. Gate Turn-off Delay 6 CH4 VIN = 48V CH1 = Inductor Current, 5A/Div. CH2 = COMP/CO, 1V/Div. CH3 = High Side Switch Gate Drive, 5V/Div. CH4 = Phase Signal, 5V/Div. Horizontal Resolution = 10 Ps/Div. Figure 9. Secondary Output Short Response AN–1368 LM5115/5025A Evaluation Board Copyright © 2005–2013, Texas Instruments Incorporated SNVA107A – April 2005 – Revised April 2013 Submit Documentation Feedback Typical Performance Characteristics www.ti.com CH1 CH1 CH2 CH2 CH3 CH3 VIN = 48V VIN = 48V CH1 = Secondary 2.0V Output, 100 mV/Div. (AC Mode). CH2 = Main 3.3V Output, 2V/Div. CH3 = Secondary Current Load (5A to 9A), 2A/Div. Horizontal Resolution = 500 Ps/Div. CH1 = Secondary 2.0V Output, 100 mV/Div. AC. CH2 = Main 3.3V Output, 2V/Div. CH3 = Main Current Load (10A to 30A), 10A/Div. Horizontal Resolution = 200 Ps/Div. Figure 10. Secondary Step Load Response Figure 11. Cross Regulation Step Load CH2 CH2 CH1 CH1 1&2 VIN = 48V; LM5115 Load = 5.0A, LM5025 Load = Open 1&2 VIN = 48V; LM5115 Load = 5.0A, LM5025 Load = Open CH1 = Secondary 2V Output, 1V/Div. CH2 = Main 3.3V Output, 1V/Div. Horizontal Resolution = 1 ms/Div. CH1 = Secondary 2V Output, 1V/Div. CH2 = Main 3.3V Output, 1V/Div. Horizontal Resolution = 200 Ps/Div. Figure 12. Startup Response SNVA107A – April 2005 – Revised April 2013 Submit Documentation Feedback Figure 13. Shutdown Response AN–1368 LM5115/5025A Evaluation Board Copyright © 2005–2013, Texas Instruments Incorporated 7 Typical Performance Characteristics www.ti.com 1.985 OUTPUT (V) 1.983 CH1 1 VIN = 36V 1.981 VIN = 48V & VIN = 72V 1.979 1.977 1.975 VIN = 48V; LM5115 Load = 8.0A 1 0 2 CH1 = Secondary 2V Output, 50 mV/Div. (AC Mode). Horizontal Resolution = 1 Ps/Div. 6 7 175 Gain 150 20 100 Phase 10 75 0 50 -10 25 1k 10k PHASE (o) 125 30 GAIN (dB) 5 Figure 15. Output vs. Load Current and VIN 50 -20 100 4 LOAD (A) Figure 14. Secondary Ripple Voltage 40 3 0 1M FREQUENCY (Hz) Figure 16. Secondary Closed Loop Response 8 AN–1368 LM5115/5025A Evaluation Board Copyright © 2005–2013, Texas Instruments Incorporated SNVA107A – April 2005 – Revised April 2013 Submit Documentation Feedback Bill of Materials www.ti.com 11 Bill of Materials Table 1. Bill of Materials Item Part Number Description Value C 1 C3216X7R1E105K CAPACITOR, CER, TDK 1.0 µF, 25V C 2 C2012X7R1H104K CAPACITOR, CER, TDK 0.1 µF, 50V C 3 C3216X7R1E105K CAPACITOR, CER, TDK 1.0 µF, 25V C 4 C2012COG1H331K CAPACITOR, CER, TDK 330 pF, 50V C 5 C2012X7R1H104K CAPACITOR, CER, TDK 0.1 µF, 50V C 6 C 7 C2012COG1H223K CAPACITOR, CER, TDK 0.022µF, 50V C 8 C2012COG1H471K CAPACITOR, CER, TDK 470 pF, 50V C 9 Not Used C 10 Not Used C 11 C4532X7SOG686M CAPACITOR, CER, TDK 68 µF, 4.0V C 12 C4532X7SOG686M CAPACITOR, CER, TDK 68 µF, 4.0V C 13 C4532X7SOG686M CAPACITOR, CER, TDK 68 µF, 4.0V D 1 CMPD2838E-NSA DIODE, SIGNAL, CENTRAL, SEMI D 2 CMPD2838E-NSA DIODE, SIGNAL, CENTRAL, SEMI D 3 D 4 CMSH3-40L-NSA DIODE SHOTTKY, CENTRAL, SEMI D 5 J 1 2515-1-01-01-00-00-07-0 SOLDER TERMINAL SLOTTED, MILL-MAX J 2 2515-1-01-01-00-00-07-0 SOLDER TERMINAL SLOTTED, MILL-MAX J 3 5002 TERMINAL, SMALL TEST POINT, KEYSTONE J 4 5002 TERMINAL, SMALL TEST POINT, KEYSTONE R 1 CRCW080510R0J RESISTOR, VISHAY 10 R 2 CRCW08051001F RESISTOR, VISHAY 1.00 K R 3 CRCW08054322F RESISTOR, VISHAY 43.2 K R 4 CRCW08051153F RESISTOR, VISHAY 115 K R 5 CRCW080510R0J RESISTOR, VISHAY 10 R 6 R 7 CRCW1206R012F RESISTOR, VISHAY , Newark # 06HO462 0.012 R 8 CRCW1206R012F RESISTOR, VISHAY , Newark # 06HO462 0.012 R 9 CRCW1206R012F RESISTOR, VISHAY , Newark # 06HO462 0.012 R 10 CRCW080510R0J RESISTOR, VISHAY R 11 R 12 CRCW08058251F RESISTOR, VISHAY R 13 CRCW08054991F RESISTOR, VISHAY R 14 R 15 CRCW08050000Z RESISTOR, VISHAY R 16 CRCW08050000Z RESISTOR, VISHAY R 17 Not Used R 18 Not Used Q 1 SI7892DP MOSFET, N-CH, POWER S0-8 PKG, VISHAY SI7892DP Q 2 SUD70N02 MOSFET, N-CH, DPAK PKG, VISHAY SUD70N02 L 1 DR356-2-272 INDUCTOR, COOPER, DR127-2R2 2.2 uH - 12A U 1 LM5115 CONTROLLER, SINGLE OUT, PWM, TEXAS INSTRUMENTS LM 5115 Not Used Not Used CMSH3-40L Not Used Not Used 10 Not Used 8.25 K 4.99K Not Used SNVA107A – April 2005 – Revised April 2013 Submit Documentation Feedback 0 OHMS 0 OHMS AN–1368 LM5115/5025A Evaluation Board Copyright © 2005–2013, Texas Instruments Incorporated 9 PCB Layout(s) 12 www.ti.com PCB Layout(s) Figure 17. Top Silk Screen LM5115 10 Figure 18. Top Layer LM5115 AN–1368 LM5115/5025A Evaluation Board Copyright © 2005–2013, Texas Instruments Incorporated SNVA107A – April 2005 – Revised April 2013 Submit Documentation Feedback PCB Layout(s) www.ti.com Figure 19. Layer 2 LM5115 SNVA107A – April 2005 – Revised April 2013 Submit Documentation Feedback Figure 20. Layer 3 LM5115 AN–1368 LM5115/5025A Evaluation Board Copyright © 2005–2013, Texas Instruments Incorporated 11 PCB Layout(s) www.ti.com Figure 21. Bottom Layer LM5115, as Viewed from Top 12 Figure 22. Bottom Silk Screen LM5115 AN–1368 LM5115/5025A Evaluation Board Copyright © 2005–2013, Texas Instruments Incorporated SNVA107A – April 2005 – Revised April 2013 Submit Documentation Feedback Application Circuit Schematic www.ti.com 13 Application Circuit Schematic Figure 23. LM5025A Eval Board SNVA107A – April 2005 – Revised April 2013 Submit Documentation Feedback AN–1368 LM5115/5025A Evaluation Board Copyright © 2005–2013, Texas Instruments Incorporated 13 Application Circuit Schematic www.ti.com Figure 24. LM5115 AC Eval Board Schematic 14 AN–1368 LM5115/5025A Evaluation Board SNVA107A – April 2005 – Revised April 2013 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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