LM53600-Q1, LM53601-Q1
SNAS660D – JUNE 2015 – REVISED MAY 2021
LM53600/01-Q1 0.65-A/1-A, 36-V Synchronous, 2.1-MHz
Automotive Step-Down DC/DC Converter
1 Features
3 Description
•
•
The LM53600-Q1 and LM53601-Q1 synchronous
buck regulator devices are optimized for automotive
applications, providing an output voltage of 5 V, 3.3 V,
or an adjustable output. Load current up to 650 mA
is supported by the LM53600-Q1, while the LM53601Q1 supports up to 1000 mA. Advanced high-speed
circuitry allows the LM53600-Q1 and LM53601-Q1
devices to regulate from an input of 18 V to an output
of 3.3 V at a fixed frequency of 2.1 MHz. Innovative
architecture allows the device to regulate a 3.3-V
output from an input voltage of only 3.8 V. The input
voltage range up to 36 V, with transient tolerance of
up to 42 V, eases input surge protection design. An
open drain reset output, with filtering and delayed
release, provides a true indication of system status.
This feature negates the requirement for an additional
supervisory component, saving cost and board space.
Seamless transitions between PWM and PFM modes,
along with a quiescent current of only 23 µA, ensures
high efficiency and superior transient response at all
loads. Few external components are needed allowing
the generation of compact PCB layout. While the
LM53600-Q1 and LM53601-Q1 devices are Q1 rated,
electrical characteristics are ensured across a junction
temperature range of –40°C up to 150°C.
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to 125°C
ambient operating temperature range
– Device HBM classification level 2
– Device CDM classification level C5
–40°C to 150°C junction temperature range
(available)
Wide operating input voltage: 3.55 V to 36 V (with
transient to 42 V)
Spread spectrum option available
2.1-MHz fixed switching frequency
Low quiescent current: 23 μA
Shutdown current: 1.8 µA
Adjustable, 3.3-V, or 5-V output
Maximum current load: 650 mA for LM53600-Q1,
1000 mA for LM53601-Q1
Pin-selectable forced PWM mode
RESET output with filter and delay release
External frequency synchronization
Internal compensation, soft start, current limit, and
UVLO
10-lead, 3-mm × 3-mm SON package with
wettable and non-wettable flanks
2 Applications
•
•
•
Device Information
Automotive camera applications
Automotive driver assistance systems
Automotive body applications
PART NUMBER
LM53600-Q1
LM53601-Q1
(1)
PACKAGE(1)
WSON (10)
BODY SIZE (NOM)
3.00 mm x 3.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VPU
RPU
RESET
AGND
FB
EN
VSUPPLY
VIN
LM53600
LM53601
SYNC/
MODE
VCC
CVCC
BOOT
CBOOT
CIN
L1
GND
SW
(DAP)
COUT
Simplified Schematic – Fixed Output
Automotive 11.2-mm x 12.7-mm Layout
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM53600-Q1, LM53601-Q1
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SNAS660D – JUNE 2015 – REVISED MAY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison......................................................... 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 System Characteristics............................................... 8
7.7 Timing Requirements.................................................. 9
7.8 Typical Characteristics.............................................. 10
8 Detailed Description...................................................... 11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................17
9 Applications and Implementation................................ 18
9.1 Application Information............................................. 18
9.2 Typical Applications.................................................. 19
9.3 Do's and Don't's........................................................ 26
10 Power Supply Recommendations..............................28
11 Layout........................................................................... 29
11.1 Layout Guidelines................................................... 29
11.2 Layout Example...................................................... 31
12 Device and Documentation Support..........................32
12.1 Documentation Support.......................................... 32
12.2 Receiving Notification of Documentation Updates..32
12.3 Support Resources................................................. 32
12.4 Trademarks............................................................. 32
12.5 Electrostatic Discharge Caution..............................32
12.6 Glossary..................................................................32
13 Mechanical, Packaging, and Orderable
Information.................................................................... 33
4 Revision History
Changes from Revision C (April 2021) to Revision D (May 2021)
Page
• Added non-wettable flank options.......................................................................................................................1
Changes from Revision B (February 2016) to Revision C (April 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
Changes from Revision A (December 2015) to Revision B (February 2016)
Page
• Updated tables in the Device Comparison Table ...............................................................................................3
• Removed last sentence in SYNC/MODE description in Pin Functions table in Pin Configuration and Functions
............................................................................................................................................................................4
• Updated IB Parameter in Section 7.5 table......................................................................................................... 6
• Changed RRESET MAX from "80" to "120" in Section 7.5 table........................................................................... 6
• Changed Vout to Vout_3_3V, Vout_5V, and Vout_ADJ for 3.3-V, 5-V, and ADJ output voltage options in Section 7.6
table.................................................................................................................................................................... 8
• Corrected references for SNAU190 and SNAU191 in Section 12.1.1 ............................................................. 32
Changes from Revision * (June 2015) to Revision A (December 2015)
Page
• Changed device status from product preview to production data.......................................................................1
2
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Product Folder Links: LM53600-Q1 LM53601-Q1
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SNAS660D – JUNE 2015 – REVISED MAY 2021
5 Device Comparison
LM53600-Q1 Devices
Part Number(1)
Output Voltage
Spread
Spectrum
Package Qty (2)
Wettable (WF)/Non-Wettable Flanks (nonWF)
LM53600AQDSXRQ1
Adjustable
No
3000
WF
LM53600AQDSXTQ1
Adjustable
No
250
WF
LM536003QDSXRQ1
3.3 V
No
3000
WF
LM536003QDSXTQ1
3.3 V
No
250
WF
LM536005QDSXRQ1
5.0 V
No
3000
WF
LM536005QDSXTQ1
5.0 V
No
250
WF
LM53600MQDSXRQ1
Adjustable
Yes
3000
WF
LM53600MQDSXTQ1
Adjustable
Yes
250
WF
LM53600NQDSXRQ1
3.3 V
Yes
3000
WF
LM53600NQDSXTQ1
3.3 V
Yes
250
WF
LM53600LQDSXRQ1
5.0 V
Yes
3000
WF
LM53600LQDSXTQ1
5.0 V
Yes
250
WF
LM53600MQUDSXRQ1
Adjustable
Yes
3000
Non-WF
(1)
(2)
LM53600-Q1 devices have maximum recommended operating current of 650 mA.
See Package Option Addendum for tape and reel details as well as links used to order parts.
LM53601-Q1 Devices
Part Number(1)
Output Voltage
Spread
Spectrum
Package Qty (2)
Wettable (WF)/Non-Wettable Flanks (non-WF)
LM53601AQDSXRQ1
Adjustable
No
3000
WF
LM53601AQDSXTQ1
Adjustable
No
250
WF
LM536013QDSXRQ1
3.3 V
No
3000
WF
LM536013QDSXTQ1
3.3 V
No
250
WF
LM536015QDSXRQ1
5.0 V
No
3000
WF
LM536015QDSXTQ1
5.0 V
No
250
WF
LM53601MQDSXRQ1
Adjustable
Yes
3000
WF
LM53601MQDSXTQ1
Adjustable
Yes
250
WF
LM53601NQDSXRQ1
3.3 V
Yes
3000
WF
LM53601NQDSXTQ1
3.3 V
Yes
250
WF
LM53601LQDSXRQ1
5.0 V
Yes
3000
WF
LM53601LQDSXTQ1
5.0 V
Yes
250
WF
LM536015QUDSXRQ1
5.0 V
No
3000
Non-WF
LM536013QUDSXRQ1
3.3 V
No
3000
Non-WF
LM53601MQUDSXRQ1
Adjustable
Yes
3000
Non-WF
(1)
(2)
LM53601-Q1 devices have maximum recommended operating current of 1000 mA.
See Package Option Addendum for tape and reel details as well as links used to order parts.
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SNAS660D – JUNE 2015 – REVISED MAY 2021
6 Pin Configuration and Functions
1
SW
2
BOOT
3
VCC
4
FB
5
AGND
10
1
SW
SYNC/
MODE
9
2
BOOT
VIN
8
3
VCC
EN
7
4
FB
RESET
6
5
BIAS
GND
DAP
Fixed Version
GND
10
SYNC/
MODE
9
VIN
8
EN
7
RESET
6
DAP
Adjustable Version
Figure 6-1. DSX Package 10-Pin WSON Top View
Table 6-1. Pin Functions
PIN
NO.
NAME
DESCRIPTION
1
SW
P
Regulator switch node. Connect to output inductor.
2
BOOT
I
High side gate driver upper supply rail. Connect a 100-nF capacitor from SW pin to BOOT. An internal
diode charges the capacitor while SW node is low.
3
VCC
P
Internal 3-V regulator output. Used as supply to internal control circuits. Connect a high quality 1.0-μF
capacitor from this pin to AGND for fixed versions or to GND for adjustable versions.
FB (Fixed
Versions)
I/P
Fixed version only, this pin serves as feedback for output voltage as well as power source for VCC’s
regulator. Connect to output node. Place 10-nF bypass capacitor immediately adjacent to this pin.
FB (ADJ
Version)
I
ADJ version only, this pin serves as feedback for output voltage only. Connect to output through a
voltage divider which determines output voltage set point.
AGND (Fixed
Version)
G
Fixed versions only, this is the ground to which input signals and FB are compared.
BIAS (ADJ
Version)
P
Power source for VCC’s regulator. Connect to output node. Place 10-nF bypass capacitor immediately
adjacent to this pin.
6
RESET
O
Open drain reset output. Connect to suitable voltage supply through a current limiting pull up resistor.
High = regulator OK, Low = regulator fault. Will go low when EN = low. See Detailed Description.
7
EN
I
Enable input to regulator. High = on, Low = off. Can be connected to Vin. Do not float.
8
VIN
I
Input supply to regulator. Connect input bypass capacitors directly between this pin and GND.
4
5
9
SYNC/MODE
I
This is a multifunction mode control input which is tolerant of voltages up to input voltage. With a valid
synchronization signal at this pin, the device will switch in forced PWM mode at the external clock
frequency and synchronize with it at the rising edge of the clock. See the Electrical Characteristics
for synchronization signal specifications. With this input tied high, the device will switch at the internal
clock frequency in forced PWM mode. With this input tied low, the device will switch at the internal
clock frequency in AUTO mode with diode emulation at light load. Spread spectrum is disabled if there
is a valid synchronization signal. Do not float.
10
GND
G
Bypass to VIN immediately adjacent to this pin.
DAP
(EXPO
SED
PAD)
(1)
4
TYPE(1)
Thermal,
GND
Connect to ground – The sole function of the DAP interface is the thermal improvement of the device,
Thermal a direct thermal connection to a ground plane is required. The DAP is not meant as an electrical
interconnect. Electrical characteristics are not ensured.
G = Ground, I = Input, O = Output, P = Power
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SNAS660D – JUNE 2015 – REVISED MAY 2021
7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)
MIN
MAX
VIN to GND(1)
–0.3
42
SW to GND(2)
–0.3
VIN+0.3
BOOT to SW
–0.3
3.6
EN to GND
(1)
–0.3
42
BIAS to GND: LM53600-Q1/LM53601-Q1-ADJ
–0.3
16
FB to GND : LM53600-Q1/LM53601-Q1 - 3.3 V, LM53600-Q1/LM53601-Q1 - 5.0 V
–0.3
16
FB to GND : LM53600-Q1/LM53601-Q1-ADJ
–0.3
5.5
RESET to GND
–0.3
8
SYNC/MODE to GND(1)
–0.3
42
VCC
RESET sink current(3)
V
8
–0.3
3.6
GND(4) to AGND (Fixed version only)
–1
2
Storage temperature, Tstg
–40
150
(1)
(2)
(3)
(4)
UNIT
mA
V
°C
A maximum of 42 V can be sustained at this pin for a duration of ≤100 ms at a duty cycle of ≤1%.
A voltage of 2-V below GND and 2-V above VIN can appear on this pin for ≤200 ns with a duty cycle of ≤ 0.01%.
Do not exceed pin’s voltage rating.
This specification applies to voltage durations of 1 µs or less. The maximum D.C. voltage should not exceed ±0.3 V.
7.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
Charged device model (CDM), per AEC Q100-011
(1)
VIN, SW, CBOOT
±2000
EN, BIAS, RESET, FB, SYNC,
PWM, VCC
±2000
Other pins
±750
Corner pins (1, 5, 6, and 10)
±750
UNIT
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)
MIN
Input voltage range after
startup(1)
Output voltage range
Operating junction temperature(4)
(1)
(2)
(3)
(4)
MAX
3.8
36
5 V(2)
0
5.5
3.3 V(2)
0
3.63
3.3
6
Output adjustment range(3)for LM53600-Q1-ADJ (2), LM53601-Q1-ADJ(2)
Load current range
NOM
LM53600-Q1
0
650
LM53601-Q1
0
1000
–40
150
UNIT
V
V
V
mA
°C
An extended input voltage range to 3.55 V is possible; see Section 7.6. See input UVLO in Section 7.5 for startup conditions.
Output voltage should not be allowed to fall below 0 V during normal operation.
The LM53600-Q1 and LM53601-Q1 devices can operate outside of the listed range output voltage range. For output voltage outside of
the listed range, contact Texas Instruments concerning alternate application circuit BOM and additional operational limitations such as
higher IQ.
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
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SNAS660D – JUNE 2015 – REVISED MAY 2021
7.4 Thermal Information
LM53600-Q1,
LM53601-Q1
THERMAL METRIC(1)
UNIT
DSX (WSON)
10 PINS
Rθ JA
Junction -to-ambient thermal resistance
46.2
°C/W
Rθ JC
Junction -to-case (top) thermal resistance
31.5
°C/W
Rθ JB
Junction -to-board thermal resistance
20.9
°C/W
φJT
Junction- to-top characterization parameter
0.3
°C/W
φJB
Junction-to-board characterization parameter
21.0
°C/W
Rθ JC(bot)
Junction-to-case (bottom) thermal resistance
4.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
7.5 Electrical Characteristics
Limits apply to the recommended operating junction temperature range of –40°C to 150°C, unless otherwise noted. Minimum
and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely
parametric norm at Tj = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions
apply: Vin = 13.5 V.
PARAMETER
TEST CONDITIONS
VFB
Initial output voltage accuracy
Vin= 3.8 V to 36 V Tj=25°C, Open
Loop
IQ
Operating quiescent current;
measured at VIN pin
Vin= 13.5 V, Not switching Vbias= 5 V
Vin= 3.8 V to 36 V, Open Loop
TYP
–1%
–1.5%
1.5%
16
µA
Bias current into BIAS pin for Vin= 13.5 V, Not switching Vbias= 5 V,
adjustable versions and FB pin Mode = 0 V
for fixed versions
46
ISD
Shutdown quiescent current;
measured at VIN pin
1.8
EN = 0, VIN = 13.5 V Tj = 25°C
EN = 0, VIN = 13.5 V Tj = 85°C
Minimum input voltage to
operate
Rising
Vin_UVLO _hyst
Minimum input voltage
hysteresis
Hysteresis
Vreset_OV
RESET upper threshold
voltage
Rising, % of Vout
Vreset_UV
RESET lower threshold
voltage
Vreset_guard
Magnitude of RESET lower
threshold difference from
steady state output voltage
Vreset_hyst
RESET hysteresis as a
percent of output voltage set
point
Vreset_valid
Minimum input voltage for
proper RESET function
Low level RESET function
output voltage
UNIT
6.5
Vin= 13.5 V, Not switching Vbias= 5 V,
Tj= 85°C
Vin_UVLO
MAX
1%
IB
VOL
6
MIN
80
3
µA
3.2
3.6
3.75
V
0.2
0.3
0.35
V
105%
106.5%
110%
Falling, % Vout
92%
94%
97%
Steady state output voltage and
RESET threshold read at the same
TJ, and VIN
3.9%
1%
50 µA pull-up to RESET pin, EN = 0
V, Tj = 25°C
1.5
50 µA pull-up to RESET pin, Vin =
1.5 V, EN = 0 V, Tj = 25°C
0.4
0.5mA pull-up to RESET pin, Vin =
13.5 V, EN = 0 V
0.4
1mA pull-up to RESET pin, Vin =
13.5 V, EN = 3.3 V
0.4
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Limits apply to the recommended operating junction temperature range of –40°C to 150°C, unless otherwise noted. Minimum
and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely
parametric norm at Tj = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions
apply: Vin = 13.5 V.
PARAMETER
Fsw
TEST CONDITIONS
Switching frequency
MIN
TYP
MAX
VIN = 13.5 V, Center frequency with
spread spectrum, PWM operation
1.89
2.1
2.4
VIN = 13.5 V, Without spread
spectrum, PWM operation
1.89
2.1
2.4
1.0
VIN = 36 V, 5-V fixed output device
1.5
Sync frequency range
Output setting + 1 V < VIN < 18 V
DSYNC
Sync input duty cycle range
High state input < 5.5 V and > 2.3 V
SYNC/MODE input high
(MODE=FPWM)
VSYNC/MODE
SYNC/MODE input threshold
voltage
Frequency span of spread
spectrum operation(2)
FPSS
Spread spectrum pattern
frequency(2)
ISYNC/MODE
SYNC/MODE leakage current
tMODE
IL_HS
1.9
2.1
25%
2.3
MHz
75%
1.5
SYNC/MODE input low (MODE =
AUTO with diode emulation)
SYNC/MODE input hysteresis
FSSS
MHz
VIN = 36 V, 3.3-V fixed output device
and adjustable devices regardless of
output voltage
FSYNC
UNIT
0.4
0.185
V
1
±4%
30
Mode change transition time
(2)
High side switch current limit
(1)
IL_LS
Low side switch current limit
IL_ZC
Zero-cross current limit
MODE/SYNC = Low
Vin = 13.5 V, VSYNC/MODE = 3.3 V
1
VIN = VSYNC/MODE = 13.5 V
5
To FPWM Mode 20 mA load, VIN =
13.5 V
100
To AUTO Mode 20-mA load, VIN =
13.5 V
60
µA
µs
LM53600-Q1 Duty cycle approaches
0%
1.0
1.35
1.65
LM53601-Q1 Duty cycle approaches
0%
1.5
1.83
2.1
LM53600-Q1
0.65
0.78
0.93
LM53601-Q1
1.0
1.2
1.43
–0.01
LM53600-Q1
–0.7
LM53601-Q1
–0.7
High side MOSFET Rdson
220
IL_NEG
Negative current limit MODE/
SYNC = High
Rdson
Power switch on-resistance
VEN
Enable input threshold voltage Enable rising
- rising
Low side MOSFET Rdson
A
A
A
A
mΩ
200
1.7
-
2.0
V
-
0.55
V
VEN_HYST
Enable threshold hysteresis
0.40
VEN_WAKE
Enable Wake-up threshold
0.4
IEN
Enable pin input current
VIN = VEN = 13.5 V
Hz
V
2.7
VIN = 13.5 V, Vbias= 0 V
3.05
VIN = 13.5 V, Vbias= 3.3 V
3.15
µA
Vcc
Internal Vcc voltage
V
Vcc_UVLO
Internal Vcc input under
voltage lock-out
VCC rising
2.7
V
Vcc_UVLO_hyst
Input under voltage lock-out
hysteresis
Hysteresis below Vcc_uvlo
190
mV
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Limits apply to the recommended operating junction temperature range of –40°C to 150°C, unless otherwise noted. Minimum
and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely
parametric norm at Tj = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions
apply: Vin = 13.5 V.
PARAMETER
IFB
TEST CONDITIONS
Input current from FB to
AGND
LM53600-Q1-ADJ, FB = 1 V
Vref
Reference voltage for ADJ
option only
Tj = 25°C
RRESET
Rdson of RESET output
TSD
Thermal shutdown rising
threshold(2)
TSDF
Thermal shutdown falling
threshold(2)
TSD_hyst
Thermal shutdown
hysteresis(2)
Dmax
Maximum switch duty cycle(2)
(1)
(2)
MIN
TYP
MAX
20
UNIT
nA
0.993
1
1.007
0.985
1
1.015
50
120
151
167
185
140
157
V
Ω
°C
10
Fsw = 2.1 MHz
While in frequency fold back
76%
96%
High side current limit is a function of duty factor. Current limit value is highest at small duty factor and less at higher duty factors.
Ensured by design, statistical analysis and production testing of correlated parameters; not tested in production.
7.6 System Characteristics
The following specifications are ensured by design provided that the component values in the typical application circuit
are used. These parameters are not ensured by production testing. Limits apply to the recommended operating junction
temperature range of –40°C to 150°C, unless otherwise noted. Minimum and Maximum limits are ensured through test,
design or statistical correlation. Typical values represent the most likely parametric norm at Tj = 25°C, and are provided for
reference purposes only. Unless otherwise stated the following conditions apply: Vin = 13.5 V.
PARAMETER
Vin_min
Vout_3_3V
Vout_5V
Vout_ADJ
IQ_VIN (2)
VDROP1
8
TEST CONDITIONS
Minimum input voltage for full
functionality at 500-mA load, after
start-up
VOUT = 3.3 V
Minimum input voltage for full
functionality at 100% of max rated
load, after start-up
VOUT = 3.3 V
Output voltage for 3.3-V option
Output voltage for 5-V option
Output voltage ADJ option
MIN
TYP
MAX
UNIT
3.55
V
3.8
V
VIN = 4.0 V to 36 V, IOUT = Maximum
recommended load current
3.23
3.3
3.37
VIN = 3.8 V to 36 V, IOUT=100 µA to
100 mA, typical value in Auto Mode
3.23
3.33
3.39
VIN = 5.8 V to 36 V, IOUT = Maximum
recommended load current
4.9
5
5.1
VIN = 5.5 V to 36 V, IOUT=100 µA to
100 mA, typical value in Auto Mode
4.9
5.05
5.125
V
V
VIN = VOUT + 0.6 V to 36 V, IOUT =
100 mA, FPWM mode
–2%
+2%
VIN = VOUT + 0.6 V to 36 V, IOUT=100
µA to 100 mA, Auto mode
–2%
+2.5%
Load regulation for ADJ option(1)
VIN = VOUT + 1 V to 36 V, IOUT = 0 A
to 1 A, TJ = 125°C, FPWM mode
–1%
Input current to VIN node of DC/DC
utilizing the LM53600-Q1/LM53601Q1
VIN = 13.5 V, VOUT = 3.3 V, IOUT = 0
A
23
VIN = 13.5 V, VOUT = 5 V, IOUT = 0 A
30
Minimum input to output voltage
VOUT=3.3 V, IOUT=1000 mA, +2/–3%
differential to maintain regulation
output accuracy
accuracy, without inductor DCR drop
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0.6
V
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The following specifications are ensured by design provided that the component values in the typical application circuit
are used. These parameters are not ensured by production testing. Limits apply to the recommended operating junction
temperature range of –40°C to 150°C, unless otherwise noted. Minimum and Maximum limits are ensured through test,
design or statistical correlation. Typical values represent the most likely parametric norm at Tj = 25°C, and are provided for
reference purposes only. Unless otherwise stated the following conditions apply: Vin = 13.5 V.
PARAMETER
VDROP2
Efficiency
(1)
(2)
TEST CONDITIONS
Minimum input to output voltage
differential to maintain FSW ≥ 1.85
MHz, without inductor DCR drop
Typical Efficiency without inductor
loss
MIN
TYP
MAX
VOUT = 3.3 V, IOUT=1000 mA, FSW =
1.85 MHz, 2% regulation accuracy
UNIT
2.0
VIN = 13.5 V, VOUT = 5.0 V, IOUT = 1
A
85%
VIN = 13.5 V, VOUT = 3.3 V, IOUT = 1
A
80%
VIN = 13.5 V, VOUT = 5.0 V, IOUT =
0.65 A
86%
VIN = 13.5 V, VOUT = 3.3 V, IOUT =
0.65 A
83%
V
125°C is worst case temperature for load regulation. Layout is critical since adjustable option does not have an AGND terminal.
See Section 8.3.7 in Section 8 for the meaning of this specification and how it can be calculated.
7.7 Timing Requirements
Limits apply to the recommended operating junction temperature range of –40°C to 150°C, unless otherwise noted. Minimum
and Maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely
parametric norm at Tj = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions
apply: Vin = 13.5 V.
NOM
MAX
ton
Minimum switch on time(1)
VIN = 18 V, IOUT = 500 mA
MIN
50
80.5
toff
Minimum switch off time(1)
IOUT = 500 mA
90
125
treset_act
Delay time to RESET high signal
6
8
ms
4.5
ms
4
treset_filter
Glitch filter time constant for RESET function
tSS
Soft-start time
Time from first SW node
pulse to Vref at 90%, VIN
≥4.2 V
tEN
Turn-on delay(2)
Time from EN high until first
SW node pulse. VIN = 13.5,
Cvcc = 1 µF
tW
Short circuit wait time (Hiccup time)
(1)
(2)
24
1.3
3
UNIT
ns
µs
0.7
ms
4.5
ms
See Section 8
Ensured by design, statistical analysis and production testing of correlated parameters; not tested in production.
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7.8 Typical Characteristics
75
95
72
93
69
91
Minimum Off Time (ns)
Minimum On Time (ns)
VIN = 13.5 V, TA = 25°C (unless otherwise noted). Specified temperatures are ambient.
66
63
60
57
54
87
85
83
81
51
79
48
77
45
-40
-20
0
20
40
60
80
Temperature (qC)
Device Type = 3.3-V Fixed Output
Input Voltage = 20 V
100
120
75
-40
140
-20
0
20
D013
Load = 500 mA
Device Type = 1 A
Output = 4.85 V
40
60
80
Temperature (qC)
100
120
140
D014
5-V Fixed Output In Dropout
Load = 500 mA
Figure 7-1. Minimum On-Time vs Temperature
Figure 7-2. Minimum Off-Time vs Temperature
108
100
107
99
Normalized Threshold (%)
Normalized Threshold (%)
89
106
105
104
103
102
101
-20
0
20
40
60
80
Temperature (qC)
100
120
97
96
95
94
Rising
Falling
Margin
93
Rising
Falling
100
-40
98
92
-40
140
-20
0
20
D015
40
60
80
Temperature (qC)
100
120
140
D016
Margin is the difference between the falling RESET threshold
and actual regulation voltage which includes the effects of
temperature.
Figure 7-3. Upper RESET Threshold
Figure 7-4. Lower Reset Threshold
1.9
100.8
1.8
100.6
100.4
EN Threshold (V)
Feedback Voltage / Nominal (%)
101
100.2
100
99.8
99.6
99.4
1.7
Rising
Falling
1.6
1.5
1.4
99.2
99
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
-20
0
D017
Figure 7-5. Normalized VFB vs Temperature
10
1.3
-40
140
20
40
60
80
Temperature (qC)
100
120
140
D018
Figure 7-6. EN Threshold vs Temperature
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8 Detailed Description
8.1 Overview
The LM53600-Q1 and LM53601-Q1 devices are wide-input voltage range, low quiescent current, highperformance regulators with internal compensation designed specifically for the automotive market. These
devices are designed to minimize end product cost and size while operating in demanding automotive
environments. Normal operating frequency is 2.1 MHz allowing the use of small passive components. State
of the art current limit allows the use of inductors that are smaller than those typically used in a 650mA or
1000mA regulator. 2.1MHz is above the AM band, allowing significant saving in input filtering. This part has a
low unloaded current consumption eliminating the need for an external back-up LDO. The low shutdown current
and high maximum operating voltage of the LM53600-Q1 and LM53601-Q1 devices also allows the elimination
of an external load switch. To further reduce system cost, an advanced reset output is provided, which can often
eliminate the use of an external reset or supervisory device.
The LM53600-Q1 and LM53601-Q1 devices are AEC Q1 qualified, and also have electrical characteristics
ensured up to a maximum junction temperature of 150°C.
8.2 Functional Block Diagram
VIN
VCC
Int. Reg.
Bias
EN
BOOT
HS Current
Sense
Voltage
Reference
FB
Error
Amplifier
+
-
COMP
Control Logic
Driver
SW
+
-
RESET
OSC
LS Current
Sense
Control
SYNC/MODE
AGND
GND
Figure 8-1. Fixed Versions
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BIAS
VIN
VCC
Int. Reg.
Bias
EN
BOOT
HS Current
Sense
Voltage
Reference
Error
Amplifier
FB
+
-
COMP
Control Logic
Driver
SW
+
-
RESET
OSC
LS Current
Sense
Control
SYNC/MODE
GND
Figure 8-2. Adjustable Versions
8.3 Feature Description
8.3.1 Control Scheme
The control scheme of the LM53600-Q1 and LM53601-Q1 devices allows this part to operate under a wide
range of conditions with a low number of external components. Peak current mode control allows a wide
range of input voltages and output capacitance values, while maintaining a constant switching frequency. Stable
operation is maintained while output capacitance is changed during operation as well. This allows use in
systems that require high performance during load transients and which have load switches which remove loads
as system operating state changes. Short minimum on- and off-times ensure constant frequency regulation over
a wide range of conversion ratios. These on- and off- times allow for a duty factor window of 13% to 77% at
2.1-MHz switching frequency.
This architecture uses frequency foldback in order to achieve low dropout voltage maintaining output regulation
as the input voltage falls close to output voltage. The frequency foldback is smooth and continuous, and
activated as off-time approaches its minimum. Under these conditions, the LM53600-Q1 and LM53601-Q1
devices operate much like a constant off-time converter allowing maximum duty cycle to reach 97%, which
allows output voltage regulation with 600-mV dropout.
If input voltage exceeds approximately 21 V, frequency is reduced smoothly as a function of input voltage.
This frequency reduction allows output voltage regulation and current mode control to operate with duty factor
below 13%. Since current mode control continues at high input voltage insensitivity to output capacitance is
maintained. This form of fold back will not be active if input voltage is below 18 V, insuring constant frequency
operation over normal automotive operating conditions.
High input voltage foldback has two settings; see FSW under 36-V input conditions for detail. Since adjustable
output voltage versions fold back under high input voltage conditions as though output voltage were 3.3 V, larger
inductance and output capacitance is required if an adjustable device is used with output voltage above 4.2
V. If a 4.7-µH inductor is used in system with greater 4.2-V output using an adjustable device, the converter
remains stable but may not achieve full output current when operating at high input voltages, such as 36 V, due
to excessive inductor current ripple.
As load current is reduced, the LM53600-Q1 and LM53601-Q1 devices transition to light load mode if SYNC/
MODE is low. In this mode, diode emulation is used to reduce RMS inductor current and switching frequency is
reduced. Also, fixed voltage versions do not need a voltage divider connected to FB saving additional power. As
12
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a result, only 23 µA (typical, while converting 13.5 V to 3.3 V) is consumed to regulate output voltage if output is
unloaded. Average output voltage increases slightly while lightly loaded.
8.3.2 Soft-Start Function
Soft-start time is fixed internally at about 3.0 ms. Soft-start is achieved by ramping the internal reference. The
LM53600-Q1 and LM53601-Q1 devices operate correctly even if there is a voltage present on output before
activation of the LM53600-Q1 or LM53601-Q1.
8.3.3 Current Limit
The LM53600-Q1 and LM53601-Q1 devices use two current limits which allow the use of smaller inductors than
systems utilizing a single current limit. A coarse high side or peak current limit is provided to protect against
faults and saturated inductors. High side current limit limits the duration of high sides FET's on period during
a given clock cycle. A precision valley current limit prevents excessive average output current from the Buck
converter of the LM53600-Q1 and LM53601-Q1 devices. A new switching cycle is not initiated until inductor
current drops below the valley current limit. This scheme allows use of inductors with saturation current rated
less than twice the rated operating current of the LM53600-Q1 or LM53601-Q1.
Vout
Peak
Valley
Figure 8-3. Current Limit Operation
Figure 8-3 shows the response of the LM53600-Q1 or LM53601-Q1 device to a short circuit: Peak current limit
prevents excessive peak current while valley current limit prevents excessive average inductor current. After a
small number of cycles, hiccup mode is activated.
8.3.4 Hiccup Mode
In order to prevent excessive heating and power consumption under sustained short circuit conditions, a hiccup
mode is included. If an over current condition is maintained, the LM53600-Q1 or LM53601-Q1 device shuts
off its output and waits for tW (approximately 4.5 ms), after which the LM53600-Q1 or LM53601-Q1 restarts
operation beginning by activating soft start.
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Vout
Figure 8-4. Hiccup Operation
Figure 8-4 shows hiccup mode operation: The switch node of the LM53600-Q1 LM53601-Q1 is high impedance
after a short circuit or over current persists for a short duration. Periodically, the LM53600-Q1 or LM53601-Q1
attempts to restart. If the short has been removed before one of these restart attempts, the LM53600-Q1 or
LM53601-Q1 operates normally.
8.3.5 RESET Function
While the reset function of the LM53600-Q1 and LM53601-Q1 devices resembles a standard power good
function, its functionality is designed to replace a discrete reset IC, reducing BOM cost. There are three major
differences between the reset function and the normal power good function seen in most regulators:
•
•
•
A delay has been added for release of reset. See waveforms below.
RESET output signals a fault (pulls its output to ground) while the part is disabled.
RESET continues to operate with input voltage as low as 1.5 V. Below this input voltage, RESET output may
be high impedance.
Input Voltage
Output Voltage
Input Voltage
treset_filter
treset_filter
ttreset_actt
Vreset_hyst
treset_filter
ttreset_actt
ttreset_actt
Vreset_OV
treset_filter
treset_filter
Vreset_UV
Vin_UVLO (rising)
Vin_UVLO ± Vin_UVLO_hyst
Vreset_valid
GND
3.3 V
LM53600/01
RESET
RESET may not
be valid if input is
below Vreset_valid
Startup
delay
Soft start
complete
Small glitches
do not reset
timer
Small glitches do not
cause RESET to
signal a fault
OV activates
RESET
RESET continues to
operate below Vin_UVLO
RESET may not
be valid if input is
below Vreset_valid
Figure 8-5. Reset Output Function Operation
The following table summarizes conditions that cause a fault to be flagged by RESET . Once a fault is flagged,
RESET will not be released (become high impedance) until either there is no fault for treset_act or VIN drops
below Vreset_valid.
Table showing conditions that cause RESET to signal a fault (pull low).
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FAULT CONDITION ENDS (AFTER WHICH Treset_act MUST PASS
BEFORE RESET OUTPUT IS RELEASED)
FAULT CONDITION INITIATED
FB below Vreset_UV for longer than treset_filt
FB above Vreset_UV + Vreset_hyst for longer than treset_filt
FB above Vreset_OV for longer than treset_filt
FB below Vreset_OV - Vreset_hyst for longer than treset_filt
Junction temperature exceeds TSD
Junction temperature falls below TSD – TSD_hyst
EN low
tEN passes after EN becomes high(1)
VIN falls below Vin_UVLO - Vin_UVLO _hyst or VCC pin falls below
Vcc_UVLO - Vcc_UVLO_hyst
Voltage on VIN exceeds Vin_UVLO and VCC exceed Vcc_UVLO
(1)
As an additional safety feature, RESET remains low until approximately 1ms after soft start ends even if all other conditions in this
table are met and treset_act has passed. Lockout during soft start does not require treset_act to pass before RESET is released.
The threshold voltage for the RESET function is specified taking advantage of the availability of the LM53600-Q1
internal feedback threshold to the RESET circuit. This allows a maximum threshold of 97% of selected output
voltage to be specified at the same time as 95.7% of actual operating point. The net result is a more accurate
reset function while expanding the system allowance for transient response without the need for extremely
accurate internal circuitry. See output voltage error stack up comparison, below.
System with
external reset IC
SMPS upper limit
System using the LM53600/01's
internal reset function
+5%
-1.5%
SMPS nominal
output voltage
SMPS lower limit,
RESET should not trip
above this voltage
1.5%
0%
1.5% LM53600/01
accuracy
-3.5%
-4.5%
Available margin for ripple
and transient response
Available margin for ripple
and transient response
-1.5%
-1.5%
-5.5%
-5%
1.5%
Nominal external
reset IC threshold
-6.5%
RESET must trip
-8%
-1.5%
1.5% Reset IC
accuracy
1% Reset threshold accuracy with
respect to LM53600/01 reference voltage
1%
-1%
-7%
LM53600/01 max
reference value
LM53600/01 min
reference value
Offset between
reference voltage
and nominal
threshold voltage
Nominal threshold
setting if reference
is 1.5% low
Figure 8-6. Reset Threshold Voltage Stack Up
8.3.6 Forced PWM Operation
When constant frequency operation is more important than light load efficiency, the SYNC/MODE input of the
LM53600-Q1 and LM53601-Q1 devices should be pulled high, or a valid synchronization input be provided.
Once activated, this feature ensures that the switching frequency will stay above the AM frequency band, while
operating between the minimum and maximum duty cycle limits. Essentially, the diode emulation feature is
turned off in this mode. This means that the device will remain in CCM under light loads. Under conditions where
the device must reduce the on-time or off-time below the ensured minimum to maintain regulation, the frequency
will reduce to maintain the effective duty cycle required for regulation. This occurs for very high and very low
input/output voltage ratios.
This feature may be activated and deactivated while the part is regulating without removing the load. This feature
activates and deactivates gradually, over approximately 40 µs, preventing perturbation of output voltage. When
in FPWM mode, a limited reverse current is allowed through the inductor allowing power to pass from the
regulators output to its input.
Note that while FPWM is activated, larger currents pass through the inductor, if lightly loaded, than in auto mode.
This may result in more EMI, though at a predictable frequency. Once loads are heavy enough to necessitate
CCM operation, FPWM mode has no measurable effect on regulator operation.
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8.3.7 Auto Mode Operation and IQ_VIN
If SYNC/MODE is held low for a period greater than a few microseconds, the LM53600-Q1 and LM53601-Q1
devices will enable automatic power saving light load operation and diode emulation. In this mode, if peak
current needed to regulate output voltage drops below a selected value, the clock of the LM53600-Q1 or
LM53601-Q1 device slows to maintain regulation. The gain of this clock slowing circuit is low to maintain stability.
Output voltage with no load is approximately 1% higher than with a load high enough to allow full frequency
operation.
IQ_VIN is the current consumed by a converter utilizing a LM53600-Q1 or LM53601-Q1 device while regulating
without a load. While operating without a load, the LM53600-Q1 or LM53601-Q1 is only powering itself. The
LM53600-Q1 and LM53601-Q1 device draws power from two sources, its VIN pin, IQ, and either its FB pin for
fixed versions or BIAS pin for adjustable versions, IB. Since BIAS or FB is connected to the circuit’s output,
the power consumed is converted from input power with an effective efficiency, ηeff, of ~80%. Here, effective
efficiency is the added input power needed when lightly loading the converter of the LM53600-Q1 and LM53601Q1 devices is divided by the corresponding additional load. This allows unloaded current to be calculated as
follows:
IQ _ VIN
IQ
IEN
IB
Idiv
Output Voltage
Keff u Input Voltage
(1)
where
•
•
•
•
•
•
IQ_VIN is the current consumed by the Buck converter utilizing the LM53600-Q1 or LM53601-Q1 while
unloaded.
IQ is the current drawn by the LM53600-Q1 or LM53601-Q1 from its VIN terminal. See IQ in section 7.6.
IEN is current drawn by the LM53600-Q1 or LM53601-Q1 from its EN terminal. Include this current if EN is
connected to VIN. See IEN in section 7.6. Note that this current drops to a very low value if connected to a
voltage less than 5 V.
IB is bias/feedback current drawn by the LM53600-Q1 or LM53601-Q1 while the Buck converter utilizing it is
unloaded. See IB in section 7.6.
Idiv is the current drawn by the feedback voltage divider used to set output voltage for adjustable devices.
This current is zero for fixed output voltage devices.
ηeff is the light load efficiency of the Buck converter with IQ_VIN removed from the Buck converter’s input
current. 0.8 is a conservative value that can be used under normal operating conditions
Note that the EN pin consumes a few microamperes when tied to high; see IEN. Add IEN to IQ as shown in the
above equation if EN is tied to VIN. If EN is tied to a voltage less than 5 V, virtually no current is consumed
allowing EN to be used as a UVL once a voltage divider is added.
8.3.8 SYNC Operation
Often it is desirable to synchronize the operation of multiple regulators in a single system. This technique
results in better defined EMI and can reduce the need for capacitance on some power rails. The LM53600-Q1
and LM53601-Q1 devices provide a SYNC/MODE input, which allows synchronization with an external clock.
The LM53600-Q1/LM53601-Q1 implements an in-phase locking scheme – the rising edge of the clock signal
provided to the input of the LM53600-Q1 or LM53601-Q1 device corresponds to turning on the high side
device within the LM53600-Q1 or LM53601-Q1. This function is implemented using phase locking over a limited
frequency range eliminating large glitches upon initial application of an external clock. The clock fed into the
LM53600-Q1 or LM53601-Q1 device replaces the internal free running clock but does not affect frequency
fold-back operation. Output voltage will continue to be well regulated with duty factors outside of the normal 15%
through 77% range though at reduced frequency.
The device remains in FPWM mode and operates in CCM for light loads when synchronization input is provided.
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8.3.9 Spread Spectrum
The spread spectrum is a factory option. In order to find which parts have spread spectrum enabled, see Section
5.
The purpose of the spread spectrum is to eliminate peak emissions at specific frequencies by spreading
emissions across a wider range of frequencies than a part with fixed frequency operation. In most systems
containing the LM53600-Q1 and LM53601-Q1 devices, low frequency conducted emissions from the first few
harmonics of the switching frequency can be easily filtered. A more difficult design criterion is reduction of
emissions at higher harmonics which fall in the FM band. These harmonics often couple to the environment
through electric fields around the switch node. The LM53600-Q1 and LM53601-Q1 devices use a ±4% spread
of frequencies which spread energy smoothly across the FM band but is small enough to limit sub-harmonic
emissions below its switching frequency. Peak emissions at the part’s switching frequency are only reduced by
slightly less than 1 dB, while peaks in the FM band are typically reduced by more than 6dB.
The LM53600-Q1 and LM53601-Q1 devices use a cycle to cycle frequency hopping method based on a linear
feedback shift register (LFSR). Intelligent pseudo random generator limits cycle to cycle frequency changes to
limit output ripple. Pseudo random pattern repeats by approximately 7 Hz which is below the audio band.
The spread spectrum is only available while the clock of the LM53600-Q1 and LM53601-Q1 devices is free
running at its natural frequency. Any of the following conditions overrides spread spectrum, turning it off:
1. An external clock is applied to the SYNC/MODE terminal.
2. The clock is slowed due to operation low input voltage – this is operation in dropout.
3. The clock is slowed due to high input voltage – input voltage above approximately 21 V disables spread
spectrum.
4. The clock is slowed under light load in Auto mode – this is normally not seen above 200 mA of load. In
FPWM mode, spread spectrum is active even if there is no load.
8.4 Device Functional Modes
8.4.1 Shutdown
The LM53600-Q1 and LM53601-Q1 devices shut down most internal circuitry and both high side and low side
power switches connected to its switch node under any of the following conditions:
1. EN is below VEN
2. VIN is below Vin_UVLO
3. Junction temperature exceeds TSD
Note that the above conditions have hysteresis. Also, RESET remains active to a very low input voltage,
Vreset_valid.
8.4.2 FPWM Operation
If SYNC/MODE is above VSYNC/MODE high or a valid synchronizing is applied to SYNC/MODE, constant
frequency operation is maintained across load. This requires negative current be allowed in the inductor if load is
light. If a large negative load is present, operation is halted by a reverse current limit, IL-NEG.
8.4.3 Auto Mode Operation
If SYNC/MODE is below VSYNC/MODE low, reverse current in the inductor is not allowed – this feature is called
diode emulation. While load is heavy, operation is the same as in FPWM operation. If load is light, switching
frequency is reduced saving energy and allowing regulation to be maintained. Note that while under loads
which require moderate reduction of frequency, pulses often are seen if small groups, often called burst mode
operation, which can increase output ripple. Under this condition, output ripple can be reduced by increasing
output capacitance.
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9 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The LM53600-Q1 and LM53601-Q1 are step-down DC–DC converters, typically used to convert a higher DC
voltage to a lower DC voltage with a maximum output current of either 1 A or 650 mA. The following design
procedure can be used to select components for the LM53600-Q1 or LM53601-Q1. Alternately, the WEBENCH®
Design Tool may be used to generate a complete design. This tool utilizes an iterative design procedure and
has access to a comprehensive database of components. This allows the tool to create an optimized design and
allows the user to experiment with various design options.
Figure 9-1 shows the minimum required application circuit for the fixed output voltage versions, while Figure 9-2
shows the connections for complete processor control of the LM53601-Q1. Please refer to these figures while
following the design procedures. Table 9-2 provides an example of typical design requirements.
VPU
RPU
RESET
AGND
FB
EN
VSUPPLY
VIN
SYNC/
MODE
CIN
(Includes
Filter)
10 µF
LM53600
LM53601
(Fixed output
voltage)
CBIAS
0.01 µF
VCC
CVCC
1 µF
BOOT
CIN_HF
0.1 µF
GND
CBOOT
0.1 µF
SW
(DAP)
L1
4.7 µH
COUT (includes load)
• 20 µF
Figure 9-1. Off Battery, Automotive, Fixed Output Voltage, Buck, 2.1 MHz, Spread Spectrum
18
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VPU
RPU
RESET
BIAS
CBIAS
0.01 µF
RFBT
FB
EN
RFBB
VSUPPLY
LM53600
LM53601
(Adjustable)
VIN
SYNC/
MODE
CIN
(Includes
Filter)
10 µF
VCC
CVCC
1 µF
BOOT
CBOOT
0.1 µF
CIN_HF
0.1 µF
GND
SW
L1
(DAP)
4.7 µH (” 4.2 V output)
6.8 µH (> 4.2 V output)
COUT (includes load)
• 20 µF (” 4.2 V output)
• 30 µF (> 4.2 V output)
Figure 9-2. Off Battery, Automotive, Adjustable Output Voltage, Buck, 2.1 MHz, Spread Spectrum
9.2 Typical Applications
9.2.1 Off-Battery 5-V, 1-A Output Automotive Converter with Spread Spectrum
VPU
LM53601LQDSXRQ1
100k
AGND
RESET
FB
EN
CBIAS
0.01 µF
VBATT (6 V to 18 V, 42 V Max)
VIN
VCC
CVCC
CIN_HF
CIN2
4.7µF
CIN1
4.7µF
1 µF
SYNC/
MODE
BOOT
CBOOT
Typically
part of load
0.1 µF
0.1 µF
SW
GND
L1
4.7 µH
(DAP)
COUT1
COUT2
10 µF
10 µF
Figure 9-3. Typical LM53601LQDSXRQ1 Application Schematic
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9.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 9-1 as the input parameters.
Table 9-1. Design Parameters
DESIGN PARAMETER
Input voltage range
VALUE
COMMENT
6 V to 18 V with excursions to 42 V
This converter will run continuously up to 36 V
Fixed option used
Output voltage
5V
Output current range
No Load to 1 A
Light load mode
Switchable
Spread spectrum
Enabled
Factory option
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Inductor Selection
The LM53600-Q1 and LM53601-Q1 devices run in current mode and has internal compensation. This
compensation is stable with inductance between 4 µH and 10 µH. For most applications, 4.7 µH should be
used with fixed 5-V and 3.3-V versions of the LM53600-Q1 and LM53601-Q1 devices. The output inductor is
limited by current ripple while operating at high input voltage to a minimum rating of 4.7 µH for 3.3 V and
5-V fixed output devices. Since adjustable devices operate at the same frequency under high input voltage
conditions as devices set to deliver 3.3 V, inductor current ripple at high input voltages can become excessive
while using a 4.7µH while using an adjustable device that is delivering output voltage above 4.2 V. 6.8 µH is
recommended if an adjustable device is used to produce output voltage above 4.2 V. Not exceeding 6.8 µH is
recommended since use of large inductance causes poor transient load response. For the LM53601-Q1 (1-A
output), a saturation rating of about 2 A is recommended since this is the maximum current limit rating. Likewise,
a saturation current rating of about 1.5 A is recommended for the LM53600-Q1. See IL_HS in the data sheet.
Table 9-2. Output Inductor
PART TYPE
LM53601-Q1 3.3 V
and 5 V
RECOMMENDED
RECOMMENDED
MINIMUM SATURATION
(1)
INDUCTANCE RATING
CURRENT(2)
4.7 µH
about 2 A
LM53601-Q1 ADJ set 4.7 µH
to ≤ 4.2-V output
about 2 A
LM53601-Q1 ADJ set 6.8 µH
to > 4.2-V output
about 2 A
LM53600-Q1 3.3 V
and 5 V
4.7 µH
about 1.5 A
LM53600-Q1 ADJ set 4.7 µH
to ≤ 4.2-V output
about 1.5 A
LM53600-Q1 ADJ set 6.8 µH
to > 4.2-V output
about 1.5 A
(1)
(2)
COMMENT
6.8 µH works in systems with less demanding transient load
requirements
Up to 10 µH works in systems with less demanding transient
load requirements
The values shown in this table are standard inductance ratings. The LM53600-Q1/LM53601-Q1 tolerates reduced inductance due to
DC current and temperature.
The LM53600-Q1/LM53601-Q1 tolerates partial saturation of inductors (reduction of ~40% reduction of inductance of the current value
listed due to saturation. Partial saturation may reduce maximum current available at maximum voltage).
9.2.1.2.2 Output Capacitor Selection
The current mode control scheme of the LM53600-Q1 and LM53601-Q1 devices allows operation over a wide
range of output capacitance. A minimum of 10 µF is needed to ensure stability. Capacitance above 20 µF
is recommended to ensure load transient response typically desired in systems. 40 µF is recommended for
applications with demanding load transient requirements and for which Auto mode ripple is important. 40 µF also
aids devices with output voltage below 4-V transition into high voltage mode. Capacitance above 400 µF can
cause excessive current to be drawn during start up so is not recommended. These capacitance values include
load capacitance – only 10 µF is needed near to the LM53600-Q1 and LM53601-Q1 devices. Output capacitors
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should have low ESR to reduce output ripple. These capacitors should have at least X7R rating and should be of
automotive grade if used in automotive applications.
Table 9-3. Output Capacitor
RECOMMENDED
MINIMUM
TOTAL OUTPUT
CAPACITANCE
LM53600-Q1 AND LM53601-Q1
TYPE AND SYSTEM NEED
COMMENTS
LM53600-Q1 5 V
20 µF
Approximately 200-mV/A step load response with 1-µs rise/fall time.
LM53601-Q1 5 V with typical
system requirements
20 µF
Approximately 200-mV/A step load response with 1-µs rise/fall time.
LM53601-Q1 5V in high
performance systems
40 µF
Approximately 150-mV/A step load, approximately 20-mV maximum Auto mode
ripple
LM53600-Q1/LM53601-Q1 3.3 V
and adjustable parts with less
20 µF
than 4.2-V output setting with
typical system requirements
Approximately 200-mV/A step load response with 1µs rise/fall time, up to 60 mV of
ripple during transition into high voltage mode and in Auto mode.
LM53600-Q1/LM53601-Q1 3.3 V
and adjustable parts with less
40 µF
than 4.2 V in high performance
systems
Approximately 150-mV/A step load, approximately 30-mV maximum Auto mode
ripple, and 15-mV maximum HV mode transition ripple.
LM53600-Q1 ADJ set to greater
than 4.2-V output
Larger capacitance is necessitated by higher inductance needed.
40 µF
9.2.1.2.3 Input Capacitor Selection
Input capacitors serve two important functions: The first is to reduce input voltage ripple into the LM53601-Q1
and the input filter of the system. The second is to reduce high frequency noise. These two functions are
implemented most effectively with separate capacitors, see Table 9-4.
Table 9-4. Input Capacitor
CAPACITOR
CIN_HF
CIN
RECOMMENDED
VALUE
COMMENT
0.1 µF
This capacitor is used to suppress high frequency noise originating during switching events. It is
important to place capacitor as close to the LM53600-Q1 and LM53601-Q1 devices as design rules
allow. Position is more important than exact capacity. Once high frequency propagates into a system,
it can be hard to suppress or filter. Since this capacitor will be exposed to battery voltage in systems
that operate directly off of battery, 50 V or greater rating is recommended.
10 µF
This capacitance is used to suppress input ripple and transients due to output load transients. If
CIN is too small, input voltage may dip during load transients resetting the system if the system is
operated under low voltage conditions. 10 µF is intended to include all capacitance in the LM53600Q1/LM53601-Q1’s input node. 4.7 µF adjacent to the LM53600-Q1 and LM53601-Q1 devices is
recommended. Since this capacitor will be exposed to battery voltage in systems that operate directly
off of battery, 50 V or greater rating is recommended.
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Table 9-5 shows recommended capacitor values other than input and output capacitors.
Table 9-5. Other Capacitors
CAPACITOR
MINIMUM
VALUE
COMMENT
CBOOT
0.1 µF
While a voltage rating of only 5 V is necessary, using a higher voltage rating is recommended.
CVCC
1 µF
While a voltage rating of only 5 V is necessary, 16-V capacitors have a low voltage coefficient.
CBIAS
0.01 µF
This capacitor should be rated to survive output voltage.
Note that performance of converters utilizing an adjustable version of the LM53600-Q1 and LM53601-Q1
devices may be enhanced by adding CFF, a capacitor in parallel with RFBT. 100 pF is recommended.
9.2.1.2.4 FB Voltage Divider for Adjustable Versions
The adjustable version of the LM53600RB-Q1 and LM53601RB-Q1 devices regulates output voltage to a level
that results in the FB node being Vref which is approximately 1.0 V; see Section 7.5 Output voltage given a
specific feedback divider can be calculated using the following equation:
Output Voltage
Vref u
RFBB RFBT
RFBB
(2)
See typical applications schematic for adjustable versions of the LM53600-Q1 and LM53601-Q1 devices. Since
the value of RFBT is typically set by board leakage considerations, the above equation can be solved for RFBB,
the remaining unknown:
RFBB
Vref u RFBT
Output Voltage Vref
(3)
Note that typically, 100 kΩ is used for RFBT.
9.2.1.2.5 RPU - RESET Pull Up Resistor
While RESET is rated to sink up to 8 mA, under low, 1.5-V input voltage conditions, a low output level is only
ensured with loads of 50 µA. If accurate RESET output is needed with 1.5-V input voltage, 100 kΩ should be
used to pull up to 5 V, or a 66-kΩ resistor should be used when pulling up to a 3.3-V supply. If input voltage
is above 3.8 V, values as low as 10 kΩ or 6.6 kΩ can be used to pull up to 5 V or 3.3 V, respectively. Other
considerations, such as power consumption may increase any of the values listed above.
9.2.1.3 Application Curves
The following characteristics apply only to the circuit shown in Figure 9-3. These parameters are not tested and represent
typical performance only. Unless otherwise stated, the following conditions apply: VIN = 13.5 V, TA = 25°C.
22
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100
100
95
95
90
90
Efficiency (%)
Efficiency (%)
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85
80
75
Input Voltage
8V
13.5 V
18 V
36 V
70
65
0.2
Device type = 1 A
0.4
0.6
Output Current (A)
Mode = High
80
75
70
Input Voltage
8V
18 V
13.5 V
36 V
65
60
0.005
60
0
85
0.8
1
0.01
5-V Fixed Output
Device Type = 1 A
Mode = Auto
1
D002
5-V Fixed Output
Figure 9-5. Efficiency
Figure 9-4. Efficiency
5.1
800
5.05
600
Dropout (mV)
Output Voltage (V)
0.1
Output Current (A)
D001
5
4.95
400
200
Ambient
25 qC
125 qC
FPWM Mode
Auto Mode
4.9
0
0.2
0.4
0.6
Output Current (A)
Device Type = 1 A
0.8
0
1
0
0.2
0.4
0.6
Output Current (A)
D005
5-V Fixed Output
Device Type = 1 A
Figure 9-6. Load Regulation
5-V Fixed Output
92-mΩ Inductor
0.8
1
D007
Output = 4.85 V
Figure 9-7. Dropout Voltage
2.5
1.8
Switching Frequency (MHz)
1.6
1.4
Dropout (V)
1.2
1
0.8
0.6
0.4
Ambient
25 qC
125 qC
0.2
0
2
1.5
1
0.5
0
0
0.2
0.4
0.6
Output Current (A)
0.8
1
0
5
10
D009
Device Type = 1 A
5-V Fixed Output
92-mΩ inductor
Frequency drops to 1.85MHz
Figure 9-8. Entry into Dropout
Device Type = 1 A
15
20
25
Input Voltage (V)
5-V Fixed Output
Load = 500 mA
30
35
40
D011
Spread Spectrum
Figure 9-9. Frequency vs. Input Voltage
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SW (2 V/DIV)
SW (2 V/DIV)
Time (200 ns/DIV)
Time (1 Ps/DIV)
D019
Device Type = 1 A
Load = 10 mA
5-V Fixed Output
D020
Mode = Auto
Device Type = 1 A
Figure 9-10. SW Node Operation
Mode = Auto
5-V Fixed Output
Load = 500 mA
Figure 9-11. SW Node Operation
9.2.2 Off-Battery 3.3 V, 1 A Output Automotive Converter with Spread Spectrum
VPU
LM53601NQDSXRQ1
100k
AGND
RESET
FB
EN
CBIAS
0.01 µF
VBATT (4 V to 18 V, 42 V Max)
VIN
VCC
CVCC
CIN_HF
CIN2
4.7µF
CIN1
4.7µF
Typically part
of load
1 µF
SYNC/
MODE
BOOT
CBOOT
0.1 µF
0.1 µF
SW
GND
L1
4.7 µH
(DAP)
COUT1
COUT2
CLOAD
10 µF
10 µF
22 µF
Figure 9-12. Typical LM53601NQDSXRQ1 Application Schematic
9.2.2.1 Design Requirements
For this design example, use the parameters in Table 9-6 as the input parameters.
Table 9-6. Design Parameters
DESIGN PARAMETER
VALUE
COMMENT
Input voltage range
4 V to 18 V with excursions to 42 V
This converter will run continuously up to 36 V
Output voltage
3.3 V
Fixed option used
Output current range
No load to 1 A
Light load mode
Switchable
Spread spectrum
Enabled
24
Factory option
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9.2.2.2 Design Procedure
The same detailed design procedure as shown starting in section 7.1.2.1 is used to create the schematic
for this example. The most important difference is that the LM53601NQDSXRQ1 is used in place of the
LM53601LQDSXRQ1. In addition, more output capacitance is recommended for this option. Most output
capacitance will be part of the load and be used as input bypassing for the load.
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9.2.2.3 Application Curves
100
100
95
95
90
90
Efficiency (%)
Efficiency (%)
The following characteristics apply only to the circuit shown in Figure 9-12. These parameters are not tested and represent
typical performance only. Unless otherwise stated, the following conditions apply: VIN = 13.5 V, TA = 25°C.
85
80
75
Input Voltage
8V
13.5 V
18 V
36 V
70
65
0.2
Device Type = 1 A
0.4
0.6
Output Current (A)
Mode = FPWM
0.8
80
75
70
Input Voltage
8V
18 V
13.5 V
36 V
65
60
0
85
60
0.005
1
0.01
3.3-V Fixed Output
Device Type = 1 A
Figure 9-13. Efficiency
Mode = Auto
1
D004
3.3-V Fixed Output
Figure 9-14. Efficiency
3.366
800
3.333
600
Dropout (mV)
Output Voltage (V)
0.1
Output Current (A)
D003
3.3
400
200
3.267
Ambient
25 qC
125 qC
FPWM Mode
Auto Mode
0
3.234
0
0.2
0.4
0.6
Output Current (A)
Device Type = 1 A
0.8
0
1
0.2
D006
3.3-V Fixed Output
Device Type = 1 A
Figure 9-15. Load Regulation
0.4
0.6
Output Current (A)
0.8
1
D008
Output = 3.2 V
92-mΩ Inductor
3.3-V Fixed Output
Figure 9-16. Dropout Voltage
2.5
1.8
Switching Frequency (MHz)
1.6
1.4
Dropout (V)
1.2
1
0.8
0.6
0.4
Ambient
25 qC
125 qC
0.2
0
2
1.5
1
0.5
0
0
0.2
Device Type = 1 A
92-mΩ Inductor
0.4
0.6
Output Current (A)
0.8
1
0
5
D010
3.3-V Fixed Output
Frequency Drops to 1.85 MHz
Figure 9-17. Entry into Dropout
Device Type = 1 A
3.3-V Fixed Output
10
15
20
25
Input Voltage (V)
30
35
40
D012
Spread Spectrum
Load = 500 mA
Figure 9-18. Frequency vs. Input Voltage
9.3 Do's and Don't's
•
•
26
Don't: Exceed the Section 7.1.
Don't: Exceed the Section 7.2.
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•
•
•
•
•
•
SNAS660D – JUNE 2015 – REVISED MAY 2021
Don't: Exceed the Section 7.3.
Don't: Allow the EN, FPWM or SYNC input to float.
Don't: Allow the output voltage to exceed the input voltage, nor go below ground.
Don't: Use the thermal data given in the Thermal Information table to design your application.
Do: Follow all of the guidelines and/or suggestions found in this data sheet, before committing your design to
production. TI Application Engineers are ready to help critique your design and PCB layout to help make your
project a success.
Do: Refer to the helpful documents found in Table 11-1 and Table 11-2.
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10 Power Supply Recommendations
The LM53600-Q1 and LM53601-Q1 devices are designed for automotive direct off battery applications needing
minimal protection. Protection recommended includes reverse battery protection and EMI/ESD filtering. The
LM53600-Q1 and LM53601-Q1 devices are able to continue regulating during load dump with peak voltage less
than 42 V, double battery (jump start) conditions down to input voltage as low as VDROP above the selected
output voltage. In addition, the LM53600-Q1 and LM53601-Q1 devices continue to operate though may be out of
regulation with input voltage as low as 3.8 V. This allows the LM53600-Q1 and LM53601-Q1 devices to operate
through cranking in all but the most demanding systems.
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low ESR ceramic input
capacitors, can form an under-damped resonant circuit. This circuit may cause over-voltage transients at the VIN
pin, each time the input supply is cycled on and off. The parasitic resistance will cause the voltage at the VIN
pin to dip when the load on the regulator is switched on, or exhibits a transient. If the regulator is operating close
to the minimum input voltage, this dip may cause the device to shutdown and/or reset. The best way to solve
these kinds of issues is to reduce the distance from the input supply to the regulator and/or use an aluminum or
tantalum input capacitor in parallel with the ceramics. The moderate ESR of these types of capacitors will help to
damp the input resonant circuit and reduce any voltage overshoots. A value in the range of 20 µF to 100 µF is
usually sufficient to provide input damping and help to hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead
to instability, as well as some of the effects mentioned above, unless it is designed carefully. The Simple
Success with Conducted EMI for DC–DC Converters User's Guide (SNVA489) provides helpful suggestions
when designing an input filter for any switching regulator
In some cases, a Transient Voltage Suppressor (TVS) is used on the input of regulators. One class of this device
has a snap-back V-I characteristic (thyristor type). The use of a device with this type of characteristic is not
recommend. When the TVS fires, the clamping voltage drops to a very low value. If this holding voltage is less
than the output voltage of the regulator, the output capacitors will be discharged through the regulator back to
the input. This uncontrolled current flow could damage the regulator.
28
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11 Layout
11.1 Layout Guidelines
The following list is in order of importance starting with the most important item:•
•
•
•
•
•
•
•
•
•
Place high frequency input bypass capacitor, Cinhf, as close to the LM53600-Q1 and LM53601-Q1 devices
as possible.
Connect AGND and GND to the DAP immediately adjacent to the LM53600-Q1 and LM53601-Q1 devices.
Do not interrupt the ground plain under the loop containing the VIN and GND pins and Cinhf of the LM53600Q1 and LM53601-Q1 devices.
The boot capacitor, CBOOT, should be close to the LM53601-Q1 and the loop from the SW pin, through the
boot capacitor and into the BOOT pin should be kept as small as possible.
Keep the SW node as small as possible. It should be wide enough to carry the converter’s full current without
significant drop.
4.7 µF of bypassing should be close to the input of the LM53600-Q1 and LM53601-Q1 devices.
Place CVCC, the VCC pin’s bypass, and CBIAS, the bypass for FB for fixed voltage devices and BIAS for
adjustable devices as close to the LM53600-Q1 and LM53601-Q1 devices as possible.
The first output the trace from the output inductor to the output node should run by an output capacitor before
joining the rest of the output node.
Keep 10 µF close to the output (output inductor and GND) of the LM53600-Q1 and LM53601-Q1 devices.
Clear the layer beneath the SW node.
Table 11-1. PCB Layout Resources
TITLE
LINK
AN-1149 Layout Guidelines for Switching Power Supplies
SNVA021
AN-1229 Simple Switcher PCB Layout Guidelines
SNVA054
Constructing Your Power Supply- Layout Considerations
SLUP230
SNVA721 Low Radiated EMI Layout Made SIMPLE with LM4360x
and LM4600x
SNVA721
VIN
CIN
SW
GND
Figure 11-1. Current Loops with Fast Transients
11.1.1 Ground and Thermal Plane Considerations
As mentioned above, it is recommended to use one of the middle layers as a solid ground plane. A ground
plane provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the
control circuitry. The AGND and PGND pins should be connected to the ground plane using vias right next to
the bypass capacitors. PGND pins are connected to the source of the internal low side MOSFET switch. They
should be connected directly to the grounds of the input and output capacitors. The PGND net contains noise
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at the switching frequency and may bounce due to load variations. The PGND trace, as well as PVIN and SW
traces, should be constrained to one side of the ground plane. The other side of the ground plane contains much
less noise and should be used for sensitive routes.
It is recommended to provide adequate device heat sinking by utilizing the exposed pad (EP) of the IC as the
primary thermal path. Use a minimum 4 by 4 array of 10 mil thermal vias to connect the EP to the system ground
plane for heat sinking. The vias should be evenly distributed under the exposed pad. Use as much copper as
possible for system ground plane on the top and bottom layers for the best heat dissipation. It is recommended
to use a four-layer board with the copper thickness, starting from the top, as: 2 oz / 1 oz / 1 oz / 2 oz. A
four-layer board with enough copper thickness and proper layout provides low current conduction impedance,
proper shielding and lower thermal resistance.
Table 11-2. Resources for Thermal PCB Design
30
TITLE
LINK
AN-2020 Thermal Design By Insight, Not Hindsight
SNVA419
AN-1520 A Guide to Board Layout for Best Thermal Resistance for
Exposed Pad Packages
SNVA183
SPRA953B Semiconductor and IC Package Thermal Metrics
SPRA953
SNVA719 Thermal Design made Simple with LM43603 and
LM43602
SNVA719
SLMA002 PowerPAD™ Thermally Enhanced Package
SLMA002
SLMA004 PowerPAD Made Easy
SLMA004
SBVA025 Using New Thermal Metrics
SBVA025
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11.2 Layout Example
Figure 11-2. Fixed Output Version
Figure 11-2 shows an example layout for a fixed output version of the LM53600-Q1 and LM53601-Q1 similar
to the one used in the Rev A EVM. Note that the via next to CBIAS connects on the back side of the board to
VOUT near CO1. This layout shows 10 µF of output capacitance and 4.7 µF of input capacitance. An additional
>10 µF of output capacitance and about 4.7 µF of input capacitance is assumed to be elsewhere in the system.
A solid, unbroken ground plane is under this entire circuit except immediately below the SW node.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: LM53600-Q1 LM53601-Q1
31
LM53600-Q1, LM53601-Q1
www.ti.com
SNAS660D – JUNE 2015 – REVISED MAY 2021
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation request the following:
AN-1149 Layout Guidelines for Switching Power Supplies (SNVA021)
Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x (SNVA721)
Constructing Your Power Supply – Layout Considerations (SLUP230)
AN-1229 Simple Switcher PCB Layout Guidelines (SNVA054)
Using New Thermal Metrics (SBVA025)
PowerPAD Made Easy (SLMA004)
PowerPAD™ Thermally Enhanced Package (SLMA002)
Thermal Design made Simple with LM43603 and LM43602 (SNVA719)
Semiconductor and IC Package Thermal Metrics (SPRA953)
AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419)
AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages (SNVA183)
Simple Success with Conducted EMI for DC-DC Converters User's Guide (SNVA489)
EVM User's Guide for Adjustable Versions of the LM53600-Q1 and LM53601-Q1 (SNAU190)
EVM User's Guide for Fixed Versions of the LM53600-Q1 and LM53601-Q1 (SNAU191)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
PowerPAD™ are trademarks of TI.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
32
This glossary lists and explains terms, acronyms, and definitions.
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: LM53600-Q1 LM53601-Q1
LM53600-Q1, LM53601-Q1
www.ti.com
SNAS660D – JUNE 2015 – REVISED MAY 2021
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: LM53600-Q1 LM53601-Q1
33
PACKAGE OPTION ADDENDUM
www.ti.com
30-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM536003QDSXRQ1
ACTIVE
WSON
DSX
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
53603
LM536003QDSXTQ1
ACTIVE
WSON
DSX
10
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
53603
LM536005QDSXRQ1
ACTIVE
WSON
DSX
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
53605
LM536005QDSXTQ1
ACTIVE
WSON
DSX
10
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
53605
LM53600AQDSXRQ1
ACTIVE
WSON
DSX
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
5360A
LM53600AQDSXTQ1
ACTIVE
WSON
DSX
10
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
5360A
LM53600LQDSXRQ1
ACTIVE
WSON
DSX
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
5360L
LM53600LQDSXTQ1
ACTIVE
WSON
DSX
10
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
5360L
LM53600MQDSXRQ1
ACTIVE
WSON
DSX
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
5360M
LM53600MQDSXTQ1
ACTIVE
WSON
DSX
10
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
5360M
LM53600MQUDSXRQ1
ACTIVE
WSON
DSX
10
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 150
360MU
LM53600NQDSXRQ1
ACTIVE
WSON
DSX
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
5360N
LM53600NQDSXTQ1
ACTIVE
WSON
DSX
10
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
5360N
LM536013QDSXRQ1
ACTIVE
WSON
DSX
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
53613
LM536013QDSXTQ1
ACTIVE
WSON
DSX
10
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
53613
LM536013QUDSXRQ1
ACTIVE
WSON
DSX
10
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 150
3613U
LM536015QDSXRQ1
ACTIVE
WSON
DSX
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
53615
LM536015QDSXTQ1
ACTIVE
WSON
DSX
10
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
53615
LM536015QUDSXRQ1
ACTIVE
WSON
DSX
10
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 150
3615U
LM53601AQDSXRQ1
ACTIVE
WSON
DSX
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
5361A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
30-Oct-2021
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM53601AQDSXTQ1
ACTIVE
WSON
DSX
10
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
5361A
LM53601LQDSXRQ1
ACTIVE
WSON
DSX
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
5361L
LM53601LQDSXTQ1
ACTIVE
WSON
DSX
10
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
5361L
LM53601MQDSXRQ1
ACTIVE
WSON
DSX
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
5361M
LM53601MQDSXTQ1
ACTIVE
WSON
DSX
10
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
5361M
LM53601MQUDSXRQ1
ACTIVE
WSON
DSX
10
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 150
361MU
LM53601NQDSXRQ1
ACTIVE
WSON
DSX
10
3000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
5361N
LM53601NQDSXTQ1
ACTIVE
WSON
DSX
10
250
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
5361N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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