LM6584
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SNOSA44C – MAY 2003 – REVISED MARCH 2013
LM6584 TFT-LCD Quad, 13V RRIO High Output Current Operational Amplifier
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FEATURES
APPLICATIONS
•
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1
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•
•
•
•
•
•
•
•
•
•
•
(VS = 5V, TA = 25°C Typical Values Unless
Specified)
Input Common Mode Voltage 0.5V Beyond
Rails
Output Voltage Swing (RL = 2kΩ) 50mV from
Rails
Output Short Circuit Current +310/−410mA
Continuous Output Current 75mA
Supply Current (Per Amp, No Load) 750μA
Supply Voltage Range 5V to 13V
Unity Gain Stable
−3dB Bandwidth (AV = +1) 24MHz
Slew Rate 11V/μSec
Settling Time 270ns
SOIC and TSSOP Package
Manufactured in Texas Instruments' State-ofthe-Art Bonded Wafer, Trench Isolated
Complementary Bipolar VIP10 Technology for
High Performance at Low Power Levels
LCD Panel VCOM Driver
LCD Panel Gamma Buffer
LCD Panel Repair Amp
DESCRIPTION
The LM6584 is a low power, high voltage, rail-to-rail
input-output amplifier ideally suited for LCD panel
VCOM driver and gamma buffer applications. The
LM6584 contains four unity gain stable amplifiers in
one package. It provides a common mode input
ability of 0.5V beyond the supply rails, as well as an
output voltage range that extends to within 50mV of
either supply rail. With these capabilities, the LM6584
provides maximum dynamic range at any supply
voltage. Operating on supplies ranging from 5V to
13V, while consuming only 750μA per amplifier, the
LM6584 has a bandwidth of 24MHz (−3dB).
The LM6584 also features fast slewing and settling
times, along with a high continuous output capability
of 75mA. This output stage is capable of delivering
approximately 310mA peak currents in order to
charge or discharge capacitive loads. These features
are ideal for use in TFT-LCDs.
The LM6584 is available in the industry standard 14pin SOIC package and in the space-saving 14-pin
TSSOP package. The amplifiers are specified for
operation over the full −40°C to +85°C temperature
range.
300:
MEASURE
CURRENT
3k:
6.5V
10:
+
10:
10:
10:
+2.5V
-6.5V
10nF
10nF
10nF
10nF
MEASURE
VOLTAGE
-2.5V
±2.5V
SQUARE WAVE
Figure 1. Test Circuit Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
LM6584
SNOSA44C – MAY 2003 – REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
ESD Tolerance (3)
Human Body Model
Machine Model
2KV
200V
Supply Voltage (V+ - V−)
14V
Differential Input Voltage
±5.5V
Output Short Circuit to Ground (4)
Continuous
Storage Temperature Range
−65°C to 150°C
Input Common Mode Voltage
V− to V+
Junction Temperature
(1)
(2)
(3)
(4)
(5)
(5)
150°C
Absolute maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
For testing purposes, ESD was applied using human body model, 1.5kΩ in series with 100pF.
Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C
The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
Operating Ratings (1)
5V ≤ VS ≤ 13V
Supply Voltage
−40°C to +85°C
Temperature Range
Thermal Resistance (θJA)
(1)
2
SOIC
145°C/W
TSSOP
155°C/W
Absolute maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
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13V DC Electrical Characteristics (1)
Unless otherwise specified, all limits ensured for at TJ = 25°C, VCM = ½VS and RL = 2kΩ. Boldface limits apply at the
temperature extremes.
Symbol
Parameter
VOS
Input Offset Voltage
TC VOS
Input Offset Voltage Average
Drift
IB
Input Bias Current
IOS
Input Offset Current
RIN
Input Resistance
CMRR
Common Mode Rejection Ratio
Conditions
Min
(2)
Typ
Max
Units
0.7
4
6
mV
(3)
5
±1
±7
16
150
300
Common Mode
20
Differential Mode
0.5
VCM = 0 to +13V
75
70
103
VCM = 0 to 11.5V
78
72
103
75
70
103
Power Supply Rejection Ratio
VCM = ±1V
CMVR
Input Common-Mode Voltage
Range
CMRR > 50dB
AV
Large Signal Voltage Gain (4)
RL = 2kΩ, VO = 0.5 to +12.5V
VO
Output Swing High (5)
RL = 2kΩ
Output Swing Low (5)
RL = 2kΩ
Output Short Circuit Current (6)
Sourcing
200
320
Sinking
200
420
ICONT
IS
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Continuous Output Current (7)
13.2
0
13
78
72
108
12.85
12.7
12.9
μA
nA
MΩ
dB
dB
−0.2
V
dB
V
0.55
Sourcing
75
Sinking
75
Supply Current (per Amp)
μV/°C
−0.3/+0.3
PSRR
ISC
(2)
780
0.150
mA
mA
1100
1350
μA
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA. See applications section for information on temperature de-rating of this device.
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Large signal voltage gain is the total output swing divided by the input signal required to produce that swing.
The open loop output current is ensured, by the measurement of the open loop output voltage swing.
Continuous operation at these output currents will exceed the power dissipation ability of the device
Power dissipation limits may be exceeded if all four amplifiers source or sink 75mA. Voltage across the output transistors and their
output currents must be taken into account to determine the power dissipation of the device
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13V AC Electrical Characteristics (1)
Unless otherwise specified, all limits ensured for at TJ = 25°C, VCM = ½VS and RL = 2kΩ. Boldface limits apply at the
temperature extremes.
Symbol
Parameter
Slew Rate (4)
SR
Conditions
AV = +1, VIN = 10VPP
Min
(2)
8
Unity Gain Bandwidth Product
−3dB Frequency
AV = +1
10
Typ
(3)
Max
(2)
Units
15
V/μs
15.4
MHz
24
MHz
61
deg
ns
Φm
Phase Margin
ts
Settling Time (0.1%)
AV = −1, AO = ±5V, RL = 500Ω
780
tp
Propagation Delay
AV = −2, VIN = ±5V, RL = 500Ω
20
ns
HD2
2nd Harmonic Distortion
FIN = 1MHz (5)
VOUT = 2VPP
−53
dBc
HD3
3rd Harmonic Distortion
FIN = 1MHz (5)
VOUT = 2VPP
−40
dBc
en
Input-Referred Voltage Noise
f = 10kHz
23
nV/√Hz
(1)
(2)
(3)
(4)
(5)
4
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA. See applications section for information on temperature de-rating of this device.
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Slew Rate is the average of the raising and falling slew rates.
Harmonics are measured with AV = +2 and RL = 100Ω and VIN = 1VPP to give VOUT = 2VPP.
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5V DC Electrical Characteristics (1)
Unless otherwise specified, all limits ensured for at TJ = 25°C, VCM = ½VS and RL = 2kΩ. Boldface limits apply at the
temperature extremes.
Symbol
Parameter
Conditions
Min
(2)
Typ
Max
Units
4
6
mV
(3)
VOS
Input Offset Voltage
0.7
TC VOS
Input Offset Voltage Average
Drift
10
IB
Input Bias Current
IOS
Input Offset Current
RIN
Input Resistance
CMRR
Common Mode Rejection Ratio
±1
±7
μA
20
150
300
nA
20
Differential Mode
0.5
VCM Stepped from 0 to 5V
72
68
105
VCM Stepped from 0 to 3.5V
75
70
105
75
70
92
PSRR
Power Supply Rejection Ratio
VS = VCC = 3.5V to 5.5V
CMVR
Input Common-Mode Voltage
Range
CMRR > 50dB
AV
Large Signal Voltage Gain (4)
RL = 2kΩ, VO = 0 to 5V
VO
Output Swing High
RL = 2kΩ
Output Swing Low
RL = 2kΩ
0.2
Output Short Circuit Current (5)
Sourcing
310
Sinking
400
Sourcing
75
Sinking
75
ISC
ICONT
IS
(1)
(2)
(3)
(4)
(5)
(6)
Continuous Output Current (6)
Supply Current (per Amp)
μV/°C
−0.3/+0.3
Common Mode
5.2
(2)
MΩ
dB
dB
−0.2
0.0
5.0
70
65
106
4.85
4.7
4.9
V
dB
V
750
0.15
mA
mA
1000
1250
μA
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA. See applications section for information on temperature de-rating of this device.
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Large signal voltage gain is the total output swing divided by the input signal required to produce that swing.
Continuous operation at these output currents will exceed the power dissipation ability of the device
Power dissipation limits may be exceeded if all four amplifiers source or sink 75mA. Voltage across the output transistors and their
output currents must be taken into account to determine the power dissipation of the device
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5V AC Electrical Characteristics (1)
Unless otherwise specified, all limits ensured for at TJ = 25°C, VCM = ½VS and RL = 2kΩ. Boldface limits apply at the
temperature extremes.
Symbol
Parameter
Conditions
Slew Rate (4)
SR
Min
(2)
AV = +1, VIN = 3.5VPP
Unity Gain Bandwidth Product
−3dB Frequency
AV = +1
Typ
(3)
Max
(2)
Units
11
V/μs
15.3
MHz
24
MHz
56
deg
ns
Φm
Phase Margin
ts
Settling Time (0.1%)
AV = −1, VO = ±1V, RL = 500Ω
270
tp
Propagation Delay
AV = −2, VIN = ±1V, RL = 500Ω
21
ns
HD2
2nd Harmonic Distortion
FIN = 1MHz (5)
VOUT = 2VPP
−53
dBc
HD3
3rd Harmonic Distortion
FIN = 1MHz (5)
VOUT = 2VPP
−40
dBc
en
Input-Referred Voltage Noise
f = 10kHz
23
nV/√Hz
(1)
(2)
(3)
(4)
(5)
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA. See applications section for information on temperature de-rating of this device.
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Slew Rate is the average of the raising and falling slew rates.
Harmonics are measured with AV = +2 and RL = 100Ω and VIN = 1VPP to give VOUT = 2VPP.
Connection Diagram
1
14
2
13
3
12
4
11
OUT A
IN A-
OUT D
IN DIN D+
IN A+
V
+
5
10
6
9
7
8
IN C+
IN B+
IN B-
-
V
IN COUT C
OUT B
Figure 2. 14-Pin SOIC or TSSOP (Top View)
See D or PW Package
6
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Typical Performance Characteristics
Unless otherwise specified, all limits ensured for TJ = 25°C, VCM = 1/2VS and RL = 2kΩ.
Gain Phase vs. Temperature
100
90
90
90
80
80
-40°C
25°C
40
40
30
30
85°C
10
10
0
-10
0
-10
-20
100M
-20
VS = 5V
-20
1M
10M
100k
FREQUENCY (Hz)
40
20
0
-10
VS = 13V
1M
100k
10k
Figure 4.
90
90
90
80
80
PHASE
70
70
60
60
0pF
50
40
10pF
30
30pF
10
0
-10
0pF
VS = 5V
-20
10k
50
1M
100k
10M
GAIN (dB)
70
60
PHASE (°)
GAIN (dB)
Gain Phase vs. Capacitive Loading
100
20
100
90
PHASE
80
0pF
50
GAIN
40
10pF
30pF
20
20
10
10
0
-10
0
-10
-20
100M
-20
20
10
VS = 13V
10k
0pF
1M
100k
10M
0
-10
-20
100M
FREQUENCY (Hz)
Figure 6.
PSRR
PSRR
110
110
100
100
90
90
+PSRR
+PSRR
80
PSRR (dB)
80
PSRR (dB)
40
30
30
Figure 5.
70
-PSRR
60
50
70
-PSRR
60
50
40
40
30
30
10
10
70
60
50
FREQUENCY (Hz)
20
-20
100M
10M
FREQUENCY (Hz)
100
GAIN
10
-40°C
Gain Phase vs. Capacitive Loading
30
30
85°C
100
40
50
25°C
Figure 3.
80
60
GAIN
30
10
70
-40°C
40
20
-40°C
80
50
20
20
10k
60
50
GAIN
0
-10
70
60
90
85°C
PHASE
PHASE (°)
50
70
GAIN (dB)
70
60
PHASE (°)
85°C
PHASE
100
PHASE (°)
100
80
GAIN (dB)
Gain Phase vs. Temperature
100
20
VS = 5V
1k
100k
10M
FREQUENCY (Hz)
10
10
VS = 13V
1k
1M
10M
FREQUENCY (Hz)
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, VCM = 1/2VS and RL = 2kΩ.
CMRR
CMRR
120
120
VS = 5V
VS = 13V
110
100
100
90
90
CMRR (dB)
CMRR (dB)
110
80
70
80
70
60
60
50
50
40
40
30
30
10
1k
1M
10
10M
1k
FREQUENCY (Hz)
10M
Figure 9.
Figure 10.
Settling Time vs. Input Step Amplitude (Output Slew and
Settle Time)
Settling Time vs. Capacitive Loading (Output Slew and
Settle Time)
300
1200
RL = 2k:
RL = 2k:
0.1% SETTLING TIME (nS)
0.1% SETTLING TIME(nS)
250
200
150
100
50
0
0.5
1000
800
600
400
200
0
0.75
1
1.25
1.5
1.75
2
0
10
20
Figure 11.
50
60
70
80
Input Voltage Noise vs. Frequency
110
1000
Hz)
100
INPUT VOLTAGE NOISE (nV/
90
CT REJECTION (dB)
40
Figure 12.
Crosstalk Rejection vs. Frequency (Output to Output)
80
70
60
50
40
30
20
10
10
30
CAPACITIVE LOADING (pF)
INPUT STEP AMPLITUDE (VPP)
100
10
1
1k
100k
FREQUENCY (Hz)
10M
1
10
100
1k
10k
1M
FREQUENCY (Hz)
Figure 13.
8
1M
FREQUENCY (Hz)
Figure 14.
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Typical Performance Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, VCM = 1/2VS and RL = 2kΩ.
Stability vs. Capacitive Load Unity Gain, VS = 13V
Large Signal Step Response
1M
VS = 12V
VO = 2VPP
100k
CAP LOAD (pF)
AV = -1, RL = 2k:
10k
UNSTABLE
1k
100
10
25% OVERSHOOT
1
-5
-4
-3
-2
-1
0
1
2
3
4
1V/DIV
5
100ns/DIV
VOUT (V)
Figure 15.
Figure 16.
Small Signal Step Response
Small Signal Step Response
VS = 12V
VS = 12V
VO = 100mVPP
VO = 100mVPP
AV = +1, RL = 2k:
AV = -1, RL = 2k:
50mV/DIV
100ns/DIV
50mV/DIV
100ns/DIV
Figure 17.
Figure 18.
Closed Loop Output Impedance vs. Frequency
ISUPPLY vs. Common Mode Voltage
1000
4
VS = ±5V
AV = +1
85°C
100
3.5
ISUPPY (mA)
ZOUT (:)
10
1
25°C
3
0.1
2.5
-40°C
0.01
2
0.001
10
1k
1M
10M
-7
-5
-3
-1
1
3
5
7
COMMON MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, VCM = 1/2VS and RL = 2kΩ.
VOS vs. Common Mode Voltage
VOS vs. VOUT (Typical Unit)
1
1
VS = 13V
0.5
85°C
VOS (mV)
0.5
VOS (mV)
VS = 10V
0.75
-40°C
0
0.25
85°C
0
-0.25
25°C
-0.5
-0.5
25°C
-40°C
-0.75
-1
-1
-7
-5
-3
-1
1
3
-7 -6 -5 -4 -3 -2 -1 0 1 2
7
5
COMMON MODE VOLTAGE (V)
Figure 21.
Figure 22.
VOUT from V− vs. ISINK
VOUT from V+ vs. ISOURCE
10
VOUT FROM V (V)
10
1
1
-
+
VOUT FROM V (V)
3 4 5 6 7
VOUT (V)
85°C
25°C
0.1
-40°C
85°C
0.1
-40°C
25°C
0.01
0.01
1
10
100
1000
1
10
ISOURCE (mA)
100
1000
ISINK (mA)
Figure 23.
Figure 24.
ISUPPLY vs. Supply Voltage
4
85°C
ISUPPLY (mA)
3.5
25°C
3
2.5
-40°C
2
4
6
8
10
12
14
16
VSUPPLY (V)
Figure 25.
10
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APPLICATION NOTES
CIRCUIT DESCRIPTION
GENERAL & SPEC
The LM6584 is a bipolar process operational amplifier. It has an exceptional output current capability of 330mA.
The part has both rail to rail inputs and outputs. It has a −3dB bandwidth of 24MHz. The part has input voltage
noise of 23nV/√Hz, and 2nd and 3rd harmonic distortion of −53dB and −40dB respectively.
INPUT SECTION
The LM6584 has rail to rail inputs and thus has an input range over which the device may be biased of V− minus
0.5V, and V+ plus V. The ultimate limit on input voltage excursion is the ESD protection diodes on the input pins.
The most important consideration in Rail-to-Rail input op amps is to understand the input structure. Most Rail-toRail input amps use two differential input pairs to achieve this function. This is how the LM6584 works. A
conventional PNP differential transistor pair provides the input gain from 0.5V below the negative rail to about
one volt below the positive rail. At this point internal circuitry activates a differential NPN transistor pair that
allows the part to function from 1 volt below the positive rail to 0.5V above the positive rail. The effect on the
inputs pins is as if there were two different op amps connected to the inputs. This has several unique
implications.
• The input offset voltage will change, sometimes from positive to negative as the inputs transition between the
two stages at about a volt below the positive rail. this effect is seen in the VOS vs. VCM chart in the Typical
Performance Characteristics section of this datasheet.
• The input bias currents can be either positive or negative. Do not expect a consistent flow in or out of the
pins.
• The part will have different specifications depending on whether the NPN or PNP stage is operating.
• There is a little more input capacitance then a single stage input although the ESD diodes often swamp out
the added base capacitance.
• Since the input offset voltages can change from positive to negative the output may not be monotonic when
the inputs are transitioning between the two stages and the part is in a high gain configuration.
It should be remembered that swinging the inputs across the input stage transition may cause output distortion
and accuracy anomalies. It is also worth noting that anytime any amps inputs are swung near the rails THD and
other specs are sure to suffer.
OUTPUT SECTION
Current Rating
The LM6584 has an output current rating, sinking or sourcing, of 300mA. The LM6584 is ideally suited to loads
that require a high value of peak current but only a reduced value of average current. This condition is typical of
driving the gate of a MOSFET. While the output drive rating is 300mA peak, and the output structure supports
rail-to-rail operation, the attainable output current is reduced when the gain and drive conditions are such that the
output voltage approaches either rail.
Output Power
Because of the increased output drive capability, internal heat dissipation must be held to a level that does not
increase the junction temperature above its maximum rated value of 150° C.
Power Requirements
The LM6584 operates from a voltage supply, of V+ and ground, or from a V− and V+ split supply. Single-ended
voltage range is +5V to +13V and split supply range is ±2.5V to ±6.5V.
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APPLICATION HINTS
POWER SUPPLIES
Sequencing
Best practice design technique for operational amplifiers includes careful attention to power sequencing.
Although the LM6584 is a bipolar op amp, recommended op amp turn on power sequencing of ground (or V−),
followed by V+, followed by input signal should be observed. Turn off power sequence should be the reverse of
the turn-on sequence. Depending on how the amp is biased the outputs may swing to the rails on power-on or
power-off. Due to the high output currents and rail to rail output stage in the LM6584 the output may oscillate
very slightly if the power is slowly raised between 2V and 4V The part is unconditionally stable at 5V. Quick turnoff and turn-on times will eliminate oscillation problems.
PSRR and Noise
Care should be taken to minimize the noise in the power supply rails. The figure of merit for an op amp’s ability
to keep power supply noise out of the signal is called Power Supply Rejection Ratio (PSRR). Observe from the
PSRR charts in the Typical Performance Characteristics section that the PSRR falls of dramatically as the
frequency of the noise on the power supply line goes up. This is one of the reasons switching power supplies
can cause problems. It should also be noticed from the charts that the negative supply pin is far more susceptible
to power noise. The design engineer should determine the switching frequencies and ripple voltages of the
power supplies in the system. If required, a series resistor or in the case of a high current op amp like the
LM6584, a series inductor can be used to filter out the noise.
Transients
In addition to the ripple and noise on the power supplies there are also transient voltage changes. This can be
caused by another device on the same power supply suddenly drawing current or suddenly stopping a current
draw. The design engineer should insure that there are no damaging transients induced on the power supply
lines when the op amp suddenly changes current delivery.
LAYOUT
Ground Planes
Do not assume the ground (or more properly, the common or return) of the power supply is an ocean of zero
impedance. The thinner the trace, the higher the resistance. Thin traces cause tiny inductances in the power
lines. These can react against the large currents the LM6584 is capable of delivering to cause oscillations,
instability, overshoot and distortion. A ground plane is the most effective way of insuring the ground is a uniform
low impedance. If a four layer board cannot be used, consider pouring a plane on one side of a two layer board.
If this cannot be done be sure to use as wide a trace as practicable and use extra decoupling capacitors to
minimize the AC variations on the ground rail.
Decoupling
A high-speed, high-current amp like the LM6584 must have generous decoupling capacitors. They should be as
close to the power pins as possible. Putting them on the back side opposite the power pins may give the tightest
layout. If ground and power planes are available, the placement of the decoupling caps are not as critical.
Breadboards
The high currents and high frequencies the LM6584 operates at, as well as thermal considerations, require that
prototyping of the design be done on a circuit board as opposed to a “Proto-Board” style breadboard.
STABILITY
General
High speed parts with large output current capability require special care to insure lack of oscillations. Keep the
“+” pin isolated from the output to insure stability. As noted above care should be take to insure the large output
currents do not appear in the ground or ground plane and then get coupled into the “+” pin. As always, good tight
layout is essential as is adequate use of decoupling capacitors on the power supplies.
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Unity Gain
The unity gain or voltage-follower configuration is the most subject to oscillation. If a part is stable at unity gain it
is almost certain to work in other configurations. In certain applications where the part is setting a reference
voltage or is being used as a buffer greater stability can be achieved by configuring the part as a gain of −1 or −2
or +2.
Phase Margin
The phase margin of an op amps gain-phase plot is an indication of the stability of the amp. It is desirable to
have at least 45°C of phase margin to insure stability in all cases. The LM6584 has 60°C of phase margin even
with it’s large output currents and Rail-to-Rail output stage, which are generally more prone to stability issues.
Capacitive Load
The LM6584 can withstand 30pF of capacitive load in a unity gain configuration before stability issues arise. At
very large capacitances, the load capacitor will attenuate the gain like any other heavy load and the part
becomes stable again. The LM6584 will be stable at 330nF and higher load capacitance. Refer to the chart in the
Typical Performance Characteristics section.
OUTPUT
Swing vs. Current
The LM6584 will get to about 25mV or 30mV of either rail when there is no load. The LM6584 can sink or source
hundreds of milliamperes while remaining less then 0.5V away from the rail. It should be noted that if the outputs
are driven to the rail and the part can no longer maintain the feedback loop, the internal circuitry will deliver large
base currents into the huge output transistors, trying to get the outputs to get past the saturation voltage. The
base currents will approach 16 milliamperes and this will appear as an increase in power supply current.
Operating at this power dissipation level for extended periods will damage the part, especially in the higher
thermal resistance TSSOP package. Because of this phenomenon, unused parts should not have the inputs
strapped to either rail, but should have the inputs biased at the midpoint or at least a diode drop (0.6V) within the
rails.
Self Heating
As discussed above the LM6584 is capable of significant power by virtue of its 300mA current handling
capability. A TSSOP package cannot sustain these power levels for more then a brief period.
TFT Display Application
INTRODUCTION
In today’s high-resolution TFT displays, op amps are used for the following three functions:
1. VCOM Driver
2. Gamma Buffer
3. Panel Repair Buffer
All of these functions utilize op amps as non-inverting, unity-gain buffers. The VCOM Driver and Gamma Buffer
are buffers that supply a well regulated DC voltage. A Panel Repair Buffer, on the other hand, provides a high
frequency signal that contains part of the display’s visual image.
In an effort to reduce production costs, display manufacturers use a minimum variety of different parts in their
TFT displays. As a result, the same type of op amp will be used for the VCOM Driver, Gamma Buffer, and Panel
Repair Buffer. To perform all these functions, such an op amp must have the following characteristics:
1. Large output current drive
2. Rail to rail input common mode range
3. Rail to rail output swing
4. Medium speed gain bandwidth and slew rate
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The LM6584 meets these requirements. It has a rail-to-rail input and output, typical gain bandwidth and slew rate
of 15MHz and 15V/μs, and it can supply up to 320mA of output current. The following sections will describe the
operation of VCOM Drivers, Gamma Buffers, and Panel Repair Buffers, showing how the LM6584 is well suited for
each of these functions.
BRIEF OVERVIEW OF TFT DISPLAY
To better understand these op amp applications, let’s first review a few basic concepts of how a TFT display
operates. Figure 26 is a simplified illustration of an LCD pixel. The top and bottom plates of each pixel consist of
Indium-Tin oxide (ITO), which is a transparent, electrically conductive material. ITO lies on the inner surfaces of
two glass substrates that are the front and back glass panels of a TFT display. Sandwiched between the two ITO
plates is an insulating material (liquid crystal) that alters the polarization of light to a lesser a greater amount,
depending on how much voltage (VPIXEL) is applied across the two plates. Polarizers are placed on the outer
surfaces of the two glass substrates, which in combination with the liquid crystal create a variable light filter that
modulates light transmitted from the back to the front of a display. A pixel’s bottom plate lies on the backside of a
display where a light source is applied, and the top plate lies on the front, facing the viewer. On a Twisted
Neumatic (TN) display, which is typical of most TFT displays, a pixel transmits the greatest amount of light when
VPIXEL is less ±0.5V, and it becomes less transparent as this voltage increases with either a positive or negative
polarity. In short, an LCD pixel can be thought of as a capacitor, through which, a controlled amount of light is
transmitted by varying VPIXEL.
TRANSMITTED LIGHT
POLARIZER
GLASS
SUBSTRATE
TOP ITO
PLATE
LIQUID CRYSTAL
MATERIAL
BOTTOM ITO
PLATE
GLASS
SUBSTRATE
VPIXEL
± POLARITY
POLARIZER
LIGHT SOURCE
Figure 26. Individual LCD Pixel
ROW DRIVERS
COLUMN DRIVERS
CSTRAY
CSTRAY
CSTRAY
VCOM
VCOM
VCOM
PIXEL
PIXEL
PIXEL
APPROX
VDD/2
+
-
TFT-LCD PANEL
VCOM
VCOM DRIVER
Figure 27. TFT Display
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Figure 27 is a simplified block diagram of a TFT display, showing how individual pixels are connected to the row,
column, and VCOM lines. Each pixel is represented by capacitor with an NMOS transistor connected to its top
plate. Pixels in a TFT panel are arranged in rows and columns. Row lines are connected to the NMOS gates,
and column lines to the NMOS sources. The back plate of every pixel is connected to a common voltage called
VCOM. Pixel brightness is controlled by voltage applied to the top plates, and the Column Drivers supply this
voltage via the column lines. Column Drivers ‘write’ this voltage to the pixels one row at a time, and this is
accomplished by having the Row Drivers select an individual row of pixels when their voltage levels are
transmitted by the Column Drivers. The Row Drivers sequentially apply a large positive pulse (typically 25V to
35V) to each row line. This turns-on NMOS transistors connected to an individual row, allowing voltages from the
column lines to be transmitted to the pixels.
VCOM DRIVER
The VCOM driver supplies a common voltage (VCOM) to all the pixels in a TFT panel. VCOM is a constant DC
voltage that lies in the middle of the column drivers’ output voltage range. As a result, when the column drivers
write to a row of pixels, they apply voltages that are either positive or negative with respect to VCOM. In fact, the
polarity of a pixel is reversed each time its row is selected. This allows the column drivers to apply an alternating
voltage to the pixels rather than a DC signal, which can ‘burn’ a pattern into an LCD display.
When column drivers write to the pixels, current pulses are injected onto the VCOM line. These pulses result from
charging stray capacitance between VCOM and the column lines (see Figure 27), which ranges typically from
16pF to 33pF per column. Pixel capacitance contributes very little to these pulses because only one pixel at a
time is connected to a column, and the capacitance of a single pixel is on the order of only 0.5pF. Each column
line has a significant amount of series resistance (typically 2kΩ to 40kΩ), so the stray capacitance is distributed
along the entire length of a column. This can be modeled by the multi-segment RC network shown in Figure 28.
The total capacitance between VCOM and the column lines can range from 25nF to 100nF, and charging this
capacitance can result in positive or negative current pulses of 100mA, or more. In addition, a similar distributed
capacitance of approximately the same value exists between VCOM and the row lines. Therefore, the VCOM
driver’s load is the sum of these distributed RC networks with a total capacitance of 50nF to 200nF, and this load
can modeled like the circuit in Figure 28.
R
R
C
C
R
R
R
VCOM
C
C
C
COLUMN
LINE
Figure 28. Model of Impedance between VCOM and Column Lines
A VCOM driver is essentially a voltage regulator that can source and sink current into a large capacitive load. To
simplify the analysis of this driver, the distributed RC network of Figure 28 has been reduced to a single RC load
in Figure 29. This load places a large capacitance on the VCOM driver output, resulting in an additional pole in the
op amp’s feedback loop. However, the op amp remains stable because CLOAD and RESR create a zero that
cancels the effect of this pole. The range of CLOAD is 50nF to 200nF and RESR is 20Ω to 100Ω, so this zero will
have a frequency in the range of 8KHz to160KHz, which is much lower than the gain bandwidth of most op
amps. As a result, the VCOM load adds very little phase lag when op amp loop gain is unity, and this allows the
VCOM Driver to remain stable. This was verified by measuring the small-signal bandwidth of the LM6584 with the
RC load of Figure 29. When driving an RC load of 50nF and 20Ω, the LM6584 has a unity gain frequency of
6.12MHz with 41.5°C of phase margin. If the load capacitor is increased to 200nF and the resistance remains
20Ω, the unity gain frequency is virtually unchanged: 6.05MHz with 42.9°C of phase margin.
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VCOM LOAD
VCOM DRIVER
APPROX
VDD/2
VCOM
+
-
CLOAD
50 - 200nF
RESR
20 - 100:
Figure 29. VCOM Driver with Simplified Load
A VCOM Driver’s large-signal response time is determined by the op amp’s maximum output current, not by its
slew rate. This is easily shown by calculating how much output current is required to slew a 50nF load
capacitance at the LM6584 slew rate of 14V/μs:
IOUT = 14V/μs x 50nF = 700mA
(1)
700mA exceeds the maximum current specification for the LM6584 and almost all other op amps, confirming that
a VCOM driver’s speed is limited by its peak output current. In order to minimize VCOM transients, the op amp used
as a VCOM Driver must supply large values of output current.
RF2
300:
RF1
3k:
VCOM
VCOM LOAD
+6.5V
-
RS
10:
RL1
10:
RL2
10:
RL3
10:
C2
10nF
C3
10nF
C4
10nF
+
-6.5V
IOUT
C1
10nF
VSW
5V
0V
Figure 30. VCOM Driver Test Circuit
Figure 30 is a common test circuit used for measuring VCOM driver response time. The RC network of RL1 to RL3
and C1 to C4 models the distributed RC load of a VCOM line. This RC network is a gross simplification of what the
actual impedance is on a TFT panel. However, it does provide a useful test for measuring the op amp’s transient
response when driving a large capacitive load. A low impedance MOSFET driver applies a 5V square wave to
VSW, generating large current pulses in the RC network. Scope photos from this circuit are shown in Figure 31
and Figure 32. Figure 31 shows the test circuit generates positive and negative voltage spikes with an amplitude
of ±3.2V at the VCOM node, and both transients settle-out in approximately 2μs. As mentioned before, the speed
at which these transients settle-out is a function of the op amp’s peak output current. The IOUT trace in Figure 32
shows that the LM6584 can sink and source peak currents of −310mA and 320mA. This ability to supply large
values of output current makes the LM6584 extremely well suited for VCOM Driver applications.
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(2V/DIV)
(5V/DIV)
www.ti.com
VSW
VCOM
2PSec/DIV
(200 mA/DIV)
(5 V/DIV)
Figure 31. VSW and VCOM Waveforms from VCOM
VSW
ICOM
2 PSec/DIV
Figure 32. VSW and IOUT Waveforms from VCOM Test Circuit
GAMMA BUFFER
Illumination in a TFT display, also referred to as grayscale, is set by a series of discrete voltage levels that are
applied to each LCD pixel. These voltage levels are generated by resistive DAC networks that reside inside each
of the column driver ICs. For example, a column driver with 64 Grayscale levels has a two 6 bit resistive DACs.
Typically, the two DACs will have their 64 resistors grouped into four segments, as shown in Figure 33. Each of
these segments is connected to external voltage lines, VGMA1 to VGMA10, which are the Gamma Levels.
VGMA1 to VGMA5 set grayscale voltage levels that are positive with respect to VCOM (high polarity gamma
levels). VGMA6 to VGMA10 set grayscale voltages negative with respect to VCOM (low polarity gamma levels).
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HIGH POLARITY GAMMA
LEVEL INPUTS
LOW POLARITY GAMMA LEVEL
INPUTS
VGMA1
VGMA9
VGMA3
VGMA5
VGMA7
VGMA6
VGMA10
VGMA2
VGMA4
VGMA8
RESISTIVE
DAC
RESISTIVE
DAC
CMOS
TRANSMISSION
GATES
CMOS TRANSMISSION
GATES
COLUMN DRIVER
BUFFERS
COLUMN DRIVER
BUFFERS
Figure 33. Simplified Schematic of Column Driver IC
Figure 34 shows how column drivers in a TFT display are connected to the gamma levels. VGMA1, VGMA5,
VGMA6, and VGMA10 are driven by the Gamma Buffers. These buffers serve as low impedance voltage sources
that generate the display’s gamma levels. The Gamma Buffers’ outputs are set by a simple resistive ladder, as
shown in Figure 34. Note that VGMA2 to VGMA4 and VGMA7 to VGMA9 are usually connected to the column
drivers even though they are not driven by external buffers. Doing so, forces the gamma levels in all the column
drivers to be identical, minimizing grayscale mismatch between column drivers. Referring again to Figure 34, the
resistive load of a column driver DAC (i.e. resistance between GMA1 to GMA5) is typically 10kΩ to 15kΩ. On a
typical display such as XGA, there can be up to 10 column drivers, so the total resistive load on a Gamma Buffer
output can be as low as 1kΩ. The voltage between VGMA1 and VGMA5 can range from 3V to 6V, depending on
the type of TFT panel. Therefore, maximum load current supplied by a Gamma Buffer is approximately 6V/1kΩ =
6mA, which is a relatively light load for most op amps. In many displays, VGMA1 can be less than 500mV below
VDD, and VGMA10 can be less than 500mV above ground. Under these conditions, an op amp used for the
Gamma Buffer must have rail-to-rail inputs and outputs, like the LM6584.
VDD
VGMA1
VGMA2
VGMA3
VGMA4
VGMA5
+
-
+
-
+
-
+
-
VGMA6
VGMA7
VGMA8
VGMA9
VGMA10
GAMMA
BUFFERS
COLUMN
DRIVERS
COLUMN
DRIVERS
TFT-LCD PANEL
Figure 34. Basic Gamma Buffer Configuration
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Another important specification for Gamma Buffers is small signal bandwidth and slew rate. When column drivers
select which voltage levels are written to a row of pixels, their internal DACs inject current spikes into the Gamma
Lines. This generates voltage transients at the Gamma Buffer outputs, and they should settle-out in less than
1μs to insure a steady output voltage from the column drivers. Typically, these transients have a maximum
amplitude of 2V, so a gamma buffer must have sufficient bandwidth and slew rate to recover from a 2V transient
in 1μs or less.
VOUT
VF
t
0
TPD
TSR
TSET
Figure 35. Large Signal Transient Response of an Operational Amplifier
Figure 35 illustrates how an op amp responds to a large-signal transient. When such a transient occurs at t = 0,
the output does not start changing until TPD, which is the op amp’s propagation delay time (typically 20ns for the
LM6584). The output then changes at the op amp’s slew rate from t = TPD to TSR. From t = TSR to TSET, the
output settles to its final value (VF) at a speed determined by the op amp’s small-signal frequency response.
Although propagation delay and slew limited response time (t = 0 to TSR) can be calculated from data sheet
specifications, the small signal settling time (TSR to TSET) cannot. This is because an op amp’s gain vs. frequency
has multiple poles, and as a result, small-signal settling time can not be calculated as a simple function of the op
amp’s gain bandwidth. Therefore, the only accurate method for determining op amp settling time is to measure it
directly.
2V
0
OR
0
AMPLIFIER UNDER
TEST
-2V
+6.5V
HP 8082
PULSE
GENERATOR
+
50:
-6.5V
RLOAD
1k:
TEK 7633
STORAGE SCOPE
+
TEK 7S14
SAMPLING INPUT
Figure 36. Gamma Buffer Settling Time Test Circuit
The test circuit in Figure 36 was used to measure LM6584 settling time for a 2V pulse and 1kΩ load, which
represents the maximum transient amplitude and output load for a gamma buffer. With this test system, the
LM6584 settled to within ±30mV of 2V pulse in approximately 170ns. Settling time for a 0 to –2V pulse was
slightly less, 150ns. These values are much smaller than the desired response time of 1μs, so the LM6584 has
sufficient bandwidth and slew rate for regulating gamma line transients.
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PANEL REPAIR BUFFER
It is not uncommon for a TFT panel to be manufactured with an open in one or two of its column or row lines. In
order to repair these opens, TFT panels have uncommitted repair lines that run along their periphery. When an
open line is identified during a panel’s final assembly, a repair line re-routes its signal past the open. Figure 37
illustrates how a column is repaired. The column driver’s output is sent to the other end of an open column via a
repair line, and the repair line is driven by a panel repair buffer. When a column or row line is repaired, the
capacitance on that line increases substantially. For instance, a column typically has 50pF to 100pF of line
capacitance, but a repaired column can have up to 200pF. Column drivers are not designed to drive this extra
capacitance, so a panel repair buffer provides additional output current to the repaired column line. Note that
there is typically a 20Ω to 100Ω resistor in series with the buffer output. This resistor isolates the output from the
200pF of capacitance on a repaired column line, ensuring that the buffer remains stable. A pole is created by this
resistor and capacitance, but its frequency will be in the range of 8MHz to 40MHz, so it will have only a minor
effect on the buffer’s transient response time. Panel repair buffers transmit a column driver signal, and as
mentioned in the GAMMA BUFFER section, this signal is set by the gamma levels. It was also mentioned that
many displays have upper and lower gamma levels that are within 500mV of the supply rails. Therefore, op amps
used as panel repair buffers should have rail-to-rail input and stages. Otherwise, they may clip the column driver
signal.
The signal from a panel repair buffer is stored by a pixel when the pixel’s row is selected. In high-resolution
displays, each row is selected for as little as 11μs. To insure that a pixel has adequate time to settle-out during
this brief period, a panel repair buffer should settle to within 1% of its final value approximately 1μs after a row is
selected. This is hardest to achieve when transmitting a column line’s maximum voltage swing, which is the
difference between the upper and lower gamma levels (i.e. voltage between VGMA1 and VGMA10). For a
LM6584, the most demanding application occurs in displays that operate from a 13V supply. In these displays,
voltage difference between the top and bottom gamma levels can be as large as 12V, so the LM6584 needs to
transmit a ±12V pulse and settle to within 60mV of its final value in approximately 1μs (60mV is approximately
1% of the dynamic range of the high or low polarity gamma levels). LM6584 settling times for 12V and –12V
pulses were measured in a test circuit similar to the one in Figure 36. V+ and V− were set to 12.5V and –0.5V,
respectively, when measuring settling time for a 0V to 12V pulse. Likewise, V+ and V− were set to 0.5V and
–12.5V when measuring settling time for a 0V to –12V pulse. In both cases, the LM6584 output was connected
to a series RC load of 51Ω and 200pF. When tested this way, the LM6584 settled to within 60mV of 12V or –12V
in approximately 1.1μs. These observed values are very close to the desired 1μs specification, demonstrating
that the LM6584 has the bandwidth and slew rate required for repair buffers in high-resolution TFT displays.
COLUMN DRIVER
PANEL
REPAIR
BUFFER
20 TO 100:
+
-
TFT-LCD
PANEL
OPEN
COLUMN
LINE
PANEL
REPAIR
LINE
Figure 37. Panel Repair Buffer
SUMMARY
This Application Notes provided a basic explanation of how op-amps are used in TFT displays, and it also
presented the specifications required for these op amps. There are three major op amp applications in a display:
VCOM Driver, Gamma Buffer, and Panel Repair Buffer, and the LM6584 can be used for all of them. As a VCOM
Driver, the LM6584 can supply large values of output current to regulate VCOM load transients. It has rail-to-rail
input common-mode range and output swing required for gamma buffers and panel repair buffers. It also has the
necessary gain bandwidth and slew-rate for regulating gamma levels and driving column repair lines. All these
features make the LM6584 very well suited for use in TFT displays.
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REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM6584MA/NOPB
ACTIVE
SOIC
D
14
55
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LM6584MA
LM6584MAX/NOPB
ACTIVE
SOIC
D
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LM6584MA
LM6584MT/NOPB
ACTIVE
TSSOP
PW
14
94
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LM658
4MT
LM6584MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LM658
4MT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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