LM7310
LM7310
SNOSDC0A – OCTOBER 2020 – REVISED DECEMBER
2020
SNOSDC0A – OCTOBER 2020 – REVISED DECEMBER 2020
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LM73100, 2.7 - 23 V, 5.5 A Integrated Ideal Diode with Input Reverse Polarity and
Overvoltage Protection
1 Features
•
•
•
•
•
•
•
•
•
•
•
Wide operating input voltage range: 2.7 V to 23 V
– 28-V absolute maximum
– Withstands negative voltages up to -15 V
Integrated back-to-back FETs with low OnResistance: RON = 28.4 mΩ (typ)
Ideal diode operation with true reverse current
blocking
Fast overvoltage protection
– 1.2-μs (typ) response time
– Adjustable overvoltage lockout (OVLO)
Fast-trip response to transient overcurrents during
steady state
– 500-ns (typ) response time
– Latch-off after fault
Analog load current monitor output (IMON)
– Current range: 0.5 A to 5.5 A
– Accuracy: ±15% (max) (IOUT ≥ 1 A)
Active high enable input with adjustable
undervoltage lockout threshold (UVLO)
Adjustable output slew rate control (dVdt)
Overtemperature protection
Power Good indication (PG) with adjustable
threshold (PGTH)
Small footprint: QFN 2 mm x 2 mm, 0.45-mm pitch
2 Applications
•
•
•
•
•
•
•
Power MUX/ORing
Adapter Input Protection
Ste-top box/Smart speakers
USB PD port protection
PC/Notebook/Monitors/Docks
Power Tools/Chargers
POS terminals
With integrated back-to-back FETs, reverse current
flow from output to input is blocked at all times,
making the device well suited for power MUX/ORing
applications. The device uses linear ORing based
scheme to ensure almost zero DC reverse current
and emulates ideal diode behavior with minimum
forward voltage drop and power dissipation.
Applications
with
particular
inrush
current
requirements can set the output slew rate with a
single external capacitor. Loads are protected from
input overvoltage conditions by cutting off the output if
input exceeds an adjustable overvoltage threshold.
The device also provides fast trip response to
transient overcurrent events during steady state.
The device provides an accurate sense of the output
load current on the analog current monitor pin.
The device is available in a 2-mm x 2-mm, 10-pin
HotRod QFN package for improved thermal
performance and reduced system footprint.
The device is characterized for operation over a
junction temperature range of –40°C to +125°C.
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
LM73100RPW
QFN (10)
2 mm x 2 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
VIN = 2.7 to 23 V
3 Description
The LM73100 is a highly integrated circuit protection
and power management solution in a small package.
The device provides multiple protection modes using
very few external components and is a robust defense
against voltage surges, reverse polarity, reverse
current and excessive inrush current.
IN
VOUT
OUT
EN/UVLO
PGTH
LM73100
VLOGIC
OVLO
dVdt
CDVDT
GND
IMON
PG
RIMON
Simplified Schematic
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2020 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................6
6.6 Timing Requirements ................................................. 7
6.7 Switching Characteristics ...........................................8
6.8 Typical Characteristics................................................ 9
7 Detailed Description......................................................15
7.1 Overview................................................................... 15
7.2 Functional Block Diagram......................................... 16
7.3 Feature Description...................................................17
7.4 Device Functional Modes..........................................26
8 Application and Implementation.................................. 27
8.1 Application Information............................................. 27
8.2 Single Device, Self-Controlled.................................. 27
8.3 Active ORing............................................................. 31
8.4 Priority Power MUXing..............................................33
8.5 USB PD Port Protection............................................35
8.6 Parallel Operation..................................................... 37
9 Power Supply Recommendations................................39
9.1 Transient Protection.................................................. 39
10 Layout...........................................................................41
10.1 Layout Guidelines................................................... 41
10.2 Layout Example...................................................... 42
11 Device and Documentation Support..........................44
11.1 Documentation Support.......................................... 44
11.2 Receiving Notification of Documentation Updates.. 44
11.3 Support Resources................................................. 44
11.4 Trademarks............................................................. 44
11.5 Electrostatic Discharge Caution.............................. 44
11.6 Glossary.................................................................. 44
12 Mechanical, Packaging, and Orderable
Information.................................................................... 45
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (October 2020) to Revision A (December 2020)
Page
• Changed status from "Advance Information" to Production Data"......................................................................1
2
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5 Pin Configuration and Functions
VIN
EN/UVLO
OVLO
1
10
DNC
2
9
IMON
3
8
GND
4
7
5
PG
PGTH
VOUT
6
DVDT
Figure 5-1. LM73100 RPW Package 10-Pin QFN Top View
Table 5-1. Pin Functions
PIN
TYPE
DESCRIPTION
1
Analog
Input
Active High Enable for the device. A Resistor Divider on this pin from input supply to GND
can be used to adjust the Undervoltage Lockout threshold. Do not leave floating. Refer to
Section 7.3.2 for more details.
OVLO
2
Analog
Input
A Resistor Divider on this pin from supply to GND can be used to adjust the Overvoltage
Lockout threshold. This pin can also be used as an Active Low Enable for the device. Do
not leave floating. Refer to Section 7.3.3 for more details.
PG
3
Digital
Output
Power Good indication. This is an Open Drain signal which is asserted High when the
internal powerpath is fully turned ON and PGTH input exceeds a certain threshold. Refer
to Section 7.3.9 for more details.
PGTH
4
Analog
Input
Power Good Threshold. Refer to Section 7.3.9 for more details.
IN
5
Power
Power Input.
OUT
6
Power
Power Output.
DVDT
7
Analog
Output
A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating
for the fastest turn on slew rate. Refer to Section 7.3.4.1 for more details.
GND
8
Ground
This is the ground reference for all internal circuits and must be connected to system GND.
IMON
9
Analog
Output
Analog load current monitor. The pin voltage can be used to monitor the output load
current. An external resistor from this pin to ground sets the current monitor gain.
Recommended to connect external clamp to limit the voltage below abs max rating in case
of large current spikes. Connect to ground if not used. Do not leave floating. Refer to
Section 7.3.5 for more details.
DNC
10
X
NAME
NO.
EN/UVLO
Internal test pin. Do not connect anything on this pin.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Parameter
Pin
Maximum Input Voltage Range, –40 ℃ ≤ TJ ≤ 125 ℃
VIN
IN
Maximum Input Voltage Range, –10 ℃ ≤ TJ ≤ 125 ℃
Maximum Output Voltage Range, –40 ℃ ≤ TJ ≤ 125 ℃
VOUT
Maximum Output Voltage Range, –10 ℃ ≤ TJ ≤ 125 ℃
MIN
MAX
max (–15, VOUT 21)
28
V
max (–15, VOUT 22)
28
V
OUT
–0.3
min (28, VIN + 21)
–0.3
min (28, VIN + 22)
UNIT
VOUT,PLS
Minimum Output Voltage Pulse (< 1 µs)
OUT
–0.8
VEN/UVLO
Maximum Enable Pin Voltage Range (2)
EN/UVLO
–0.3
6.5
V
–0.3
6.5
V
VOVLO
Maximum OVLO Pin Voltage Range
VdVdT
Maximum dVdT Pin Voltage Range
(2)
OVLO
dVdt
(2)
Internally Limited
V
VPGTH
Maximum PGTH Pin Voltage Range
PGTH
–0.3
6.5
V
VPG
Maximum PG Pin Voltage Range
PG
–0.3
6.5
V
VIMON
Maximum IMON Pin Voltage Range
IMON
1.8
V
IMAX
Maximum Continuous Switch Current
IN to OUT
TJ
Junction temperature
TLEAD
Maximum Lead Temperature
TSTG
Storage temperature
(1)
(2)
5.5
A
Internally Limited
–65
°C
300
°C
150
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
If this pin has a pull-up up to VIN, it is recommended to use a resistance of 350 kΩ or higher to limit the current under conditions where
IN can be exposed to reverse polarity.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins(1)
±2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Parameter
Pin
VIN
Input Voltage Range
IN
VOUT
Output Voltage Range
OUT
VEN/UVLO
Enable Pin Voltage Range
EN/UVLO
MIN
MAX
2.7
23
V
min (23, VIN + 20)
V
5 (2)
V
VOVLO
OVLO Pin Voltage Range
OVLO
VdVdT
dVdT Capacitor Voltage Rating
dVdt
VPGTH
PGTH Pin Voltage Range
PGTH
5 (3)
V
VPG
PG Pin Voltage Range
PG
5 (3)
V
VIMON
IMON Pin Voltage
IMON
1.5
V
IMAX
Continuous Switch Current, , TJ ≤ 125 ℃
IN to OUT
5.5
A
TJ
Junction temperature
125
°C
(1)
(2)
(3)
0.5
UNIT
1.5
VIN + 5 V (1)
–40
V
V
In a PowerMUX/ORing scenario with unequal supplies, the dVdt capacitor rating for each device should be chosen based on the
highest of the 2 rails.
For supply voltages below 5V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 5V or systems which can
be exposed to reverse polarity on input supply, it is recommended to use a pull-up resistor with a minimum value of 350 kΩ.
For systems which can be exposed to reverse polarity on input supply, if this pin is referred to input supply, it is recommended to use a
pull-up resistor with a minimum value of 350 kΩ to limit the current through the pin.
6.4 Thermal Information
LM73100
THERMAL METRIC
(1)
RPW (QFN)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
ΨJT
Junction-to-top characterization parameter
ΨJB
(1)
(2)
(3)
Junction-to-board characterization parameter
41.7 (2)
°C/W
74.5 (3)
°C/W
1
°C/W
20 (2)
27.6
(3)
°C/W
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Based on simulations conducted with the device mounted on a custom 4-layer PCB (2s2p) with 8 thermal vias under device
Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with no thermal vias under device
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6.5 Electrical Characteristics
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, VEN/UVLO = 2 V, VOVLO = 0 V, dVdT = Open, RIMON
= 549 Ω, PGTH = Open, PG = Open, OUT = Open. All voltages referenced to GND.
Test
Parameter
Description
MIN
TYP
MAX
UNITS
INPUT SUPPLY (IN)
VUVP(R)
IN supply UVP rising threshold
2.44
2.53
2.64
V
VUVP(F)
IN supply UVP falling threshold
2.35
2.42
2.55
V
IN supply quiescent current, VIN = 2.7 V
347
492
µA
IQ(ON)
IN supply quiescent current, VIN = 12 V
426
509
µA
IN supply quiescent current, VIN = 23 V
IQ(RCB)
IN supply quiescent current during RCB, VOUT > VIN
459
612
µA
189.7
234
µA
74.5
97.6
µA
4.6
8.2
µA
IQ(OFF)
IN supply disabled state current (VSD(F) < VEN < VUVLO(R))
ISD
IN supply shutdown current (VEN < VSD(F))
IQ(OVLO)
IN supply OFF state current (OVLO condition), VOUT > VIN
191
µA
IINLKG(IRPP)
IN supply leakage current (VIN = –14 V, VOUT = 0 V)
-3.5
µA
28.4
mΩ
ON RESISTANCE (IN - OUT)
VIN = 12 V, IOUT = 3 A, TJ = 25 ℃
RON
2.7 ≤ VIN ≤ 23 V, –40 ℃ ≤ TJ ≤ 125 ℃
44.85
mΩ
ENABLE/UNDERVOLTAGE LOCKOUT (EN/UVLO)
VUVLO(R)
EN/UVLO rising threshold
1.183
1.2
1.223
V
VUVLO(F)
EN/UVLO falling threshold
1.076
1.09
1.116
V
VSD(F)
EN/UVLO falling threshold for lowest shutdown current
0.45
0.74
IENLKG
EN/UVLO leakage current
–0.1
0.1
µA
V
V
OVERVOLTAGE LOCKOUT (OVLO)
VOV(R)
OVLO rising threshold
1.183
1.2
1.223
VOV(F)
OVLO falling threshold
1.076
1.09
1.116
V
IOVLKG
OVLO pin leakage current, 0.5 V < VOVLO < 1.5 V
0.1
µA
–0.1
IOUTLKG(OVLO) OUT leakage current (OVLO condition), VOUT > VIN
317
µA
21.9
A
FIXED FAST-TRIP (OUT)
IFT
Fixed fast-trip current threshold
OUTPUT LOAD CURRENT MONITOR (IMON)
GIMON
Analog load current monitor gain (IMON : IOUT), IOUT = 0.5 A to
1A
144
181
216
µA/A
Analog load current monitor gain (IMON : IOUT), IOUT = 1 A to
5.5 A
153
181
207
µA/A
REVERSE CURRENT BLOCKING (IN - OUT)
6
VFWD
(VIN - VOUT) forward regulation voltage, IOUT = 10 mA
4.8
16.4
28.4
mV
VREVTH
(VOUT - VIN) threshold for fast BFET turn off (enter reverse
current blocking)
22.7
29.3
36.5
mV
VFWDTH
(VIN - VOUT) threshold for fast BFET turn on (exit reverse
current blocking)
85.9
105.8
125
mV
IREVLKG(OFF)
Reverse leakage current (unpowered condition), VOUT = 12
V, VIN = 0 V
IREVLKG
Reverse leakage current, (VOUT - VIN) = 21.5 V
10.10
15.86
µA
IOUTLKG(RCB)
OUT leakage current during RCB state while ON, (VOUT VIN) = 1 V
247.6
322
µA
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6.5 Electrical Characteristics (continued)
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, VEN/UVLO = 2 V, VOVLO = 0 V, dVdT = Open, RIMON
= 549 Ω, PGTH = Open, PG = Open, OUT = Open. All voltages referenced to GND.
Test
Parameter
Description
MIN
TYP
MAX
UNITS
PG pin low voltage while de-asserted, VIN < VUVP(F), VEN <
VSD, IPG = 26 µA
0.67
0.9
V
VPGD
PG pin low voltage while de-asserted, VIN < VUVP(F), VEN <
VSD, IPG = 242 µA
0.78
1
V
IPGLKG
PG pin leakage current while asserted
POWER GOOD INDICATION (PG)
PG pin low voltage while de-asserted, VIN > VUVP(R)
0.6
V
0.5
2
µA
V
POWERGOOD THRESHOLD (PGTH)
VPGTH(R)
PGTH rising threshold
1.183
1.2
1.223
VPGTH(F)
PGTH falling threshold
1.076
1.09
1.116
V
IPGTHLKG
PGTH leakage current
–1
1
µA
OVERTEMPERATURE PROTECTION (OTP)
TSD
Thermal shutdown rising threshold, TJ↑
TSDHYS
Thermal shutdown hysteresis, TJ↓
154
°C
10
°C
DVDT
IdVdt
dVdt pin charging current
1.15
2.34
3.66
µA
6.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
tOVLO
Overvoltage lock-out response time
VOVLO > VOV(R) to VOUT↓
1.1
µs
tFT
Fixed fast-trip response time
IOUT > IFT to IOUT↓
500
ns
tSWRCB
Reverse Current Blocking recovery time
(VIN - VOUT) > VFWDTH to VOUT ↑
50
µs
tRCB
Reverse Current Blocking fast comparator
response time
(VOUT - VIN) > 1.3 x VREVTH to BFET OFF
1
µs
tPGA
PG Assertion de-glitch
12
µs
tPGD
PG De-assertion de-glitch
12
µs
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6.7 Switching Characteristics
The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the turn
on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from the dVdt pin
to ground. As CdVdt is increased it will slow the rising slew rate (SR). See Slew Rate and Inrush Current Control (dVdt)
section for more details. The Turn-Off Delay and Fall Time, however, are dependent on the RC time constant of the load
capacitance (COUT) and Load Resistance (RL). The Switching Characteristics are only valid for the power-up
sequence where the supply is available in steady state condition and the load voltage is completely discharged before the
device is enabled.Typical Values are taken at TJ = 25°C unless specifically noted otherwise. RL = 100 Ω, COUT = 1 µF
PARAMETER
SRON
tD,ON
tR
tON
tD,OFF
VIN
Output Rising slew rate
Turn on delay
Rise time
Turn on time
Turn off delay
CdVdt = Open
CdVdt = 1800 pF
CdVdt =
3300 pF
2.7 V
12.14
0.87
0.5
12 V
28.1
1.09
0.61
23 V
44.78
1.25
0.71
2.7 V
0.09
0.6
0.97
12 V
0.1
1.32
2.35
23 V
0.11
1.99
3.69
2.7 V
0.17
2.51
4.33
12 V
0.35
8.1
15.37
23 V
0.40
14.4
25.89
2.7 V
0.27
3.11
5.31
12 V
0.45
10.08
17.72
23 V
0.50
16.41
29.57
2.7 V
64.44
64.44
64.44
12 V
25.32
25.32
25.32
23 V
23.02
23.02
23.02
UNIT
V/ms
ms
ms
ms
µs
VEN/UVLO
VUVLO(R)
EN/UVLO
VUVLO(F)
0
tD,OFF
tON
VIN
90%
SRON
OUT
0V
10%
tR
tD,ON
tF
Time
Figure 6-1. LM73100 Switching Times
8
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6.8 Typical Characteristics
Figure 6-2. ON-Resistance vs Supply Voltage
Figure 6-3. Forward Voltage Drop vs Load Current
Figure 6-4. IN Quiescent Current vs Supply Voltage
Figure 6-5. IN Quiescent Current vs Temperature
Figure 6-6. IN Undervoltage Threshold vs Temperature
Figure 6-7. EN/UVLO Threshold vs Temperature
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6.8 Typical Characteristics (continued)
10
Figure 6-8. EN/UVLO Shutdown Threshold vs Temperature
Figure 6-9. EN/UVLO Shutdown Threshold vs Supply Voltage
Figure 6-10. OVLO Threshold vs Temperature
Figure 6-11. PGTH Threshold vs Temperature
Figure 6-12. Reverse Comparator Threshold vs Temperature
Figure 6-13. Forward Regulation Voltage vs Temperature
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6.8 Typical Characteristics (continued)
Figure 6-14. Forward Regulation Voltage vs Supply Voltage
Figure 6-15. Forward Comparator Threshold vs Temperature
Figure 6-16. OUT Leakage Current During ON-State Reverse
Current Blocking
Figure 6-17. Reverse Leakage Current During OFF-State
Figure 6-18. Analog Current Monitor Gain Accuracy
Figure 6-19. Analog Current Monitor gain vs Temperature
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6.8 Typical Characteristics (continued)
12
Figure 6-20. Analog Current Monitor Gain vs Load Current
Figure 6-21. DVDT Charging Current vs Temperature
Figure 6-22. Steady State Fast-Trip Comparator Threshold vs
Temperature
Figure 6-23. Steady State Fast-Trip Current Threshold vs
Temperature
Figure 6-24. Time to Thermal Shut-Down During Inrush State
Figure 6-25. Time to thermal Shut-Down During Steady State
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6.8 Typical Characteristics (continued)
VEN/UVLO = 3 V, COUT = 220 μF, CdVdt = 10 nF, VIN ramped up to
12 V
VIN = 12 V, COUT = 220 μF, CdVdt = 10 nF, VEN/UVLO stepped up
to 3 V
Figure 6-26. Start Up with IN Supply
Figure 6-27. Start Up with EN
COUT = 220 μF, CdVdt = 10 nF, EN/UVLO connected to IN
through resistor ladder, 12 V hot-plugged to IN
VIN = 12 V, ROUT = 20 Ω, COUT = 220 μF, CdVdt = 10 nF, VEN/
UVLO stepped up to 3 V
Figure 6-29. Inrush Current with RC Load
Figure 6-28. Input Hot-Plug
COUT = 220 μF, PG pulled up to 3 V, -15 V hot-plugged to IN
COUT = 220 μF, PG pulled up to 3 V, VIN ramped down from 0 V
to -15 V and then ramped up to 0 V
Figure 6-30. Input Reverse Polarity Protection - Fast Ramp
Figure 6-31. Input Reverse Polarity Protection - Slow Ramp
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6.8 Typical Characteristics (continued)
IN= Open, COUT = 220 μF, PG pulled up to 3 V, 20 V hotplugged to OUT
IN= Open, COUT = 220 μF, PG pulled up to 3 V, VOUT ramped
up from 0 V to 20 V
Figure 6-32. Reverse Current Blocking Response in OFF State
Figure 6-33. Reverse Current Blocking Response in OFF State
COUT = 220 μF, ROUT = 20 Ω, OVLO threshold = 13.2 V, VIN
ramped up from 12 V to 16 V
VIN = 12 V, COUT = Open, OUT stepped from Open → Shortcircuit to GND
Figure 6-34. Input Overvoltage Protection
Figure 6-35. Fast-Trip Response During Steady State
VIN = 12 V, COUT = Open, OUT stepped from Open → Short-circuit to GND
Figure 6-36. Fast-Trip Response During Steady State - Zoomed In
14
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7 Detailed Description
7.1 Overview
The LM73100 is an integrated ideal diode that is used to ensure safe power delivery in a system. The device
starts its operation by monitoring the IN bus. When the input supply voltage (VIN) exceeds the undervoltage
protection threshold (VUVP), the device samples the EN/UVLO pin. A high level (> VUVLO(R)) on this pin enables
the internal power path (BFET+HFET) to start conducting and allow current to flow from IN to OUT. When EN/
UVLO pin is held low (< VUVLO(F)), the internal power path is turned off. In case of reverse voltages appearing at
the input, the power path remains OFF thereby protecting the output load.
After a successful start-up sequence, the device now actively monitors its load current and input voltage, and
controls the internal HFET to ensure that the fast-trip threshold (IFT) is not exceeded and overvoltage spikes are
cut-off once they cross the user adjustable overvoltage lockout threshold (VOVLO). This helps to keep the system
safe from harmful levels of voltage and current.
The device has integrated reverse current blocking FET (BFET) which operates like an ideal diode. The BFET is
linearly regulated to maintain a small constant forward drop (VFWD) in forward conduction mode and turned off
completely to block reverse current from OUT to IN if output voltage exceeds the input voltage.
The device also has a built-in thermal sensor based shutdown mechanism to protect itself in case the device
temperature (TJ) exceeds the recommended operating conditions.
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7.2 Functional Block Diagram
LM73100
FFT
-
+
-
+
16.4 mV
350 mV
Temp Sense &
Overtemperature
protection
IN
5
BFET
TSD
6
OUT
7
DVDT
INRUSH_
DONE
HFET
IRPP
CP
2.8 V
+
2.42 V;
1.2 V9
1.09 V;
+
1
1.2 V9
1.09 V;
IMON
BFET Control
HFET Control
UVLOb
-
EN/UVLO
9
OVLOb
+
2
181 A/A
GHI
RCB
-
OVLO
UVPb
-
2.53 V9
-
+
2.3 A
SWEN
INRUSH_DONE
SD
+
0.74 V
PG_int
INRUSH_DONE
SD
UVPb
R
/Q
RCB
PG_int
TSD
S
Q
10
FLT
PG_int
Q
/Q
8
GHI FFT
16
GND
+
S
-
R
1.2 V9
1.09 V;
3
4
PG
PGTH
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7.3 Feature Description
The LM73100 integrated ideal diode is a compact, feature rich power management device that provides
detection, protection and indication in the event of system faults.
7.3.1 Input Reverse Polarity Protection
The LM73100 device is internally protected against transient and steady state negative voltages applied at the
input supply pin. The device blocks the negative voltage from appearing at the output, thereby protecting the
load circuits. There’s no reverse current flowing from output to the input in this condition. The maximum negative
voltage the device can handle at the input is limited to -15 V or VOUT – 21 V, whichever is higher. It’s also
recommended that all signal pins (e.g. EN/UVLO, OVLO, PGTH) which are derived from input supply should
have a sufficiently large pull-up resistor to limit the current flowing out of these pins during reverse polarity
conditions. Please refer to Absolute Maximum Ratings table for more details.
7.3.2 Undervoltage Protection (UVLO & UVP)
The LM73100 implements undervoltage protection on IN in case the applied voltage becomes too low for the
system or device to properly operate. The undervoltage protection has a default lockout threshold of VUVP which
is fixed internally. Apart from that, the UVLO comparator on the EN/UVLO pin allows the undervoltage Protection
threshold to be externally adjusted to a user defined value. The Figure 7-1 and Equation 1 below show how a
resistor divider can be used to set the UVLO set point for a given voltage supply.
Power
Supply
IN
R1
EN/UVLO
R2
GND
Figure 7-1. Adjustable Undervoltage Protection
VIN(UV) =
VUVLO x (R1 + R2)
R2
(1)
7.3.3 Overvoltage Lockout (OVLO)
The LM73100 allows the user to implement overvoltage lockout to protect the load from input overvoltage
conditions. The OVLO comparator on the OVLO pin allows the overvoltage protection threshold to be adjusted to
a user defined value. Once the voltage at the OVLO pin crosses the OVLO rising threshold VOV(R), the device
turns off the power to the output. Thereafter, the devices wait for the voltage at the OVLO pin to fall below the
OVLO falling threshold VOV(F) before the output power is turned ON again. The rising and falling thresholds are
slightly different to provide hysterisis. The Figure 7-2 and Equation 2 below show how a resistor divider can be
used to set the OVLO set point for a given input supply voltage.
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Power
Supply
IN
R1
OVLO
R2
GND
Figure 7-2. Adjustable Overvoltage Protection
VIN(OV) =
VOV x (R1 + R2)
R2
(2)
While recovering from an overvoltage event, the LM73100 starts up with inrush control (dVdt).
Input Overvoltage Event
Input Overvoltage Removed
IN
0
OVLO
VOV(R)
VOV(F)
tOVLO
0
OUT
dVdt Limited Start-up
0
tPGA
tPGD
VPG
PG
0
Time
Figure 7-3. LM73100 Overvoltage Lockout and Recovery
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7.3.4 Inrush Current control and Fast-trip
LM73100 incorporates 2 mechanisms to handle overcurrent:
1. Adjustable slew rate (dVdt) for inrush current control
2. Fixed threshold (IFT) for fast-trip response to transient overcurrent events during steady-state
7.3.4.1 Slew Rate (dVdt) and Inrush Current Control
During hot-plug events or while trying to charge a large output capacitance at start-up, there can be a large
inrush current. If the inrush current is not managed properly, it can damage the input connectors and/or cause
the system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current
during turn on is directly proportional to the load capacitance and rising slew rate. Equation 3 can be used to find
the slew rate (SR) required to limit the inrush current (IINRUSH) for a given load capacitance (COUT):
SR (V/ms) =
IINRUSH (mA)
COUT (µF)
(3)
A capacitor can be connected to the dVdt pin to control the rising slew rate and lower the inrush current during
turn on. The required CdVdt capacitance to produce a given slew rate can be calculated using the following
equation:
CdVdt (pF) =
2000
SR (V/ms)
(4)
The fastest output slew rate is achieved by leaving the dVdt pin open.
Note
For CdVdt > 10 nF, it's recommended to add a 100-Ω resistor in series with the capacitor on the dVdt
pin.
7.3.4.2 Fast-Trip During Steady State
During certain system faults, the current through the device can increase very rapidly. In such events, the device
provides fast-trip response with a fixed threshold (IFT) during steady state. Once the current exceeds IFT, the
HFET is turned off completely within tFT. Thereafter, the device remains latched-off until it's power cycled or reenabled by toggling the EN/UVLO pin.
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Device enabled
Load step
Transient overcurrent
during steady state
Device re-enabled
Device latched-off
VUVLO(R)
EN/UVLO VSD(F)
0
IN
0
tFT
IFT
Fast-trip
IOUT IINRUSH
0
VIN
OUT
0
tPGA
VPG
tPGD
tPGA
PG
0
Time
Figure 7-4. LM73100 Fast-Trip Response
Note
The LM73100 fast-trip response is active only during steady state and offers one level of fast
response to severe overcurrents of transient nature. However, for systems which may experience
persistent faults such as short-circuits or overloads, it's recommended to use an additional level of
overcurrent protection in series for safety.
7.3.5 Analog Load Current Monitor Output
The device allows the system to accurately monitor the output load current by providing an analog current sense
output on the IMON pin which is proportional to the current through the FET. The user can sense the voltage
(VIMON) across the RIMON to get a measure of the output load current.
IOUT (A) =
VIMON (V) x 10-6
RIMON :À; š GIMON (µA/A)
(5)
The waveform below shows the IMON signal response to a dynamically varying load profile at the output.
20
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VIN = 12 V, COUT = 22 μF, RIMON = 1.15 kΩ, IOUT varied dynamically between 0 A and 3.5 A
Figure 7-5. Analog Load Current Monitor Output Response
Note
1. It's recommended to choose RIMON such that VIMON ≤ 1.5 V at the maximum DC load current.
2. It's also recommended to add a zener diode on the IMON pin to clamp the voltage below 1.8 V
during high current transients.
3. Connect IMON pin to GND if not used. Do not leave the pin floating.
7.3.6 Reverse Current Protection
The LM73100 functions like an ideal diode and blocks reverse current flow from OUT to IN under all conditions.
The device has integrated back-to-back MOSFETs connected in a common drain configuration. The voltage drop
between the IN and OUT pins is constantly monitored and the gate drive of the blocking FET (BFET) is adjusted
as needed to regulate the forward voltage drop at VFWD. This closed loop regulation scheme enables graceful
turn off of the MOSFET during a reverse current event and ensures there's no DC reverse current flow.
The device also uses a conventional comparator (VREVTH) based reverse blocking mechanism to provide fast
response to transient reverse currents.Once the device enters reverse current blocking condition, it waits for the
(VIN - VOUT) forward drop to exceed the VFWDTH before it performs a fast recovery to reach full forward
conduction state. This provides sufficient hysterisis to prevent supply noise or ripple from affecting the reverse
current blocking response. The recovery from reverse current blocking is very fast (tSWRCB). This ensures
minimum supply droop which is helpful in applications such as power MUX/ORing.
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VFWD
IN
OUT
IN
BFET regulation mode
BFET turned OFF
VREVTH
BFET full conduction mode
VFWTH
VFWD
0V
OUT
VIN - VOUT
Figure 7-6. Reverse Current Blocking Response
The waveforms below illustrate the reverse current blocking performance in various scenarios.
During fast voltage step at output (e.g. hot-plug), the fast comparator based reverse blocking mechanism
ensures minimum jump/glitch on the input rail.
Figure 7-7. Reverse Current Blocking Performance During Fast Voltage Step at Output
During slow voltage ramp at output, the linear ORing based reverse blocking mechanism ensures there's no DC
current flow from OUT to IN, thereby avoiding input rail from getting slowly charged up to output voltage.
22
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Figure 7-8. Reverse Current Blocking Performance During Slow Voltage Ramp at Output
When the input supply droops or gets disconnected while the output storage element (capacitor bank or super
capacitor) is charged to the full voltage, the linear ORing scheme minimizes the self-discharge from OUT to IN.
This ensures maximum hold-up time for the output storage element in critical power back-up applications.
It also prevents incorrect supply presence indication in applications which sense the input voltage to detect if the
supply is connected.
Figure 7-9. Reverse Current Blocking Performance During Input Supply Failure
7.3.7 Overtemperature Protection (OTP)
The LM73100 monitors the internal die temperature (TJ) at all times and shuts down the part as soon as the
temperature exceeds a safe operating level (TSD) thereby protecting the device from damage. The device will
not turn back on until the junction cools down sufficiently, that is the die temperature falls below (TSD - TSDHYS).
When the device detects thermal overload, it will shut down and remain latched-off until the device is power
cycled or re-enabled by toggling the EN/UVLO pin.
Table 7-1. Thermal Shutdown
Enter TSD
Exit TSD
TJ ≥ TSD
TJ < TSD - TSDHYS
VIN cycled to 0 V and then above VUVP(R) OR EN/UVLO toggled
below VSD(F)
7.3.8 Fault Response
The following table summarizes the LM73100 response to various fault conditions.
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Table 7-2. Fault Summary
Event
Protection Response
Fault Latched Internally
Overtemperature
Shutdown
Y
Undervoltage (UVP or UVLO)
Shutdown
N
Input Reverse Polarity
Shutdown
N
Overvoltage
Shutdown
N
Reverse Current
Reverse Current Blocking
N
Transient overcurrent during steady state
Shutdown
Y
Faults which are not latched internally are automatically cleared once the trigger condition goes away and
thereafter the device recovers without any external intervention. Faults which are latched internally can be
cleared either by power cycling the part (pulling VIN to 0 V and then above VUVP(R)) or by pulling the EN/UVLO
pin voltage below VSD(F).
After a latched fault, pulling the EN/UVLO just below the UVLO threshold (VUVLO(F)) has no impact on the device.
7.3.9 Power Good Indication (PG)
The LM73100 provides an active high digital output (PG) which serves as a power good indication signal and is
asserted high depending on the voltage at the PGTH pin along with the device state information. The PG is an
open-drain pin and needs to be pulled up to an external supply.
After power up, PG is pulled low initially. The device initiates a inrush sequence in which the HFET is turned on
in a controlled manner. When the HFET gate voltage reaches the full overdrive indicating that the inrush
sequence is complete and the voltage at PGTH is above VPGTH(R), the PG is asserted after a de-glitch time
(tPGA).
PG is de-asserted if at any time during normal operation, the voltage at PGTH falls below VPGTH(F), or the device
detects a fault. The PG de-assertion de-glitch time is tPGD.
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Device Enabled
VUVLO(R)
EN/UVLO
0
IN
Slew rate (dVdt) controlled
startup/Inrush current limiting
0
VIN
OUT
0
VPGTH(R)
VPGTH(F)
PGTH
0
VPG
PG
tPGA
0
VIN
dVdt
0
VOUT + 2.8V
VHGate
0
IINRUSH
IOUT
0
Time
Figure 7-10. LM73100 PG Timing Diagram
Table 7-3. LM73100 PG Indication Summary
Event
Protection Response
PG Pin
PG Delay
Undervoltage (UVP or UVLO)
Shutdown
L
Input Reverse Polarity
Shutdown
L
Overvoltage (OVLO)
Shutdown
L
tPGD
Steady State
N/A
H (If PGTH pin voltage > VPGTH(R))
L (If PGTH pin voltage < VPGTH(F))
tPGA
tPGD
Transient overcurrent during
steady state
Fast-trip
H (If PGTH pin voltage > VPGTH(R))
L (If PGTH pin voltage < VPGTH(F))
tPGA
tPGD
Reverse current ((VOUT - VIN) >
VREVTH)
Reverse current blocking
L
tPGD
Overtemperature
Shutdown
L
tPGD
When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pull-down
in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to an independent supply
which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the
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pin sink current, which is a function of the pull-up supply voltage and resistor. Minimize the sink current to keep
this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.
7.4 Device Functional Modes
The device has one mode of operation that applies when operated within the Recommended Operating
Conditions.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The LM73100 is an integrated 5.5-A ideal diode that is typically used for power rail monitoring and protection
applications . It operates from 2.7 V to 23 V with adjustable overvoltage and undervoltage protection. It provides
ability to control inrush current and protection against input reverse polarity as well as reverse current conditions.
It also has integrated analog load current monitoring and digital power good indication with adjustable threshold.
It can be used in a variety of systems such as set-top boxes, smart speakers, handheld power tools/chargers,
PC/notebooks and Retail ePOS (Point-of-sale) terminals.
The design procedure explained in the subsequent sections can be used to select the supporting component
values based on the application requirement. Additionally, a spreadsheet design tool LM73100 Design Calculator
is available in the web product folder.
8.2 Single Device, Self-Controlled
VIN = 2.7 to 23 V
IN
VOUT
OUT
COUT
PGTH
EN/UVLO
VLOGIC
LM73100
OVLO
PG
dVdt
GND
IMON
Figure 8-1. Single Device, Self-Controlled
Other variations:
In a Host MCU controlled system, EN/UVLO or OVLO can also be driven from the host GPIO to control the
device.
IMON pin can be connected to the MCU ADC input for current monitoring purpose.
Either VIN or VOUT can be used to drive the PGTH resistor divider depending on which supply needs to be
monitored for power good indication.
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8.2.1 Typical Application
VIN = 12 V
IN
VOUT
OUT
R4
R1
COUT
47 kO
470 kO
D2*
PGTH
EN/UVLO
3.3 V
LM73100
R2
R2
D1*
5.6 kO
11 kO
CIN
470 …F
47 kO
1 …F
OVLO
PG
dVdt
R3
47 kO
GND
IMON
CdVdt
RIMON
3300 pF
549 O
D3*
1.8 V
* Optional circuit components needed for transient protection depending on input and output inductance. Please
refer to Transient Protection section for details.
Figure 8-2. AC-DC Adapter Powered System - Barrel Jack Input Protection
8.2.1.1 Design Requirements
Table 8-1. Design Parameters
28
PARAMETER
VALUE
Adapter nominal output voltage (VIN)
12 V
Maximum input reverse voltage
–12 V
Undervoltage threshold (VIN(UV))
10.8 V
Overvoltage threshold (VIN(OV))
13.2 V
Output Power Good threshold (VPG)
11.4 V
Max continuous current (IOUTmax)
5A
Analog load current monitor voltage range (VIMONmax)
0.5 V
Output capacitance (COUT)
470 μF
Output rise time (tR)
20 ms
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Setting Undervoltage and Overvoltage Thresholds
The supply undervoltage and overvoltage thresholds are set using the resistors R1, R2 & R3 whose values can
be calculated using Equation 6 and Equation 7:
VIN(UV) =
VUVLO(R) x (R1 + R2 + R3)
R2 + R3
VIN(OV) =
(6)
VOV(R) x (R1 + R2 + R3)
R3
(7)
Where VUVLO(R) is the UVLO rising threshold and VOV(R) is the OVLO rising threshold . Because R1, R2 and R3
leak the current from input supply VIN, these resistors must be selected based on the acceptable leakage current
from input power supply VIN. The current drawn by R1, R2 and R3 from the power supply is IR123 = VIN / (R1 +
R2 + R3). However, leakage currents due to external active components connected to the resistor string can add
error to these calculations. So, the resistor string current, IR123 must be chosen to be 20 times greater than the
leakage current expected on the EN/UVLO and OVLO pins.
From the device electrical specifications, both the EN/UVLO and OVLO leakage currents are 0.1 μA (max),
VOV(R) = 1.2 V and VUVLO(R) = 1.2 V. From design requirements, VIN(OV) = 13.2 V and VIN(UV) = 10.8 V. To solve
the equation, first choose the value of R1 = 470 kΩ and use the above equations to solve for R2 = 10.7 kΩ and
R3= 48 kΩ.
Using the closest standard 1% resistor values, we get R1 = 470 kΩ, R2 = 11 kΩ, and R3 = 47 kΩ.
8.2.1.2.2 Setting Output Voltage Rise Time (tR)
The slew rate (SR) needed to achieve the desired output rise time can be calculated as:
SR (V/ms) =
VIN (V)
12 V
=
= 0.6 V/ms
tR (ms) 20 ms
(8)
The CdVdt needed to achieve this slew rate can be calculated as:
CdVdt :pF; =
2000
2000
=
= 3333 pF
SR :V/ms;
0.6
(9)
Choose the nearest standard capacitor value as 3300 pF.
For this slew rate, the inrush current can be calculated as:
IINRUSH :mA; = SR (V/ms) x COUT :µF; = 0.6 x 470 = 282 mA
(10)
The average power dissipation inside the part during inrush can be calculated as:
PDINRUSH :W; =
IINRUSH :A; T VIN :8; 0.282 x 12
=
= 1.69 W
2
2
(11)
The power dissipation is below the allowed limit for a successful start-up without hitting thermal shut-down within
the target rise time as shown in the Figure 8-3.
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Figure 8-3. Thermal shut-down plot during inrush
8.2.1.2.3 Setting Power Good Assertion Threshold
The Power Good assertion threshold can be set using the resistors R4 & R5 connected to the PGTH pin whose
values can be calculated as:
VPG =
VPGTH(R) x (R4 + R5)
R5
(12)
Because R4 and R5 leak the current from the output rail VOUT, these resistors must be selected to minimize the
leakage current. The current drawn by R4 and R5 from the power supply is IR45 = VOUT / (R4 + R5). However,
leakage currents due to external active components connected to the resistor string can add error to these
calculations. So, the resistor string current, IR123 must be chosen to be 20 times greater than the PGTH
leakage current expected.
From the device electrical specifications, PGTH leakage current is 1 μA (max), VPGTH(R) = 1.2 V and from design
requirements, VPG = 11.4 V. To solve the equation, first choose the value of R4 = 47 kΩ and calculate R5 = 5.52
kΩ. Choose nearest 1% standard resistor value as R5 = 5.6 kΩ.
8.2.1.2.4 Setting Analog Current Monitor Voltage (IMON) Range
The analog current monitor voltage range can be set using the RIMON resistor whose value can be calculated as:
RIMON :À; =
VIMONmax (V) x 10-6
0.5 x 10-6
=
= 549.5 À
IOUTmax(A) x GIMON (µA/A)
5 x 182
(13)
Choose nearest 1% standard resistor value as 549 Ω.
Note
An additional 1.8 V zener may be needed in parallel with the RIMON in applications which expect large
transient currents. Please refer to the Analog Load Current Monitor section for more details.
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8.2.1.3 Application Curves
Figure 8-4. Power up
Figure 8-5. Overvoltage protection
Figure 8-6. Analog Load Current Monitor Output
8.3 Active ORing
A typical redundant power supply configuration is shown in Figure 8-7 below. Schottky ORing diodes have been
popular for connecting parallel power supplies, such as parallel operation of wall adapter with a battery or a holdup storage capacitor. Similar ORing requirements can be seen in end equipements such as PC, Notebook,
Docking stations, Monitors etc.. which can take power from multiple USB ports and/or power adapter. The
disadvantage of using ORing diodes is high voltage drop and associated power loss. The LM73100 with
integrated, low-ohmic, back-to-back FETs provides a simple and efficient solution. Figure below shows the Active
ORing implementation using the devices.
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IN
VIN1
VOUT
OUT
VLOGIC
EN/UVLO
LM73100
OVLO
VIN1
COUT
PGTH
PG_SYS
PG
IMON
VIN2
VIN2
IN
OUT
EN/UVLO
PGTH
VLOGIC
LM73100
OVLO
PG
IMON
Figure 8-7. Two Devices, Active ORing Configuration
The linear ORing mechanism in LM73100 ensures that there's no reverse current flowing from one power source
to the other during fast or slow ramp of either supply.
The following waveforms illustrate the active ORing behavior.
VIN1 = 12 V, ROUT = 25 Ω, COUT = 440 μF, IN2 stepped up to 13
V and then ramped down
Figure 8-8. Active ORing Response
VIN1 = 12 V, ROUT = 25 Ω, COUT = 440 μF, IN2 stepped up to 13
V and then ramped down
Figure 8-9. Active ORing Response
When bus voltages (IN1 and IN2) are matched, device in each rail sees a forward voltage drop and is ON
delivering the load current. During this period, current is shared between the rails in the ratio of differential
voltage drop across each device.
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In addition to supply ORing, the devices protect the system from overvoltage, excessive inrush current and
transient overcurrent events during steady state.
Note
1. ORing can be done either between two similar rails (such as 12 V & 12 V; 3.3 V & 3.3 V) or
between dissimilar rails (such as 12 V & 5 V).
2. For ORing cases with skewed voltage combinations, care must be taken to design circuit
components on PGTH, EN/UVLO & OVLO pins for the lower voltage channel device such that the
absolute maximum ratings on those pins are not exceeded when higher voltage is present on the
other channel. Also, the dVdt pin capacitor rating should be chosen based on the highest of the 2
supplies. Refer to Absolute Maximum Ratings and Recommended Operating Conditions tables for
more details.
8.4 Priority Power MUXing
Applications having two or more power sources such as POS terminals, Tablets and other portable battery
powered equipment require preference of one source to another. For example, mains power (wall-adapter) has
the priority over the internal battery back-up power. These applications demand for switchover from mains power
to backup power only when main input voltage falls below a user defined threshold. The LM73100 devices
provide a simple solution for priority power multiplexing needs.
Figure 8-10 below shows a typical priority power multiplexing implementation using LM73100 devices. When the
primary (priority) power source (IN1) is present and above the undervoltage (UVLO) threshold, the primary path
device path powers the OUT bus irrespective of whether auxiliary supply voltage condition. The device in
auxiliary path is held in off condition by forcing its OVLO pin to high using the EN/UVLO signal of the primary
path device.
Once the primary supply voltage falls below the user-defined undervoltage threshold (UVLO), the primary path
device is turned off. At the same the auxiliary, the auxiliary path device turns on and starts delivering power to
the load.
In this configuration, supply overvoltage protection is not available on both channels.
The PG pins of the devices can be used as a digital indication to identify which of the 2 supplies is active and
delivering power to the load.
A key consideration in power MUXing applications is the minimum voltage the output bus droops to during the
switchover from one supply to another. This in turn depends on multiple factors including the output load current
(ILOAD), output bus hold-up capacitance (COUT) and switchover time (tSW).
While switching from one supply rail to the other, the minimum bus voltage can be calculated using Equation 14
below. Here, the maximum switchover time (tSW) is the time taken by the device to turn on and start delivering
power to the load, which is equal to the device turn on time (tON), which in turn includes the turn on delay (tD,ON)
and rise time (tR) determined by the dVdt capacitor (CdVdt) and bus voltage.
V OUT min V
min V IN1,V IN2
t SW
V u , LOAD $
COUT
(14)
)
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IN
VIN1
VOUT
OUT
VLOGIC
IMON
EN/UVLO
COUT
LM73100
PGTH
IN1 supply active
PG
OVLO
dVdt
GND
CdVdt
IN
VIN2
OUT
IMON
EN/UVLO
VLOGIC
LM73100
PGTH
OVLO
dVdt
GND
IN2 supply active
PG
CdVdt
Figure 8-10. Two Devices, Priority Power MUX Configuration
Note
1. Power MUXing can be done either between two similar rails (such as 12-V Primary & 12-V Aux;
3.3-V Primary & 3.3-V Aux) or between dissimilar rails (such as 12 V-Primary & 5-V Aux or vice
versa).
2. For Power MUXing cases with skewed voltage combinations, care must be taken to design circuit
components on PGTH, EN/UVLO & OVLO pins for the lower voltage channel devices such that the
absolute maximum ratings on those pins are not exceeded when higher voltage is present on the
other channel. Also, the dVdt pin capacitor rating should be chosen based on the highest of the 2
supplies. Refer to Absolute Maximum Ratings and Recommended Operating Conditions tables for
more details.
34
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8.5 USB PD Port Protection
End equipments like PC, Notebooks, Docking Stations, Monitors etc. have USB PD ports which can be
configured as DFP (Source), UFP (Sink) or DRP (Source+Sink). LM73100 can be used independently or in
conjunction with TPS259470x to handle the power path protection requirements of USB PD ports as shown in
Figure 8-11 below.
LM73100 provides overvoltage protection on the sink path, while blocking reverse current from internal sink rail
to the port.
TPS259470x provides overcurrent & short-circuit protection in the source path, while blocking any reverse
current from the port to the internal source power rail. The fast recovery from reverse current blocking ensures
minimum supply droop during Fast Role Swap (FRS) events. The PD controller can also use the OVLO pin as
an active low enable signal to control the power path. Holding the OVLO pin high keeps the device in OFF state
in sink mode and blocks current in both directions. Once the PD controller determines the need to start sourcing
power, it can pull the OVLO pin low to trigger a fast recovery from OFF to ON state, meeting the FRS timing
requirements.
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VOUT = 5 V to 20 V
IN
OUT
OVLO
LM73100
IMON
PGTH
dVdt
GND
EN/UVLO PG
RIMON
VBUS = 5 V to 20V
CDVDT
PD Controller
VLOGIC
OVLO EN/UVLO FLT
VIN = 5 V to 20 V
IN
OUT
TPS259470L
AUXOFF
ITIMER dVdt GND
CITIMER
CDVDT
ILM
RILM
Figure 8-11. USB PD Port Protection
The linear ORing mechanism in TPS259470x & LM73100 ensures that there's no reverse current flowing from
one power source to the other during fast or slow ramp of either supply.
The following waveforms illustrate the LM73100 reverse current blocking behavior in USB applications.
36
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Figure 8-12. LM73100 Reverse Current Protection
During 20-V Hot-Plug at Output
Figure 8-13. LM73100 Reverse Current Protection
During 20-V Voltage Ramp at Output
8.6 Parallel Operation
Applications which need higher steady state current can use multiple LM73100 devices connected in parallel as
shown in Figure 8-14 below. In this configuration, the first device turns on initially to provide the inrush current
limiting. The second device is held in an OFF state by driving its EN/UVLO pin low by the PG signal of the first
device. Once the inrush sequence is complete, the first device asserts its PG pin high, allowing the second
device to turn. The second device asserts its PG signal to indicate that it has turned on fully, thereby indicating to
the system that the parallel combination is ready to deliver the full steady state current.
Once in steady state, the devices share current nearly equally. There could be a slight skew in the currents
depending on the part-to-part variation in the RON as well as the PCB trace resistance mismatch.
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IN
OUT
VLOGIC
EN/UVLO
LM73100
PGTH
PG
OVLO
dVdt
VIN = 2.7 to 23 V
GND
IMON
VOUT
CdVdt
COUT
IN
OUT
VLOGIC
EN/UVLO
LM73100
PGTH
PG
IMON
OVLO
dVdt
To
downstream
enable
GND
Figure 8-14. Two Devices Connected in Parallel for Higher Steady State Current Capability
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9 Power Supply Recommendations
The LM73100 devices are designed for a supply voltage range of 2.7 V ≤ VIN ≤ 23 V. An input ceramic bypass
capacitor higher than 0.1 μF is recommended if the input supply is located more than a few inches from the
device. The power supply must be rated higher than the set current limit to avoid voltage droops during
overcurrent and short-circuit conditions.
The maximum negative voltage the device can handle at the input is limited to -15 V or VOUT – 21 V, whichever
is higher. Any low voltage signals (e.g. EN/UVLO, OVLO, PGTH) derived from the input supply must have a
sufficiently large pull-up resistor to limit the current through those pins to < 10 μA during reverse polarity
conditions. Please refer to Absolute Maximum Ratings table for more details.
9.1 Transient Protection
When the device interrupts current flow in the case of a fast-trip event or during normal switch off, the input
inductance generates a positive voltage spike on the input, and the output inductance generates a negative
voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of
inductance in series to the input or output of the device. Such transients can exceed the absolute maximum
ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients
include:
•
•
•
•
•
Minimize lead length and inductance into and out of the device.
Use a large PCB GND plane.
Connect a Schottky diode from the OUT pin ground to absorb negative spikes.
Connect a low ESR capacitor of value greater than 1 μF at the OUT pin very close to the device.
Use a low-value ceramic capacitor CIN = 1 μF to absorb the energy and dampen the transients. The capacitor
voltage rating should be atleast twice the input supply voltage to be able to withstand the positive voltage
excursion during inductive ringing.
The approximate value of input capacitance can be estimated with Equation 15:
VSPIKE(Absolute) = VIN + ILOAD x
LIN
CIN
(15)
where
•
•
•
•
VIN is the nominal supply voltage.
ILOAD is the load current.
LIN equals the effective inductance seen looking into the source.
CIN is the capacitance present at the input.
Some applications may require the addition of a Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the absolute maximum ratings of the device. In some cases, even if the maximum amplitude of the
transients is below the absolute maximum rating of the device, a TVS can help to absorb the excessive energy
dump and prevent it from creating very fast transient voltages on the input supply pin of the IC, which can couple
to the internal control circuits and cause unexpected behavior.
Note
If there's a likelihood of input reverse polarity in the system, it's recommended to use a bi-directional
TVS, or a reverse blocking diode in series with the TVS.
The circuit implementation with optional protection components is shown in Figure 9-1.
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VIN = 2.7 to 23 V
IN
PGTH
EN/UVLO
D1
VOUT
OUT
LM73100
VLOGIC
D2
COUT
CIN
OVLO
dVdt
CDVDT
GND
IMON
PG
RIMON
Figure 9-1. Circuit Implementation with Optional Protection Components
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10 Layout
10.1 Layout Guidelines
•
For all applications, a ceramic decoupling capacitor of 0.1 μF or greater is recommended between the IN
terminal and GND terminal.
•
The optimal placement of the decoupling capacitor is closest to the IN pin and GND terminals of the device.
Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin and the
GND terminal of the IC.
•
High current-carrying power-path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
•
The GND terminal of the device must be tied to the PCB ground plane at the terminal of the IC with the
shortest possible trace. The PCB ground must be a copper plane or island on the board. It's recommended to
have a separate ground plane island for the device. This plane doesn't carry any high currents and serves as
a quiet ground reference for all the critical analog signals of the device. The device ground plane should be
connected to the system power ground plane using a star connection.
•
The IN and OUT pins are used for heat dissipation. Connect to as much copper area on top and bottom PCB
layers using as possible with thermal vias. The vias under the device also help to minimize the voltage
gradient accross the IN and OUT pads and distribute current unformly through the device, which is essential
to achieve the best on-resistance and current sense accuracy.
•
Locate the following support components close to their connection pins:
– RIMON
– CdVdT
– Resistors for the EN/UVLO, OVLO and PGTH pins
•
Connect the other end of the component to the GND pin of the device with shortest trace length. The trace
routing for the CdVdt must be as short as possible to reduce parasitic effects on the soft-start timing. These
traces must not have any coupling to switching signals on the board.
•
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect. These protection devices must be routed with short traces to reduce
inductance. For example, a protection Schottky diode is recommended between OUT terminal and GND
terminal to address negative transients due to switching of inductive loads. It's also recommended to add a
ceramic decoupling capacitor of 1 μF or greater between OUT and GND. These components must be
physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky
diode/bypass-capacitor connection, the OUT pin and the GND terminal of the IC.
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10.2 Layout Example
Inner GND layer
IN
OUT
8
7
3
4
9
Top layer
10
Power layer
6
2
1
5
Figure 10-1. Layout Example - Single LM73100 with PGTH Referred to OUT
42
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Inner GND layer
OUT
IN1
8
7
3
4
10
Top layer
9
Power layer
6
2
1
5
3
3
2
1
IN2
Figure 10-2. Layout Example - 2 x LM73100 in ORing Configuration
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• LM73100EVM Ideal Diode Evaluation Board
• Application note - eFuses for USB Type-C protection
• LM73100 Design Calculator
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
44
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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19-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM73100RPWR
ACTIVE
VQFN-HR
RPW
10
3000
RoHS & Green
Call TI | NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2AEH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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