LM74720-Q1
SLVSFH8B – SEPTEMBER 2021 – REVISED MARCH 2022
LM74720-Q1 Low IQ Automotive Ideal Diode Controller with Active Rectification and
Load Dump Protection
1 Features
3 Description
•
The LM74720-Q1 ideal diode controller drives and
controls external back-to-back N-Channel MOSFETs
to emulate an ideal diode rectifier with power path
ON/OFF control and overvoltage protection. The wide
input supply of 3 V to 65 V allows protection and
control of 12-V and 24-V automotive battery powered
ECUs. The device can withstand and protect the
loads from negative supply voltages down to –65 V.
An integrated ideal diode controller (GATE) drives
the first MOSFET to replace a Schottky diode for
reverse input protection and output voltage holdup.
A strong boost regulator with fast turn ON and OFF
comparators ensures robust and efficient MOSFET
switching performance during automotive testing such
as ISO16750 or LV124 where an ECU is subjected
to input short interruptions and AC superimpose input
signals up to 100-kHz frequency. Low Quiescent
Current 35 µA (maximum) in operation enables
always ON system designs. With a second MOSFET
in the power path, the device allows load disconnect
control using EN pin. Quiescent current reduces to
3.3 μA (maximum) with EN low. The device features
an adjustable overvoltage cut-off protection feature for
load dump protection.
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified with the following results
– Device temperature grade 1:
–40°C to +125°C ambient operating
temperature range
– Device HBM ESD classification level 2
– Device CDM ESD classification level C4B
3-V to 65-V input range
Reverse input protection down to –65 V
Low quiescent current, 35 µA (max) in operation
Low 3.3-µA (max) shutdown current (EN = Low)
Ideal diode operation with 17-mV A to C forward
voltage drop regulation
Drives external back-to-back N-Channel MOSFETs
Integrated 29-mA boost regulator
Fast response to reverse current blocking: 0.5 µs
Active rectification up to 100 kHz
Adjustable overvoltage protection
Meets automotive ISO7637 transient requirements
with a suitable TVS diode
Available in space saving 12-pin WSON package
Pin-to-pin compatible with LM74721-Q1
2 Applications
•
Automotive battery protection
– ADAS domain controller
– Premium audio amplifier
– Head unit
– Gateway
Device Information
(1)
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
LM74720-Q1
WSON (12)
3.0 mm × 3.0 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Q1
Q1
VBA TT
12 V
GATE
A
VSNS
SW
D1
SMBJ36CA
C VS CAP LX
GATE
A
VSNS
SW
R1
C VS CAP LX
PD
LM74720-Q1
BATT_MON
R2
BATT_MON
R2
EN
EN
R3
VOUT
D1
SMBJ36CA
PD
LM74720-Q1
R1
Q2
VBA TT
12 V
VOUT
OV
ON OFF
R3
OV
ON OFF
GND
GND
Low IQ Ideal Diode
Low IQ Ideal Diode with Switched Output
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM74720-Q1
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Typical Characteristics................................................ 7
7 Parameter Measurement Information............................ 9
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagram......................................... 10
8.3 Feature Description...................................................11
8.4 Device Functional Mode (Shutdown Mode).............. 13
9 Application and Implementation.................................. 14
9.1 Application Information............................................. 14
9.2 Typical 12-V Reverse Battery Protection
Application...................................................................14
9.3 Do's and Don'ts.........................................................22
10 Power Supply Recommendations..............................23
10.1 Transient Protection................................................ 23
10.2 TVS Selection for 12-V Battery Systems................ 24
10.3 TVS Selection for 24-V Battery Systems................ 24
11 Layout........................................................................... 25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 25
12 Device and Documentation Support..........................26
12.1 Third-Party Products Disclaimer............................. 26
12.2 Receiving Notification of Documentation Updates..26
12.3 Support Resources................................................. 26
12.4 Trademarks............................................................. 26
12.5 Electrostatic Discharge Caution..............................26
12.6 Glossary..................................................................26
13 Mechanical, Packaging, and Orderable
Information.................................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (January 2022) to Revision B (March 2022)
Page
• Changed status from "Advance Information" to "Production Data".....................................................................1
Changes from Revision * (September 2021) to Revision A (January 2022)
Page
• Updated the Electrical Characteristics and Switching Characteristics with specification limits.......................... 4
• Added the Typical Characteristics section.......................................................................................................... 7
2
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5 Pin Configuration and Functions
GATE
1
12
C
A
2
11
VS
VSNS
3
10
CAP
9
LX
8
PD
7
GND
RTN
SW
4
OV
5
EN
6
Exposed
Thermal
Pad
Figure 5-1. WSON 12-Pin DRR Transparent Top View
Table 5-1. Pin Functions
PIN
NAME
LM74720-Q1
TYPE
DESCRIPTION
DRR-12 (WSON)
GATE
1
O
Diode controller gate drive output. Connect to the GATE of the external
MOSFET.
A
2
I
Anode of the ideal diode. Connect to the source of the external MOSFET.
VSNS
3
I
Voltage sensing input
SW
4
I
Voltage sensing disconnect switch terminal. VSNS and SW are internally
connected through a switch. Use SW as the top connection of the battery
sensing or OV resistor ladder network. When EN is pulled low, the switch is
OFF, disconnecting the resistor ladder from the battery line, thereby cutting off
the leakage current. If the internal disconnect switch between VSNS and SW
is not used, then short them together and connect to C pin.
OV
5
I
Adjustable overvoltage threshold input. Connect a resistor ladder across SW
to OV terminal. When the voltage at OV exceeds the overvoltage cut-off
threshold, then the PD is pulled low turning OFF the HSFET. PD is driven
high when the sense voltage goes below the OV falling threshold.
EN
6
I
EN Input. Connect to A or C pin for always ON operation. In this mode, the
device consumes an IQ of 35 µA (maximum). Can be driven externally from a
micro controller I/O. Pulling the pin low below 0.5 V enters the device in low Iq
shutdown mode.
GND
7
G
Connect to the system ground plane.
PD
8
O
Pull down connection for the external load disconnect FET. Connect to the
GATE of the external FET to PD pin.
Leave PD pin floating if the load disconnect FET is not used.
LX
9
I
Switch node of the internal boost regulator. This node must be kept small
on the PCB for good performance and low EMI. Connect the boost inductor
between this pin and the DRAIN connection of the external FET.
CAP
10
O
Boost Regulator Output. This pin is used to provide a drive voltage to the gate
driver of the ideal diode stage as well as drive supply for the HSFET. Connect
a 1-µF capacitor between this pin and the VS pin.
VS
11
I
Supply voltage pin
C
12
I
Cathode of the ideal diode. Connect to the DRAIN of the external MOSFET.
The voltage sensed at this pin is used to control the external MOSFET GATE.
RTN
Thermal Pad
—
Leave exposed pad floating. Do not connect to GND plane.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Input Pins
MIN
MAX
A to GND
–65
70
VS, C to GND
–0.3
70
VSNS, SW, EN, OV to GND, V(A) > 0 V
–0.3
70
VSNS, SW, EN, OV to GND, V(A) ≤ 0 V
V(A)
(70 + V(A))
RTN to GND
–65
0.3
IVSNS, ISW
–1
10
IEN, IOV, V(A) > 0 V
–1
IEN, IOV, V(A) ≤ 0 V
Output Pins
Output to Input Pins
CAP to C
–0.3
15.9
CAP to A
–0.3
85
GATE to A
–0.3
15
LX, CAP, PD to GND
–0.3
85
–5
85
–40
150
Storage temperature, Tstg
–40
150
(2)
V
mA
Internally limited
Operating junction temperature, Tj (2)
(1)
UNIT
C to A
V
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002(1)
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
UNIT
±2000
Corner pins (GATE, EN, GND,
C)
±750
Other pins
±500
V
AEC-Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specifications.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
A to GND
Input Pins
External
capacitance
C to GND
NOM
MAX
UNIT
65
65
V
EN to GND
–60
A
0.1
µF
1
µF
100
µH
15
V
VS, CAP to C
External
Inductor
LX
External
MOSFET max
VGS rating
GATE to A
TJ
Operating junction temperature range(2)
(1)
4
–60
–40
65
150
°C
Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see Electrical Characteristics.
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High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.4 Thermal Information
LM74720-Q1
THERMAL METRIC(1)
DRR (WSON)
UNIT
12 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ΨJT
ΨJB
RθJC
(1)
61.6
°C/W
50
°C/W
32.7
°C/W
Junction-to-top characterization parameter
1.4
°C/W
Junction-to-board characterization parameter
32.7
°C/W
Junction-to-case (bottom) thermal resistance
6.9
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(VS) = 12 V, C(CAP) = 1 µF, V(EN) = 2 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VA POR Rising threshold
3.1
3.4
3.85
V
VA POR Falling threshold
2.2
2.6
2.9
V
3
V
SUPPLY VOLTAGE
V(A POR)
V(VS)
Minimum Voltage at VS
I(SHDN)
Shutdown Supply Current
I(Q)
Total System Quiescent Current
V(EN) = 0 V
1.5
3.3
µA
V(EN) = 2 V, Active Rectifier Controller
In Regulation, –40°C ≤ TJ ≤ +85°C
27
32
µA
V(EN) = 2 V, Active Rectifier Controller
In Regulation, –40°C ≤ TJ ≤ +125°C
27
35
µA
ENABLE INPUT
V(EN_IH)
Enable input high threshold
V(EN_IL)
Enable input low threshold
V(EN_Hys)
Enable Hysteresis
I(EN)
Enable sink current
2
0.5
0.85
1.2
380
V(EN) = 12 V
V
mV
52
155
nA
VANODE to VCATHODE (VA – C)
V(AC REG)
Regulated Forward V(AC) Threshold
9
16.4
22.7
mV
V(AC_FWD)
V(AC) threshold from RCB to oFCB
75
105
140
mV
V(AC_REV)
V(AC) threshold for reverse current
blocking
–12
–5.65
–1.3
mV
GATE DRIVE
V(GATE) – V(A)
I(GATE)
RGATE
3 V < V(VS) < 65 V
Peak sink current
V(A) – V(C) = –20 mV
Regulation max sink current
V(A) – V(C) = 0 V,
V(GATE) – V(A) = 5 V
GATE pulldown resistance
V(A) – V(C) = –20 mV,
V(GATE) – V(A) = 100 mV
9.5
13
2.5
14
26
V
A
39
1.2
µA
Ω
BOOST REGULATOR
V(CAP) – V(VS)
Boost output rising threshold
13
Hysteresis
I(CAP)
Boost load capacity
V(CAP) – V(VS) = 7.5 V
15.5
V
1.1
V
29
mA
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(VS) = 12 V, C(CAP) = 1 µF, V(EN) = 2 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(LX)
Peak inductor current limit threshold
R(LX)
Low side switch On-Resistance
V(VS) = 12 V
MIN
TYP
MAX
UNIT
110
140
170
mA
210
mA
1.3
2.7
5.1
Ω
430
Ω
V(VS) = 3 V
BATTERY SENSING (VSNS, SW) AND OVER VOLTAGE DETECTION (OV, PD)
R(SW)
Battery sensing disconnect switch
resistance
104
226
V(OVR)
Overvoltage threshold input, rising
1.13
1.231
1.33
V
V(OVF)
Overvoltage threshold input, falling
1.03
1.125
1.215
V
V(OV_Hys)
OV Hysteresis
I(OV)
OV Input leakage current
0 V < V(OV) < 5 V
I(PD_SRC)
Pullup current
3 V < V(VS) < 65 V
I(PD_SINK)
110
Peak pulldown current
V(OV) > V(OVR)
DC pulldown current
50
mV
110
nA
43
50
60
µA
55
88
117
mA
7
10
14
mA
8.5
15
µA
10.6
18
µA
CATHODE (C)
I(C)
V(A) = 12 V, V(A) – V(C) = –100 mV
CATHODE sink current
V(A) = –14 V, V(C) = 14 V
6.6 Switching Characteristics
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(VS) = 12 V, C(CAP) = 1 µF, V(EN) = 2 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER
6
TEST CONDITIONS
MIN
TYP
MAX
UNIT
200
µs
ENTDLY
A (low to high) to GATE Turn On delay
V(A) ↑ V(A POR) to V(GATE – A) > 5 V,
C(GATE – A) = 10 nF,
tGATE_OFF(DLY)
Reverse voltage detection to Gate Turn
Off delay
V(A) – V(C) = +30 mV to –100
mV, V(GATE) – V(A) < 1 V, C(GATE – A) =
10 nF
0.47
0.81
µs
tGATE_ON(DLY)
Forward voltage detection to Gate Turn
On delay
V(A) – V(C) = –100 mV to +700
mV, V(GATE) – V(A) > 5 V, C(GATE – A) =
10 nF
1.9
2.9
µs
tEN_OFF(DLY)PD EN to PD Delay
EN ↓ to PD ↓
6.5
12
µs
tOV_OFF(DLY)PD OV to PD Delay
OV ↑ to PD ↓
0.9
1.5
µs
tPD_Pk
I(PD_SINK, Pk) ↑ to I(PD_SINK, DC) ↓
38
65
µs
Peak Pull Down duration
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650
600
550
500
450
400
350
300
250
200
150
100
50
0
8
−40C
25C
85C
125C
150C
7
6
I(SHDN) (A)
IQ (A)
6.7 Typical Characteristics
5
4
3
−40C
25C
85C
125C
150C
2
1
0
5
10
15
20
25
30 35
VS (V)
40
45
50
55
60
65
0
0
5
10
15
Figure 6-1. Operating Quiescent Current vs Supply Voltage
20
25
30 35
VA (V)
40
45
50
55
60
65
Figure 6-2. Shutdown Supply Current vs Supply Voltage
VS POR Thresholds (V)
3.5
3
2.5
2
1.5
VS PORR
VS PORF
1
-50
Figure 6-3. VA POR Threshold vs Temperature
50
100
Temperature (C)
200
40
VS = 12 V
VS = 3 V
35
30
I(CAP) (mA)
13
12
11
25
20
15
10
(VCAP−VS) R
(VCAP−VS) F
10
-50
150
Figure 6-4. VS POR Threshold vs Temperature
14
Boost Comparator Thresholds (V)
0
0
50
100
Temperature (C)
150
200
Figure 6-5. Boost Comparator Threshold vs Temperature
5
0
-50
0
50
100
Temperature (C)
150
200
Figure 6-6. Boost Loading Capacity vs Temperature
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6.7 Typical Characteristics (continued)
1.3
1.2
tOV_OFF(deg)PD (s)
OVP Thresholds (V)
1
1.2
1.1
0.8
0.6
0.4
VOV_R
VOV_F
1
-50
0
50
100
Temperature (C)
150
0.2
-50
0
50
100
Temperature (C)
200
150
200
Figure 6-8. PD Turn-off Delay During OV
Figure 6-7. OV Threshold vs Temperature
4
8
7
tGATE_ON(DLY) (s)
tEN_OFF(dly)PD (s)
3
6
5
4
2
C(GATE − A)
C(GATE − A)
C(GATE − A)
C(GATE − A)
C(GATE − A)
1
3
2
-50
0
50
100
Temperature (C)
150
0
-50
200
50
100
Temperature (C)
4.7 nF
10 nF
22 nF
33 nF
47 nF
150
200
Figure 6-10. Forward Turn-on Delay vs Temperature
Figure 6-9. PD Turn-off Delay During EN
5
90
60
RPD = 270
RPD = 330
PD Turn-Off Delay (s)
4.5
30
I(GATE) (A)
0
=
=
=
=
=
0
-30
-60
4
3.5
3
2.5
-90
-10
0
10
20
V(A− C) mV
30
40
50
2
5
10
Figure 6-11. Gate Current vs Forward Voltage Drop
15
20
25
30
35 40
VS (V)
45
50
55
60
65
Figure 6-12. PD Turn-off Delay vs Supply Voltage
8
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7 Parameter Measurement Information
V A – VC
30 mV
VA > VC
0 mV
VC > VA
–100 mV
VGATE – VA
VGATE
1V
0V
ttGATE_OFF(DLY)t
V A – VC
700 mV
VA > VC
0 mV
VC > V A
–100 mV
VGATE – VA
VGATE
5V
0V
ttGATE_ON(DLY)t
VOV
VOVR + 0.1 V
0V
VPD – VOUT
VPD
0V
ttOV_OFF(DLY)PDt
Figure 7-1. Timing Waveforms
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8 Detailed Description
8.1 Overview
The LM74720-Q1 ideal diode controller drives and controls external back-to-back N-Channel MOSFETs to
emulate an ideal diode rectifier with power path ON and OFF control and overvoltage protection. The wide
input supply of 3 V to 65 V allows protection and control of 12-V and 24-V automotive battery powered ECUs.
IQ during operation (EN = High) is < 35 µA and < 3.3 µA during shutdown mode (EN = Low). The device
can withstand and protect the loads from negative supply voltages down to –65 V. An integrated ideal diode
controller (GATE) drives the first MOSFET to replace a Schottky diode for reverse input protection and output
voltage holdup. A strong 29-mA boost regulator and short turn-ON and turn-OFF delay times of comparators
ensures fast transient response ensuring robust and efficient MOSFET switching performance during automotive
testing such as ISO16750 or LV124 where an ECU is subjected to input short interruptions and AC superimpose
input signals up to 100-kHz frequency. The device features an adjustable over voltage cut-off protection feature
for load dump protection.
The LM74720-Q1 controls the GATE of the MOSFET to regulate the forward voltage drop at 17 mV. The linear
regulation scheme in these devices enables graceful control of the GATE voltage and turns off of the MOSFET
during a reverse current event and ensures zero DC reverse current flow.
Low quiescent current (< 35 µA) in operation enables always ON system designs. With a second MOSFET in the
power path, the device allows load disconnect control using EN pin. Quiescent current reduces to 3.3 μA with
EN low.
8.2 Functional Block Diagram
Q1
VBATT
Q2
VOUT
18V
A
C VS
GATE
CAP
LX
PD
VSNS
50 µA
EN
SW
R1
BATT_MON
A+10 V
Boost
Converter and
control
Reverse Current
Protection controller and
Gate Driver
EN
88 mA
10 mA
R2
OV
+
1.231 V
R3
1.125 V
RTN
OV
–
C
2.55 V
2.5 V
EN
EN
+
–
OV
+
2V
0.5 V
VCAP
–
VA
RTN
A
A+10 V
Bias Rails
Reverse
Protection Logic
GND
10
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8.3 Feature Description
8.3.1 Dual Gate Control (GATE, PD)
The LM74720-Q1 features two separate gate control and driver outputs. That is, GATE and PD to drive back-toback N-channel MOSFETs.
8.3.1.1 Reverse Battery Protection (A, C, GATE)
A, C, GATE comprises of Ideal Diode stage. Connect the Source of the external MOSFET to A, Drain to C and
Gate to GATE pin. The LM74720-Q1 has integrated reverse input protection down to –65 V.
In LM74720-Q1, the voltage drop across the MOSFET is continuously monitored between the A and C pins,
and the GATE to A voltage is adjusted as needed to regulate the forward voltage drop at 17 mV (typical)
for LM74720-Q1. This closed loop regulation scheme enables graceful turn-off of the MOSFET during a
reverse current event and ensures zero DC reverse current flow. This scheme ensures robust performance
during slow input voltage ramp down tests. Along with the linear regulation amplifier scheme, the LM74720-Q1
also integrates a fast reverse voltage comparator. When the voltage drop across A and C reaches V(AC_REV)
threshold, then the GATE goes low within 0.5 µs (typical). This fast reverse voltage comparator scheme ensures
robust performance during fast input voltage ramp down tests such as input micro-shorts. The external MOSFET
is turned back ON when the voltage across A and C hits V(AC_FWD) threshold within 1.9 µs (typical). For ideal
diode only designs, connect LM74720-Q1 as shown in Figure 8-1.
Q1
VBA TT
12 V
VOUT
GATE
A
VSNS
SW
D1
SMBJ36CA
C VS CAP LX
PD
LM74720-Q1
R1
BATT_MON
R2
EN
R3
OV
ON OFF
GND
Figure 8-1. Configuring LM74720-Q1 for Ideal Diode Only
8.3.1.2 Load Disconnect Switch Control (PD)
PD pin provides a 50-µA drive and 88-mA peak pulldown strength for the load disconnect switch stage. Connect
the Gate of the FET to PD pin. Place a 18-V Zener (Dz) across the FET gate and source.
For inrush current limiting, connect CdVdT capacitor and R1 as shown in Figure 8-2.
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Q1
Dz
18 V
COUT
R1
RPD
50 µA
Fault
Off
CdVdT
PD
88 mA
10 mA
GND
Figure 8-2. Inrush Current Limiting
The CdVdT capacitor is required for slowing down the PD voltage ramp during power up for inrush current
limiting. Use Equation 1 to calculate CdVdT capacitance value.
CdVdT =
I PD_DRV
I INRUSH
x COUT
(1)
where IPD_DRV is 50 μA (typical), IINRUSH is the inrush current, and COUT is the output load capacitance. An extra
resistor, R1, in series with the CdVdT capacitor improves the turn-off time.
PD is pulled low during the following conditions:
•
•
•
During an OV event with the OV pin voltage rising above the V(OVR) threshold
When the EN pin is pulled low with V(EN) driven lower than V(EN_IL) level
When the voltage at VS pin drops below the V(VS POR) falling threshold
During these conditions, the FET Q1 turns OFF with its GATE connected to its SOURCE terminal through the
external Zener (Dz).
The peak power dissipated in the LM74720-Q1 at the instance of PD pulldown can be calculated approximately
using Equation 2.
PPD_peak = VOUT × IPD_SINK
(2)
where
•
IPDSINK_peak is the peak sink current of 88 mA (typical)
In the system designs with input voltage above 48 V, TI recommends to place a resistor, RPD, in series with
the PD pin as shown in Figure 8-2. The peak power dissipation during the pulldown events gets distributed in
RPD and the internal PD switch. A resistor value in the range of 270 Ω to 330 Ω can be selected to limit the
device power dissipation within the safe limits. Figure 6-12 shows the turn-OFF delay characteristics with various
resistors.
8.3.2 Overvoltage Protection and Battery Voltage Sensing (VSNS, SW, OV)
Connect a resistor ladder as shown in Figure 8-3 for overvoltage threshold programming.
12
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VBATT
A
SNS
EN
SW
R1
BATT_MON
LM74720-Q1
R2
OV
R3
+
1.231 V
1.125 V
PD_OFF
–
Figure 8-3. Programming Overvoltage Threshold and Battery Sensing
A disconnect switch is integrated between VSNS and SW pins. This switch is turned OFF when EN pin is pulled
low. This action helps to reduce the leakage current through the resistor divider network during system shutdown
state (IGN_OFF state).
8.3.3 Boost Regulator
The LM74720-Q1 integrates a boost converter to provide voltage necessary to drive the external N-channel
MOSFETs for the ideal diode and the load disconnect stages. The boost converter uses hysteretic mode control
scheme for the output voltage (VCAP–VVS) regulation along with the constant peak inductor current limit (ILX).
When the CAP–VS voltage is below its nominal value of typically 11.9 V, the low side switch of the boost is
turned on and the inductor current rises with the slope of VS/L approximately. After the current hits the limit
of ILX , that is,140 mA (typical), then the low side switch is turned off and the inductor current discharges to
the output till it reaches zero. The low side switch is turned on again and the switching cycle repeats until the
CAP–VS voltage has risen above the boost rising threshold of 13 V (typical). After this threshold level is reached,
the boost converter switching is turned OFF to reduce the quiescent current.
For the boost converter to be enabled, the EN pin voltage must be above the specified input high threshold,
V(ENR). The boost converter has a maximum output load capacity of 29-mA typical. If EN pin is pulled low, then
the boost converter remains disabled.
8.4 Device Functional Mode (Shutdown Mode)
The LM74720-Q1 enters shutdown mode when the EN pin voltage is below the specified input low threshold,
V(EN_IL). Both the gate drivers (GATE and PD) and the boost regulator are disabled in shutdown mode. During
shutdown mode, the LM74720-Q1 enters low IQ operation with a total input quiescent consumption of 1.5 µA
(typical).
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
LM74720-Q1 controls two N-channel power MOSFETs with GATE used to control diode MOSFET to emulate an
ideal diode and PD controlling second MOSFET for power path cut-off when disabled or during an overvoltage
protection and provide inrush current limiting. IQ during operation (EN = High) is < 35 µA and 37 V
AC super imposed test
2-V peak-peak 30 kHz, extendable to 6-V peak-peak 30 kHz
Automotive transient immunity compliance
ISO 7637-2, ISO 16750-2 and LV124
Battery monitor ratio
8:1
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9.2.2 Automotive Reverse Battery Protection
9.2.2.1 Input Transient Protection: ISO 7637-2 Pulse 1
ISO 7637-2 pulse 1 specifies negative transient immunity of electronic modules connected in parallel with
an inductive load when the battery is disconnected. A typical pulse 1 specified in ISO 7637-2 starts with
battery disconnection where supply voltage collapses to 0 V followed by –150 V 2 ms applied with a source
impedance of 10 Ω at a slew rate of 1 µs on the supply input. LM74720-Q1 blocks reverse current and
prevents the output voltage from swinging negative, protecting the rest of the electronic circuits from damage
due to negative transient voltage. MOSFET Q1 is quickly turned off within 0.5 µs by fast reverse comparator of
LM74720-Q1. A single bidirectional TVS is required at the input to clamp the negative transient pulse within the
operating maximum voltage across cathode to anode of 85 V and does not violate the MOSFET Q1 drain-source
breakdown voltage rating.
Figure 9-2 shows ISO 7637-2 pulse 1 performance of LM74720-Q1.
VOUT
VIN
IIN
VGATE
Figure 9-2. Performance During ISO 7637-2 Pulse 1 Test
9.2.2.2 AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
All electronic modules are tested for proper operation with superimposed AC ripple on the DC battery voltage.
AC super imposed test specified in ISO 16750-2 and LV124 E-06 requires AC ripple of 2-V peak-peak on a
13.5-V DC battery voltage, swept from 15 Hz to 30 kHz. LM74720-Q1 rectifies the AC superimposed voltage by
turning the MOSFET Q1 OFF quickly to cut off reverse current and turning the MOSFET Q1 ON quickly during
forward conduction. Active rectification of 2-V peak-peak 5-kHz AC input by LM74720-Q1 is shown in Figure
9-3. Fast turn-OFF and quick turn-ON of the MOSFET reduces power dissipation in the MOSFET Q1 and active
rectification reduces power dissipation in the output hold-up capacitor's ESR by half. Active rectification of 2-V
peak-peak 30-kHz AC input is shown in Figure 9-4.
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VIN
VIN
VOUT
VOUT
VGATE
VGATE
IIN
IIN
Figure 9-3. AC Super Imposed Test – 2-V PeakPeak 5 kHz
Figure 9-4. AC Super Imposed Test – 2-V PeakPeak 30 kHz
9.2.2.3 Input Micro-Short Protection: LV124 E-10
E-10 test specified in LV124 standard checks for immunity of electronic modules to short interruptions in power
supply input due to contact issues or relay bounce. During this test (case 2), micro-short is applied on the input
for a duration as low as 10 µs to several ms. For a functional pass status A, electronic modules are required to
run uninterrupted during the E-10 test (case 2) with 100-µs duration. When input micro-short is applied for 100
µs, LM74720-Q1 quickly turns off MOSFET Q1 by shorting GATE to ANODE (source of MOSFET) within 0.5 µs
to prevent the output from discharging and the PD remains ON keeping MOSFET Q2 ON, enabling fast recovery
after the input short is removed.
Figure 9-5 shows performance of LM74720-Q1 during E10 input power supply interruption test case 2. After the
input short is removed, input voltage recovers and MOSFET Q1 is turned back ON within 200 µs. Note that
dual-gate drive topology allows MOSFET Q2 to remain ON during the test and helps in restoring the input power
faster. Output voltage remains unperturbed during the entire duration, achieving functional status A.
VIN
VIN
VOUT
VOUT
VGATE
VGATE
VPD
IIN
Figure 9-5. Input Micro-Short – LV124 E10 TC 2 100 Figure 9-6. Input Micro-Short – LV124 E10 TC 2 100
µs
µs With PD
16
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9.2.3 Detailed Design Procedure
9.2.3.1 Design Considerations
Table 9-1 summarizes the design parameters that must be known for designing an automotive reverse battery
protection circuit with overvoltage cut-off. During power up, inrush current through MOSFET Q2 must be limited
so that the MOSFET operates well within its SOA. Maximum load current, maximum ambient temperature,
and thermal properties of the PCB determine the RDSON of the MOSFET Q2 and maximum operating voltage
determines the voltage rating of the MOSFET Q2. Selection of MOSFET Q2 is determined mainly by the
maximum operating load current, maximum ambient temperature, maximum frequency of AC super imposed
voltage ripple, and ISO 7637-2 pulse 1 requirements. Overvoltage threshold is decided based on the rating
of downstream DC/DC converter or other components after the reverse battery protection circuit. A single
bidirectional TVS or two back-back unidirectional TVS are required to clamp input transients to a safe operating
level for the MOSFETs Q1, Q2, and LM74720-Q1.
9.2.3.2 Boost Converter Components (C2, C3, L1)
Place a minimum of a 1-μF capacitor across drain of the FET to GND (C2) and across CAP pin of LM74720Q1 to drain of the FET (C3). Use a 100-μH inductor (L1) with saturation current rating > 175 mA. Example:
XPL2010-104ML from coil craft.
9.2.3.3 Input and Output Capacitance
TI recommends a minimum input capacitance C1 of 0.1 µF and output capacitance COUT of 0.1 µF.
9.2.3.4 Hold-Up Capacitance
Usually bulk capacitors are placed on the output due to various reasons such as uninterrupted operation during
power interruption or micro-short at the input, hold-up requirements for doing a memory dump before turning of
the module and filtering requirements as well. This design considers minimum bulk capacitors requirements for
meeting functional status "A" during LV124 E10 test case 2 100-µs input interruption. To achieve functional pass
status A, acceptable voltage droop in the output of LM74720-Q1 is based on the UVLO settings of downstream
DC/DC converters. For this design, a 1-V drop in output voltage for 100 µs is considered and the minimum
hold-up capacitance required is calculated by
CHOLD_UP_MIN =
I LOAD_MAX
dVOUT
x100 P s
(3)
Hold-up capacitance required for 1-V drop in 100 µs is 470 µF.
9.2.3.5 Overvoltage Protection and Battery Monitor
Resistors R1, R2 and R3 connected in series are used to program the overvoltage threshold and battery monitor
ratio. The resistor values required for setting the overvoltage threshold VOV to 37 V and battery monitor ratio
VBATT_MON : VBATT to 1:8 are calculated by solving Equation 3 and Equation 4.
VOVR =
R3
x VOV
R1 + R 2 + R 3
VBAT_MON =
(4)
R2 + R3
x VBATT
R1 + R 2 + R 3
(5)
For minimizing the input current drawn from the battery through resistors R1, R2 and R3, TI recommends to use
higher value of resistance. Using high value resistors adds error in the calculations because the current through
the resistors at higher value become comparable to the leakage current into the OV pin. Maximum leakage
current into the OV pin is 1 µA and choosing (R1 + R2 + R3) < 120 kΩ ensures current through resistors is 100
times greater than leakage through OV pin.
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Based on the device electrical characteristics, VOVR is 1.23 V and battery monitor ratio (VBATT_MON / VBATT) is
designed for a ratio of 1:8. To limit (R1 + R2 + R3) < 120 kΩ, select (R1 + R2) = 100 kΩ. Solving Equation 3 gives
R3 = 3.45 kΩ. Solving Equation 4 for R2 using (R1 + R2) = 100 kΩ and R3 = 3.45 kΩ, gives R2 = 9.48 kΩ and R1
= 90.52 kΩ.
Standard 1% resistor values closest to the calculated resistor values are R1 = 90.9 kΩ, R2 = 9.09 kΩ, and R3 =
3.48 kΩ.
9.2.3.6 MOSFET Selection: Blocking MOSFET Q1
For selecting the blocking MOSFET Q1, important electrical parameters are the maximum continuous drain
current ID, the maximum drain-to-source voltage VDS(MAX), the maximum drain-to-source voltage VGS(MAX), the
maximum source current through body diode and the drain-to-source ON resistance RDSON.
The maximum continuous drain current, ID, rating must exceed the maximum continuous load current.
The maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest differential
voltage seen in the application. This action includes all the automotive transient events and any anticipated fault
conditions. TI recommends to use MOSFETs with VDS voltage rating of 60 V along with a single bidirectional
TVS or a VDS rating 40-V maximum rating along with two unidirectional TVS connected back-to-back at the
input.
The maximum VGS LM74720-Q1 can drive is 14 V, so a MOSFET with 15-V minimum VGS rating must be
selected. If a MOSFET with < 15-V VGS rating is selected, a zener diode can be used to clamp VGS to safe level,
but this results in increased IQ current.
To reduce the MOSFET conduction losses, lowest possible RDS(ON) is preferred, but selecting a MOSFET
based on low RDS(ON) cannot be beneficial always. Higher RDS(ON) provides increased voltage information to
LM74720-Q1's reverse comparator at a lower reverse current. Reverse current detection is better with increased
RDS(ON). Choosing a MOSFET with < 50-mV forward voltage drop at maximum current is a good starting point.
Based on the design requirements, BUK7Y4R8-60E MOSFET is selected
9.2.3.7 MOSFET Selection: Load Disconnect MOSFET Q2
The VDS rating of the MOSFET Q2 must be sufficient to handle the maximum system voltage along with the
input transient voltage. For this 12-V design, transient overvoltage events are during suppressed load dump 35
V 400 ms and ISO 7637-2 pulse 2 A 50 V for 50 µs. Furthermore, ISO 7637-2 Pulse 3B is a very fast repetitive
pulse of 100 V 100 ns that is usually absorbed by the input and output ceramic capacitors and the maximum
voltage on the 12-V battery can be limited to < 40 V the minimum recommended input capacitance of 0.1 µF.
The 50-V SO 7637-2 Pulse 2 A can also be absorbed by input and output capacitors and its amplitude can be
reduced to 40-V peak by placing sufficient amount of capacitance at input and output. Choose a MOSFET with ≥
40-V VDS rating.
The VGS rating of the MOSFET Q2 must be higher than that maximum boost drive output of 15.5 V. FET with
VGS absolute maximum rating of +/– 20 VGS is selected.
Inrush current through the MOSFET during input hot-plug into the 12-V battery is determined by output
capacitance. External capacitor on PD, CDVDT, is used to limit the inrush current during input hot-plug or startup.
The value of inrush current determined by Equation 1 must be selected to ensure that the MOSFET Q2 is
operating well within its safe operating area (SOA). To limit inrush current to 1.8-A, value of CDVDT is 10.43 nF,
closest standard value of 10.0 nF is chosen.
Duration of inrush current is calculated by:
dTINRUSH =
12
I INRUSH
x COUT
(6)
Calculated inrush current duration is 3.13 ms with 1.8-A inrush current.
18
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MOSFET BUK7Y4R8-60E having 60-V VDS and ±20-V VGS rating is selected for Q2. Power dissipation during
inrush is well within the MOSFET's safe operating area (SOA).
9.2.3.8 TVS Selection
TI recommends a 600-W SMBJ TVS such as SMBJ33CA for input transient clamping and protection. For
detailed explanation on TVS selection for 12-V battery systems, refer to TVS Selection for 12-V Battery Systems.
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9.2.4 Application Curves
VIN
VIN
VOUT
VCAP
VGATE
VPD
VLX
IL
Figure 9-7. Start-up 12 V with EN Pulled to VIN
Figure 9-8. Start-up 12 V Showing Boost Output
(VCAP) and Switching (VLX)
VIN
VIN
VOUT
VPD
VOUT
VGATE
IIN
IIN
Figure 9-9. Reverse Input Voltage –14 V for 60 s
Figure 9-10. Inrush Current with No Load at Output
VIN
VIN
VOUT
VOUT
VPD
VPD
IIN
IIN
Figure 9-11. Inrush Current with 60-Ω Load
20
Figure 9-12. Hot-Plug into 12 V
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VIN
VIN
VOUT
VOUT
VEN
VGATE
VEN
IIN
Figure 9-13. Output Turn-on with Enable
Figure 9-14. GATE Turn-on with Enable
VIN
VIN
VOUT
VPD
VOUT
VPD
VEN
IIN
Figure 9-15. PD Turn-on with Enable
Figure 9-16. Overvoltage Protection
VIN
VIN
VOUT
VPD
VOUT
VEN
VPD
IIN
Figure 9-17. Overvoltage Recovery
Figure 9-18. Turn-on Delay – PD
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VIN
VIN
VOUT
VOUT
VPD
VGATE
VEN
VEN
Figure 9-19. Turn-off Delay – GATE
Figure 9-20. Turn-off Delay – PD
9.3 Do's and Don'ts
•
•
22
Leave the exposed pad (RTN) of the IC floating. Do not connect the exposed pad to the GND plane.
Connecting RTN to GND disables the reverse polarity protection feature.
Connect a limiting resistor RPD in series with the PD pin in the system application designs with input voltage
above 48 V. This resistor value can be chosen in the range of 270 Ω to 330 Ω.
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10 Power Supply Recommendations
10.1 Transient Protection
When the external MOSFETs turn OFF during the conditions, such as overvoltage cut-off, reverse current
blocking, EN causing an interruption of the current flow, the input line inductance generates a positive voltage
spike on the input and output inductance generates a negative voltage spike on the output. The peak amplitude
of voltage spikes (transients) depends on the value of inductance in series to the input or output of the device.
These transients can exceed the Absolute Maximum Ratings of the device if steps are not taken to address the
issue.
Typical methods for addressing transients include:
•
•
•
•
Minimizing lead length and inductance into and out of the device
Using large PCB GND plane
Using a Schottky diode across the output and GND to absorb negative spikes
Using a low value ceramic capacitor (C(IN) to approximately 0.1 μF) to absorb the energy and dampen the
transients.
The approximate value of input capacitance can be estimated with Equation 7.
L(IN)
Vspike(Absolute ) = V(IN) + I(Load) ´
C(IN)
(7)
where
•
•
•
•
V(IN) is the nominal supply voltage
I(LOAD) is the load current
L(IN) equals the effective inductance seen looking into the source
C(IN) is the capacitance present at the input
Some applications can require additional Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device. These transients can occur during EMC testing such as
automotive ISO7637 pulses.
The circuit implementation with optional protection components (a ceramic capacitor, TVS, and Schottky diode)
is shown in Figure 10-1.
Q1
Q2
VOUT
VIN
*
C2
*
C3
CIN
L1
D1
GATE
A
VSNS
SW
C VS CAP LX
D2
D3
PD
LM74720-Q1
R1
BATT_MON
R2
EN
R3
*
OV
ON OFF
GND
Optional components needed for suppression of transients
Figure 10-1. Circuit Implementation With Optional Protection Components for LM74720-Q1
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10.2 TVS Selection for 12-V Battery Systems
In selecting the TVS, important specifications are breakdown voltage and clamping voltage. The breakdown
voltage of the TVS+ must be higher than 24-V jump start voltage and 35-V suppressed load dump voltage and
less than the maximum ratings of LM74720-Q1 (65 V). The breakdown voltage of TVS– must be beyond than
maximum reverse battery voltage –16 V, so that the TVS– is not damaged due to long time exposure to reverse
connected battery.
Clamping voltage is the voltage the TVS diode clamps in high current pulse situations and this voltage is much
higher than the breakdown voltage. In the case of an ISO 7637-2 pulse 1, the input voltage goes up to –150 V
with a generator impedance of 10 Ω. This action translates to 15 A flowing through the TVS–, and the voltage
across the TVS is close to its clamping voltage.
The next criterion is that the absolute maximum rating of cathode to anode voltage of the LM74720-Q1 (85 V)
and the maximum V DS rating MOSFET are not exceeded. In the design example, 60-V rated MOSFET is chosen
and maximum limit on the cathode to anode voltage is 60 V.
During ISO 7637-2 pulse 1, the anode of LM74720-Q1 is pulled down by the ISO pulse, clamped by TVS– and
the MOSFET Q1 is turned off quickly to prevent reverse current from discharging the bulk output capacitors.
When the MOSFET turns off, the cathode to anode voltage seen is equal to (TVS Clamping voltage + Output
capacitor voltage). If the maximum voltage on output capacitor is 16 V (maximum battery voltage), then the
clamping voltage of the TVS– must not exceed, (60 V – 16) V = –44 V.
The SMBJ33CA TVS diode can be used for 12-V battery protection application. The breakdown voltage of 36.7
V meets the jump start, load dump requirements on the positive side and 16-V reverse battery connection on the
negative side. During ISO 7637-2 pulse 1 test, the SMBJ33CA clamps at –44 V with 12 A of peak surge current
as shown in and it meets the clamping voltage ≤ 44 V.
SMBJ series of TVS' are rated up to 600-W peak pulse power levels and are sufficient for ISO 7637-2 pulses.
10.3 TVS Selection for 24-V Battery Systems
For 24-V battery protection application, the TVS and MOSFET in Figure 9-1 must be changed to suit 24-V
battery requirements.
The breakdown voltage of the TVS+ must be higher than 48-V jump start voltage, less than the absolute
maximum ratings of anode and enable pin of LM74720-Q1 (70 V) and must withstand 65-V suppressed load
dump. The breakdown voltage of TVS– must be lower than maximum reverse battery voltage –32 V, so that the
TVS– is not damaged due to long time exposure to reverse connected battery.
During ISO 7637-2 pulse 1, the input voltage goes up to –600 V with a generator impedance of 50 Ω. This
translates to 12 A flowing through the TVS–. The clamping voltage of the TVS– cannot be same as that of 12-V
battery protection circuit. Because during the ISO 7637-2 pulse, the Anode to Cathode voltage seen is equal to
(– TVS Clamping voltage + Output capacitor voltage). For 24-V battery application, the maximum battery voltage
is 32 V, then the clamping voltage of the TVS- must not exceed, 85 V – 32 V = 53 V.
Single bidirectional TVS cannot be used for 24-V battery protection because breakdown voltage for TVS+ ≥
65 V, maximum clamping voltage is ≤ 53 V and the clamping voltage cannot be less than the breakdown
voltage. Two un-directional TVS connected back-to-back must be used at the input. For positive side TVS+, TI
recommends SMBJ58A with the breakdown voltage of 64.4 V (minimum), 67.8 (typical). For the negative side
TVS–, TI recommends SMBJ28A with breakdown voltage close to 32 V (to withstand maximum reverse battery
voltage –32 V) and maximum clamping voltage of 42.1 V.
For 24-V battery protection, TI recommends a 75-V rated MOSFET to be used along with SMBJ28A and
SMBJ58A connected back-to-back at the input.
24
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11 Layout
11.1 Layout Guidelines
•
•
•
•
•
For the ideal diode stage, connect A, GATE and C pins of LM74720-Q1 close to the MOSFET's SOURCE,
GATE and DRAIN pins.
The high current path of for this solution is through the MOSFET; therefore, it is important to use thick and
short traces for source and drain of the MOSFET to minimize resistive losses.
The GATE pin of the LM74720-Q1 must be connected to the MOSFET GATE with short trace.
Boost converter switching currents flow into LX, CAP, GND pins and C3 (across DRAIN of the FET to GND).
The loops formed by capacitor across CAP pin and DRAIN of the FET and C3 to GND must be minimized by
placing these capacitors as close as possible. Keep the GND side of the C3 capacitor close to GND pin of
LM74720-Q1.
Place transient suppression components like input TVS and output Schottky close to LM74720-Q1.
D
S
D
D
S
G
D
11.2 Layout Example
s
Q1
VIN PLANE
D
D
G
Q2
s
D
D
S
GATE
C
A
VS
VSNS
CAP
SW
LX
OV
PD
EN
GND
s
D2
C2
VOUT PLANE
L1
C3
D1
COUT
GND PLANE
Figure 11-1. LM74720-Q1 Layout Example
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Product Folder Links: LM74720-Q1
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LM74720-Q1
www.ti.com
SLVSFH8B – SEPTEMBER 2021 – REVISED MARCH 2022
12 Device and Documentation Support
12.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: LM74720-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM74720QDRRRQ1
ACTIVE
WSON
DRR
12
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
L74720
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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