LM76
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LM76 ±0.5°C, ±1°C, 12-Bit + Sign Digital Temperature Sensor and Thermal Window
Comparator with Two-Wire Interface
Check for Samples: LM76
FEATURES
DESCRIPTION
•
The LM76 is a digital temperature sensor and thermal
window comparator with an I2C Serial Bus interface
with an accuracy of ±1°C. This accuracy for the
LM76CHM is specified for a −10°C to 45°C
temperature range. The LM76CHM is specified with
an accuracy ±0.5°C at 25°C. The window-comparator
architecture of the LM76 eases the design of
temperature control systems conforming to the ACPI
(Advanced Configuration and Power Interface)
specification for personal computers. The open-drain
Interrupt (INT) output becomes active whenever
temperature goes outside a programmable window,
while a separate Critical Temperature Alarm
(T_CRIT_A) output becomes active when the
temperature exceeds a programmable critical limit.
The INT output can operate in either a comparator or
event mode, while the T_CRIT_A output operates in
comparator mode only.
1
2
•
•
•
•
•
Window Comparison Simplifies Design of
ACPI Compatible Temperature Monitoring and
Control.
Serial Bus Interface
Separate Open-Drain Outputs for Interrupt and
Critical Temperature Shutdown
Shutdown Mode to Minimize Power
Consumption
Up to 4 LM76s can be Connected to a Single
Bus
12-bit + Sign Output; Full-scale Reading of
Over 127°C
KEY SPECIFICATIONS
•
•
•
•
Supply Voltage 5.0V
Supply Current
– Operating
– 250 µA (typ)
– 450 µA (max)
– Shutdown
– 8 µA (max)
Temperature +25ºC ±0.5ºC (max)
– Accuracy
– –10ºC to +45ºC ±10°C (max)
– 70°C to 100°C ±1.0°C (max)
Resolution 0.0625°C
The host can program both the upper and lower limits
of the window as well as the critical temperature limit.
Programmable hysterisis as well as a fault queue are
available to minimize false tripping. Two pins (A0, A1)
are available for address selection. The sensor
powers up with default thresholds of 2°C THYST, 10°C
TLOW, 64°C THIGH, and 80°C T_CRIT.
The LM76's 5.0V supply voltage, Serial Bus interface,
12-bit + sign output, and full-scale range of over
127°C make it ideal for a wide range of applications.
These include thermal management and protection
applications in personal computers, electronic test
equipment, office electronics and bio-medical
applications.
APPLICATIONS
•
•
•
•
System Thermal Management
Personal Computers
Office Electronics
HVAC
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM76
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Simplified Block Diagram
Connection Diagram
Figure 1. SOIC-8
LM76 See Package Number D
PIN DESCRIPTIONS
Label
Pin #
Function
Typical Connection
SDA
1
Serial Bi-Directional Data Line, Open Drain Output, CMOS
Logic Level
SCL
2
Serial Bus Clock Input, CMOS Logic Level
From Controller I2C Clock Line
T_CRIT_A
3
Critical Temperature Alarm, Open Drain Output
Pull Up Resistor, Controller Interrupt Line or
System Hardware Shutdown
GND
4
Power Supply Ground
Ground
5
Interrupt, Open Drain Output
Pull Up Resistor, Controller Interrupt Line
User-Set Address Inputs, TTL Logic Level
Ground (Low, “0”) or +VS (High, “1”)
Positive Supply Voltage Input
DC Voltage from 3.3V power supply or 5V.
INT
A0–A1
+VS
7, 6
8
Pull Up Resistor, Controller I2C Data Line
Figure 2. Typical Application
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
−0.3V to 6.5V
Supply Voltage
−0.3V to (+VS + 0.3V)
Voltage at any Pin
Input Current at any Pin
Package Input Current
5mA
(2)
20mA
T_CRIT_A and
INT Output Sink Current
10mA
T_CRIT_A and
INT Output Voltage
6.5V
−65°C to +125°C
Storage Temperature
Soldering Information, Lead Temperature
SOIC Package (3)
ESD Susceptibility
Vapor Phase (60 seconds)
(4)
215°C
Infrared (15 seconds)
220°C
Human Body Model
3000V
Machine Model
(1)
(2)
(3)
(4)
250V
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its rated operating conditions.
When the input voltage (VI) at any pin exceeds the power supplies (VI < GND or VI > +VS) the current at that pin should be limited to 5
mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input
current of 5 mA to four.
See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current
Texas Instruments Linear Data Book for other methods of soldering surface mount devices.
Human body model, 100 pF discharged through a 1.5 kΩ resistor. Machine model, 200 pF discharged directly into each pin.
Operating Ratings (1) (2)
−55°C to +150°C
Operating Temperature Range
Specified Temperature Range (3)
TMIN to TMAX
−20°C to +85°C
LM76CHM-5
Supply Voltage Range (+VS) (4)
(1)
(2)
(3)
(4)
+4.5V to +5.5V
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its rated operating conditions.
LM76 θJA (thermal resistance, junction-to-ambient) when attached to a printed circuit board with 2 oz. foil is 200°C/W.
While the LM76 has a full-scale-range in excess of 128°C, prolonged operation at temperatures above 125°C is not recommended.
The LM76 will operate properly over the +VS supply voltage range of 3V to 5.5V for the LM76CNM-3 and the LM76CHM-5. The
LM76CNM-3 is tested and specified for rated accuracy at the nominal supply voltage of 3.3V. Accuracy of the LM76CNM-3 will degrade
0.2°C for a ±1% variation in +VS from the nominal value. The LM76CHM-5 is tested and specified for a rated accuracy at the nominal
supply voltage of 5.0V. Accuracy of the LM76CHM-5 will degrade 0.08°C for a ±1% variation in +VS from the nominal value.
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Temperature-to-Digital Converter Characteristics
Unless otherwise noted, these specifications apply for +VS = +5.0 Vdc ±10% for the LM76CHM-5. (1). Boldface limits apply
for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C, unless otherwise noted.
Parameter
Conditions
Typical (2)
TA = +70°C to +100°C
Accuracy (1)
TA = −20°C to +85°C for
LM76CHM-5
LM76CNM-3
Limits (3)
±1.5
±1.0
TA = +25°C
±0.5
13
0.0625
Resolution
See
Temperature Conversion Time
See (5)
400
I2C Inactive
0.25
I2C Active
0.25
Quiescent Current
Shutdown Mode:
Bits
°C
500
1000
0.5
0.45
mA (max)
µA
12
18
8
TA = +25°C
ms
mA
5
TA = +85°C
(6) (7)
Units
(Limit)
±1.0
TA = −10°C to +45°C
(4)
LM76CHM-5
Limits (3)
µA (max)
µA (max)
12
µA (max)
THYST Default Temperature
See
2
°C
TLOW Default Temperature
See (7)
10
°C
THIGH Default Temperature
See (7)
64
°C
TCRIT Default Temperature
(7)
80
°C
(1)
(2)
(3)
(4)
(5)
(6)
(7)
4
See
The LM76 will operate properly over the +VS supply voltage range of 3V to 5.5V for the LM76CNM-3 and the LM76CHM-5. The
LM76CNM-3 is tested and specified for rated accuracy at the nominal supply voltage of 3.3V. Accuracy of the LM76CNM-3 will degrade
0.2°C for a ±1% variation in +VS from the nominal value. The LM76CHM-5 is tested and specified for a rated accuracy at the nominal
supply voltage of 5.0V. Accuracy of the LM76CHM-5 will degrade 0.08°C for a ±1% variation in +VS from the nominal value.
Typicals are at TA = 25°C and represent most likely parametric norm.
Limits are ensured to AOQL (Average Outgoing Quality Level).
12 bits + sign, two's complement
This specification is provided only to indicate how often temperature data is updated. The LM76 can be read at any time without regard
to conversion state (and will yield last conversion result). If a conversion is in process it will be interrupted and restarted after the end of
the read.
Hysteresis value adds to the TLOW setpoint value (e.g.: if TLOW setpoint = 10°C, and hysteresis = 2°C, then actual hysteresis point is
10+2 = 12°C); and subtracts from the THIGH and T_CRIT setpoints (e.g.: if THIGH setpoint = 64°C, and hysteresis = 2°C, then actual
hysteresis point is 64−2 = 62°C). For a detailed discussion of the function of hysteresis refer to TEMPERATURE COMPARISON, and
Figure 6.
Default values set at power up.
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Logic Electrical Characteristics
DIGITAL DC CHARACTERISTICS Unless otherwise noted, these specifications apply for +VS = +5.0 Vdc ±10% for the
LM76CHM-5. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C, unless otherwise noted.
Symbol
Parameter
VIN(1)
SDA and SCL Logical “1” Input
Voltage
VIN(0)
SDA and SCL Logical “0” Input
Voltage
VIN(HYST)
SDA and SCL Digital Input Hysteresis
Conditions
500
VIN(1)
A0 and A1 Logical “1” Input Voltage
VIN(0)
A0 and A1 Logical “0” Input Voltage
IIN(1)
Logical “1” Input Current
VIN = + VS
IIN(0)
Logical “0” Input Current
VIN = 0V
CIN
Capacitance of All Digital Inputs
IOH
High Level Output Current
VOH = + VS
VOL
Low Level Output Voltage
IOL = 3 mA
T_CRIT_A Output Saturation Voltage
Typical (1)
(1)
(2)
(3)
+VS × 0.7
V (min)
+VS+0.3
V (max)
−0.3
V (min)
+VS × 0.3
V (max)
250
mV (min)
2.0
V (min)
+VS+0.3
V (max)
V (min)
0.8
V (max)
0.005
1.0
μA (max)
−0.005
−1.0
μA (max)
10
μA (max)
0.4
V (max)
20
IOUT = 4.0 mA
(3)
CL = 400 pF
Output Fall Time
Units
(Limit)
−0.3
T_CRIT_A Delay
tOF
Limits (2)
IO = 3 mA
pF
0.8
V (max)
1
Conversions
(max)
250
ns (max)
Typicals are at TA = 25°C and represent most likely parametric norm.
Limits are ensured to AOQL (Average Outgoing Quality Level).
For best accuracy, minimize output loading. Higher sink currents can affect sensor accuracy with internal heating. This can cause an
error of 0.64°C at full rated sink current and saturation voltage based on junction-to-ambient thermal resistance.
SERIAL BUS DIGITAL SWITCHING CHARACTERISTICS Unless otherwise noted, these specifications apply for +VS = +5.0
Vdc ±10% for the LM76CHM-5, CL (load capacitance) on output lines = 80 pF unless otherwise specified. Boldface limits
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Typical (1)
Limits (2) (3)
Units
(Limit)
t1
SCL (Clock) Period
2.5
μs(min)
t2
Data in Set-Up Time to SCL High
100
ns(min)
t3
Data Out Stable after SCL Low
0
ns(min)
t4
SDA Low Set-Up Time to SCL Low (Start Condition)
100
ns(min)
t5
SDA High Hold Time after SCL High (Stop Condition)
100
ns(min)
(1)
(2)
(3)
Typicals are at TA = 25°C and represent most likely parametric norm.
Limits are ensured to AOQL (Average Outgoing Quality Level).
Timing specifications are tested at the bus input logic levels (Vin(0)=0.3xVA for a falling edge and Vin(1)=0.7xVA for a rising edge) when
the SCL and SDA edge rates are similar.
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Figure 3. Timing Diagram
Figure 4. Temperature-to-Digital Transfer Function (Non-linear scale for clarity)
6
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FUNCTIONAL DESCRIPTION
The LM76 temperature sensor incorporates a band-gap type temperature sensor, 13-bit ADC, and a digital
comparator with user-programmable upper and lower limit values. The comparator activates either the INT line
for temperatures outside the TLOW and THIGH window, or the T_CRIT_A line for temperatures which exceed
T_CRIT. The lines are programmable for mode and polarity.
TEMPERATURE COMPARISON
LM76 provides a window comparison against a lower (TLOW) and upper (THIGH) trip point. A second upper trip
point (T_CRIT) functions as a critical alarm shutdown. Figure 6 depicts the comparison function as well as the
modes of operation.
Status Bits
The internal Status bits operate as follows:
“True”: Temperature above a THIGH or T_CRIT is “true” for those respective bits. A “true” for TLOW is
temperature below TLOW.
“False”: Assuming temperature has previously crossed above THIGH or T_CRIT, then the temperature must
drop below the points corresponding THYST(THIGH − THYST or T_CRIT − THYST) in order for the condition to be
false. For TLOW, assuming temperature has previously crossed below TLOW, a “false” occurs when temperature
goes above TLOW + THYST.
The Status bits are not affected by reads or any other actions, and always represent the state of temperature vs.
setpoints.
Hardwire Outputs
The T_CRIT_A hardwire output mirrors the T_CRIT_A flag, when the flag is true, the T_CRIT_A output is
asserted at all times regardless of mode. Reading the LM76 has no effect on the T_CRIT_A output, although the
internal conversion is restarted.
The behavior of the INT hardwire output is as follows:
Comparator Interrupt Mode (Default): User reading part resets output until next measurement completes. If
condition is still true, output is set again at end of next conversion cycle. For example, if a user never reads the
part, and temperature goes below TLOW then INT becomes active. It would stay that way until temperature goes
above TLOW + THYST. However if the user reads the part, the output would be reset. At the end of the next
conversion cycle, if the condition is true, it is set again. If not, it remains reset.
Event Interrupt Mode: User reading part resets output until next condition "event" occurs (in other words,
output is only set once for a true condition, if reset by a read, it remains reset until the next triggering threshold
has been crossed). Conversely, if a user never read the part, the output would stay set indefinitely after the first
event that set the output. An “event” for Event Interrupt Mode is defined as:
1. Transitioning upward across a setpoint, or
2. Transitioning downward across a setpoint's corresponding hysteresis (after having exceeded that setpoint).
For example, if a user never read the part, and temperature went below TLOW then INT would become active. It
would stay that way forever if a user never read the part.
However if the user read the part, the output would be reset. Even if the condition is true, it will remain reset. The
temperature must cross above TLOW + THYST to set the output again.
In either mode, reading any register in the LM76 restarts the conversion. This allows a designer to know exactly
when the LM76 begins a comparison. This prevents unnecessary Interrupts just after reprogramming setpoints.
Typically, system Interrupt inputs are masked prior to reprogramming trip points. By doing a read just after
resetting trip points, but prior to unmasking, unexpected Interrupts are prevented.
Avoid programming setpoints so close that their hysteresis values overlap. An example would be that with a
THYST value of 2°C then setting THIGH and TLOW to within 4°C of each other will violate this restriction. To be more
specific, with THYST set to 2°C assume THIGH set to 64°C. If TLOW is set equal to, or higher than 60°C this
restriction is violated.
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DEFAULT SETTINGS
The LM76 always powers up in a known state. LM76 power up default conditions are:
1. Comparator Interrupt Mode
2. TLOW set to 10°C
3. THIGH set to 64°C
4. T_CRIT set to 80°C
5. THYST set to 2°C
6. INT and T_CRIT_A active low
7. Pointer set to “00”; Temperature Register
The LM76 registers will always reset to these default values when the power supply voltage is brought up from
zero volts as the supply crosses the voltage level plotted in the following curve. The LM76 registers will reset
again when the power supply drops below the voltage plotted in this curve.
Figure 5. Average Power on Reset Voltage vs Temperature
SERIAL BUS INTERFACE
The LM76 operates as a slave on the Serial Bus, so the SCL line is an input (no clock is generated by the LM76)
and the SDA line is a bi-directional serial data line. According to Serial Bus specifications, the LM76 has a 7-bit
slave address. The five most significant bits of the slave address are hard wired inside the LM76 and are
“10010”. The two least significant bits of the address are assigned to pins A1–A0, and are set by connecting
these pins to ground for a low, (0); or to +VS for a high, (1).
Therefore, the complete slave address is:
1
0
0
1
MSB
8
0
A1
A0
LSB
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Event Interrupt mode is drawn as if the user is reading the part. If the user doesn't read, the outputs would go low and
stay that way until the LM76 is read.
Figure 6. Temperature Response Diagram
TEMPERATURE DATA FORMAT
Temperature data can be read from the Temperature and Set Point registers; and written to the Set Point
registers. Temperature data can be read at any time, although reading faster than the conversion time of the
LM76 will prevent data from being updated. Temperature data is represented by a 13-bit, two's complement word
with an LSB (Least Significant Bit) equal to 0.0625°C:
Temperature
Digital Output
Binary
Hex
+130°C
0 1000 0 010 0000
08 20h
+125°C
0 0111 1101 0000
07 D0h
+80°C
0 0101 1010 0000
05 90h
+64°C
0 0100 0000 0000
04 00h
+25°C
0 0001 1001 0000
01 90h
+10°C
0 0000 1010 0000
00 A0h
+2°C
0 0000 0010 0000
00 20h
+0.0625°C
0 0000 0000 0001
00 01h
0°C
00 0000 0000
00 00h
−0.0625°C
1 1111 1111 1111
1F FFh
−25°C
1 1110 0111 0000
1E 70h
−55°C
1 1100 1001 0000
1C 90h
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SHUTDOWN MODE
Shutdown mode is enabled by setting the shutdown bit in the Configuration register via the Serial Bus. Shutdown
mode reduces power supply current to 5 μA typical. T_CRIT_A is reset if previously set. Since conversions are
stoped during shutdown, T_CRIT_A and INT will not be operational. The Serial Bus interface remains active.
Activity on the clock and data lines of the Serial Bus may slightly increase shutdown mode quiescent current.
Registers can be read from and written to in shutdown mode. The LM76 takes miliseconds to respond to the
shutdown command.
INT AND T_CRIT_A OUTPUT
The INT and T_CRIT_A outputs are open-drain outputs and do not have internal pull-ups. A "high" level will not
be observed on these pins until pull-up current is provided from some external source, typically a pull-up resistor.
Choice of resistor value depends on many system factors but, in general, the pull-up resistor should be as large
as possible. This will minimize any errors due to internal heating of the LM76. The maximum resistance of the
pull up, based on LM76 specification for High Level Output Current, to provide a 2 volt high level, is 30K ohms.
FAULT QUEUE
A fault queue of up to 4 faults is provided to prevent false tripping when the LM76 is used in noisy environments.
The 4 faults must occur consecutively to set flags as well as INT and T_CRIT_A outputs. The fault queue is
enabled by setting bit 4 of the Configuration Register high (see CONFIGURATION REGISTER ).
INTERNAL REGISTER STRUCTURE
There are four data registers in the LM76, selected by the Pointer register. At power-up the Pointer is set to “00”;
the location for the Temperature Register. The Pointer register latches the last location it was set to. In Interrupt
Mode, a read from the LM76 resets the INT output. Placing the device in Shutdown mode resets the INT and
T_CRIT_A outputs. All registers are read and write, except the Temperature register which is read only.
A write to the LM76 will always include the address byte and the Pointer byte. A write to the Configuration
register requires one data byte, while the TLOW, THIGH, and T_CRIT registers require two data bytes.
Reading the LM76 can take place either of two ways: If the location latched in the Pointer is correct (most of the
time it is expected that the Pointer will point to the Temperature register because it will be the data most
frequently read from the LM76), then the read can simply consist of an address byte, followed by retrieving the
corresponding number of data bytes. If the Pointer needs to be set, then an address byte, pointer byte, repeat
start, and another address byte plus required number of data bytes will accomplish a read.
10
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The first data byte is the most significant byte with most significant bit first, permitting only as much data as
necessary to be read to determine the temperature condition. For instance, if the first four bits of the temperature
data indicates a critical condition, the host processor could immediately take action to remedy the excessive
temperature. At the end of a read, the LM76 can accept either Acknowledge or No Acknowledge from the Master
(No Acknowledge is typically used as a signal for the slave that the Master has read its last byte).
An inadvertent 8-bit read from a 16-bit register, with the D7 bit low, can cause the LM76 to stop in a state where
the SDA line is held low as shown in Figure 7. This can prevent any further bus communication until at least 9
additional clock cycles have occurred. Alternatively, the master can issue clock cycles until SDA goes high, at
which time issuing a “Stop” condition will reset the LM76.
Figure 7. Inadvertent 8-Bit Read from 16-Bit Register where D7 is Zero (“0”)
POINTER REGISTER
(Selects which registers will be read from or written to):
P7
P6
P5
P4
P3
0
0
0
0
0
P2
P1
P0
Register Select
P0–P2: Register Select:
P2
P1
P0
0
0
0
Temperature (Read only) (Power-up default)-
Register
0
0
1
Configuration (Read/Write)
0
1
0
THYST (Read/Write)
0
1
1
T_CRIT (Read/Write)
1
0
0
TLOW (Read/Write)
1
0
1
THIGH (Read/Write)
P3–P7: Must be kept zero.
TEMPERATURE REGISTER
Table 1. (Read Only):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
Sign
MSB
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CRIT
D1
D0
HIGH
LOW
Status Bits
D0–D2: Status Bits
D3–D15: Temperature Data. One LSB = 0.0625°C. Two's complement format.
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CONFIGURATION REGISTER
Table 2. (Read/Write):
D7
D6
0
D5
0
D4
0
Fault Queue
D3
D2
D1
D0
INT Polarity
T_CRIT_A
Polarity
INT Mode
Shutdown
D0: Shutdown - When set to 1 the LM76 goes to low power shutdown mode. Power up default of “0”.
D1: Interrupt mode - 0 is Comparator Interrupt mode, 1 is Event Interrupt mode. Power up default of “0”.
D2, D3: T_CRIT_A and INT Polarity - 0 is active low, 1 is active high. Outputs are open-drain. Power up default
of “0”
D4: Fault Queue - When set to 1 the Fault Queue is enabled, see FAULT QUEUE. Power up default of “0”.
D5–D7: These bits are used for production testing and must be kept zero for normal operation.
THYST, TLOW, THIGH AND T_CRIT_A REGISTERS
Table 3. (Read/Write):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Sign
MSB
Bit 10
Bit 9
Bit 8
Bit7
Bit6
Bit5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
D0–D2: Undefined
D3–D15: THYST, TLOW, THIGH or T_CRIT Trip Temperature Data. Power up default is TLOW = 10°C, THIGH = 64°C,
T_CRIT = 80°C, THYST = 2°C.
THYST is subtracted from THIGH, and T_CRIT, and added to TLOW.
Avoid programming setpoints so close that their hysteresis values overlap. See CONFIGURATION REGISTER .
TEST CIRCUIT DIAGRAMS
I2C Timing Diagrams
Figure 8. Typical 2-Byte Read From Preset Pointer Location Such as Temp or Comparison Registers
Figure 9. Typical Pointer Set Followed by Immediate Read for 2-Byte Register such as Temp or
Comparison Registers
12
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Figure 10. Typical 1-Byte Read from Configuration Register with Preset Pointer
Figure 11. Typical Pointer Set Followed by Immediate Read from Configuration Register
Figure 12. Configuration Register Write
Figure 13. Comparison Register Write
Application Hints
The temperature response graph in Figure 14 depicts a typical application designed to meet ACPI requirements.
In this type of application, the temperature scale is given an arbitrary value of "granularity", or the window within
which temperature notification events should occur. The LM76 can be programmed to the window size chosen by
the designer, and will issue interrupts to the processor whenever the window limits have been crossed. The
internal flags permit quick determination of whether the temperature is rising or falling.
The T_CRIT limit would typically use its separate output to activate hardware shutdown circuitry separate from
the processor. This is done because it is expected that if temperature has gotten this high that the processor may
not be responding. The separate circuitry can then shut down the system, usually by shutting down the power
supply.
Note that the INT and T_CRIT_A outputs are separate, but can be wire-or'd together. Alternatively the T_CRIT_A
can be diode or'd to the INT line in such a way that a T_CRIT_A event activates the INT line, but an INT event
does not activate the T_CRIT_A line. This may be useful in the event that it is desirable to notify both the
processor and separate T_CRIT_A shutdown circuitry of a critical temperature alarm at the same time (maybe
the processor is still working and can coordinate a graceful shutdown with the separate shutdown circuit).
To implement ACPI compatible sensing it is necessary to sense whenever the temperature goes outside the
window, issue an interrupt, service the interrupt, and reprogram the window according to the desired granularity
of the temperature scale. The reprogrammed window will now have the current temperature inside it, ready to
issue an interrupt whenever the temperature deviates from the current window.
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To understand this graph, assume that at the left hand side the system is at some nominal temperature. For the
1st event temperature rises above the upper window limit, THIGH, causing INT to go active. The system responds
to the interrupt by querying the LM76's status bits and determines that THIGH was exceeded, indicating that
temperature is rising. The system then reprograms the temperature limits to a value higher by an amount equal
to the desired granularity. Note that in Event Interrupt Mode, reprogramming the limits has caused a second,
known, interrupt to be issued since temperature has been returned within the window. In Comparator Interrupt
Mode, the LM76 simply stops issuing interrupts.
The 2nd event is another identical rise in temperature. The 3rd event is typical of a drop in temperature. This is
one of the conditions that demonstrates the power of the LM76, as the user receives notification that a lower limit
is exceeded in such a way that temperature is dropping.
The Critical Alarm Event activates the separate T_CRIT_A output. Typically, this would feed circuitry separate
from the processor on the assumption that if the system reached this temperature, the processor might not be
responding.
Note: Event Interrupt mode is drawn as if the user is reading the part. If the user doesn't read, the outputs would go
low and stay that way until the LM76 is read.
Figure 14. Temperature Response Diagram for ACPI Implementation
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Typical Applications
Figure 15. Typical Application
Figure 16. ACPI Compatible Terminal Alarm Shutdown
By powering the LM76 from auxiliary output of the power supply, a non-functioning overheated computer can be
powered down to preserve as much of the system as possible.
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REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
•
16
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM76CHM-5
NRND
SOIC
D
8
95
TBD
Call TI
Call TI
-55 to 150
LM76
CHM-5
LM76CHM-5/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 150
LM76
CHM-5
LM76CHMX-5/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 150
LM76
CHM-5
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM76CHMX-5/NOPB
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
5.4
2.0
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM76CHMX-5/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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