LM8333EVALKIT

LM8333 www.ti.com SNLS246K – SEPTEMBER 2006 – REVISED MAY 2013 LM8333 Mobile I/O Companion Supporting Key-Scan, I/O Expansion, PWM, and ACCESS.bus Host Interface Check for Samples: LM8333 FEATURES DESCRIPTION • • The LM8333 Mobile I/O Companion offloads the burden of keyboard scanning from the host, while providing extremely low power consumption in both operational and standby modes. It supports keypad matrices up to 8 × 8 in size (plus another 8 specialfunction keys), for portable applications such as cellphones, PDAs, games, and other handheld applications. 1 2 • • • • • • 8 × 8 Standard Keys 8 Special Function Keys (SF Keys) Providing a Total of 72 Keys for the Maximum Keyboard Matrix ACCESS.Bus (I2C-compatible) Communication Interface to the Host Four General Purpose Host Programmable I/O Pins with Two Optional (Slow) External Interrupts 15-byte FIFO Buffer to Store Key Pressed and Key Released Events Error Control with Error Reports on (FIFO Overrun, Keypad Overrun, Invalid Command) Host Programmable PWM Host Programmable Active Time and Debounce Time APPLICATIONS • • • • Mobile Phones Personal Digital Assistants (PDAs) Smart Handheld Devices Personal Media Players Key press and release events are encoded into a byte format and loaded into a FIFO buffer for retrieval by the host processor. An interrupt output (IRQ) is used to signal events such as keypad activity, a state change on either of two interrupt-capable generalpurpose I/O pins, or an error condition. Interrupt and error codes are available to the host by reading dedicated registers. Four general-purpose I/O pins are available, two of which have interrupt capability. A pulse-width modulated output based on a host-programmable internal timer is also available, which can be used as a general-purpose output if the PWM function is not required. To minimize power, the LM8333 automatically enters a low-power standby mode when there is no keypad, I/O, or host activity. The device is packaged in a 32–pin WQFN and a 49-pin csBGA. Both are chip-scale packages. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated LM8333 SNLS246K – SEPTEMBER 2006 – REVISED MAY 2013 www.ti.com Block Diagram Pin Assignments Figure 1. 32-Lead WQFN (Top View) See Package Number NJE0032A 2 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM8333 LM8333 www.ti.com SNLS246K – SEPTEMBER 2006 – REVISED MAY 2013 Figure 2. 49-Ball csBGA (Top View) See Package Number NYC0049A Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM8333 3 LM8333 SNLS246K – SEPTEMBER 2006 – REVISED MAY 2013 www.ti.com SIGNAL DESCRIPTIONS 4 Name 32 Pins 49 Pins I/O Description WAKE_IN0 29 D7 Input Wake-up input/Keyboard scanning input 0 WAKE_IN1 30 C7 Input Wake-up input/Keyboard scanning input 1 WAKE_IN2 27 E7 Input Wake-up input/Keyboard scanning input 2 WAKE_IN3 28 D6 Input Wake-up input/Keyboard scanning input 3 WAKE_IN4 31 B6 Input Wake-up input/Keyboard scanning input 4 WAKE_IN5 32 A7 Input Wake-up input/Keyboard scanning input 5 WAKE_IN6 1 A6 Input Wake-up input/Keyboard scanning input 6 Wake-up input/Keyboard scanning input 7 WAKE_IN7 2 B5 Input K_OUT0 21 G3 Output Keyboard scanning output 0 K_OUT1 22 F4 Output Keyboard scanning output 1 K_OUT2 23 G4 Output Keyboard scanning output 2 K_OUT3 24 G5 Output Keyboard scanning output 3 K_OUT4 3 A5 Output Keyboard scanning output 4 K_OUT5 4 B4 Output Keyboard scanning output 5 K_OUT6 5 A4 Output Keyboard scanning output 6 K_OUT7 6 A3 Output Keyboard scanning output 7 GEN_IO_0 12 D2 I/O General-purpose I/O 0 GEN_IO_1 13 D1 I/O General-purpose I/O 1 GEN_IO_2 7 B3 I/O General-purpose I/O 2 GEN_IO_3 8 A2 I/O General-purpose I/O 3 SDA 25 F7 I/O ACCESS.bus data signal SCL 26 E6 Input ACCESS.bus clock signal IRQ 17 F2 Output Interrupt request output PWM 16 F1 Output Pulse-width modulated output WD_OUT 18 G1 Output Watchdog timer output (connect to RESET input) RESET 20 F3 Input Reset input CLK_IN 11 B1 Input Clock input (connect to ground through a 68k ohm resistor) VCC 15 E1, E2 n.a. Vcc GND 9, 10, 14 A1, B2, C3, C4, C5, D3, D4, D5, E3, E4, E5 n.a. Ground NC 19 B7, C1, C2, C6, F5, F6, G2, G6, G7 n.a. No connect Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM8333 LM8333 www.ti.com SNLS246K – SEPTEMBER 2006 – REVISED MAY 2013 Typical Application Figure 3. Typical Keypad Configuration FEATURES The following features are supported: • 8 x 8 Standard Keys. • 8 Special Function Keys (SF keys) with Wake-Up Capability by Forcing a WAKE_INx Pin to Ground. Pressing a SF Key Overrides any other Key in the Same Row. • A Total of 72 Keys can be Scanned. • ACCESS.Bus (I2C-Compatible) Interface for Communication with the Host. • The Watchdog Timer is Mandatory, so WD_OUT Must be Connected to RESET. I/O EXPANSION OPTIONS • One Host-Programmable PWM Output which also may be Used as a General-Purpose Output. • Four Host-Programmable General-Purpose I/O Pins, GEN_IO_0, GEN_IO_1, GEN_IO_2, and GEN_IO_3. GEN_IO_0 and GEN_IO_1 can also be Configured for “Slow” Interrupts, in which any Transition will Trigger a Hardware Interrupt Event to the Host. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM8333 5 LM8333 SNLS246K – SEPTEMBER 2006 – REVISED MAY 2013 www.ti.com WATCHDOG TIMER The watchdog timer is always enabled in hardware. To use the timer, connect the WD_OUT output to the RESET input. HALT MODE The fully static architecture of the LM8333 allows stopping the internal RC clock in Halt mode, which reduces power consumption to the minimum level. Halt mode is entered when no key-press, key-release, or ACCESS.bus activity is detected for a certain period of time (by default, 500 milliseconds). The mechanism for entering Halt mode is always enabled in hardware, but the host can program the period of inactivity which triggers entry into Halt mode. The LM8333 will remain in Active mode as long as a key event, or any other event, which causes the IRQ output to be asserted is not resolved. ACCESS.bus Activity When the LM8333 is in Halt mode, any activity on the ACCESS.bus interface will cause the LM8333 to exit from Halt mode. However, the LM8333 will not be able to acknowledge the first bus cycle immediately following wakeup from Halt mode. It will respond with a negative acknowledgement, and the host should then repeat the cycle. The LM8333 will be prevented from entering Halt mode if it shares the bus with peripherals that are continuously active. For lowest power consumption, the LM8333 should only share the bus with peripherals that require little or no bus activity after system initialization. KEYPAD SCANNING The LM8333 starts new scanning cycles at fixed time intervals of about 4 ms. If a change in the state of the keypad is detected, the keypad is rescanned after a debounce delay. When the state change has been reliably captured, it is encoded and written to the FIFO buffer. If more than two keys are pressed simultaneously, the pattern of key closures may be ambiguous, so pressing more than two keys asserts the Error Flag condition and the IRQ output (if enabled). The host may attempt to interpret the events stored in the FIFO or discard them. The SF keys connect the WAKE_INx pins directly to ground. There can be up to eight SF-keys. If any of these keys are pressed, other key presses that use the same WAKE_INx pin will be ignored. COMMUNICATION INTERFACE The two-wire ACCESS.bus interface is used to communicate with a host. The ACCESS.bus interface is fully compliant with the I2Cbus standard. The LM8333 operates as a bus slave at speeds up to 400 kHz. An ACCESS.bus transfer starts with a byte that includes a 7-bit slave device address. The LM8333 responds to a fixed device address. This address is 0xA2, when aligned to the MSB (7-bit address mapped to bits 7:1, rather than bits 6:0). Bit 0 is a direction bit (0 on write, 1 on read). Because it is a slave, the LM8333 never initiates an ACCESS.bus cycle, it only responds to bus cycles initiated by the host. The LM8333 may signal events to the host by asserting the IRQ interrupt request. Interrupts Between the Host and LM8333 The IRQ output is used to signal unresolved interrupts, errors, and key-events to the host. The host can use an available GEN_IO_0 or GEN_IO_1 pin to interrupt (or wake-up) the LM8333, if it is not being used for another function. The host can also wake-up the LM8333 by sending a Start Condition on the ACCESS.bus interface. NOTE The LM8333 it will not be able to acknowledge the first byte received from the host after wake-up. In this case, the host will have to resend the slave address. 6 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM8333 LM8333 www.ti.com SNLS246K – SEPTEMBER 2006 – REVISED MAY 2013 Interrupt Sources The IRQ output is asserted on these conditions: • Any new key-event. • Any error condition, which is indicated by the error code. • Any enabled interrupt on either of the GEN_IO_0 or GEN_IO_1 pins that can be configured as external interrupt inputs. When enabled, any rising or falling edge triggers an interrupt. The IRQ output remains asserted until the interrupt code is read. Device Operation EVENT CODE ASSIGNMENT After power-on reset, the LM8333 starts scanning the keypad. It stays active for a default time of about 500 ms after the last key is released, after which it enters a standby mode to minimize power consumption (