LMG3522R030
SNOSDF3 – NOVEMBER 2022
LMG3522R030 650-V 30-mΩ GaN FET With Integrated Driver, Protection, and
Temperature Reporting
1 Features
3 Description
•
The LMG3522R030 GaN FET with integrated driver
and protections is targeting switch-mode power
converters and enables designers to achieve new
levels of power density and efficiency.
•
•
•
650-V GaN-on-Si FET with integrated gate driver
– Integrated high precision gate bias voltage
– 200-V/ns FET hold-off
– 2-MHz switching frequency
– 20-V/ns to 150-V/ns slew rate for optimization
of switching performance and EMI mitigation
– Operates from 7.5-V to 18-V supply
Robust protection
– Cycle-by-cycle overcurrent and latched shortcircuit protection with < 100-ns response
– Withstands 720-V surge while hard-switching
– Self-protection from internal overtemperature
and UVLO monitoring
Advanced power management
– Digital temperature PWM output
Top-side cooled 12-mm × 12-mm VQFN package
separates electrical and thermal paths for lowest
power loop inductance
2 Applications
•
•
•
•
•
Switch-mode power converters
Merchant network and server PSU
Merchant telecom rectifiers
Solar inverters and industrial motor drives
Uninterruptable power supplies
The LMG3522R030 integrates a silicon driver that
enables switching speed up to 150 V/ns. TI’s
integrated precision gate bias results in higher
switching SOA compared to discrete silicon gate
drivers. This integration, combined with TI's lowinductance package, delivers clean switching and
minimal ringing in hard-switching power supply
topologies. Adjustable gate drive strength allows
control of the slew rate from 20 V/ns to 150 V/ns,
which can be used to actively control EMI and
optimize switching performance.
Advanced power management features include digital
temperature reporting and fault detection. The
temperature of the GaN FET is reported through
a variable duty cycle PWM output, which simplifies
managing device loading. Faults reported include
overtemperature, overcurrent, and UVLO monitoring.
Device Information
(1)
PART NUMBER
PACKAGE (1)
BODY SIZE (NOM)
LMG3522R030
VQFN (52)
12.00 mm × 12.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
DRAIN
Slew
Rate
Direct-Drive
GaN
SOURCE
RDRV
IN
VDD
VNEG
LDO5V
LDO,
BB
OCP, SCP,
OTP, UVLO
Current
TEMP
FAULT
OC
SOURCE
Simplified Block Diagram
Switching Performance at > 100 V/ns
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMG3522R030
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SNOSDF3 – NOVEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................8
6.7 Typical Characteristics................................................ 9
7 Parameter Measurement Information.......................... 11
7.1 Switching Parameters............................................... 11
8 Detailed Description......................................................13
8.1 Overview................................................................... 13
8.2 Functional Block Diagram......................................... 13
8.3 Feature Description...................................................14
8.4 Start Up Sequence....................................................23
8.5 Safe Operation Area (SOA)...................................... 24
8.6 Device Functional Modes..........................................24
9 Application and Implementation.................................. 25
9.1 Application Information............................................. 25
9.2 Typical Application.................................................... 26
9.3 Do's and Don'ts.........................................................30
9.4 Power Supply Recommendations.............................30
9.5 Layout....................................................................... 32
10 Device and Documentation Support..........................36
10.1 Documentation Support.......................................... 36
10.2 Receiving Notification of Documentation Updates..36
10.3 Support Resources................................................. 36
10.4 Trademarks............................................................. 36
10.5 Electrostatic Discharge Caution..............................36
10.6 Export Control Notice..............................................36
10.7 Glossary..................................................................36
11 Mechanical, Packaging, and Orderable
Information.................................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
November 2022
*
Initial release.
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5 Pin Configuration and Functions
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
52
NC2
18
51
LDO5V
19
50
RDRV
20
49
TEMP
21
48
OC
THERMAL PAD
22
47
NC2
23
46
FAULT
24
45
IN
25
44
VDD
26
43
NC2
28
29
30
31
32
33
34
35
36
37
38
39
40
41
NC2
27
42
BBSW
SOURCE
NC2
NC1
NC1
DRAIN
SOURCE
VNEG
Figure 5-1. RQS Package 52-Pin VQFN (Top View)
Table 5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
NC1
1, 16
—
Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are
non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally
connected to DRAIN.
DRAIN
2-15
P
GaN FET drain. Internally connected to NC1.
NC2
17, 27, 43, 47,
52
—
Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are
non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally
connected to SOURCE, and THERMAL PAD.
SOURCE
18-26, 28-39
P
GaN FET source. Internally connected to NC2, and THERMAL PAD.
VNEG
40, 41
P
Internal buck-boost converter negative output. Used as the negative supply to turn off the depletion mode GaN
FET. Bypass to SOURCE with a 2.2-µF capacitor.
BBSW
42
P
Internal buck-boost converter switch pin. Connect an inductor from this point to SOURCE.
VDD
44
P
Device input supply.
IN
45
I
CMOS-compatible non-inverting input used to turn the FET on and off.
FAULT
46
O
Push-pull digital output that asserts low during a fault condition. Refer to Fault Detection for details.
OC
48
O
Push-pull digital output that asserts low during overcurrent and short-circuit fault conditions. Refer to Fault
Detection for details.
TEMP
49
O
Push-pull digital output that gives information about the GaN FET temperature. Outputs a fixed 9-kHz pulsed
waveform. The device temperature is encoded as the duty cycle of the waveform.
RDRV
50
I
Drive strength selection pin. Connect a resistor from this pin to SOURCE to set the turn-on drive strength to
control slew rate. Tie the pin to SOURCE to enable 150 V/ns and tie the pin to LDO5V to enable 100 V/ns.
LDO5V
51
P
5-V LDO output for external digital isolator. If using this externally, connect a 0.1-µF or greater capacitor to
SOURCE.
THERMAL
PAD
—
—
Thermal pad. Internally connected to SOURCE, and NC2.
(1)
I = input, O = output, P = power
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6 Specifications
6.1 Absolute Maximum Ratings
Unless otherwise noted: voltages are in respect to SOURCE connected to reference ground(1)
MIN
UNIT
VDS
Drain-source voltage, FET off
650
V
VDS(surge)
Drain-source voltage, FET switching, surge condition(2)
720
V
VDS,tr
Drain-source transient ringing peak voltage, FET off, surge
Pin voltage
ID(RMS)
800
V
-0.3
20
V
LDO5V
-0.3
5.5
V
VNEG
-16
0.5
V
BBSW
VVNEG–
1
VVDD+0.5
V
IN
-0.3
20
V
FAULT, OC, TEMP
-0.3
VLDO5V+0.3
V
RDRV
-0.3
5.5
V
55
A
Internally Limited
A
80
A
-40
150
°C
-55
150
°C
Drain RMS current, FET on
µs(4)
Drain pulsed current, FET on, tp < 10
IS(pulse)
Source pulsed current, FET off, tp < 1 µs
temperature(5)
TJ
Operating junction
TSTG
Storage temperature
(2)
(3)
(4)
(5)
condition(2) (3)
VDD
ID(pulse)
(1)
4
MAX
-125
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
See Section 8.3.3 for an explanation of the switching cycle drain-source voltage ratings.
t1 < 200 ns in Figure 8-1.
The positive pulsed current must remain below the overcurrent threshold to avoid the FET being automatically shut off. The FET drain
intrinsic positive pulsed current rating for tp < 10 µs is 120 A.
Refer to the Electrical and Switching Characteristics Tables for junction temperature test conditions.
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6.2 ESD Ratings
PARAMETER
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC
VALUE
JS-001(1)
UNIT
±2000
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Unless otherwise noted: voltages are in respect to SOURCE connected to reference ground.
ID(RMS
)
Supply voltage
VDD
(Maximum switching frequency derated for VVDD < 9
V)
Input voltage
IN
MIN
NOM
7.5
12
18
V
0
5
18
V
38
A
25
mA
500
kΩ
Drain RMS current
Positive source current
LDO5V
RRDRV RDRV to SOURCE resistance from external slew-rate control resistor
0
CVNEG VNEG to SOURCE capacitance from external bypass capacitor
1
LBBSW BBSW to SOURCE inductance from external buck-boost inductor (1)
3
(1)
4.7
MAX UNIT
10
uF
10
uH
> 1 A current rating is recommended.
6.4 Thermal Information
LMG3522R030
THERMAL METRIC(1)
RQS (VQFN)
UNIT
52 PINS
RθJC(top)
(1)
Junction-to-case (top) thermal resistance
0.28
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Unless otherwise noted: voltage, resistance, capacitance, and inductance are in respect to SOURCE connected with
reference ground; –40 ℃ ≤ TJ ≤ 125 ℃;
VDS = 520 V; 9 V ≤ VVDD ≤ 18 V; VIN = 0 V; RDRV connected to LDO5V; LBBSW = 4.7 µH
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
26
35
UNIT
GAN POWER TRANSISTOR
RDS(on)
VIN = 5 V, TJ = 25°C
Drain-source on resistance
Third-quadrant mode source-drain
voltage
VSD
IDSS
Drain leakage current
COSS
Output capacitance
CO(er)
Energy related effective output
capacitance
VIN = 5 V, TJ = 125°C
45
mΩ
IS = 0.1 A
3.6
V
IS = 20 A
3
VDS = 650 V, TJ = 25°C
VDS = 650 V, TJ = 125°C
VDS = 400 V
CO(tr)
Time related effective output capacitance
QOSS
Output charge
QRR
Reverse recovery charge
mΩ
VDS = 0 V to 400 V
5
V
1
uA
10
uA
235
pF
320
pF
460
pF
190
nC
0
nC
VDD - SUPPLY CURRENTS
VDD quiescent current
VVDD = 12 V, VIN = 0 V or 5V
700
1200
uA
VDD operating current
VVDD = 12 V, fIN = 140 kHz, softswitching
15.5
20
mA
BUCK BOOST CONVERTER
VNEG output voltage
VNEG sinking 50 mA
-14
V
Peak BBSW sourcing current at low peak
IBBSW,PK(l current mode setting
(Peak external buck-boost inductor
ow)
current)
0.3
0.4
0.5
A
Peak BBSW sourcing current at low peak
IBBSW,PK( current mode setting
(Peak external buck-boost inductor
high)
current)
0.8
1
1.2
A
High peak current mode setting enable –
IN positive-going threshold frequency
280
420
515
kHz
LDO5V
Output voltage
4.75
5
5.25
V
Short-circuit current
LDO5V sourcing 25 mA
25
50
100
mA
VIN,IT+
Positive-going input threshold voltage
1.7
1.9
2.45
V
VIN,IT-
Negative-going input threshold voltage
0.7
1.0
1.3
V
Input threshold hysteresis
0.7
0.9
1.3
V
100
150
200
kΩ
0.16
0.4
V
0.2
0.45
V
6.4
7
7.6
V
6
6.5
7.1
V
IN
Input pulldown resistance
VIN = 2 V
FAULT, OC, TEMP – OUPUT DRIVE
Low-level output voltage
Output sinking 8 mA
High-level output voltage
Output sourcing 8 mA, Measured as
VLDO5V – VO
VDD, VNEG – UNDER VOLTAGE LOCKOUT
VVDD,T+
(UVLO)
VDD UVLO – positive-going threshold
voltage
VDD UVLO – negative-going threshold
voltage
6
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6.5 Electrical Characteristics (continued)
Unless otherwise noted: voltage, resistance, capacitance, and inductance are in respect to SOURCE connected with
reference ground; –40 ℃ ≤ TJ ≤ 125 ℃;
VDS = 520 V; 9 V ≤ VVDD ≤ 18 V; VIN = 0 V; RDRV connected to LDO5V; LBBSW = 4.7 µH
PARAMETER
TEST CONDITIONS
MIN
VDD UVLO – Input threshold voltage
hysteresis
TYP
MAX
510
UNIT
mV
VNEG UVLO – negative-going threshold
voltage
-13.6
-13.0
-12.3
V
VNEG UVLO – positive-going threshold
voltage
-13.3
-12.75
-12.1
V
GATE DRIVER
Turn-on slew rate
From VDS < 320 V to VDS < 80 V, RDRV
disconnected from LDO5V, RRDRV = 300
kΩ, TJ = 25℃, VBUS = 400 V, LHB current
= 10 A, see Figure 7-1
20
V/ns
From VDS < 320 V to VDS < 80 V, RDRV
tied to LDO5V, TJ = 25℃, VBUS = 400 V,
LHB current = 10 A, see Figure 7-1
90
V/ns
150
V/ns
From VDS < 320 V to VDS < 80 V, RDRV
disconnected from LDO5V, RRDRV = 0 Ω,
TJ = 25℃, VBUS = 400 V, LHB current = 10
A, see Figure 7-1
Maximum GaN FET switching frequency.
VNEG rising to > –13.25 V, soft-switched,
maximum switching frequency derated for
VVDD < 9 V
2
MHz
FAULTS
IT(OC)
DRAIN overcurrent fault – threshold
current
60
70
80
A
IT(SC)
DRAIN short-circuit fault – threshold
current
75
90
105
A
di/dtT(SC)
di/dt threshold between overcurrent and
short-circuit faults
150
GaN temperature fault – postive-going
threshold temperature
GaN temperature fault – threshold
temperature hysteresis
Driver temperature fault – positive-going
threshold temperature
Driver Temperature fault – threshold
temperature hysteresis
A/µs
175
°C
30
°C
185
°C
20
°C
TEMP
Output Frequency
4.3
9
GaN TJ = 125℃
58.5
64.6
70
%
GaN TJ = 85℃
36.2
40
43.7
%
GaN TJ = 25℃
0.3
3
6
%
-0.15
0
0.15
V
0℃ ≤ TJ ≤ 125℃
-0.2
0
0.2
A
–40°C ≤ TJ ≤ 0°C
-0.35
0
0.35
A
GaN TJ = 150℃
Output PWM Duty Cycle
14
82
kHz
%
IDEAL-DIODE MODE CONTROL
VT(3rd)
Drain-source third-quadrant detection –
threshold voltage
IT(ZC)
Drain zero-current detection – threshold
current
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6.6 Switching Characteristics
Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to SOURCE connected with reference
ground; –40 ℃ ≤ TJ ≤ 125 ℃; 9 V ≤ VVDD ≤ 18 V; VIN = 0 V; RDRV connected to LDO5V; LBBSW = 4.7 µH
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SWITCHING TIMES
Drain-current turn-on delay time
From VIN > VIN,IT+ to ID > 1 A, VBUS =
400 V, LHB current = 10 A, see Figure 7-1
and Figure 7-2
28
42
ns
td(on)
Turn-on delay time
From VIN > VIN,IT+ to VDS < 320 V, VBUS =
400 V, LHB current = 10 A, see Figure 7-1
and Figure 7-2
33
54
ns
tr(on)
Turn-on rise time
From VDS < 320 V to VDS < 80 V, VBUS =
400 V, LHB current = 10 A, see Figure 7-1
and Figure 7-2
2.8
4.3
ns
td(off)
Turn-off delay time
From VIN < VIN ,IT– to VDS > 80 V, VBUS =
400 V, LHB current = 10 A, see Figure 7-1
and Figure 7-2
48
69
ns
tf(off)
Turn-off fall time(1)
From VDS > 80 V to VDS > 320 V, VBUS =
400 V, LHB current = 10 A, see Figure 7-1
and Figure 7-2
22
ns
Minimum IN high pulse-width for FET
turn-on
VIN rise/fall times < 1 ns, VDS falls to <
200 V, VBUS = 400 V, LHB current = 10 A,
see Figure 7-1
24
ns
td(on)
(Idrain)
STARTUP TIMES
t(start)
Driver start-up time
From VVDD > VVDD,T+
(UVLO) to FAULT high, CLDO5V = 100
nF, CVNEG = 2.2 µF at 0-V bias linearly
decreasing to 1.5 µF at 15-V bias
310
470
us
FAULT TIMES
toff(OC)
Overcurrent fault FET turn-off time, FET
on before overcurrent
VIN = 5 V, From ID > IT(OC) to ID < 50 A, ID
di/dt = 100 A/µs
115
170
ns
toff(SC)
Short-circuit current fault FET turn-off
time, FET on before short circuit
VIN = 5 V, From ID > IT(SC) to ID < 50 A, ID
di/dt = 700 A/µs
65
100
ns
Overcurrent fault FET turn-off time, FET
turning on into overcurrent
From ID > IT(OC) to ID < 50 A
200
250
ns
Short-circuit fault FET turn-off time, FET
turning on into short circuit
From ID > IT(SC) to ID < 50 A
80
180
ns
IN reset time to clear FAULT latch
From VIN < VIN,IT– to FAULT high
380
580
us
t(window)
(OC)
250
Overcurrent fault to short-circuit fault
window time
50
ns
IDEAL-DIODE MODE CONTROL TIMES
Ideal-diode mode FET turn-on time
VDS < VT(3rd) to FET turn-on, VDS being
discharged by half-bridge configuration
inductor at 5 A
50
65
ns
Ideal-diode mode FET turn-off time
ID > IT(ZC) to FET turn-off, ID di/dt
= 100 A/µs created with a half-bridge
configuration
55
76
ns
230
360
ns
Overtemperature-shutdown ideal-diode
mode IN falling blanking time
(1)
8
150
During turn-off, VDS rise time is the result of the resonance of COSS and loop inductance as well as load current.
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95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
160
-40C
0C
25C
85C
125C
-40C
0C
25C
85C
125C
140
Turn-On Delay Time (ns)
Drain-Current Turn-On Delay Time (ns)
6.7 Typical Characteristics
120
100
80
60
40
20
0
50
100
150 200 250 300 350
RDRV Resistance (k)
400
450
0
500
Figure 6-1. Drain-Current Turn-On Delay Time vs Drive Strength
Resistance
50
100
150 200 250 300 350
RDRV Resistance (k)
400
450
500
Figure 6-2. Turn-On Delay Time vs Drive Strength Resistance
140
-40C
0C
25C
85C
125C
Turn-On Slew Rate (V/ns)
120
100
80
60
40
20
0
0
600
6.5
500
6
400
-40C
25C
125C
OC limit
300
200
100
100
150 200 250 300 350
RDRV Resistance (k)
400
450
500
Figure 6-4. Turn-On Slew Rate vs Drive Strength Resistance
Source-Drain Voltage (V)
Drain Current (A)
Figure 6-3. Turn-On Rise Time vs Drive Strength Resistance
50
-40C
0C
25C
85C
125C
5.5
5
4.5
4
3.5
0
0
5
10
15
20
25
30
35
Drain-Source Voltage (V)
40
45
Figure 6-5. Drain Current vs Drain-Source Voltage
50
3
0
5
10
15
20
Source Current (A)
25
30
35
IN = 0 V
Figure 6-6. Off-State Source-Drain Voltage vs Source Current
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2
1750
1.8
1500
Output Capacitance (pF)
Normalized On Resistance
6.7 Typical Characteristics (continued)
1.6
1.4
1.2
1
1250
1000
750
500
250
0.8
0.6
-40
0
-20
0
20
40
60
80 100
Junction Temperature (°C)
120
140
0
160
50
100
150 200 250 300 350
Drain-Source Voltage (V)
400
450
500
Figure 6-8. Output Capacitance vs Drain-Source Voltage
Figure 6-7. Normalized On-Resistance vs Junction Temperatue
250
250
Vds = 0 V
Vds = 50 V
Vds = 400 V
200
150
Vds = 400 V
VDD Supply Current (mA)
VDD Supply Current (mA)
-40C
0C
25C
85C
125C
Vds = 50 V
100
Vds = 0 V
50
0
Vds = 0 V
Vds = 50 V
Vds = 400 V
200
150
Vds = 400 V
Vds = 50 V
100
Vds = 0 V
50
0
0
400
800
1200
1600
IN Switching Frequency (kHz)
VDD = 12 V;
2000
TJ = 25 °C.
0
400
800
1200
1600
IN Switching Frequency (kHz)
VDD = 12 V;
Figure 6-9. VDD Supply Current vs IN Switching Frequency
2000
TJ = 125 °C.
Figure 6-10. VDD Supply Current vs IN Switching Frequency
80
70
Drain Current (A)
60
50
40
30
20
10
0
0
50
100 150 200 250 300 350 400 450 500 550
Drain-Source Voltage (V)
Figure 6-11. Repetitive Safe Operation Area
10
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7 Parameter Measurement Information
7.1 Switching Parameters
Figure 7-1 shows the circuit used to measure most switching parameters. The top device in this circuit is used
to re-circulate the inductor current and functions in third-quadrant mode only. The bottom device is the active
device that turns on to increase the inductor current to the desired test current. The bottom device is then turned
off and on to create switching waveforms at a specific inductor current. Both the drain current (at the source) and
the drain-source voltage is measured. Figure 7-2 shows the specific timing measurement. TI recommends to use
the half-bridge as a double pulse tester. Excessive third-quadrant operation can overheat the top device.
DRAIN
RDRV
Slew
Rate
Direct-Drive
GaN
SOURCE
IN
VDD
VNEG
OCP, OTP,
LDO,
UVLO,
BB
TEMP
LDO5V
Current
LHB
TEMP
FAULT
OC
VBUS
+
CVDC
SOURCE
–
DRAIN
RDRV
Slew
Rate
Direct-Drive
GaN
SOURCE
+
IN
VDD
LDO5V
VDS
VNEG
OCP, OTP,
LDO,
UVLO,
BB
TEMP
Current
_
TEMP
PWM input
FAULT
OC
SOURCE
ID
Figure 7-1. Circuit Used to Determine Switching Parameters
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IN
50%
50%
td(on)(Idrain)
ID
1A
td(on)
td(off)
tr(on)
VDS
tf(off)
80%
80%
20%
20%
Figure 7-2. Measurement to Determine Propagation Delays and Slew Rates
7.1.1 Turn-On Times
The turn-on transition has three timing components: drain-current turn-on delay time, turn-on delay time, and
turn-on rise time. The drain-current turn-on delay time is from when IN goes high to when the GaN FET
drain-current reaches 1 A. The turn-on delay time is from when IN goes high to when the drain-source voltage
falls 20% below the bus voltage. Finally, the turn-on rise time is from when drain-source voltage falls 20% below
the bus voltage to when the drain-source voltage falls 80% below the bus voltage. Note that the turn-on rise time
is the same as the VDS 80% to 20% fall time. All three turn-on timing components are a function of the RDRV pin
setting.
7.1.2 Turn-Off Times
The turn-off transition has two timing components: turn-off delay time, and turn-off fall time. The turn-off delay
time is from when IN goes low to when the drain-source voltage rises to 20% of the bus voltage. The turn-off
fall time is from when the drain-source voltage rises to 20% of the bus voltage to when the drain-source voltage
rises to 80% of the bus voltage. Note that the turn-off fall time is the same as the VDS 20% to 80% rise time.
The turn-off timing components are independent of the RDRV pin setting, but heavily dependent on the LHB load
current.
7.1.3 Drain-Source Turn-On Slew Rate
The drain-source turn-on slew rate, measured in volts per nanosecond, is the inverse of the turn-on rise time or
equivalently the inverse of the VDS 80% to 20% fall time. The RDRV pin is used to program the slew rate.
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8 Detailed Description
8.1 Overview
The LMG3522R030 is a high-performance power GaN device with integrated gate driver. The GaN device
offers zero reverse recovery and ultra-low output capacitance, which enables high efficiency in bridge-based
topologies. Direct Drive architecture is applied to control the GaN device directly by the integrated gate driver.
This architecture provides superior switching performance compared to the traditional cascode approach and
helps solve a number of challenges in GaN applications.
The integrated driver ensures the device stays off for high drain slew rates. The integrated driver also protects
the GaN device from overcurrent, short-circuit, undervoltage, and overtemperature. Regarding fault signal
reporting, LMG3522R030 provides different reporting method which is shown in Table 8-1. Refer to Fault
Detection for more details. The integrated driver is also able to sense the die temperature and send out the
temperature signal through a modulated PWM signal.
Unlike Si MOSFETs, GaN devices do not have a p-n junction from source to drain and thus have no reverse
recovery charge. However, GaN devices still conduct from source to drain similar to a p-n junction body diode,
but with higher voltage drop and higher conduction loss. Therefore, source-to-drain conduction time must be
minimized while the LMG3522R030 GaN FET is turned off.
8.2 Functional Block Diagram
TEMP
VDD
LDO5V
DRAIN
Third-Quadrant
Detection
GaN
LDO
UVLO
(+5V, VDD, VNEG)
FAULT
Thermal
Shutdown
Die
Temp
Sensing
Series
Si FET
Short Circuit Protection
OC
Overcurrent Protection
IN
Gating logic control
& level shifting
BBSW
Buck-Boost
Controller
VNEG
RDRV
SOURCE
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8.3 Feature Description
The LMG3522R030 includes advanced features to provide superior switching performance and converter
efficiency.
8.3.1 GaN FET Operation Definitions
For the purposes of this data sheet, the following terms are defined below. The SOURCE pin is assumed to be at
0 V for these definitions.
First-Quadrant Current = Positive current flowing internally from the DRAIN pin to the SOURCE pin.
Third-Quadrant Current = Positive current flowing internally from the SOURCE pin to the DRAIN pin.
First-Quadrant Voltage = Drain pin voltage – Source pin voltage = Drain pin voltage
Third-Quadrant Voltage = SOURCE pin voltage – DRAIN pin voltage = –DRAIN pin voltage
FET On-State = FET channel is at rated RDS(on). Both first-quadrant current and third-quadrant current can flow
at rated RDS(on).
For LMG3522R030 in On-State, GaN FET internal gate voltage is held at the SOURCE pin voltage to achieve
rated R DS(on). The GaN FET channel is at rated RDS(on) with VGS = 0 V because the LMG3522R030 GaN FET is
a depletion mode FET.
FET Off-State = FET channel is fully off for positive first-quadrant voltage. No first-quadrant current can flow.
While first-quadrant current cannot flow in the FET Off-State, third-quadrant current still flows if the DRAIN
voltage is taken sufficiently negative (positive third-quadrant voltage). For devices with an intrinsic p-n junction
body diode, current flow begins when the DRAIN voltage drops enough to forward bias the p-n junction.
GaN FETS do not have an intrinsic p-n junction body diode. Instead, current flows because the GaN FET
channel turns back on. In this case, the DRAIN pin becomes the electrical source and the SOURCE pin
becomes the electrical drain. To enhance the channel in third-quadrant, the DRAIN (electrical source) voltage
must be taken sufficiently low to establish a VGS voltage greater than the GaN FET threshold voltage. The GaN
FET channel is operating in saturation and only turns on enough to support the third-quadrant current as its
saturated current.
For LMG3522R030 in Off-State, GaN FET internal gate voltage is held at the VNEG pin voltage to block all
first-quadrant current. The VNEG voltage is lower than the GaN FET negative threshold voltage to cut off the
channel.
To enhance the channel in off-state third quadrant, the LMG3522R030 DRAIN (electrical source) voltage must
be taken sufficiently close to VNEG to establish a VGS voltage greater than the GaN FET threshold voltage.
Again, because the LMG3522R030 GaN FET is a depletion mode FET with a negative threshold voltage, this
means the GaN FET turns on with DRAIN (electrical source) voltage between 0 V and VNEG. The typical
off-state third-quadrant voltage is 5 V for third-quadrant current at 20 A. Thus, the off-state third-quadrant losses
for the LMG3522R030 are significantly higher than a comparable power device with an intrinsic p-n junction body
diode.
8.3.2 Direct-Drive GaN Architecture
The LMG3522R030 uses a series Si FET to ensure the power IC stays off when VDD bias power is not applied.
When the VDD bias power is off, the series Si FET is interconnected with the GaN device in a cascode mode,
which is shown in the Functional Block Diagram. The gate of the GaN device is held within a volt of the series Si
FET's source. When a high voltage is applied on the drain and the silicon FET blocks the drain voltage, the VGS
of the GaN device decreases until the GaN device passes the threshold voltage. Then, the GaN device is turned
off and blocks the remaining major part of drain voltage. There is an internal clamp to make sure that the VDS of
the Si FET does not exceed its maximum rating. This feature avoids the avalanche of the series Si FET when
there is no bias power.
When LMG3522R030 is powered up with VDD bias power, the internal buck-boost converter generates a
negative voltage (VVNEG) that is sufficient to directly turn off the GaN device. In this case, the series Si FET is
held on and the GaN device is gated directly with the negative voltage.
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Comparing with traditional cascode drive GaN architecture, where the GaN gate is grounded and the Si
MOSFET gate is being driven to control the GaN device, direct-drive configuration has multiple advantages.
First, as the Si MOSFET does need to switch in every switching cycle, GaN gate-to-source charge (QGS) is
lower and there’s no Si MOSFET reverse-recovery related losses. Second, the voltage distribution between the
GaN and Si MOSFET in off-mode in a cascode configuration can cause the MOSFET to avalanche due to
high GaN drain-to-source capacitance (CDS). Finally, the switching slew rate in direct-drive configuration can be
controlled while cascode drive cannot. More information about the direct-drive GaN architecture can be found in
Direct-drive configuration for GaN devices.
8.3.3 Drain-Source Voltage Capability
Due to the silicon FET’s long reign as the dominant power-switch technology, many designers are unaware
that the headline drain-source voltage cannot be used as an equivalent point to compare devices across
technologies. The headline drain-source voltage of a silicon FET is set by the avalanche breakdown voltage.
The headline drain-source voltage of a GaN FET is set by the long term reliability with respect to data sheet
specifications.
Exceeding the headline drain-source voltage of a silicon FET can lead to immediate and permanent damage.
Meanwhile, the breakdown voltage of a GaN FET is much higher than the headline drain-source voltage. For
example, the breakdown voltage of the LMG3522R030 is more than 800 V.
A silicon FET is usually the weakest link in a power application during an input voltage surge. Surge protection
circuits must be carefully designed to ensure the silicon FET avalanche capability is not exceeded because it
is not feasible to clamp the surge below the silicon FET breakdown voltage. Meanwhile, it is easy to clamp the
surge voltage below a GaN FET breakdown voltage. In fact, a GaN FET can continue switching during the surge
event which means output power is safe from interruption.
The LMG3522R030 drain-source capability is explained with the assistance of Figure 8-1. The figure shows the
drain-source voltage versus time for a GaN FET for a single switch cycle in a switching application. No claim is
made about the switching frequency or duty cycle.
VDS(tr)
VDS(off)
VDS(switching)
t0
t1
t2
Figure 8-1. Drain-Source Voltage Switching Cycle
The waveform starts before t0 with the FET in the on state. At t0 the GaN FET turns off and parasitic elements
cause the drain-source voltage to ring at a high frequency. The peak ring voltage is designated VDS(tr). The
high frequency ringing has damped out by t1. Between t1 and t2 the FET drain-source voltage is set by
the characteristic response of the switching application. The characteristic is shown as a flat line, but other
responses are possible. The voltage between t1 and t2 is designated VDS(off). At t2 the GaN FET is turned on at
a non-zero drain-source voltage. The drain-source voltage at t2 is designated VDS(switching). Unique VDS(tr), VDS(off)
and VDS(switching) parameters are shown because each can contribute to stress over the lifetime of the GaN FET.
The LMG3522R030 drain-source surge voltage capability is seen with the absolute maximum ratings VDS(tr)(surge)
and VDS(surge) in the Specifications where VDS(tr)(surge) maps to VDS(tr) in Figure 8-1 and VDS(surge) maps to both
VDS(off) and VDS(switching) in Figure 8-1. More information about the surge capability of TI GaN FETs is found in A
New Approach to Validate GaN FET Reliability to Power-line Surges Under Use-conditions.
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8.3.4 Internal Buck-Boost DC-DC Converter
An internal inverting buck-boost converter generates a regulated negative rail for the turn-off supply of the GaN
device. The buck-boost converter is controlled by a peak current mode, hysteretic controller. In normal operation,
the converter remains in discontinuous-conduction mode, but can enter continuous-conduction mode during
start-up. The converter is controlled internally and requires only a single surface-mount inductor and output
bypass capacitor. Typically, the converter is designed to use a 4.7 μH inductor and a 2.2 μF output capacitor.
The buck-boost converter uses a peak current hysteretic control. As shown in Figure 8-2, the inductor current
increases at the beginning of a switching cycle until the inductor reaches the peak current limit. Then the
inductor current goes down to zero. The idle time between each current pulse is determined automatically by
the buck-boost controller, and can be reduced to zero. Therefore, the maximum output current happens when
the idle time is zero, and is decided by the peak current but to a first order is independent of the inductor value.
However, the peak output current the buck-boost can deliver to the -14V rail is proportional to the VDD input
voltage. Therefore, the maximum switching frequency of the GaN that the buck-boost can support varies with
VDD voltage and is only specified for operation up to 2 MHz for VDD voltages above 9V.
VNEG_avg
ûVNEG
VNEG
IDCDC,PK
Smaller
inductor
Buck-boost
inductor current
Larger
inductor
Idle time
1/(buck-boost frequency)
Figure 8-2. Buck-Boost Converter Inductor Current
The LMG3522R030 supports the GaN operation up to 2 MHz. As power consumption is very different in a wide
switching frequency range enabled by the GaN device, two peak current limits are used to control the buck-boost
converter. The two ranges are separated by IN positive-going threshold frequency. As shown in Figure 8-3,
when switching frequency is in the lower range, the peak current is initially set to the lower value IBBSW,M(low)
(typically 0.4 A) . When switching frequency is in the higher range, the peak current is raised to the higher
value IBBSW,M(high) (typically 1 A) and requires a larger inductor. There is a filter on this frequency detection
logic, therefore the LMG3522R030 requires five consecutive cycles at the higher frequency before it is set to the
higher buck-boost peak current limit. The current limit does not go down again until power off after the higher
limit is set. Even if the switching frequency returns to the lower range, the current limit does not decrease to the
lower limit.
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IBBSW,PK(high)
IBBSW,PK(low)
IBBSW,PK
IN
Figure 8-3. Buck-Boost Converter Peak Current
As the peak current of the buck-boost is subject to two different peak current limits which are 0.4 A and 1 A
for low and high frequency operation (see Internal Buck-Boost DC-DC Converter), so the inductor must have a
saturation current well above the rated peak current limit. After the higher limit is established by switching at a
higher frequency, the current limit does not go back to the lower level even when GaN device is then switched at
a lower frequency. Therefore, selecting an inductor according to the higher 1-A limit is recommended.
8.3.5 VDD Bias Supply
Wide VDD voltage ranges from 7.5 V to 18 V are supported by internal regulators which supply the bias supplies
needed for the internal circuits to function. TI recommends to use a 12-V unregulated power supply to supply
VDD.
8.3.6 Auxiliary LDO
There is a 5-V voltage regulator inside the part used to supply external loads, such as digital isolators for the
high-side drive signal. The digital outputs of the part use this rail as their supply. No capacitor is required for
stability, but transient response is poor if no external capacitor is provided. If the application uses this rail to
supply external circuits, TI recommends to have a capacitor of at least 0.1 μF for improved transient response.
A larger capacitor can be used for further transient response improvement. The decoupling capacitor used
here must be a low-ESR ceramic type. Capacitances above 0.47 μF will slow down the start-up time of the
LMG3522R030 due to the ramp-up time of the 5-V rail.
8.3.7 Fault Detection
The GaN power IC integrates overcurrent protection (OCP), short-circuit protection (SCP), overtemperature
protection (OTP) and undervoltage lockout (UVLO).
8.3.7.1 Overcurrent Protection and Short-Circuit Protection
There are two types of current faults which can be detected by the driver: overcurrent fault and short-circuit fault.
The overcurrent protection (OCP) circuit monitors drain current and compares that current signal with an
internally set limit IT(OC). Upon detection of the overcurrent, the LMG3522R030 conducts cycle-by-cycle
overcurrent protection as shown in Figure 8-4. In this mode, the GaN device is shut off and the OC pin is
pulled low when the drain current crosses the IT(OC) plus a delay toff(OC), but the overcurrent signal clears after
the IN pin signal goes low. In the next cycle, the GaN device can turn on as normal. The cycle-by-cycle function
can be used in cases where steady-state operation current is below the OCP level but transient response can
still reach current limit, while the circuit operation cannot be paused. The cycle-by-cycle function also prevents
the GaN device from overheating by overcurrent induced conduction losses.
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The short-circuit protection (SCP) monitors the drain current and triggers if the di/dt of the current exceeds a
threshold di/dt T(SC) as the current crosses between the OC and SC thresholds. It performs this di/dt detection
by delaying the OC detection signal by an amount tOC,window and using a higher current SC detection threshold.
If the delayed OC occurs before the non-delayed SC, the di/dt is below the threshold and an OC is triggered. If
the SC is detected first, the di/dt is fast enough and the SC is detected as shown in Figure 8-5. This extremely
high di/dt current would typically be caused by a short of the output of the half-bridge and can be damaging for
the GaN to continue to operate in that condition. Therefore, if a short-circuit fault is detected, the GaN device
is turned off with an intentionally slowed driver so that a lower overshoot voltage and ringing can be achieved
during the turn-off event. This fast response circuit helps protect the GaN device even under a hard short-circuit
condition. In this protection, the GaN device is shut off and held off until the fault is reset by either holding the IN
pin low for a period of time defined in the Specifications or removing power from VDD.
During OCP or SCP in a half bridge, after the current reaches the upper limit and the device is turned off by
protection, the PWM input of the device could still be high and the PWM input of the complementary device
could still be low. In this case, the load current can flow through the third quadrant of the complementary device
with no synchronous rectification. The high negative VDS of the GaN device (–3 V to –5 V) from drain to source
could lead to high third-quadrant loss, similar to dead-time loss but for a longer time.
For safety considerations, OCP allows cycle-by-cycle operation while SCP latches the device until reset. By
reading the FAULT and OC pins, the exact current fault type can be determined. Refer to Fault Reporting for
detailed information.
IT(OC)
Inductor current
VSW
Input PWM
Figure 8-4. Cycle-by-Cycle OCP Operation
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toff(SC)
toff(OC)
IT(SC)
< t(window)(OC)
IT(OC)
ID
IN
OC
Cycle by cycle OCP
Latched SCP
Figure 8-5. Overcurrent Detection vs Short-Circuit Detection
8.3.7.2 Overtemperature Shutdown
The LMG3522R030 implements two overtemperature-shutdown (OTSD) functions, the GaN OTSD and the
Driver OTSD. Two OTSD functions are needed to maximize device protection by sensing different locations in
the device and protecting against different thermal-fault scenarios.
The GaN OTSD senses the GaN FET temperature. The GaN FET can overheat from both first-quadrant current
and third-quadrant current. As explained in GaN FET Operation Definitions, a FET can prevent first-quadrant
current by going into the off-state but is unable to prevent third-quadrant current. FET third-quadrant losses are
a function of the FET technology, current magnitude, and if the FET is operating in the on-state or off-state.
As explained in GaN FET Operation Definitions, the LMG3522R030 has much higher GaN FET third-quadrant
losses in the off-state.
When the GaN FET is too hot, the best protection is to turn off the GaN FET when first-quadrant current tries
to flow and turn on the GaN FET when third-quadrant current is flowing. This type of FET control is known
as ideal-diode mode (IDM). When the GaN OTSD trip point is exceeded, the GaN OTSD puts the GaN FET
into overtemperature-shutdown ideal-diode mode (OTSD-IDM) operation to achieve this optimum protection.
OTSD-IDM is explained in Section 8.3.10 .
The Driver OTSD senses the integrated driver temperature and trips at a higher temperature compared to the
GaN OTSD. This second OTSD function exists to protect the LMG3522R030 from driver thermal-fault events
while allowing sufficient temperature difference for OTSD-IDM to operate. These driver thermal events include
shorts on the LDO5V, BBSW, and VNEG device pins. When the Driver OTSD trip point is exceeded, the Driver
OTSD shuts off the LDO5V regulator, the VNEG buck-boost converter, and the GaN FET. Note that OTSD-IDM
does not function in Driver OTSD. This is why the Driver OTSD must trip higher than the GaN OTSD function.
Otherwise, GaN FET third-quadrant overheating cannot be addressed.
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Besides the temperature difference in the GaN OTSD and Driver OTSD trip points, further temperature
separation is obtained due to the thermal gradient difference between the GaN OTSD and Driver OTSD sense
points. The GaN OTSD sensor is typically at least 20°C hotter than the driver OTSD sensor when the device is in
GaN OTSD due to GaN FET power dissipation.
The FAULT pin is asserted for either or both the GaN OTSD state and the Driver OTSD state. FAULT de-asserts
and the device automatically returns to normal operation after both the GaN OTSD and Driver OTSD fall below
their negative-going trip points. During cool down, when the device exits the Driver OTSD state but is still in the
GaN OTSD state, the device automatically resumes OTSD-IDM operation.
8.3.7.3 UVLO Protection
The LMG3522R030 supports a wide range of VDD voltages. However, when the device is below UVLO
threshold, the GaN device stops switching and is held off. The FAULT pin is pulled low as an indication of
UVLO. The LDO and buck-boost are turned on by the rising-edge of the VIN UVLO and shuts off around 5 V to 6
V.
8.3.7.4 Fault Reporting
The FAULT and OC outputs form a fault reporting scheme together. The FAULT and OC outputs are both
push-pull outputs indicating the readiness and fault status of the driver. These two pins are logic high in normal
operation, and change logic according to Table 8-1.
Table 8-1. Fault Types and Reporting
NORMAL
UVLO, OT, and RDRV-OPEN
OVERCURRENT
SHORT-CIRCUIT
FAULT
1
0
1
0
OC
1
1
0
0
FAULT is held low when starting up until the series Si FET is turned on. During operation, if the power supplies
go below the UVLO thresholds or the device temperature go above the OT thresholds, power device is disabled
and FAULT is held low until a fault condition is no longer detected. If RDRV is open, FAULT is also held low.
In a short-circuit or overtemperature fault condition, FAULT is held low until the fault latches are reset or fault is
cleared. The OC pin is held low if there is a short-circuit or overcurrent fault. The signals help notify the controller
the exact type of faults by reading the truth table. If a combined reporting of the faults on a single pin is desired,
one can short the OC pin to ground during power up. All faults assert the FAULT pin then and the OC pin is not
used. Please note: internal protection happens regardless of the connection of the pin outputs, which means that
the protection features continue to operate even if fault reporting is ignored.
8.3.8 Drive Strength Adjustment
The LMG3522R030 allows users to adjust the drive strength of the device and obtain a desired slew rate, which
provides flexibility when optimizing switching losses and noise coupling.
To adjust drive strength, a resistor can be placed between the RDRV pin and SOURCE pin. The resistance
determines the slew rate of the device, from 20 V/ns to 150 V/ns, during turn-on. On the other hand, there are
two dv/dt values that can be selected without the resistor: shorting the RDRV pin to ground sets the slew rate
to 150 V/ns, and shorting the RDRV pin to LDO5V sets the slew rate to 100 V/ns. The device detects the short
to LDO5V one time at power up. Once the short to LDO5V condition is detected, the device no longer monitors
the RDRV pin. Otherwise, the RDRV pin is continuously monitored and the dv/dt setting can be changed by
modulating the resistance during device operation. The modulation must be fairly slow since there is significant
internal filtering to reject switching noise.
Please note: parasitic power loop inductance can influence the voltage slew rate reading from the VDS switching
waveform.The inductance induces a drop on VDS in the current rising phase before voltage falling phase, if this
drop is more than 20% of the VDC, the voltage slew rate reading can be influenced. Refer to Section 9.5.1.2 for
the power loop design guideline and how to estimate the parasitic power loop inductance.
20
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8.3.9 Temperature-Sensing Output
The integrated driver senses the GaN die temperature and outputs the information through a modulated PWM
signal on the TEMP pin. The typical PWM frequency is 9 kHz with the same refresh rate. The minimum PWM
duty cycle is around 1%, which can be observed at temperature below 25°C. The target temperature range is
from 25°C to 150°C, and the corresponding PWM duty cycle is typically from 3% to 82%. Following equation can
be used to calculate the typical junction temperature TJ,typ in °C from the duty cycle DTEMP:
TJ,typ (°C) = 162.3 * DTEMP + 20.1
The tolerances of typical measurement are listed in Table 8-2.
Table 8-2. Typical Junction Temperature Measurement based on TEMP Signal and Tolerance
Typical TJ Measurement based on TEMP Signal (°C)
25
85
125
Tolerance (°C)
±5
±6
± 10
At temperatures above 150°C, the duty cycle continues to increase linearly until overtemperature fault happens.
When overtemperature happens, the TEMP pin is pulled high to indicate this fault until the temperature is
reduced to the normal range. There is a hysteresis to clear overtemperature fault.
8.3.10 Ideal-Diode Mode Operation
Off-state FETs act like diodes by blocking current in one direction (first quadrant) and allowing current in the
other direction (third quadrant) with a corresponding diode like voltage drop. FETs, though, can also conduct
third-quadrant current in the on-state at a significantly lower voltage drop. Ideal-diode mode (IDM) is when an
FET is controlled to block first-quadrant current by going to the off-state and conduct third-quadrant current by
going to the on-state, thus achieving an ideal lower voltage drop.
FET off-state third-quadrant current flow is commonly seen in power converters, both in normal and fault
situations. As explained in GaN FET Operation Definitions, GaN FETs do not have an intrinsic p-n junction
body diode to conduct off-state third-quadrant current. Instead, the off-state third-quadrant voltage drop for the
LMG3522R030 is several times higher than a p-n junction voltage drop, which can impact efficiency in normal
operation and device ruggedness in fault conditions.
To improve device ruggedness in a GaN FET overtemperature fault situation, LMG3522R030 devices
implement a GaN FET overtemperature-shutdown ideal-diode mode (OTSD-IDM) function as referenced in
Overtemperature Shutdown. The OTSD-IDM function is described in more detail below.
8.3.10.1 Overtemperature-Shutdown Ideal-Diode Mode
Overtemperature-shutdown ideal-diode mode (OTSD-IDM) is implemented in LMG3522R030. As explained in
Overtemperature Shutdown, ideal-diode mode provides the best GaN FET protection when the GaN FET is
overheating.
OTSD-IDM accounts for all, some, or none of the power system operating when OTSD-IDM is protecting the
GaN FET. The power system may not have the capability to shut itself down, in response to the LMG3522R030
asserting the FAULT pin in a GaN OTSD event, and just continue to try to operate. Parts of the power system
can stop operating due to any reason such as a controller software bug or a solder joint breaking or a device
shutting off to protect itself. At the moment of power system shutdown, the power system stops providing gate
drive signals but the inductive elements continue to force current flow while they discharge.
The OTSD-IDM state machine is shown in Figure 8-6. Each state is assigned a state number in the upper right
side of the state box. The OTSD-IDM state machine has a similar structure to the OP-IDM state machine. Similar
states use the same state number.
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1
FET OFF
OTSD-IDM waiting for IN
falling-edge blank time to
expire
IN falling-edge blank
time expired
IN falling edge
IN falling edge
FET OFF
2
First-quadrant drain
current
FET ON
OTSD-IDM looking for negative
VDS
3
OTSD-IDM looking for firstquadrant drain current
Negative VDS due to
third-quadrant drain
current
Enter OTSD
Figure 8-6. Overtemperature-Shutdown Ideal-Diode Mode (OTSD-IDM) State Machine
1. The LMG3522R030 GaN FET always goes to state #1 if a falling edge is detected on the IN pin. OTSD-IDM
turns off the GaN FET in OTSD-IDM state #1. OTSD-IDM is waiting for the IN falling edge blank time to
expire. This time gives the opposite-side FET time to switch to create a positive drain voltage. After the blank
time expires, the device moves to OTSD-IDM state #2.
2. For OTSD-IDM state #2, OTSD-IDM keeps the GaN FET off if it is coming from OTSD-IDM state #1 and
turns the GaN FET off if it is coming from OTSD-IDM state #3. OTSD-IDM is monitoring the GaN FET drain
voltage in OP-IDM state #2. It is looking for a negative drain voltage which means third-quadrant current is
flowing. This is also the starting state when the device enters OTSD. After a negative GaN FET drain voltage
is detected, the device moves to OTSD-IDM state #3
3. OP-IDM turns on the GaN FET in OTSD-IDM state #3. OP-IDM monitors the drain current in this state. If
first-quadrant drain current is detected, the device moves to OP-IDM state #2.
State #1 is used to protect against shoot-through current. The state #1 in the OTSD-IDM state machine waits for
a fixed time period before proceeding to state #2. The fixed time period is to give the opposite-side switch time
to switch and create a positive drain voltage. A fixed time is used to avoid a stuck condition for cases where a
positive drain voltage is not created.
State #1 will help protect against shoot-through currents if the converter continues switching when the
LMG3522R030 enters OTSD. Meanwhile, if the converter initiates switching with the LMG3522R030 already
in OTSD, shoot-through current protection can be obtained by switching the OTSD device first to force it to
progress though state #1. For example, the synchronous rectifier in a boost PFC can go into OTSD during initial
input power application as the inrush current charges the PFC output cap. A shoot-through current event can be
avoided if converter switching begins by switching the synchronous rectifier FET before switching the boost PFC
FET.
If there is no IN signal, the state machine only moves between states #2 and #3 as a classic ideal-diode
mode state machine. This allows all the inductive elements to discharge, when the power system shuts off, with
minimum discharge stress created in the GaN FET.
Note that the OTSD-IDM state machine has no protection against repetitive shoot-through current events. There
are degenerate cases, such as the LMG3522R030 losing its IN signal during converter operation, which can
expose the OTSD-IDM to repetitive shoot-through current events. There is no good solution in this scenario.
If OTSD-IDM did not allow repeated shoot-thru current events, the GaN FET would instead be exposed to
excessive off-state third-quadrant losses.
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8.4 Start Up Sequence
Figure 8-7 shows the start up sequence of LMG3522R030.
Time interval A: VDD starts to build up. FAULT signal is initially pulled low.
Time interval B: After VDD passes the UVLO threshold VVDD,T+(UVLO), both LDO5V and VNEG start to built up. In a
typical case where CLDO5V = 100 nF and CVNEG = 2.2 μF, LDO5V reaches its UVLO thresold earlier than VNEG.
The start-up time may vary if different capacitors are utilized. If VDD has some glitches and falls below UVLO
threshold VVDD,T-(UVLO) in this time interval, LDO5V and VNEG will stop building up and only resume when VDD
goes above VVDD,T+(UVLO) again. A longer start-up time is expected in this case.
Time interval C: After LDO5V and VNEG both reach their thresholds, the FAULT signal is cleared (pulled high)
and the device is able to switch following the IN pin signal.
VVDD,T+(UVLO)
VDD
VNEG
VLDO5V
t(start)
FAULT
(A)
(B)
(C)
Figure 8-7. Start Up Timing Diagram
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8.5 Safe Operation Area (SOA)
8.5.1 Safe Operation Area (SOA) - Repetitive SOA
The allowed repetitive SOA for the LMG3522R030 (Figure 6-11) is defined by the peak drain current (IDS) and
the drain to source voltage (VDS) of the device during turn on. The peak drain current during switching is the
sum of several currents going into drain terminal: the inductor current (Iind); the current required to charge the
COSS of the other GaN device in the totem pole; and the current required to charge the parasitic capacitance
(Cpar) on the switching node. 310 pF is used as an average COSS of the device during switching. The parasitic
capacitance on the switch node may be estimated by using the overlap capacitance of the PCB. A boost
topology is used for the SOA testing. The circuit shown in Figure 8-8 is used to generate the SOA curve in
Figure 6-11. For reliable operation, the junction temperature of the device must also be limited to 125 °C. The IDS
of Figure 6-11 can be calculated by:
IDS = Iind + (310 pF + Cpar) * Drain slew rate at peak current
where drain slew rate at the peak current is estimated between 70 percent and 30 percent of the bus voltage,
and Cpar is the parasitic board capacitance at the switched node.
Q1,Q2:
LMG3522R030
Q1
FAULT
D
GaN
IN
L
RDRV
Cout
Temp, Current
S
Vin
Iind
Q2
FAULT
D
GaN
Vbus
520 V
50 pF
IN
RDRV
Cpar
L
O
A
D
Temp, Current
S
Figure 8-8. Circuit Used for SOA Curve
Refer to Achieving GaN Products With Lifetime Reliability for more details.
8.6 Device Functional Modes
The device has one mode of operation that applies when operated within the Recommended Operating
Conditions.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The LMG3522R030 is a power IC targeting hard-switching and soft-switching applications operating up to
520-V bus voltages. GaN devices offer zero reverse-recovery charge enabling high-frequency, hard-switching in
applications like the totem-pole PFC. Low Qoss of GaN devices also benefits soft-switching converters, such as
the LLC and phase-shifted full-bridge configurations. As half-bridge configurations are the foundation of the two
mentioned applications and many others, this section describes how to use the LMG3522R030 in a half-bridge
configuration.
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9.2 Typical Application
LMG352x
Vdc
D
CDRVH
RDRV
RDRVH
PWM_H
Isolator
ISO77X1F
CNEGH
TEMP_H
/OC_H
ROCH
/FAULT_H
RFTH
CFTH
COCH
CINH
ISO
TEMP
/OC
VCC2
/FAULT
CLDOH
SGND
VNEG
LBBSWHBBSW
SGND
PWR
IN
RINH
LDO5V
VDD
Transformer
driver
SN6505
CVDDH
GND
S
SW
LMG352x
Cdecoupling
D
CDRVL
RDRV
RDRVL
PWM_L
Isolator
ISO77X1F
IN
RINL
TEMP_L
CINL
CNEGL
VNEG
LBBSWLBBSW
/OC_L
TEMP
/FAULT_L
/OC
CLDOL
/FAULT
LDO5V
PWR
SGND
VDD
Transformer
driver
SN6505
CVDDL
GND
S
PGND
Figure 9-1. Typical Half-Bridge Application with Isolated Power Supply
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LMG352x
Vdc
D
CDRVH
RDRV
RDRVH
Isolator
ISO77X1F
PWM_H
IN
RINH
CNEGH
TEMP_H
CINH
VNEG
ROCH
LBBSWHBBSW
/FAULT_H
RFTH
TEMP
CFTH
COCH
/OC_H
/OC
/FAULT
CLDOH
LDO5V
SGND
VDD
Dbootstrap
CVDDH
Rbootstrap
GND
S
DZ
SW
LMG352x
RDRVL_start
Cdecoupling
D
CDRVH
Isolator
ISO77X1F
RDRV
RDRVL
PWM_L
IN
RINL
TEMP_L
CINL
CNEGL
VNEG
LBBSWLBBSW
/OC_L
TEMP
/FAULT_L
/OC
CLDOL
/FAULT
LDO5V
PWR
SGND
VDD
Transformer
driver
SN6505
CVDDL
GND
S
PGND
Figure 9-2. Typical Half-Bridge Application with Bootstrap
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9.2.1 Design Requirements
This design example is for a hard-switched boost converter which is representative of PFC applications. Table
9-1 shows the system parameters for this design.
Table 9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
200 VDC
Output voltage
400 VDC
Input (inductor) current
20 A
Switching frequency
100 kHz
9.2.2 Detailed Design Procedure
In high-voltage power converters, circuit design and PCB layout are essential for high-performance power
converters. As designing a power converter is out of the scope of this document, this data sheet describes how
to build well-behaved half-bridge configurations with the LMG3522R030.
9.2.2.1 Slew Rate Selection
The slew rate of LMG3522R030 can be adjusted between approximately 20 V/ns and 150 V/ns by connecting a
resistor, RRDRV, from the RDRV pin to GND. The RDRV pin is a high-impedance node if a large RRDRV resistor is
used. Therefore it can be susceptible to coupling from the drain or other fast-slewing high-voltage nodes if it isn’t
well-shielded. This will manifest itself as an unstable switching dv/dt and in extreme cases transient faults due to
the RDRV being detected as open. Shielding the pin in the layout should be a priority, however if this coupling is
still a problem, a cap of up to 1nF from RDRV to GND can be added to stabilize the pin voltage.
The slew rate affects GaN device performance in terms of:
•
•
•
•
Switching loss
Voltage overshoot
Noise coupling
EMI emission
Generally, high slew rates provide low switching loss, but high slew rates can also create higher voltage
overshoot, noise coupling, and EMI emissions. Following the design recommendations in this data sheet helps
mitigate the challenges caused by a high slew rate. The LMG3522R030 offers circuit designers the flexibility to
select the proper slew rate for the best performance of their applications.
9.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
Using a bootstrap supply introduces additional constraints on the start-up of the high-side LMG3522R030. Prior
to powering up, the GaN device operates in cascode mode with reduced performance. In some circuits, a slower
slew rate can be required for the start-up of a bootstrap-supplied half-bridge configuration. More information can
be found in Section 9.4.2.
9.2.2.2 Signal Level-Shifting
In half-bridges, high-voltage level shifters or digital isolators must be used to provide isolation for signal paths
between the high-side device and control circuit. Using an isolator is optional for the low-side device. However,
using and isolator equalizes the propagation delays between the high-side and low-side signal paths, and
provides the ability to use different grounds for the GaN device and the controller. If an isolator is not used on
the low-side device, the control ground and the power ground must be connected at the device and nowhere
else on the board. For more information, see Layout Guidelines. With fast-switching devices, common ground
inductance can easily cause noise issues without the use of an isolator.
Choosing a digital isolator for level-shifting is important for improvement of noise immunity. As GaN device
can easily create high dv/dt, > 50 V/ns, in hard-switching applications, TI highly recommends to use isolators
with high common-mode transient immunity (CMTI) and low barrier capacitance. Isolators with low CMTI can
easily generate false signals, which could cause shoot-through. The barrier capacitance is part of the isolation
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capacitance between the signal ground and power ground, which is in direct proportion to the common mode
current and EMI emission generated during the switching. Additionally, TI strongly encourages to select isolators
which are not edge-triggered. In an edge-triggered isolator, a high dv/dt event can cause the isolator to flip states
and cause circuit malfunction.
Generally, ON/OFF keyed isolators with default output low are preferred, such as the TI ISO77xxF or ISO67xxF
series. Default low state ensures the system will not shoot-through when starting up or recovering from fault
events. As a high CMTI event would only cause a very short (a few nanoseconds) false pulse, TI recommends a
low pass filter, like 300 Ω and 22 pF R-C filter, to be placed at the driver input to filter out these false pulses.
9.2.2.3 Buck-Boost Converter Design
Figure 9-3 and Figure 9-4 show the buck-boost converter efficiency versus load current with different inductors
and peak current modes. A minimum inductance value of 3 µH is preferred for the buck-boost converter so that
the di/dt across the inductor is not too high. This leaves enough margin for the control loop to respond. As a
result, the maximum di/dt of the inductor is limited to 6 A/µs. On the other hand, large inductance also limits the
transient response for stable output voltage, and it is preferred to have inductors less than 10 µH.
85
Buck-Boost Efficiency (%)
80
75
70
LBBSW = 3.3 H
LBBSW = 4.7 H
LBBSW = 10 H
65
60
55
50
0
10
20
30
40
50
60
70
Buck-Boost Load Current (mA)
VDD = 12 V;
80
90
VDD = 12 V;
TJ = 25 °C.
Figure 9-3. Buck-Boost Efficiency vs Load when
IBBSW,PK = IBBSW,PK(low)
TJ = 25 °C.
Figure 9-4. Buck-Boost Efficiency vs Load when
IBBSW,PK = IBBSW,PK(high)
9.2.3 Application Curves
VDS (50 V/div)
ID (2.5 A/div)
VDS (50 V/div)
ID (1.25 A/div)
VOUT = 400V
IL = 5 A
RDRV = 40 k:
VBUS = 400 V
IL = 5 A
RDRV = 40 k:
Time (5 ns/div)
Time (5 ns/div)
D006
Figure 9-5. Turn-On Waveform in Application
Example
D007
Figure 9-6. Turn-Off Waveform in Application
Example
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9.3 Do's and Don'ts
The successful use of GaN devices in general, and LMG3522R030 in particular, depends on proper use of the
device. When using the LMG3522R030, DO:
•
•
•
•
•
•
Read and fully understand the data sheet, including the application notes and layout recommendations.
Use a four-layer board and place the return power path on an inner layer to minimize power-loop inductance.
Use small, surface-mount bypass and bus capacitors to minimize parasitic inductance.
Use the proper size decoupling capacitors and locate them close to the IC as described in Layout Guidelines.
Use a signal isolator to supply the input signal for the low-side device. If not, ensure the signal source is
connected to the signal GND plane which is tied to the power source only at the LMG3522R030 IC.
Use the FAULT pin to determine power-up state and to detect overcurrent and overtemperature events and
safely shut off the converter.
To avoid issues in your system when using the LMG3522R030, DON'T:
•
•
•
•
•
Use a single-layer or two-layer PCB for the LMG3522R030 as the power-loop and bypass capacitor
inductances is excessive and prevent proper operation of the IC.
Reduce the bypass capacitor values below the recommended values.
Allow the device to experience drain transients above 600 V as they can damage the device.
Allow significant third-quadrant conduction when the device is OFF or unpowered, which can cause
overheating. Self-protection features cannot protect the device in this mode of operation.
Ignore the FAULT pin output.
9.4 Power Supply Recommendations
The LMG3522R030 only requires an unregulated VDD power supply from 7.5 V to 18 V. The low-side supply
can be obtained from the local controller supply. The supply of the high-side device must come from an isolated
supply or a bootstrap supply.
9.4.1 Using an Isolated Power Supply
Using an isolated power supply to power the high-side device has the advantage that it works regardless of
continued power-stage switching or duty cycle. Using an isolated power supply can also power the high-side
device before power-stage switching begins, eliminating the power-loss concern of switching with an unpowered
LMG3522R030 (see Start-Up and Slew Rate With Bootstrap High-Side Supply for details). Finally, a properlyselected isolated supply introduces less parasitics and reduces noise coupling.
The isolated supply can be obtained with a push-pull converter, a flyback converter, a FlyBuck™ converter, or
an isolated power module. When using an unregulated supply, the input of LMG3522R030 must not exceed
the maximum supply voltage. A 16-V TVS diode can be used to clamp the VDD voltage of LMG3522R030 for
additional protection. Minimizing the inter-winding capacitance of the isolated power supply or transformer is
necessary to reduce switching loss in hard-switched applications. Furthermore, capacitance across the isolated
bias supply inject high currents into the signal-ground of the LMG3522R030 and can cause problematic groundbounce transients. A common-mode choke can alleviate most of these issues.
9.4.2 Using a Bootstrap Diode
In half-bridge configuration, a floating supply is necessary for the high-side device. To obtain the best
performance of LMG3522R030, TI highly recommends Using an Isolated Power Supply. A bootstrap supply
can be used with the recommendations of this section.
In applications like a boost converter, the low side LMG3522R030 always start switching while high side
LMG3522R030 is unpowered. If the low side is adjusted to achieve very high slew rate before the high side
bias is fully settled, there can be unintentional turn-on at the high side due to parasitic coupling at high slew rate.
The start-up slew rate must be slowed down to 100 V/ns by changing the resistance of RDRV pin of the low side.
This slow down can be achieved by controlling the low side RDRV resistance with the high side FAULT as given
in Figure 9-1.
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9.4.2.1 Diode Selection
The LMG3522R030 offers no reverse-recovery charge and very limited output charge. Hard-switching circuits
using the LMG3522R030 also exhibit high voltage slew rates. A compatible bootstrap diode must not introduce
high output charge and reverse-recovery charge.
A silicon carbide diode, like the GB01SLT06-214, can be used to avoid reverse-recovery effects. The SiC diode
has an output charge of 3 nC. Althought there is additional loss from its output charge, it does not dominate the
losses of the switching stage.
9.4.2.2 Managing the Bootstrap Voltage
In a synchronous buck or other converter where the low-side switch occasionally operates in third-quadrant,
the bootstrap supply charges through a path that includes the third-quadrant voltage drop of the low-side
LMG3522R030 during the dead time as shown in Figure 9-7. This third-quadrant drop can be large, which can
over-charge the bootstrap supply in certain conditions. The VDD supply of LMG3522R030 must be kept below 18
V.
VDD
DRAIN
VF
SOURCE
+
±
DRAIN
VDD
VF
SOURCE
Figure 9-7. Charging Path for Bootstrap Diode
As shown in Figure 9-8, the recommended bootstrap supply includes a bootstrap diode, a series resistor,
and a 16-V TVS or zener diode in parallel with the VDD bypass capacitor to prevent damaging the high-side
LMG3522R030. The series resistor limits the charging current at start-up and when the low-side device
is operating in third-quadrant mode. This resistor must be selected to allow sufficient current to power
the LMG3522R030 at the desired operating frequency. At 100-kHz operation, TI recommends a value of
approximately 2 Ω . At higher frequencies, this resistor value must be reduced or the resistor omitted entirely to
ensure sufficient supply current.
+12 V
VDD
DRAIN
VF
SOURCE
Figure 9-8. Suggested Bootstrap Regulation Circuit
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9.5 Layout
9.5.1 Layout Guidelines
The layout of the LMG3522R030 is critical to its performance and functionality. Because the half-bridge
configuration is typically used with these GaN devices, layout recommendations are considered with this
configuration. A four-layer or higher layer count board is required to reduce the parasitic inductances of the
layout to achieve suitable performance. Figure 9-9 summarizes the critical layout guidelines, and more details
are further elaborated in the descriptions below.
Use RC circuits if
SGND is floating to
FET signal ground
for CMTI
PWM_H
Use high-side signal
ground plane
(connected to SW)
to shield traces
Isolator
ISO77X1F
LMG352x
IN
RINH
CNEGH
TEMP_H
CINH
VNEG
ROCH
LBBSWHBBSW
/FAULT_H
RFTH
TEMP
CFTH
COCH
/OC_H
/OC
/FAULT
CLDOH
SGND
PWR
SGND
Minimize power
loop to mitigate
transient
overvoltage
RDRV
RDRVH
Vdc
D
CDRVL
LDO5V
VDD
Transformer
driver
SN6505
CVDDH
GND
Recommend to parallel a
cap to reduce the noise
Use low-side signal
ground plane
(connected to GND)
to shield traces
PWM_L
Isolator
ISO77X1F
Minimize the loops of
these caps to mitigate
switching noises
LMG352x
/FAULT_L
SW
Cdecoupling
D
RDRV
RDRVL
CINL
/OC_L
Use Kelvin connection
between high side signal
ground and SW
CDRVL
IN
RINL
TEMP_L
S
CNEGL
VNEG
LBBSWLBBSW
TEMP
/OC
CLDOL
/FAULT
LDO5V
PWR
SGND
VDD
Transformer
driver
SN6505
CVDDL
GND
Minimize the loops of
these caps to mitigate
switching noises
S
Use Kelvin connection
between low side signal
ground and GND
PGND
Figure 9-9. Typical Schematic with Layout Considerations
9.5.1.1 Solder-Joint Reliability
Large QFN packages can experience high solder-joint stress. TI recommends several best practices to ensure
solder-joint reliability. First, the instructions for the NC1 and NC2 anchor pins found in Table 5-1 must be
followed. Second, all the LMG3522R030 board solder pads must be non-solder-mask defined (NSMD) as shown
in the land pattern example in Mechanical, Packaging, and Orderable Information. Finally, any board trace
connected to an NSMD pad must be less than 2/3 the width of the pad on the pad side where it is connected.
The trace must maintain this 2/3 width limit for as long as it is not covered by solder mask. After the trace is
under solder mask, there are no limits on the trace dimensions. All these recommendations are followed in the
Layout Example.
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9.5.1.2 Power-Loop Inductance
The power loop, comprising of the two devices in the half bridge and the high-voltage bus capacitance,
undergoes high di/dt during switching events. By minimizing the inductance of this loop, ringing and electromagnetic interference (EMI) can be reduced, as well as reducing voltage stress on the devices.
Place the power devices as close as possible to minimize the power loop inductance. The decoupling capacitors
are positioned in line with the two devices. They can be placed close to either device. In Layout Examples, the
devices are placed on the bottom layer and the decoupling capacitors are placed on the top layer. The PGND
is placed on the top layer, the HVBUS is located on top and third layer, and the switching node is on the top
layer. They are connected to the power devices on bottom layer with vias. Area of traces close to the devices are
minimized by bottom layer in order to keep clearance between heatsink and conductors.
The power loop inductance can be estimated based on the ringing frequency fring of the drain-source voltage
switching waveform based on the following equation
Lpl =
1
4π2f 2
ringCring
(1)
where Cring is equal to COSS at the bus voltage (refer to Figure 6-8 for the typical value) plus the drain-source
parasitic capacitance from the board and load inductor or transformer.
As the parasitic capacitance of load components is hard to character, it's recommended to capture the VDS
switching waveform without load components to estimate the power loop inductance. Typically, the power loop
inductance of the Layout Example is around 2.5 nH.
9.5.1.3 Signal-Ground Connection
The LMG3522R030's SOURCE pins are internally connected to the power IC signal ground. The return path
for the passives associated to the driver (for example, bypass capacitance) must be connected to the SOURCE
pins. Local signal ground planes must be connected to SOURCE pins with low impedance star connection. In
Layout Examples, local signal ground planes are located on third layer to act as the return path for the local
circuitry, and connected to the SOURCE pins with vias between the third layer and the bottom layer.
9.5.1.4 Bypass Capacitors
The gate drive loop impedance must be minimized to obtain good performance. Although the gate driver is
integrated on package, the bypass capacitance for the driver is placed externally. As the GaN device is turned
off to a negative voltage, the impedance of the path to the external VNEG capacitor is included in the gate drive
loop. The VNEG capacitor must be placed close to VNEG and SOURCE pins. In the Section 9.5.2, the bypass
capacitors , C3 and C13, are located in the top layer and are connected to VNEG pins with vias and SOURCE
pins through the local signal ground plane.
The VDD pin bypass capacitors, C1 and C11, must also be placed close to the VDD pin with low impedance
connections.
9.5.1.5 Switch-Node Capacitance
GaN devices have very low output capacitance and switch quickly with a high dv/dt, yielding very low switching
losses. To preserve this low switching losses, additional capacitance added to the output node must be
minimized. The PCB capacitance at the switch node can be minimized by following these guidelines:
•
•
•
•
•
•
•
Minimize overlap between the switch-node plane and other power and ground planes.
Make the GND return path under the high-side device thinner while still maintaining a low-inductance path.
Choose high-side isolator ICs and bootstrap diodes with low capacitance.
Place the power inductor as close to the GaN device as possible.
Power inductors must be constructed with a single-layer winding to minimize intra-winding capacitance.
If a single-layer inductor is not possible, consider placing a small inductor between the primary inductor and
the GaN device to effectively shield the GaN device from the additional capacitance.
If a back-side heat-sink is used, use the least amount of area of the switch-node copper coverage on the
bottom copper layer to improve the thermal dissipation.
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9.5.1.6 Signal Integrity
The control signals to the LMG3522R030 must be protected from the high dv/dt caused by fast switching.
Coupling between the control signals and the drain can cause circuit instability and potential destruction. Route
the control signals (IN, FAULT and OC) over a ground plane placed on an adjacent layer. In Layout Example, for
example, all the signals are routed on layers close to the local signal ground plane.
Capacitive coupling between the traces for the high-side device and the static planes, such as PGND and
HVBUS, could cause common mode current and ground bounce. The coupling can be mitigated by reducing
overlap between the high-side traces and the static planes. For the high-side level shifter, ensure no copper from
either the input or output side extends beneath the isolator or the CMTI of the device can be compromised.
9.5.1.7 High-Voltage Spacing
Circuits using the LMG3522R030 involve high voltage, potentially up to 650 V. When laying out circuits using
the LMG3522R030, understand the creepage and clearance requirements for the application and how they
apply to the GaN device. Functional (or working) isolation is required between the source and drain of each
transistor, and between the high-voltage power supply and ground. Functional isolation or perhaps stronger
isolation (such as reinforced isolation) can be required between the input circuitry to the LMG3522R030 and the
power controller. Choose signal isolators and PCB spacing (creepage and clearance) distances which meet your
isolation requirements.
If a heat sink is used to manage thermal dissipation of the LMG3522R030, ensure necessary electrical isolation
and mechanical spacing is maintained between the heat sink and the PCB.
9.5.1.8 Thermal Recommendations
The LMG3522R030 is a lateral device grown on a Si substrate. The thermal pad is connected to the source
of device. The LMG3522R030 can be used in applications with significant power dissipation, for example,
hard-switched power converters. In these converter, TI recommends a heat sink connected to the top side of
LMG3522R030. The heat sink can be applied with thermal interface materials (TIMs), like thermal pad with
electrical isolation.
Refer to the High Voltage Half Bridge Design Guide for LMG3410 Smart GaN FET application note for more
recommendations and performance data on thermal layouts.
34
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9.5.2 Layout Examples
Correct layout of the LMG3522R030 and its surrounding components is essential for correct operation. The
layouts shown here reflect the GaN device schematic in Figure 9-1. These layouts are shown to produce good
results and is intended as a guideline. However, it can be possible to obtain acceptable performance with
alternate layout schemes. Additionally, please refer to the land pattern example in Mechanical, Packaging, and
Orderable Information for the latest recommended PCB footprint of the device.
The the top-layer layout, mid-layer and bottom-layer layout are shown. The mid-layer layout includes the outlines
of the top level components to assist the reader in lining up the top-layer and mid-layer layouts.
Minimize the loops of C1,
C3, C11, C13.
Isolation boundary
Figure 9-10. Half-Bridge Top-Layer Layout
Kelvin connections between
Source and signal ground plane
Low side signal
ground plane for
shielding
High side signal
ground plane for
shielding
Minimize the power loop by
using vertical structure and
nearest signal layer for return
Figure 9-11. Half-Bridge Third-Layer (Light Grey) and Bottom-Layer (Dark Grey) Layout
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
•
•
Texas Instruments, High Voltage Half Bridge Design Guide for LMG3410 Smart GaN FET application note.
Texas Instruments, A New Approach to Validate GaN FET Reliability to Power-line Surges Under Useconditions.
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
FlyBuck™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
10.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
36
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PACKAGE OPTION ADDENDUM
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8-Aug-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
LMG3522R030RQSR
ACTIVE
VQFN
RQS
52
2000
RoHS-Exempt
& Green
NIPDAU
Level-3-260C-168 HR
-40 to 150
LMG3522R030
Samples
LMG3522R030RQST
ACTIVE
VQFN
RQS
52
250
RoHS-Exempt
& Green
NIPDAU
Level-3-260C-168 HR
-40 to 150
LMG3522R030
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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