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LMH0344
SNLS233O – APRIL 2007 – REVISED JULY 2015
LMH0344 3-Gbps HD - SD SDI Adaptive Cable Equalizer
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
•
•
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Compliant With ST 424, ST 292, ST 344, and ST
259 (1)
Supports DVB-ASI at 270 Mbps
Wide Range of Data Rates: 125 Mbps to 2.97
Gbps
Equalizes up to 120 Meters of Belden 1694A at
2.97 Gbps, up to 140 Meters of Belden 1694A at
1.485 Gbps, or up to 400 Meters of Belden 1694A
at 270 Mbps
Equalizes up to 120m of Belden 1694A at 2.97
Gbps With 0.3 UI Maximum Output Jitter
Manual Bypass and Output Mute With a
Programmable Threshold
Single-Ended or Differential Input
50-Ω Differential Outputs (Internal 50-Ω Pullups)
Single 3.3-V Supply Operation
280-mW Typical Power Consumption
16-Pin WQFN or 25-Ball CS-BGA Package
Industrial Temperature Range: −40°C to +85°C
HBM ESD Rating: 8 kV
WQFN Version Footprint Compatible With the
LMH0044, LMH0384, and LMH0074
Replaces the Semtech GS2974A or GS2974B
•
•
ST 424, ST 292, ST 344, and ST 259 Serial
Digital Interfaces (1)
Serial Digital Data Equalization and Reception
Data Recovery Equalization
3 Description
The LMH0344 3-Gbps HD – SD SDI Adaptive Cable
Equalizer is designed to equalize data transmitted
over cable (or any media with similar dispersive loss
characteristics). The equalizer operates over a wide
range of data rates from 125 Mbps to 2.97 Gbps and
supports ST 424, ST 292, ST 344, and ST 259.
The LMH0344 device implements DC restoration to
correctly handle pathological data conditions. The
equalizer may be driven in either a single-ended or
differential configuration.
Additional features include separate carrier detect
and output mute pins which may be tied together to
mute the output when no signal is present. A
programmable mute reference is provided to mute the
output at a selectable level of signal degradation.
For applications using the 4:4:4:4 10 bits video
format, the LMH0394 cable equalizer will provide
better performance.
The device is available in two space–saving
packages: a 4-mm × 4-mm 16-pin WQFN and even
more space-efficient 3-mm × 3-mm 25-ball CS-BGA
package.
Device Information(1)
PART NUMBER
(1)
Due to SMPTE naming convention, all SMPTE Engineering
Documents will be numbered as a two-letter prefix and a
number. Documents and references with the same root
number and year are functionally identical; for example ST
424-2006 and SMPTE 424M-2006 refer to the same
document.
LMH0344
PACKAGE
BODY SIZE (NOM)
WQFN (16)
4.00 mm × 4.00 mm
CS-BGA (25)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
BYPASS
Output
Driver
SDI
SDI
DC
Restoration/
Level Control
Equalizer
Filter
Energy
Detect
SDO
SDO
Energy
Detect
6
Automatic
Equalization
Control
Carrier
Detect/
Mute
CD
MUTE
MUTEREF
AEC+
AEC-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH0344
SNLS233O – APRIL 2007 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configurations and Functions .......................
Specifications.........................................................
1
1
1
2
3
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6
6
6
6
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
DC Electrical Characteristics ....................................
AC Electrical Characteristics.....................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
8.3 Dos and Don'ts........................................................ 13
9 Power Supply Recommendations...................... 13
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 15
11 Device and Documentation Support ................. 16
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision N (June 2015) to Revision O
•
Page
Fixed typo in Features bullet to change "Equalizes up 120m of Belden 1694A" to "Equalizes up to 120m of Belden
1694A" ................................................................................................................................................................................... 1
Changes from Revision M (January 2014) to Revision N
Page
•
Added, updated, or renamed the following sections: Device Information Table, Pin Configuration and Functions;
Specifications; Applications and Implementation; Detailed Description; Layout;Device and Documentation Support;
Mechanical, Packaging, and Ordering Information ............................................................................................................... 1
•
Changed "RGBα data patterns" to "4:4:4:4 10-bit video format" in Description section ........................................................ 1
Changes from Revision L (April 2013) to Revision M
Page
•
Added BYPASS Sentence...................................................................................................................................................... 3
•
Added BYPASS Sentence...................................................................................................................................................... 4
Changes from Revision K (April 2013) to Revision L
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 10
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5 Pin Configurations and Functions
VEE
1
SDI
2
VCC
CD
MUTE
VCC
RUM Package
16-Pin WQFN
Top View
16
15
14
13
12
VEE
11
SDO
LMH0344
VEE
4
9
VEE
5
6
7
8
MUTEREF
SDO
BYPASS
10
AEC-
3
AEC+
SDI
The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative
power supply voltage.
Pin Functions – RUM Package
PIN
I/O
DESCRIPTION
NAME
WQFN
AEC+
5
I/O, Analog
AEC loop filter external capacitor (1-µF) positive connection.
AEC-
6
I/O, Analog
AEC loop filter external capacitor (1-µF) negative connection.
BYPASS
7
I, LVCMOS
Bypasses equalization and DC restoration when high. No equalization occurs in this mode.
This pin does not have an internal pulldown. If the bypass function is not used, this pin requires
an external pulldown resistor to disable bypass.
CD
15
O, LVCMOS
Carrier detect. CD is high when no signal is present. CD has no function in BYPASS mode.
Output mute. To disable the mute function and enable the output, MUTE must be tied to GND
or a low level signal. To force the outputs to a muted state, tie to VCC. CD may be tied to this
pin to inhibit the output when no input signal is present. MUTE has no function in BYPASS
mode.
MUTE
14
I, LVCMOS
MUTEREF
8
I, Analog
NC
—
—
SDI
2
I, Analog
Serial data true input.
Serial data complement input.
Mute reference. Sets the threshold for CD and (with CD tied to MUTE) determines the
maximum cable to be equalized before muting. MUTEREF may be either unconnected or
connected to ground for maximum equalization.
No connect.
SDI
3
I,Analog
SDO
11
O, Analog
Serial data true output.
SDO
10
O, Analog
Serial data complement output.
Power
Positive power supply (+3.3V).
Ground
Negative power supply (ground). Note Figure 7 for layout example.
VCC
13
16
DAP
1
VEE
4
9
12
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NYA Package
25-Ball CS-BGA
Top View
1
2
3
4
5
VCC
CD
VCC
VCC
NC
A1
A2
A3
A4
A5
VEE
VCC
MUTE
VEE
NC
B1
B2
B3
B4
B5
SDI
NC
NC
NC
SDO
C1
C2
C3
C4
C5
SDI
VEE
BYPASS
NC
SDO
D1
D2
D3
D4
D5
NC
AEC+
AEC-
MUTEREF
VEE
E1
E2
E3
E4
E5
A
B
C
D
E
Pin Functions – NYA Package
PIN
I/O
DESCRIPTION
NAME
CS-BGA BALL
AEC+
E2
I/O, Analog
AEC loop filter external capacitor (1-µF) positive connection.
AEC-
E3
I/O, Analog
AEC loop filter external capacitor (1-µF) negative connection.
BYPASS
D3
I, LVCMOS
Bypasses equalization and DC restoration when high. No equalization occurs in this
mode. This pin does not have an internal pulldown. If the bypass function is not used,
this pin requires an external pulldown resistor to disable bypass.
CD
A2
O, LVCMOS
Carrier detect. CD is high when no signal is present. CD has no function in BYPASS
mode.
MUTE
B3
I, LVCMOS
Output mute. To disable the mute function and enable the output, MUTE must be tied
to GND or a low level signal. To force the outputs to a muted state, tie to VCC. CD may
be tied to this pin to inhibit the output when no input signal is present. MUTE has no
function in BYPASS mode.
MUTEREF
E4
I, Analog
Mute reference. Sets the threshold for CD and (with CD tied to MUTE) determines the
maximum cable to be equalized before muting. MUTEREF may be either unconnected
or connected to ground for maximum equalization.
A5
B5
C2
NC
C3
—
No connect.
C4
D4
E1
SDI
C1
I, Analog
Serial data true input.
SDI
D1
I,Analog
Serial data complement input.
SDO
C5
O, Analog
Serial data true output.
SDO
D5
O, Analog
Serial data complement output.
4
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Pin Functions – NYA Package (continued)
PIN
NAME
CS-BGA BALL
I/O
DESCRIPTION
A1
VCC
A3
A4
Power
Positive power supply (+3.3V).
Ground
Negative power supply (ground).
B2
B1
VEE
B4
D2
E5
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage
MAX
UNIT
4
V
−0.3 to VCC+0.3
V
Junction temperature
125
°C
Lead temperature
260
°C
150
°C
Input voltage (all inputs)
(soldering 4 seconds)
−65
Storage temperature
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
Electrostatic discharge
(1)
±8000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±2000
Machine model (MM)
(1)
(2)
UNIT
V
400
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±8000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
6.3 Recommended Operating Conditions
(VCC – VEE)
TA
Supply Voltage
MIN
TYP
MAX
UNIT
3.135
3.3
3.465
V
Input Coupling Capacitance
1
AEC Capacitor (Connected between AEC+ and AEC-)
1
−40
Operating Free Air Temperature
25
µF
µF
85
°C
6.4 Thermal Information
LMH0344
THERMAL METRIC
(1)
RUM (WQFN)
NYA (CS-BGA)
16 PINS
25 BALL
UNIT
RθJA
Junction-to-ambient thermal resistance
40
58.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
4.5
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 DC Electrical Characteristics
over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1) (2).
PARAMETER
VCMIN
Input Common-Mode Voltage
VSDI
Input Voltage Swing (SDI, SDI)
TEST CONDITIONS
(1)
(2)
(3)
(4)
6
Output Voltage Swing
TYP
MAX
UNIT
950
mVP−P
1.9
At LMH0344 input (3) (4)
VCMOUT Output Common-Mode Voltage
(SDO, SDO)
VSDO
MIN
720
800
V
VCC – VSDO/2
100-Ω load, differential
750
V
mVP-P
Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated
referenced to VEE = 0 Volts.
Typical values are stated for VCC = +3.3 V and TA = +25°C.
Specification is ensured by characterization.
This specification is for 1m cable only.
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DC Electrical Characteristics (continued)
over Supply Voltage and Operating Temperature ranges, unless otherwise specified(1)(2).
PARAMETER
TEST CONDITIONS
MIN
MUTER MUTEREF DC Voltage (floating)
TYP
MAX
UNIT
1.3
V
0.6
V
EF
MUTEREF Range
CD Output Voltage
Carrier not present
2.4
V
Carrier present
MUTE Input Voltage
Min to mute outputs
0.4
2.0
V
Max to force outputs active
ICC
Supply Current
V
85
0.8
V
100
mA
MAX
UNIT
6.6 AC Electrical Characteristics
over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1) (2)
PARAMETER
BRMIN
Minimum Input Data Rate
(SDI, SDI)
BRMax
Maximum Input Data Rate
(SDI, SDI)
TJRaw
Jitter for Various Cable
Lengths
TEST CONDITIONS
MIN
TYP
143
Mbps
2970
270 Mbps, Belden 1694A,
0 to 400 meters (3)
0.2
270 Mbps, Belden 1694A,
0 to 400 meters (4)
0.07
1.485 Gbps, Belden 1694A,
0 to 140 meters (3)
0.25
UI
1.485 Gbps, Belden 1694A,
0-140 meters (4)
0.08
2.97 Gbps, Belden 1694A,
0 to 120 meters (3)
0.3
2.97 Gbps, Belden 1694A,
0 to 120 meters (4)
Output Rise Time, Fall
Time (SDO, SDO)
tr,tf
TR_F_Del Mismatch in Rise/Fall Time
(SDO, SDO)
ta
20% to 80%
See
(5)
(5)
Mbps
0.18
(5)
60
130
ps
2
15
ps
1%
5%
tOS
Output Overshoot (SDO,
SDO)
See
ROUT
Output Resistance (SDO,
SDO)
single-ended
Input Return Loss (SDI,
SDI)
5 MHz
to 1.5 GHz (6)
15
dB
1.5 GHz
to 3.0 GHz (6)
10
dB
RLIN
RIN
Input Resistance (SDI, SDI) single-ended
CIN
Input Capacitance (SDI,
SDI)
(1)
(2)
(3)
(4)
(5)
(6)
Ω
50
single-ended
1.3
kΩ
1
pF
Typical values are stated for VCC = +3.3 V and TA = +25°C.
Due to SMPTE naming convention, all SMPTE Engineering Documents will be numbered as a two-letter prefix and a number.
Documents and references with the same root number and year are functionally identical; for example ST 424-2006 and SMPTE 424M2006 refer to the same document.
Based on characterization data over the full range of recommended operating conditions of the device. Jitter is measured in accordance
with RP 184, RP 192, and the applicable serial data transmission standard: ST 424, ST 292, or ST 259.
Measured with Pseudo Matrix Pathological test signal.
Specification is ensured by characterization.
Input return loss is dependent onboard design. The LMH0344 exceeds this specification on the SD344 evaluation board with a return
loss network consisting of an 8.2-nH inductor in parallel with a 0.5-pF capacitor in parallel with the 75Ω series resistor on the input.
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8
Amplitude: 125 mV/div
Amplitude: 125 mV/div
6.7 Typical Characteristics
Time: 56 ps/div
Time: 56 ps/div
Figure 1. Serial Data Output After Equalizing 120 m of
Belden 1694A 2.97-Gbps PRBS10
Figure 2. Serial Data Output After Equalizing 120 m of
Belden 1694A 2.97-Gbps Pseudo Matrix Pathological
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7 Detailed Description
7.1 Overview
The LMH0344 3-Gbps HD–SD SDI Adaptive Cable Equalizer is designed to equalize data transmitted over cable
or any other media with similar dispersive loss characteristics. The equalizer operates over a wide range of data
rates from 125 Mbps to 2.97 Gbps and supports ST 424, ST 292, ST 344, and ST 259.
7.2 Functional Block Diagram
BYPASS
Output
Driver
SDI
DC
Restoration/
Level Control
Equalizer
Filter
SDI
Energy
Detect
SDO
SDO
Energy
Detect
6
Automatic
Equalization
Control
Carrier
Detect/
Mute
CD
MUTE
MUTEREF
AEC+
AEC-
7.3 Feature Description
7.3.1 Block Description
The Equalizer Filter block is a multistage adaptive filter. If BYPASS is high, the equalizer filter is disabled.
The DC Restoration / Level Control block receives the differential signals from the equalizer filter block. This
block incorporates a self-biasing DC restoration circuit to fully DC restore the signals. If BYPASS is high, this
function is disabled.
The signals before and after the DC Restoration / Level Control block are used to generate the Automatic
Equalization Control (AEC) signal. This control signal sets the gain and bandwidth of the equalizer filter. The
loop response in the AEC block is controlled by an external 1-µF capacitor placed across the AEC+ and AEC–
pins.
The Carrier Detect / Mute block generates the carrier detect signal and controls the mute function of the output.
This block uses the CD and MUTE signals along with Mute Reference (MUTEREF).
The Output Driver produces SDO and SDO.
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Feature Description (continued)
7.3.2 Mute Reference (MuteREF)
The mute reference sets the threshold for CD and (with CD tied to MUTE) determines the amount of cable to
equalize before automatically muting the outputs. This is set by applying a voltage inversely proportional to the
length of cable to equalize. The applied voltage must be greater than the MUTEREF floating voltage (typically 1.3
V) to change the CD threshold. As the applied MUTEREF voltage is increased, the amount of cable that can be
equalized before carrier detect is deasserted and the outputs are muted is decreased. MUTEREF may be left
unconnected or connected to ground for maximum equalization before muting.
7.3.3 Carrier Detect (CD) and Mute
Carrier detect CD indicates if a valid signal is present at the LMH0344 input. If MUTEREF is used, the carrier
detect threshold will be altered accordingly. CD provides a high voltage when no signal is present at the
LMH0344 input. CD is low when a valid input signal is detected.
MUTE can be used to manually mute or enable SDO and SDO. Applying a high input to MUTE will mute the
LMH0344 outputs by forcing the output to a logic zero. Applying a low input will force the outputs to be active.
CD and MUTE may be tied together to automatically mute the output when no input signal is present.
7.3.4 Input Interfacing
The LMH0344 accepts either differential or single-ended input. The input must be AC-coupled. Transformer
coupling is not supported.
The LMH0344 correctly handles equalizer pathological signals for standard definition and high definition serial
digital video, as described in SMPTE RP 178 and RP 198, respectively.
7.3.5 Output Interfacing
The SDO and SDO outputs are internally loaded with 50 Ω. These outputs produce a 750-mVP-P differential
output, or a 375-mVP-P single-ended output.
7.4 Device Functional Modes
The LMH0344 features can be programmed using pin mode only.
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMH0344 is a single channel 3 Gbps HD – SD SDI Adaptive Cable Equalizer designed to equalize data
transmitted over cable or any media with similar dispersive loss characteristics. The equalizer operates over a
wide range of data rates from 125 Mbps to 2.97 Gbps and supports ST 424, ST 292, ST 344, and ST 259.
Additional features include separate carrier detect and output mute pins which may be tied together to mute the
output when no signal is present. A programmable mute reference is provided to mute the output at a selectable
level of signal degradation. The bypass pin allows the adaptive equalizer to be bypassed.
The LMH0344 accepts either a differential or single-ended input. The input must be AC-coupled. The LMH0344
correctly handles equalizer pathological signals for standard definition and high definition serial digital video, as
described in RP 178 and RP 198, respectively.
8.2 Typical Application
Coaxial Cable
LMH0344 3G SDI
Adaptive Cable
Equalizer
75:
1.0 PF
SDO
SDI
SDI
3.9 nH
LMH0341 3G SDI
Deserializer
RXIN0
RXIN0
TXOUT
Reclocked
Loopthrough
TXOUT
SDO
1.0 PF
MUTE
75:
BYPASS
CD
To FPGA
RXCLK
5-bit LVDS
+ clk
AEC-
AEC+
37.4:
RX[4:0]
MUTEREF
MUTE
MUTEREF
1.0 PF
BYPASS
CD
Figure 3. Typical 2.97-Gbps SDI De-Serializer Application
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Typical Application (continued)
8.2.1 Design Requirements
Table 1 lists the design parameters for the LMH0344.
Table 1. LMH0344 Design Parameters
DESIGN PARAMETER
REQUIREMENT
Input AC-coupling capacitors
Required. A common type of AC-coupling capacitor is
1 µF ±10% X7R ceramic capacitor (0402 or 0201
size). Capacitors may be implemented on the PCB or
in the connector.
Output AC-coupling capacitors
The user should check input common mode voltage of
the device attached to SDO . If AC-coupling Capacitor
is required, AC-coupling capacitor is expected to be
4.7 µF ±10%.
Input launch amplitude
Refer to DC Electrical Characteristics and AC
Electrical Characteristics.
8.2.2 Detailed Design Procedure
To
1.
2.
3.
4.
begin the design process, determine the following:
Maximum power draw for PCB regulator selection. Use maximum power consumption in the data sheet.
Closely compare schematic against typical connection diagram in the data sheet.
Plan out the PCB layout and component placement to minimize parasitic losses and reflections.
To optimize return loss result, return loss components may need to be adjusted.
8.2.3 Application Curves
Amplitude: 125 mV/div
Amplitude: 125 mV/div
Figure 4 and Figure 5 depict the differential output eye diagrams for SDO and SDO at 2.97 Gbps using B1694A
cable.
Time: 56 ps /div
Time: 56 ps /div
Figure 4. Serial Data Output After Equalizing 100m of
Belden 1694A 2.97-Gbps PRBS10
12
Figure 5. Serial Data Output After Equalizing 10m of
Belden 1694A 2.97-Gbps PRBS10
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8.3 Dos and Don'ts
Pay special attention to the PCB layout for the high speed signals. The SMPTE organization specifies the
requirements for the Serial Digital Interface to transport digital video at SD, HD, and 3 Gbps data rates over
coaxial cables. One of the requirements is meeting the required Return Loss. This requirement specifies how
closely the port resembles 75-Ω impedance across a specified frequency band. The SMPTE specifications also
defines the use of AC-coupling capacitors for transporting uncompressed serial data streams with heavy low
frequency content. This specification requires the use of a 1 µF, AC-coupling capacitors on the input of the
LMH0344 to avoid low frequency DC wander.
9 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
1. The power supply should be designed to provide the recommended operating conditions in terms of DC
voltage.
2. The maximum current draw for the LMH0344 is provided in the data sheet. This figure can be used to
calculate the maximum current the supply must provide.
3. The LMH0344 does not require any special power supply filtering, provided the recommended operating
conditions are met. Only standard supply decoupling is required.
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10 Layout
10.1 Layout Guidelines
For information on layout and soldering of the WQFN package, please refer to the following application note: AN1187 Leadless Leadframe Package (LLP) (SNOA401).
The ST 424, 292, and 259 standards have stringent requirements for the input return loss of receivers, which
essentially specify how closely the input must resemble a 75-Ω network. Any non-idealities in the network
between the BNC and the equalizer will degrade the input return loss. Take care to minimize impedance
discontinuities between the BNC and the equalizer to ensure that the characteristic impedance of this trace is 75
Ω.
Please consider the following PCB recommendations:
• Use surface-mount components, and use the smallest components available. In addition, use the smallest
size component pads.
• Select trace widths that minimize the impedance mismatch between the BNC and the equalizer.
• Select a board stack up that supports both 75-Ω single-ended traces and 100-Ω loosely-coupled differential
traces.
• Place return loss components closest to the equalizer input pins.
• Maintain symmetry on the complementary signals.
• Route 100-Ω traces uniformly (keep trace widths and trace spacing uniform along the trace).
• Avoid sharp bends in the signal path; use 45° or radial bends.
• Place bypass capacitors close to each power pin, and use the shortest path to connect equalizer power and
ground pins to the respective power or ground planes.
14
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LMH0344
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10.2 Layout Example
Figure 6 and Figure 7 demonstrates the LMH0344EVM PCB layout. Ground and supply relief under the return
loss passive components and pads reduces parasitic - improving return loss performance. Note in Figure 7 that
the five vias between the four solder paste squares do not have solder paste. This practice improves both
thermal performance and soldering during board assembly.
Figure 6. LMH0344EVM Top Etch Layout Example
Figure 7. LMH0344EVM Top Solder Paste Mask
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For additional information, see the following:
Application Note AN- 1187, Leadless Leadframe Package (LLP) (SNOA401).
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
LMH0344GR/NOPB
ACTIVE
csBGA
NYA
25
1000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
344G
Samples
LMH0344GRE/NOPB
ACTIVE
csBGA
NYA
25
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
344G
Samples
LMH0344SQ/NOPB
ACTIVE
WQFN
RUM
16
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
L0344
Samples
LMH0344SQE/NOPB
ACTIVE
WQFN
RUM
16
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
L0344
Samples
LMH0344SQX/NOPB
ACTIVE
WQFN
RUM
16
4500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
L0344
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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