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LMH0394
SNLS312M – AUGUST 2010 – REVISED JULY 2015
LMH0394 3G HD/SD SDI Low Power Extended Reach Adaptive Cable Equalizer
1 Features
3 Description
•
The LMH0394 3-Gbps HD/SD SDI Low Power
Extended Reach Adaptive Cable Equalizer is
designed to equalize data transmitted over cable (or
any
media
with
similar
dispersive
loss
characteristics). The equalizer operates over a wide
range of data rates from 125 Mbps to 2.97 Gbps and
supports ST 424, ST 292, ST 344, ST 259, and DVBASI standards (1).
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ST 424, ST 292, ST 344, ST 259, and DVB-ASI
Compliant (1)
Equalized Cable Lengths (Belden 1694A): 200
Meters at 2.97 Gbps, 220 Meters at 1.485 Gbps,
and 400 Meters at 270 Mbps
Ultra Low Power Consumption: 115 mW (Normal
Operation)
Power-Save Mode With Auto Sleep Control
(17-mW Typical Power Consumption in PowerSave Mode)
Designed for Crosstalk Immunity
Output De-Emphasis to Compensate for FR4
Board Trace Losses
Digital and Analog Programmable MUTEREF
Threshold
Optional SPI Register Access
Input Data Rates: 125 Mbps to 2.97 Gbps
Internally Terminated 100-Ω LVDS Outputs With
Programmable Output Common-Mode Voltage
and Swing
Programmable Launch Amplitude Optimization
Cable Length Indicator
Single 2.5-V Supply Operation
16-pin WQFN Package
Industrial Temperature Range: −40°C to +85°C
Footprint Compatible with the LMH0384 and also
the LMH0344, LMH0044, and LMH0074 in Pin
Mode
The LMH0394 provides extended cable reach with
improved immunity to crosstalk and ultra low power
consumption. The equalizer includes active sensing
circuitry that ensures robust performance and
enhanced immunity to variations in the input signal
launch amplitude. The output driver offers
programmable de-emphasis for up to 40” of FR4
trace losses. The LMH0394 includes power
management to further reduce power consumption
when no input signal is present.
The LMH0394 supports two modes of operation. In
pin mode, the LMH0394 operates with control pins to
set its operating state, and is footprint compatible with
the LMH0384, LMH0344, and legacy SDI equalizers.
In SPI mode, an optional SPI serial interface can be
used to access and configure multiple LMH0394
devices in a daisy-chain configuration. This allows
users to program the output common-mode voltage
and swing, output de-emphasis level, input launch
amplitude, and power management settings. Users
may also access a cable length indicator and all pin
mode features.
Device Information(1)
PART NUMBER
PACKAGE
2 Applications
•
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
ST 424, ST 292, ST 344, and ST 259 Serial
Digital Interfaces (1)
Broadcast Video Routers, Switchers, and
Distribution Amplifiers
WQFN (16)
BODY SIZE (NOM)
LMH0394
4.00 mm × 4.00 mm
Functional Block Diagram
BYPASS
Output
Driver
SDI
DC
Restoration/
Level Control
Equalizer
Filter
SDI
SDO
SDO
De-Emphasis
Control
CD
Energy
Detect
Carrier
Detect
6
MUTEREF
MUTEREF
(1)
1
Due to SMPTE naming convention, all SMPTE Engineering
Documents will be numbered as a two-letter prefix and a
number. Documents and references with the same root
number and year are functionally identical; for example ST
424-2006 and SMPTE 424M-2006 refer to the same
document.
Energy
Detect
MUTE
SPI Control
SPI_EN
Automatic
Equalization
Control
AEC+
AEC-
AUTO SLEEP
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH0394
SNLS312M – AUGUST 2010 – REVISED JULY 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5
5
6
6
6
7
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
DC Electrical Characteristics ....................................
AC Electrical Characteristics.....................................
SPI Interface AC Electrical Characteristics...............
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 13
7.5 Programming........................................................... 14
7.6 Register Maps ......................................................... 19
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application ................................................. 23
8.3 Do's and Dont's ....................................................... 25
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 28
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
Changes from Revision L (April 2013) to Revision M
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision K (April 2013) to Revision L
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 21
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SNLS312M – AUGUST 2010 – REVISED JULY 2015
5 Pin Configuration and Functions
VEE
1
SDI
2
CD
MUTE
16
15
14
VCC
VCC
RUM Package
16-Pin WQFN (Non-SPI)
Top View
13
12
AUTO SLEEP
11
SDO
LMH0394
SPI_EN
4
9
VEE
5
6
7
8
MUTEREF
SDO
BYPASS
10
AEC-
3
AEC+
SDI
DAP = VEE
Pin Functions – Pin Mode (non-SPI) / SPI_EN = GND / LMH0344 Compatible
PIN
NO.
NAME
I/O, TYPE
DESCRIPTION
1
VEE
Ground
2
SDI
I, Analog
Negative power supply (ground).
Serial data true input.
3
SDI
I, Analog
Serial data complement input.
4
SPI_EN
I, LVCMOS
SPI register access enable. This pin has an internal pulldown.
H = SPI register access mode.
L = Pin mode.
5
AEC+
I/O, Analog
AEC loop filter external capacitor (1-µF) positive connection (capacitor is optional).
6
AEC-
I/O, Analog
AEC loop filter external capacitor (1-µF) negative connection (capacitor is optional).
7
BYPASS
I, LVCMOS
Equalization bypass. This pin has an internal pull-down.
H = Equalization is bypassed (no equalization occurs).
L = Normal operation.
8
MUTEREF
I, Analog
9
VEE
I, LVCMOS
10
SDO
O, LVDS
Serial data complement output.
11
SDO
O, LVDS
Serial data true output.
12
AUTO SLEEP
I, LVCMOS
13
VCC
Power
Mute reference input. Sets the threshold for CD and (with CD tied to MUTE) determines the
maximum cable to be equalized before muting. MUTEREF may be either unconnected or
connected to ground for normal CD operation.
Connect this pin to ground or drive it logic low.
Auto Sleep. AUTO SLEEP has precedence over MUTE and BYPASS. This pin has an
internal pullup.
H = Device will power down when no input is detected.
L = Normal operation (device will not enter auto power down).
Positive power supply (+2.5 V).
14
MUTE
I, LVCMOS
Output mute. CD may be tied to this pin to inhibit the output when no input signal is present.
MUTE has precedence over BYPASS. This pin has an internal pull-down.
H = Outputs forced to a muted state.
L = Outputs enabled.
15
CD
O, LVCMOS
Carrier detect.
H = No input signal detected.
L = Input signal detected.
16
VCC
Power
Positive power supply (2.5 V).
DAP
VEE
Ground
Connect exposed DAP to negative power supply (ground). See Figure 22 for layout example.
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VEE
1
SDI
2
VCC
MOSI
SCK
VCC
RUM Package
16-Pin WQFN (SPI)
Top View
16
15
14
13
12
MISO
11
SDO
LMH0394
SPI_EN
4
9
SS
5
6
7
8
MUTEREF
SDO
CD
10
AEC-
3
AEC+
SDI
DAP = VEE
Pin Functions – SPI Mode / SPI_EN = VCC
PIN
NO.
NAME
I/O, TYPE
DESCRIPTION
1
VEE
Ground
2
SDI
I, Analog
Negative power supply (ground).
Serial data true input.
3
SDI
I, Analog
Serial data complement input.
4
SPI_EN
I, LVCMOS
SPI register access enable. This pin has an internal pull-down.
H = SPI register access mode.
L = Pin mode.
5
AEC+
I/O, Analog
AEC loop filter external capacitor (1 µF) positive connection (capacitor is optional).
6
AEC-
I/O, Analog
AEC loop filter external capacitor (1 µF) negative connection (capacitor is optional).
7
CD
O, LVCMOS
Carrier detect.
H = No input signal detected.
L = Input signal detected.
8
MUTEREF
I, Analog
9
SS (SPI)
I, LVCMOS
10
SDO
O, LVDS
Serial data complement output.
11
SDO
O, LVDS
Serial data true output.
12
MISO (SPI)
O, LVCMOS
Mute reference input. Sets the threshold for CD and (with CD tied to MUTE) determines the
maximum cable to be equalized before muting. MUTEREF may be either unconnected or
connected to ground for normal CD operation.
SPI slave select. This pin has an internal pullup.
SPI Master Input / Slave Output. LMH0394 control data transmit.
13
VCC
Power
14
SCK (SPI)
I, LVCMOS
SPI serial clock input.
15
MOSI (SPI)
I, LVCMOS
SPI Master Output / Slave Input. LMH0394 control data receive. This pin has an internal
pulldown.
16
VCC
Power
Positive power supply (2.5 V).
DAP
VEE
Ground
Connect exposed DAP to negative power supply (ground). See Figure 22 for layout example.
4
Positive power supply (2.5 V).
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage
Input voltage (all inputs)
–0.3
Junction temperature
Storage temperature, Tstg
(1)
–65
MAX
UNIT
3.1
V
VCC + 0.3
V
125
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±6000
V
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
Supply voltage (VCC – VEE)
MIN
NOM
MAX
2.375
2.5
2.625
Input coupling capacitance
UNIT
V
1
Operating free-air temperature (TA)
–40
µF
25
85
°C
6.4 Thermal Information
LMH0394
THERMAL METRIC
(1)
RUM (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
40
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 DC Electrical Characteristics
over supply voltage and operating temperature ranges, unless otherwise specified (1) (2).
MAX
UNIT
VIH
Input voltage high level
PARAMETER
Logic inputs
TEST CONDITIONS
1.7
VCC
V
VIL
Input voltage low level
Logic inputs
VEE
0.7
V
880
mVP−P
Input voltage swing
VCMIN
Input common-mode voltage
VSSP-P
Differential output voltage, P-P
500
700
900
mVP-P
VOD
Differential output voltage
250
350
450
mV
ΔVOD
Change in magnitude of VOD for
complementary output states
50
mV
VOS
Offset voltage
ΔVOS
Change in magnitude of VOS for
complementary output states
IOS
Output short circuit current
MUTEREF
MUTEREF DC voltage (floating)
MUTEREF
MUTERNG
MUTEREF range
MUTEREF
VOH
Output voltage high level
IOH = -2 mA (CD, MISO)
VOL
Output voltage low level
IOL = +2 mA (CD, MISO)
(1)
(2)
(3)
(4)
(5)
6
Supply current
(SDI)
720
TYP
VSDI
ICC
0m cable length
(3)
MIN
800
1.65
100-Ω load, default register settings,
Figure 1 (4) (SDO, SDO)
1.1
Normal operation
(5)
Power-save mode
1.2
V
1.35
V
50
mV
30
mA
1.3
V
0.8
V
2.0
V
0.2
V
45
65
mA
7
10
mA
Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated
referenced to VEE = 0 Volts.
Typical values are stated for VCC = 2.5 V and TA = 25°C.
The LMH0394 can be optimized for different launch amplitudes through the SPI.
The differential output voltage and offset voltage are adjustable through the SPI.
Typical ICC is measured with a 2.97 Gbps input signal.
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6.6 AC Electrical Characteristics
over supply voltage and operating temperature ranges, unless otherwise specified (1).
PARAMETER
TEST CONDITIONS
BRMIN
Minimum input data rate
SDI, SDI
BRMAX
Maximum input data rate
SDI, SDI
TJRAW
Jitter for various cable lengths
MIN
TYP
MAX
125
UNIT
Mbps
2970
Mbps
2.97 Gbps, Belden 1694A,
0-100 meters (2)
0.2
UI
2.97 Gbps, Belden 1694A,
100-140 meters (2)
0.3
UI
2.97 Gbps, Belden 1694A,
140-180 meters (2)
0.5
UI
2.97 Gbps, Belden 1694A,
180-200 meters
0.55
1.485 Gbps, Belden 1694A,
0-200 meters (2)
UI
0.2
1.485 Gbps, Belden 1694A,
200-220 meters
UI
0.3
270 Mbps, Belden 1694A,
0-400 meters (2)
UI
0.3
UI
130
ps
ps
Output rise time, fall time
SDO, SDO, 20% – 80%, and
100-Ω load Figure 1 (3)
ΔTR_F
Mismatch in rise / fall time
SDO, SDO
tOS
Output overshoot
RLIN
Input return loss
RIN
Input resistance
single-ended SDI or SDI
1.5
kΩ
CIN
Input capacitance
single-ended SDI or SDI
0.7
pF
tR, tF
(1)
(2)
(3)
(4)
SDO, SDO
90
(3)
2
15
(3)
1%
5%
5 MHz - 1.5 GHz (4) SDI or SDI
15
dB
1.5 GHz - 3.0 GHz (4) SDI or SDI
10
dB
Typical values are stated for VCC = 2.5 V and TA = 25°C.
Based on design and characterization data over the full range of recommended operating conditions of the device. Jitter is measured in
accordance with ST RP 184, ST RP 192, and the applicable serial data transmission standard: ST 424, ST 292, or ST 259.
Specification is ensured by characterization.
Input return loss is dependent on board design. The LMH0394 exceeds this specification on the SD394EVK evaluation board with a
return loss network consisting of a 5.6-nH inductor in parallel with a 75-Ω series resistor on the input.
6.7 SPI Interface AC Electrical Characteristics
over supply voltage and operating temperature ranges, unless otherwise specified (1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Recommended Input Timing Requirements
fSCK
SCK frequency
SCK pulse width high
tPH
20
See Figure 2 and Figure 3
SCK pulse width low
tPL
See Figure 2 Figure 3
MHz
40
% SCK
period
40
% SCK
period
4
ns
4
ns
14
ns
tSU
MOSI set-up time
tH
MOSI hold time
tSSSU
SS set-up time
tSSH
SS hold time
4
ns
tSSOF
SS OFF-time
1
SCK period
See Figure 2 and Figure 3
Switching Characteristics
tODZ
MISO driven-to-TRI-STATE time
20
ns
tOZD
MISO TRI-STATE-to-driven time
10
ns
tOD
MISO output delay time
15
ns
(1)
See Figure 3
Typical values are stated for VCC = 2.5 V and TA = 25°C.
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VODVOS
VOD+
80%
80%
+ VOD
VSSP-P
0V differential
20%
- VOD
20%
VSSP-P = (VOD+) – (VOD-)
tr
tf
Figure 1. LVDS Output Voltage, Offset, and Timing Parameters
SS
(host)
tSSSU
tPH
tPL
tSSH
SCK
(host)
tH
tSU
MOSI
(host)
0
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
tOZD
MISO
(device)
tSSOF
D1
D0
tODZ
Hi-Z
Hi-Z
'21¶7&$5(
Figure 2. SPI Write
SS
(host)
tSSSU
tSSH tSSOF
tSSH tSSOF tSSSU
tPL
tPH
SCK
(host)
tSU
MOSI
(host)
tH
1 A6 A5 A4 A3 A2 A1 A0
tOZD
MISO Hi-Z
(device)
³8x1´
³16x1´
tODZ
'21¶7&$5(
tOZD
Hi-Z
tOD
tODZ
1 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1
Hi-Z
Figure 3. SPI Read
8
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6.8 Typical Characteristics
Figure 4. Differential Serial Data Output After Equalizing 161
Meters of Belden 1694A at 2.97 Gbps, PRBS10 Pattern
Figure 5. Differential Serial Data Output After Equalizing 400
Meters of Belden 1694A at 270 Mbps, PRBS10 Pattern
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7 Detailed Description
7.1 Overview
The LMH0394 is a 3 Gbps HD/SD SDI low power extended reach adaptive cable equalizer. It is designed to
equalize data transmitted over cable or any media with similar dispersive loss characteristics. The equalizer
operates over a wide range of data rates from 125 Mbps to 2.97 Gbps and supports ST 424, ST 292, ST 344, ST
259, and DVB-ASI standards. The LMH0394 features design enhancements including longer cable equalization,
lower output jitter, configurable pin mode and SPI modes, a power-saving sleep mode, and programmable output
common-mode voltage and swing. The LMH0394 implements DC restoration to correctly handle pathological
data conditions.
The LMH0394 provides extended cable reach with improved immunity to crosstalk and ultra-low power
consumption. The equalizer includes active sensing circuitry that ensures robust performance and enhanced
immunity to variations in the input signal launch amplitude. The output driver offers programmable de-emphasis
for up to 40” of FR4 trace losses. The LMH0394 includes power management to further reduce power
consumption when no input signal is present.
7.2 Functional Block Diagram
The LMH0394 supports two modes of operation. In pin mode, the LMH0394 operates with control pins to set its
operating state and is footprint compatible with the LMH0384, LMH0344, and legacy SDI equalizers. In SPI
mode, an optional SPI serial interface can be used to access and configure multiple LMH0394 devices in a
daisy-chain configuration.
This allows users to program the output common-mode voltage and swing, output de-emphasis level, input
launch amplitude, and power management settings. Users may also access a cable length indicator and all pin
mode features.
BYPASS
Output
Driver
SDI
DC
Restoration/
Level Control
Equalizer
Filter
SDI
SDO
SDO
De-Emphasis
Control
CD
Energy
Detect
Carrier
Detect
Energy
Detect
SPI Control
SPI_EN
6
MUTEREF
MUTEREF
MUTE
Automatic
Equalization
Control
AEC+
AEC-
AUTO SLEEP
Figure 6. Functional Block Diagram (Pin Mode)
10
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7.3 Feature Description
7.3.1 Block Description
The Equalizer Filter block is a multi-stage adaptive filter. If Bypass is high, the equalizer filter is disabled.
The DC Restoration / Level Control block receives the differential signals from the equalizer filter block. This
block incorporates a self-biasing DC restoration circuit to fully DC restore the signals. If Bypass is high, this
function is disabled.
The signals before and after the DC Restoration / Level Control block are used to generate the Automatic
Equalization Control (AEC) signal. This control signal sets the gain and bandwidth of the equalizer filter.
The Carrier Detect block generates the carrier detect signal based on the SDI input and an adjustment from the
Mute Reference block.
The SPI Control block uses the MOSI, MISO, SCK, and SS signals in SPI mode to control the SPI registers.
SPI_EN selects between SPI mode and pin mode. In pin mode, SPI_EN is driven logic low.
The Output Driver produces SDO and SDO.
7.3.2 Mute Reference (MuteREF)
The mute reference sets the threshold for CD and (with CD tied to MUTE) determines the amount of cable to
equalize before automatically muting the outputs. This is set by applying a voltage inversely proportional to the
length of cable to equalize. The applied voltage must be greater than the MUTEREF floating voltage (typically 1.3
V) in order to change the CD threshold. As the applied MUTEREF voltage is increased, the amount of cable that
can be equalized before carrier detect is de-asserted and the outputs are muted is decreased. MUTEREF may be
left unconnected or connected to ground for normal CD operation. Optionally, the LMH0394 allows the mute
reference to be set digitally through SPI register 03h.
Figure 7 shows the minimum MUTEREF input voltage required to force carrier detect to inactive vs. Belden 1694A
cable length. The results shown are valid for Belden 1694A cable lengths of 0-200 m at 2.97 Gbps, 0-220 m at
1.485 Gbps, and 0-400 m at 270 Mbps.
2.2
MUTEREF(V)
2.0
1.8
1.6
1.4
1.2
0 50 100 150 200 250 300 350 400
BELDEN 1694A CABLE LENGTH (m)
Figure 7. MUTEREF vs. Belden 1694A Cable Length
7.3.3 Carrier Detect (CD) and Mute
Carrier detect CD indicates if a valid signal is present at the LMH0394 input. This signal is a logical OR operation
of the internal energy detector and MUTEREF setting (if used). The internal energy detector detects energy across
different data rates. If MUTEREF is used, the carrier detect threshold will be altered accordingly. CD provides a
high voltage when no signal is present at the LMH0394 input. CD is low when a valid input signal is detected.
MUTE can be used to manually mute or enable SDO and SDO. Applying a high input to MUTE will mute the
LMH0394 outputs by forcing the output to a logic 1. Applying a low input will force the outputs to be active.
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Feature Description (continued)
In pin mode, CD and MUTE may be tied together to automatically mute the output when no input signal is
present.
7.3.4 Input Interfacing
The LMH0394 accepts single-ended input. The input must be AC coupled. The Functional Block Diagram shows
the typical configuration for a single-ended input. The unused input must be properly terminated as shown in
Figure 8 or Figure 9.
The LMH0394 can be optimized for different launch amplitudes through the SPI (see Launch Amplitude
Optimization in the SPI Register Access section).
The LMH0394 correctly handles equalizer pathological signals for standard definition and high definition serial
digital video, as described in ST RP 178 and RP 198, respectively.
7.3.5 Output Interfacing
SDO and SDO together are internally terminated 100-Ω LVDS outputs. These outputs can be DC coupled to
most common differential receivers.
The default output common-mode voltage (VOS) is 1.2 V. The output common-mode voltage may be adjusted
through the SPI in 200 mV increments, from 0.8 V to 1.2 V (see Output Driver Adjustments and De-emphasis
Setting in the SPI Register Access section). When the output common mode is supply referenced, the commonmode voltage is about 1.35 V (for 700 mVP-P differential swing). This adjustable output common-mode voltage
offers flexibility for interfacing to many types of receivers.
The default differential output swing (VSSP-P) is 700 mVP-P. The differential output swing may be adjusted through
the SPI. Valid options are 400, 600, 700, or 800 mVP-P (see Output Driver Adjustments and De-emphasis Setting
in the SPI Register Access section).
The LMH0394 output must be DC coupled to the input of the receiving device where possible. 100-Ω differential
transmission lines must be used to connect between the LMH0394 outputs and the input of the receiving device.
The LMH0394 output must not be DC coupled to CML inputs. If there are strong pullup resistors (that is, 50 Ω) at
the receiving device, AC coupling must be used. The value of these AC-coupling capacitors must be large
enough (typically 4.7 µF) to accommodate for the SD pathological video pattern.
Figure 8 shows an example of a DC-coupled interface between the LMH0394 and LMH0346 SDI reclocker. The
differential transmission line must be terminated with a 100-Ω resistor at the receiving device as shown. The
resistor should be placed as close as possible to the LMH0346 input. If desired, this network may be terminated
with two 50-Ω resistors and a center-tap capacitor to ground in place of the single 100-Ω resistor.
Figure 9 shows an example of a DC-coupled interface between the LMH0394 and LMH0356 SDI reclocker. The
LMH0356 inputs have internal 50-Ω terminations (100-Ω differential) to terminate the transmission line, so no
additional components are required.
The LMH0394 output driver is equipped with programmable output de-emphasis to minimize inter-symbol
interference caused by the loss dispersion from driving signals across PCB traces (see Output Driver
Adjustments and De-emphasis Setting in the SPI Register Access section). De-emphasis works with all
combinations of output common-mode voltage and output voltage swing settings to support DC coupling to the
receiving device.
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Feature Description (continued)
Coaxial Cable
1.0 PF
75:
SDI
LMH0394
1.0 PF
5.6 nH
SDI
SDO
SDI
100: Differential T-Line
LMH0346
3G/HD/SD
SDI Reclocker
100:
SDI
SDO
75:
37.4:
Figure 8. DC Output Interface to LMH0346 Reclocker
Coaxial Cable
75:
1.0 PF
SDI
1.0 PF
5.6 nH
SDO
LMH0394
SDI
SDI0
LMH0356
3G/HD/SD
SDI Reclocker
100: Differential T-Line
SDO
SDI0
75:
37.4:
Figure 9. DC Output Interface to LMH0356 Reclocker
7.4 Device Functional Modes
The LMH0394 supports two modes of operation. In pin mode, the LMH0394 operates with control pins to set its
operating state and is footprint compatible with the LMH0384, LMH0344, and legacy SDI equalizers. In SPI
mode, an optional SPI serial interface can be used to access and configure multiple LMH0394 devices in a
daisy-chain configuration.
7.4.1 Auto Sleep
The auto sleep mode allows the LMH0394 to power down when no input signal is detected. If the AUTO SLEEP
pin is set high, the LMH0394 goes into a deep power-save mode when no signal is detected. The device powers
on again once an input signal is detected. The auto sleep functionality can be turned off by setting AUTO SLEEP
low or tying this pin to ground. An additional auto sleep setting available in SPI mode can be used to force the
equalizer to power down regardless of whether there is an input signal or not. Auto sleep has precedence over
mute and bypass modes.
In auto sleep mode, the time to power down the equalizer when the input signal is removed is less than 200 µs
and should not have any impact on the system timing requirements. The device will wake up automatically once
an input signal is detected, and the delay between signal detection and full functionality of the equalizer is
negligible (about 5 ms). The overall system will be limited only by the settling time constant of the equalizer
adaptation loop.
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7.5 Programming
7.5.1 SPI Register Access
Setting SPI_EN high enables the optional SPI register access mode. In SPI mode, the LMH0394 provides
register access to all of its features along with a cable length indicator, programmable output de-emphasis,
programmable output common-mode voltage and swing, digital MUTEREF, and launch amplitude optimization.
There are eight supported 8-bit registers in the device (see Table 1). The LMH0394 supports SPI daisy-chaining
among an unlimited number of LMH0394 devices. With SPI_EN set low, the device operates in pin mode and is
footprint compatible with the LMH0384, LMH0344, LMH0044, and LMH0074.
7.5.1.1 SPI Transaction Overview
Each SPI transaction to a single device is 16-bits long. The transaction is initiated by driving SS low, and
completed by returning SS high. The 16-bit MOSI payload consists of the read/write command (“1” for reads and
“0” for writes), the seven address bits of the device register (MSB first), and the eight data bits (MSB first). The
LMH0394 MOSI input data is latched on the rising edge of SCK, and the MISO output data is sourced on the
falling edge of SCK.
In order to facilitate daisy-chaining, the prior SPI command, address, and data are shifted out on the MISO
output as the current command, address, and data are shifted in on the MOSI input. For SPI writes, the MISO
output is typically ignored as “Don't Care” data. For SPI reads, the MISO output provides the requested read data
(after 16 periods of SCK). The MISO output is active when SS low, and tri-stated when SS is high.
7.5.1.2 SPI Write
The SPI write is shown in Figure 2. The SPI write is 16 bits long. The 16-bit MOSI payload consists of a “0” (write
command), seven address bits, and eight data bits. The SS signal is driven low, and the 16 bits are sent to the
LMH0394's MOSI input. After the SPI write, SS must return high. The prior SPI command, address, and data
shifted out on the MISO output during the SPI write is shown as “Don't Care” on the MISO output in Figure 2.
7.5.1.3 SPI Read
The SPI read is shown in Figure 3. The SPI read is 32 bits long, consisting of a 16-bit read transaction followed
by a 16-bit dummy read transaction to shift out the read data on the MISO output. The first 16-bit MOSI payload
consists of a “1” (read command), seven address bits, and eight “1”s which are ignored. The second 16-bit MOSI
payload consists of 16 “1”s which are ignored but necessary in order to shift out the requested read data on the
MISO output. The SS signal is driven low, and the first 16 bits are sent to the LMH0394's MOSI input. The prior
SPI command, address, and data are shifted out on the MISO output during the first 16-bit transaction, and are
typically ignored (this is shown as “Don't Care” on the MISO output in Figure 3. SS must return high and then is
driven low again before the second 16 bits (all “1”s) are sent to the LMH0394's MOSI input. Once again, the prior
SPI command, address, and data are shifted out on the MISO output, but this data now includes the requested
read data. The read data is available on the MISO output during the second 8 bits of the 16-bit dummy read
transaction, as shown by D7-D0 in Figure 3.
7.5.1.4 SPI Daisy-Chain Operation
The LMH0394 SPI controller supports daisy-chaining the serial data between an unlimited number of LMH0394
devices. Each LMH0394 device is directly connected to the SCK and SS pins on the host. However, only the first
LMH0394 device in the chain is connected to the host’s MOSI pin, and only the last device in the chain is
connected to the host’s MISO pin. The MISO pin of each intermediate LMH0394 device in the chain is connected
to the MOSI pin of the next LMH0394 device, creating a serial shift register.
This daisy-chain architecture is shown in Figure 10.
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Programming (continued)
MISO
Device 2
Device 3
Device N
LMH0394
LMH0394
LMH0394
LMH0394
MISO
MOSI
SS
MISO
SS
MOSI
SCK
MISO
SCK
MOSI
SS
MISO
SCK
MOSI
SCK
MOSI
Device 1
SS
Host
SCK
SS
Figure 10. SPI Daisy Chain System Architecture
In a daisy-chain configuration of N LMH0394 devices, the host conceptually sees a shift register of length 16xN.
Therefore the length of SPI transactions (as previously described) is 16xN bits, and SS must be asserted for
16xN clock cycles for each SPI transaction.
7.5.1.5 SPI Daisy-Chain Write
Figure 11 shows the SPI daisy-chain write for a daisy-chain of N devices. The SS signal is driven low and SCK is
toggled for 16xN clocks. The 16xN bit MOSI payload (sent to Device 1 in the daisy-chain) consists of the 16-bit
SPI write data for Device N (the last device in the chain), followed by the write data for Device –1, Device –2,
etc., ending with the write data for Device 1 (the first device in the chain). The 16-bit SPI write data for each
device consists of a “0” (write command), seven address bits, and eight data bits. After the SPI daisy-chain write,
SS must return high and then the write occurs for all devices in the daisy-chain.
SPI Write Data
0 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SS
(host)
SCK
(host)
16xN clocks
MOSI (host)
MOSI Device 1
Device N
Write Data
Device N-1
Write Data
Device N-2
Write Data
Device N-3
Write Data
Device 1
Write Data
MISO Device 1
MOSI Device 2
'21¶7&$5(
Device N
Write Data
Device N-1
Write Data
Device N-2
Write Data
Device 2
Write Data
MISO Device N-1
MOSI Device N
'21¶7&$5(
'21¶7&$5(
'21¶7&$5(
'21¶7&$5(
Device N
Write Data
Figure 11. SPI Daisy-Chain Write
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Programming (continued)
7.5.1.6 SPI Daisy-Chain Read
Figure 12 shows the SPI daisy-chain read for a daisy-chain of N devices. The SPI daisy-chain read is 32xN bits
long, consisting of 16xN bits for the read transaction followed by 16xN bits for the dummy read transaction (all
“1”s) to shift out the read data on the MISO output. The SS signal is driven low and SCK is toggled for 16xN
clocks. The first 16xN bit MOSI payload (sent to Device 1 in the daisy-chain) consists of the 16-bit SPI read data
for Device N (the last device in the chain), followed by the read data for Device –1, Device –2, etc., ending with
the read data for Device 1 (the first device in the chain). The 16-bit SPI read data for each device consists of a
“1” (read command), seven address bits, and eight “1”s (which are ignored). After the first 16xN bit transaction,
SS must return high (to latch the data) and then is driven low again before the second 16xN bit transaction of all
“1”s is sent to the MOSI input. The requested read data is shifted out on MISO starting with the data for Device N
and ending with the data for Device 1. After this transaction, SS must return high.
SPI Read Data
³8x1´
1 A6 A5 A4 A3 A2 A1 A0
SS
(host)
SCK
(host)
MOSI
(host)
MISO
(host)
16xN clocks
Device N
Read Data
Device N-1
Read Data
16xN clocks
Device 1
Read Data
'21¶7&$5(
³16x1´
³16x1´
³16x1´
Device N
Read Data
Device N-1
Read Data
Device 1
Read Data
SPI Read Data
1 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 12. SPI Daisy-Chain Read
7.5.1.7 SPI Daisy-Chain Read and Write Example
The following example further clarifies LMH0394 SPI daisy-chain operation. Assume a daisy-chain of three
LMH0394 devices (Device 1, Device 2, and Device 3), with Device 1 as the first device in the chain and Device 3
as the last device in the chain, as shown by the first three devices in Figure 10. Because there are three devices
in the daisy-chain, each SPI transaction is 48-bits long.
This example shows an SPI operation combining SPI reads and writes in order to accomplish the following three
tasks:
1. Write 0x22 to register 0x01 of Device 3 in order to set the output swing to 400 mVP-P.
2. Read the contents of register 0x00 of Device 2.
3. Write 0x10 to register 0x00 of Device 1 in order to force the sleep mode.
Figure 13 shows the two 48-bit SPI transactions required to complete these tasks (the bits are shifted in left to
right).
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Programming (continued)
48-bit SPI Transaction #1
(Device 2)
(Device 3)
R/W Addr
48-bit SPI Transaction #2
(Device 1)
(Device 3)
Data R/W Addr
Data R/W Addr
Data
R/W Addr
(Device 2)
(Device 1)
Data R/W Addr
Data R/W Addr
Data
MOSI
(host)
0
0x01
0x22
1
0x00
0xFF
0
0x00
0x10
1
0x7F
0xFF
1
0x7F
0xFF
1
0x7F
0xFF
MISO
(host)
X
XX
XX
X
XX
XX
X
XX
XX
0
0x01
0x22
1
0x00
0x88
0
0x00
0x10
Figure 13. SPI Daisy-Chain Read and Write Example
The following occurs at the end of the first transaction:
1. Write 0x22 to register 0x01 of Device 3.
2. Latch the data from register 0x00 of Device 2.
3. Write 0x10 to register 0x00 of Device 1.
In the second transaction, three dummy reads (each consisting of 16 “1”s) are shifted in, and the read data from
Device 2 (with value 0x88) appears on MISO in the 25th through 32nd clock cycles.
7.5.1.8 SPI Daisy-Chain Length Detection
A useful operation for the host may be to detect the length of the daisy-chain. This is a simple matter of shifting
in a series of dummy reads with a known data value (such as 0x5A). For an SPI daisy-chain of N LMH0394
devices, the known data value will appear on the host's MISO pin after N+1 writes. Assuming a daisy-chain of
three LMH0394 devices, the result of this operation is shown in Figure 14.
R/W Addr
MOSI
(host)
1
MISO
(host)
X
Data R/W Addr
Data R/W Addr
Data R/W Addr
Data
0x7F
0x5A
1
0x7F
0x5A
1
0x7F
0x5A
1
0x7F
0x5A
XX
XX
X
XX
XX
X
XX
XX
1
0x7F
0x5A
Figure 14. SPI Daisy-Chain Length Detection
7.5.1.9 Output Driver Adjustments and De-emphasis Setting
The output driver swing (amplitude), offset voltage (common-mode voltage), and de-emphasis level are
adjustable through SPI register 01h.
The output swing is adjustable through bits [7:6] of SPI register 01h. The default value for these register bits is
10b for a peak to peak differential output voltage of 700 mVP-P. The output swing can be set for 400 mVP-P,
600 mVP‑P, 700 mVP-P, or 800 mVP-P.
The offset voltage is adjustable through bits [5:4] of SPI register 01h. The default value for these register bits is
10b for an output offset of 1.2 V. The output common-mode voltage may be adjusted in 200 mV increments, from
0.8 V to 1.2 V. It can be set to “11b” for the maximum offset voltage. At this maximum offset voltage setting, the
outputs are referenced to the positive supply and the offset voltage is around 1.35 V.
The output de-emphasis is turned on or off by bit 3 of SPI register 01h, and the de-emphasis level is set by bits
[2:1] of SPI register 01h. The output de-emphasis level may be set for 0 dB (for driving up to 10” FR4), -3 dB (for
driving 10-20” FR4), -5 dB (for driving 20-30” FR4), or -7 dB (for driving 30-40” FR4).
7.5.1.10 Launch Amplitude Optimization
The LMH0394 can compensate for attenuation of the input signal prior to the equalizer. This compensation is
useful for applications with a passive splitter at the equalizer input or a non-ideal input termination network, and
is controlled by SPI register 02h.
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Programming (continued)
Bit 7 of SPI register 02h is used for the launch amplitude setting. At the default setting of “0b”, the LMH0394
operates normally and expects a launch amplitude of 800 mVP-P. Bit 7 may be set to “1b” to optimize the
LMH0394 for input signals with 6 dB of attenuation (400 mVP-P).
7.5.1.11 Cable Length Indicator (CLI)
The cable length indicator (CLI) provides an indication of the length of the cable attached to input. CLI is
accessible through bits [7:0] of SPI register 06h. The 8-bit setting ranges in decimal value from 0 to 247
(“00000000” to “11110111” binary), corresponding to 0 to 400 m of Belden 1694A cable. For 3G and HD input,
CLI is 1.25 m per step. For SD input, CLI is 1.25 m per step, less 20 m, from 0 to 191 decimal, and 3.5 m per
step from 192 to 247 decimal.
To calculate the Belden 1694A cable length (in meters) from the CLI decimal value for 3G or HD input:
(1)
To calculate the Belden 1694A cable length (in meters) from the CLI decimal value for SD input:
(2)
Figure 15 shows typical CLI values vs. Belden 1694A cable length. CLI is valid for Belden 1694A cable lengths of
0-200 m at 2.97 Gbps, 0-220 m at 1.485 Gbps, and 0-400 m at 270 Mbps. Note: Given the continuous adaptive
nature of the equalizer, the CLI values may vary constantly within several steps.
250
225
CLI (decimal value)
200
175
150
SD
125
100
75
50
3G/HD
25
0
0 50 100 150 200 250 300 350 400
BELDEN 1694A CABLE LENGTH (m)
Figure 15. CLI vs. Belden 1694A Cable Length
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7.6 Register Maps
Table 1. SPI Registers
Address
00h
R/W
R/W
Name
Bits
Field
Default
Description
7
Carrier Detect
Read only.
0: No carrier
detected.
1: Carrier detected.
6
Mute
0
Mute has
precedence over
Bypass.
0: Normal operation.
1: Outputs muted.
5
Bypass
0
0: Normal operation.
1: Equalizer
bypassed.
4:3
Sleep Mode
01
Sleep mode control.
Sleep has
precedence over
Mute and Bypass.
00: Disable sleep
mode (force
equalizer to stay
enabled).
01: Sleep mode
active when no input
signal detected.
10: Force equalizer
into sleep mode
(powered down)
regardless of
whether there is an
input signal or not.
11: Reserved.
2
Reserved
0
Reserved as 0.
Always write 0 to
this bit.
0
Reset registers and
state machine. (This
bit is self-clearing.)
0: Normal operation.
1: Reset registers
and state machine.
0
Reset state
machine. (This bit is
self-clearing.)
0: Normal operation.
1: Reset state
machine.
General Control
1
0
Master Reset
Acquisition Reset
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Register Maps (continued)
Table 1. SPI Registers (continued)
Address
R/W
Name
Bits
7:6
5:4
01h
R/W
20
R/W
Default
Output Swing
Offset Voltage
De-Emphasis
Description
10
Output driver swing
(VSSP-P).
00: VSSP-P = 400
mVP-P.
01: VSSP-P = 600
mVP-P.
10: VSSP-P = 700
mVP-P.
11: VSSP-P = 800
mVP-P.
10
Output driver offset
voltage (commonmode voltage).
00: VOS = 0.8 V.
01: VOS = 1.0 V.
10: VOS = 1.2 V.
11: VOS referenced
to positive supply.
0
Output driver deemphasis control.
0: De-emphasis
disabled.
1: De-emphasis
enabled.
Output Driver
3
02h
Field
2:1
De-Emphasis
Amplitude Level
01
Output driver deemphasis level.
00: 0 dB (no deemphasis).
01: -3 dB deemphasis.
10: -5 dB deemphasis.
11: -7 dB deemphasis.
0
Reserved
0
Reserved (read
only).
Launch amplitude
optimization setting.
0: Normal
optimization with no
external attenuation
(800 mVP-P launch
amplitude).
1: Optimized for 6
dB external
attenuation (400
mVP-P launch
amplitude).
7
Launch Amplitude
Control
0
6:0
Reserved
1101000
Launch Amplitude
Control
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Reserved as
1101000. Always
write 1101000 to
these bits.
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Register Maps (continued)
Table 1. SPI Registers (continued)
Address
03h
04h
05h
06h
07h
R/W
R/W
R
R
R
R
Name
Bits
Field
Default
7:6
Reserved
00
Reserved as 00.
Always write 00 to
these bits.
5
MUTEREF Mode
0
0: Use MUTEREF
pin.
1: Use digital
MUTEREF.
MUTEREF
Device ID
Rate Indicator
Cable Length
Indicator
Digital MUTEREF
(10m per step).
00000: Mute when
cable (EQ boost) ≥
10 m.
......
01111: Mute when
cable (EQ boost) ≥
160 m.
......
11111: Never mute.
4:0
Digital MUTEREF
Setting
11111
7:6
Reserved
00
Reserved.
00: LMH0384
device.
01: LMH0394
device.
10: LMH0395
device.
11: Reserved.
5:4
EQ ID
01
3:0
Die Revision
0011
7:6
Reserved
00
5
Rate Indicator
4:0
Reserved
Die revision.
Reserved.
0: SD.
1: 3G/HD.
11000
Reserved.
Cable Length
Indicator
Cable Length
Indicator (CLI), with
10% accuracy.
00000000: Short
cable.
......
11110111:
Maximum cable.
11111000:
Reserved.
......
11111111:
Reserved.
7:2
Launch Amplitude
Indication
Indication of launch
amplitude: 1% or
0.08 dB per step
with 5% accuracy.
000000: Nominal 32%.
......
011111: Nominal 1%.
100000: Nominal.
100001: Nominal
+1%.
......
111111: Nominal
+31%.
1:0
Reserved
7:0
Launch Amplitude
Indication
Description
Reserved.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers must
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMH0394 3-Gbps HD/SD SDI Low Power Extended Reach Adaptive Cable Equalizer is designed to
equalize data transmitted over cable (or any media with similar dispersive loss characteristics). The equalizer
operates over a wide range of data rates from 125 Mbps to 2.97 Gbps and supports ST 424, ST 292, ST 344, ST
259, and DVB-ASI standards. Additional features include separate carrier detect and output mute pins which may
be tied together to mute the output when no signal is present. A programmable mute reference is provided to
mute the output at a selectable level of signal degradation. The bypass pin allows the adaptive equalizer to be
bypassed. The LMH0394 accepts single-ended input. The input must be AC coupled. The LMH0394 correctly
handles equalizer pathological signals for standard definition and high definition serial digital video, as described
in ST RP 178 and RP 198, respectively.
8.1.1 Interfacing to 3.3-V SPI
The LMH0394 may be controlled through optional SPI register access. The LMH0394 SPI pins support 2.5-V
LVCMOS logic levels and are compliant with JEDEC JESD8-5 (see DC Electrical Characteristics). Care must be
taken when interfacing the SPI pins to other voltage levels.
The 2.5-V LMH0394 SPI pins may be interfaced to a 3.3-V compliant SPI host by using a voltage divider or level
translator. One implementation is a simple resistive voltage divider as shown in Figure 16.
MOSI
3.16 k:
MISO
3.3V
SCK
Compliant
SPI Host
3.16 k:
9.76 k:
SS
LMH0394
9.76 k:
3.16 k:
9.76 k:
Figure 16. 3.3-V SPI Interfacing
8.1.2 Crosstalk Immunity
Single-ended SDI signals are susceptible to crosstalk and good design practices must be employed to minimize
its effects. Most crosstalk originates through capacitive coupling from adjacent signals routed closely together
through traces and connectors. To reduce capacitive coupling, SDI signals must be appropriately spaced apart or
insulated from one another. This can be accomplished by physically isolating signal traces in the layout and by
providing additional ground pins between signal traces in connectors as necessary. These techniques help to
reduce crosstalk but do not eliminate it.
The LMH0394 was designed specifically with crosstalk in mind and incorporates advanced circuit design
techniques that help to isolate and minimize the effects of cross-coupling in high-density system designs. The
LMH0394’s enhanced design results in minimal degradation in cable reach in the presence of crosstalk and
overall superior immunity against cross-coupling from neighboring channels.
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8.2 Typical Application
Figure 17 shows the application circuit for the LMH0394 in SPI mode. (Note: The application circuit shows an
external capacitor connected between the AEC+ and AEC- pins as commonly configured in legacy equalizers.
This capacitor is optional and not necessary for the LMH0394; the AEC+ and AEC- pins may be left unconnected
with no change in performance.)
(SPI) MISO
(SPI) SCK
(SPI) MOSI
VCC
VCC
0.1 PF
VCC
75:
13
VCC
14
SCK
15
SDI
SDO
SPI_EN
5
37.4:
4
MUTEREF
1.0 PF
AEC+
5.6 nH
LMH0394
SS
12
11
10
Differential
Output
9
DAP
8
3
SDO
SDI
CD
2
7
1.0 PF
MISO
6
75:
VEE
AEC-
1
Coaxial Cable
MOSI
VCC
16
0.1 PF
1.0 PF
CD
MUTEREF
(SPI) SS
Figure 17. Application Circuit (SPI Mode)
8.2.1 Design Requirements
Table 2 lists the design parameters for the LMH0394.
Table 2. LMH0394 Design Parameters
DESIGN PARAMETER
REQUIREMENT
Input AC coupling capacitors
Required. A common type of AC
coupling capacitor is 1-µF ± 10%
X7R ceramic capacitor (0402 or
0201 size). Capacitors may be
implemented on the PCB or in the
connector.
Distance from Device to BNC
Keep this distance as short as
possible.
High-Speed SDI, and SDI trace
impedance
Design single-ended trace
impedance with 75 Ω ± 5%
High-Speed SDO, and SDO
trace impedance
Design differential trace impedance
with 100 Ω ± 5%
DC Power Supply Coupling
Capacitors
To minimize power supply noise, use
0.01-µF capacitors as close to the
device VDD pins as possible
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8.2.2 Detailed Design Procedure
To
1.
2.
3.
4.
begin the design process, determine the following:
Maximum power draw for PCB regulator selection: Use maximum current consumption in the data sheet.
Closely compare schematic against typical connection diagram in the data sheet.
Plan out the PCB layout and component placement to minimize parasitic.
Consult the BNC vendor for optimum BNC landing pattern
8.2.3 Application Curves
Figure 18. Differential Serial Data Output After Equalizing
200 Meters of Belden 1694A 1.485 Gbps, PRBS10
Figure 19. Differential Serial Data Output After 40 Inches
FR4 With 0 dB De-Emphasis at 2.97 Gbps, PRBS10
Figure 20. Differential Serial Data Output After 40 Inches FR4 With 7 dB De-Emphasis at 2.97 Gbps, PRBS10
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8.3 Do's and Dont's
Pay special attention to the PCB layout for the high-speed signals. SMPTE specifies the requirements for the
Serial Digital Interface to transport digital video at SD, HD, and 3 Gbps data rates over coaxial cables. One of the
requirements is meeting the required Return Loss. This requirement specifies how closely the port resembles 75Ω impedance across a specified frequency band. The SMPTE specifications also defines the use of AC coupling
capacitors for transporting uncompressed serial data streams with heavy low frequency content. This
specification requires the use of a 1-µF AC coupling capacitor on the input of the LMH0394 to avoid low
frequency bandwidth limitation.
9 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
1. The power supply must be designed to provide the recommended operating conditions in terms of DC
voltage and maximum current consumption.
2. The maximum current draw for the LMH0394 is provided in the data sheet. This number can be used to
calculate the maximum current the supply must provide.
3. The LMH0394 does not require any special power supply filtering, provided the recommended operating
conditions are met. Use 0.01-µF capacitors as close to the device VDD pins as possible.
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10 Layout
10.1 Layout Guidelines
For information on layout and soldering of the WQFN package, please refer to the following application note: AN1187 Leadless Leadframe Package (LLP) (SNOA401).
The ST 424, 292, and 259 standards have stringent requirements for the input return loss of receivers, which
essentially specify how closely the input must resemble a 75-Ω network. Any non-idealities in the network
between the BNC and the equalizer will degrade the input return loss. Care must be taken to minimize
impedance discontinuities between the BNC and the equalizer to ensure that the characteristic impedance of this
trace is 75 Ω. Please consider the following PCB recommendations:
• Use surface mount components, and use the smallest components available. In addition, use the smallest
size component pads.
• Select trace widths that minimize the impedance mismatch between the BNC and the equalizer.
• Select a board stack-up that supports both 75-Ω single-ended traces and 100-Ω loosely-coupled differential
traces.
• Place return loss components closest to the equalizer input pins.
• Maintain symmetry on the complementary signals.
• Route 100-Ω traces uniformly (keep trace widths and trace spacing uniform along the trace).
• Avoid sharp bends in the signal path; use 45° or radial bends.
• Place bypass capacitors close to each power pin, and use the shortest path to connect equalizer power and
ground pins to the respective power or ground planes.
10.2 Layout Example
Figure 22 and Figure 21 demonstrate the LMH0394EVM PCB layout. Ground and supply relief under the return
loss passive components and pads reduces parasitic - improving return loss performance. The solder mask for
the DAP is divided into four quadrants. Five via are placed such that they are in the boundary of the 4 quadrants.
This is done to ensure that the via are not covered by solder mask for improving solder quality. This practice
improves both thermal performance and soldering during board assembly.
Ground and VCC relief under BNC landing pad
and return loss passive components
to achieve good return loss
Figure 21. LMH0394EVM Top Etch Layout
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Layout Example (continued)
5 Vias in between 4 quadrant
Of top solder paste
Figure 22. LMH0394EVM Top Solder Paste Mask
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
AN-1187 Leadless Leadframe Package (LLP), SNOA401.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMH0394SQ/NOPB
ACTIVE
WQFN
RUM
16
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
L0394
LMH0394SQE/NOPB
ACTIVE
WQFN
RUM
16
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
L0394
LMH0394SQX/NOPB
ACTIVE
WQFN
RUM
16
4500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
L0394
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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