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LMH2832
SBOS709A – JULY 2016 – REVISED JULY 2016
LMH2832 Fully Differential, Dual, 1.1-GHz, Digital Variable-Gain Amplifier
1 Features
3 Description
•
•
•
•
•
•
•
The LMH2832 is a high-linearity, dual-channel, digital
variable-gain amplifier (DVGA) for high-speed signal
chain and data-acquisition systems. The LMH2832 is
optimized to provide high bandwidth, low distortion,
and low noise, thus making the device ideally suited
as a dual, 14-bit, analog-to-digital converter (ADC)
driver. The device consists of one fixed-gain block
and one variable attenuator consisting of a total gain
of 30 dB with a maximum attenuation of 39 dB. The
gain range is from 30 dB to –9 dB in 1-dB gain steps
with a gain accuracy of ±0.2 dB. The input impedance
can be easily matched to 50-Ω or 75-Ω systems using
a 1:3-Ω or 1:2-Ω ratio balun, respectively. The
LMH2832 is designed to drive general-purpose ADCs
and also meets the requirements for both data over
cable service interface specification (DOCSIS) 3.0 32
quadrature amplitude modulation (QAM) carriers and
DOCSIS 3.1 wideband orthogonal frequency-division
multiplexing (OFDM) systems. With excellent NF
(6.5 dB) and linearity, the LMH2832 is designed to
perform to within DOCSIS specifications. The
quiescent current in the power-down state is less
than 5 mA per channel with the typical current
consumption during operation at 105 mA per channel.
1
•
•
•
•
•
Dual-Channel, Individual SPI™-Controlled DVGA
Single 5-V Supply
–3-dB Bandwidth: 1.1 GHz (Max Gain)
Flat Bandwidth Response: 300 MHz
Channel-to-Channel Gain Matching: ±0.05 dB
Channel-to-Channel Phase Matching: ±0.1°
Gain:
– 30 dB to –9 dB
– 1-dB Steps ±0.2 dB
Output Third-Order Intercept Point (OIP3):
– 43 dBm at 300 MHz
– 51 dBm at 200 MHz
Noise Figure (NF):
– 6.5 dB (Max Gain) at 300 MHz, ZIN = 150 Ω
Adjustable Power Consumption:
– 90 mA to 108 mA per Channel
Power-Saving, Power-Down Feature:
– IQ < 4.5 mA per Channel
– Power-Down Pin and SPI Programmability
Input Return Loss at 300 MHz:
– 17 dB (RS = 150 Ω)
Device Information(1)
PART NUMBER
LMH2832
2 Applications
•
•
•
•
•
DOCSIS 3.1 CMTS Upstream Direct Sampling
Receivers
CATV Modem Signal Scaling
Programmable Gain IF Amplifiers
Generic RF, IF Gain Stages
ADC Drivers
PACKAGE
VQFN (40)
BODY SIZE (NOM)
6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Output Third-Order Intercept Point (OIP3) Performance
60
Channel A
Channel B
55
OIP3 (dBm)
50
45
40
35
30
25
0
50 100 150 200 250 300 350 400 450 500 550 600
Frequency (MHz)
D005
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH2832
SBOS709A – JULY 2016 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
5
6
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements: SPI ........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 16
8.1
8.2
8.3
8.4
8.5
8.6
Setup Diagrams ......................................................
ATE Testing and DC Measurements ......................
Frequency Response ..............................................
Distortion .................................................................
Noise Figure............................................................
Pulse Response, Slew Rate, and Overdrive
Recovery ..................................................................
8.7 Power-Down............................................................
8.8 Crosstalk, Gain Matching, and Phase Matching.....
8.9 Output Measurement Reference Points..................
9
16
17
17
17
17
18
18
18
18
Detailed Description ............................................ 19
9.1
9.2
9.3
9.4
9.5
9.6
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
19
19
19
21
21
24
10 Application and Implementation........................ 29
10.1 Application Information.......................................... 29
10.2 Typical Applications .............................................. 32
10.3 Do's and Don'ts ..................................................... 35
11 Power Supply Recommendations ..................... 35
11.1 Split Supplies ........................................................ 35
11.2 Supply Decoupling ................................................ 35
12 Layout................................................................... 36
12.1 Layout Guidelines ................................................. 36
12.2 Layout Example .................................................... 36
13 Device and Documentation Support ................. 37
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Device Support ....................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
37
38
38
14 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2016) to Revision A
•
2
Page
Released to production........................................................................................................................................................... 1
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SBOS709A – JULY 2016 – REVISED JULY 2016
5 Device Comparison Table
Table 1. DVGA Device Comparison
DEVICE
MAX GAIN, BW
DISTORTION
NOISE FIGURE
LMH6401
26 dB, 4.5 GHz
43-dBm OIP3 at 200 MHz, –80-dBc HD3 at 200 MHz
7.7 dB
LHM6517
22 dB, 1.2 GHz
43-dBm OIP3 at 200 MHz, –74-dBc HD3 at 200 MHz
5.5 dB
LMH6521
26 dB, 1.2 GHz
49-dBm OIP3 at 200 MHz, –84-dBc HD3 at 200 MHz
7.3 dB
LMH6881
26 dB, 2.4 GHz
42-dBm OIP3 at 200 MHz, –76-dBc HD3 at 200 MHz
9.7 dB
6 Pin Configuration and Functions
INPA
GND
VCC
VCC
PDA
VCC
VCC
VCC
GND
OUTPA
40
39
38
37
36
35
34
33
32
31
RHA Package
40-Pin VQFN
Top View
INMA
1
30
OUTMA
GND
2
29
GND
VCC
3
28
VCC
CS
4
27
VCC
SCLK,Thermal_pad
5
26
VCC
SDI
6
25
VCC
SDO
7
24
VCC
VCC
8
23
VCC
GND
9
22
GND
INMB
10
21
OUTMB
Thermal
11
12
13
14
15
16
17
18
19
20
INPB
GND
VCC
VCC
PDB
VCC
VCC
VCC
GND
OUTPB
Pad
Not to scale
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SBOS709A – JULY 2016 – REVISED JULY 2016
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Pin Functions
PIN
NAME
NO.
CS
I/O
DESCRIPTION
4
I
Serial interface enable, active low
2, 9, 12, 19, 22, 29, 32, 39
I
Analog ground
INMA
1
I
Negative differential input, channel A
INMB
10
I
Negative differential input, channel B
INPA
40
I
Positive differential input, channel A
INPB
11
I
Positive differential input, channel B
OUTMA
30
O
Negative differential output, channel A
OUTMB
21
O
Negative differential output, channel B
OUTPA
31
O
Positive differential output, channel A
OUTPB
20
O
Positive differential output, channel B
PDB
15
I
Power-down control, channel B (logic high = power-down)
PDA
36
I
Power-down control, channel A (logic high = power-down)
SCLK
5
I
Serial interface clock input
SDI
6
I
Serial interface data input
SDO
7
O
Serial interface data output
VCC
3, 8, 13, 14, 16, 17, 18, 23, 24, 25,
26, 27, 28, 33, 34, 35, 37, 38
I
Analog voltage supply
—
Connected to ground
GND
Thermal pad
4
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SBOS709A – JULY 2016 – REVISED JULY 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Power supply
Input applied to analog inputs
INPA, INMA, INPB, INMB
MIN
MAX
UNIT
–0.5
5.5
V
–0.5
5.5
V
Voltage applied to input pins
–0.5
5.5
V
Digital input/output voltage range
–0.3
2
V
125
°C
125
°C
Operating junction temperature, TJ
Storage temperature, Tstg
(1)
–40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VS
MIN
NOM
MAX
UNIT
Power-supply voltage
4.75
5
5.25
V
Specified operating temperature range
–40
85
°C
7.4 Thermal Information
LMH2832
THERMAL METRIC (1)
RHA (VQFN)
UNIT
40 PINS
RθJA
Junction-to-ambient thermal resistance
29.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
20.4
°C/W
RθJB
Junction-to-board thermal resistance
6.6
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
6.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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7.5 Electrical Characteristics
at TA = 25°C, VS+ = 5 V, Ri = 75 Ω, RL = 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to
300 MHz, VO converted to single-ended (SE) measurement with a transformer, and default current setting (unless otherwise
noted); upon power-up, gain is set to mid-range
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
AC PERFORMANCE
LSBW
Large-signal,
–3-dB bandwidth
BW
Bandwidth for 0.1-dB flatness
HD2
HD3
IMD3
OIP3
P1dB
NF
Second-order harmonic
distortion
Third-order harmonic
distortion
Third-order intermodulation
distortion
Output third-order intercept
point
1-dB compression point
G = 30 dB, VO = 2 VPP
1140
G = 0 dB, VO = 2 VPP
2350
MHz
300
MHz
C
C
C
f = 100 MHz, VO = 2 VPP
–88
f = 200 MHz, VO = 2 VPP
–76
f = 300 MHz, VO = 2 VPP
–63
f = 450 MHz, VO = 2 VPP
–58
C
f = 100 MHz, VO = 2 VPP
–94
C
f = 200 MHz, VO = 2 VPP
–90
f = 300 MHz, VO = 2 VPP
–81
f = 450 MHz, VO = 2 VPP
–75
f = 100 MHz, tone spacing = 2 MHz,
POUT (2) = 0 dBm per tone
C
dBc
dBc
C
C
C
C
C
–106
C
dBc
f = 200 MHz, tone spacing = 2 MHz
–102
f = 300 MHz, tone spacing = 2 MHz
–86
C
f = 100 MHz, tone spacing = 2 MHz,
POUT = 0 dBm per tone
53
C
f = 200 MHz, tone spacing = 2 MHz,
POUT = 0 dBm per tone
51
f = 300 MHz, tone spacing = 2 MHz,
POUT = 0 dBm per tone
43
f = 100 MHz, RL = 150 Ω
16
f = 200 MHz, RL = 150 Ω
16
f = 300 MHz, RL = 150 Ω
16.5
Noise figure
Ri = 150 Ω, f = 300 MHz, max gain
Output-referred voltage noise
f = 300 MHz, max gain
S11
Input return loss
f = 300 MHz
S22
Reverse Isolation
Including input transformer, f < 300 MHz
dBm
C
C
C
C
dBm
C
C
6.5
dB
C
47.7
nV/√Hz
C
17
dB
C
53
dB
C
dB
C
f = 300 MHz, channel A to B
–77
f = 300 MHz, channel B to A
–81
Channel-to-channel phase
matching
f = 200 MHz
±0.1
°
C
Channel-to-channel gain
matching
f = 200 MHz
±0.05
dB
C
A
Channel-to-channel crosstalk
GAIN PARAMETERS
Maximum voltage gain
f = dc, gain code = 00h
29.5
30
30.5
dB
Minimum voltage gain
f = dc, gain code = 27h
–9.5
–9
–8.5
dB
A
dB
C
Gain range
EG
39
Gain step size
Between any two adjacent gain settings
0.75
1
1.25
dB
A
Gain error
For any gain value
–0.5
0
0.5
dB
A
Cumulative gain error
Referenced to max gain
1
dB
A
ns
C
Gain step transition time
(1)
(2)
6
–1
6
Test levels: (A) 100% tested at 25°C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
POUT is the signal tone power at the output of the device.
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Electrical Characteristics (continued)
at TA = 25°C, VS+ = 5 V, Ri = 75 Ω, RL = 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to
300 MHz, VO converted to single-ended (SE) measurement with a transformer, and default current setting (unless otherwise
noted); upon power-up, gain is set to mid-range
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
135
150
165
UNIT
TEST
LEVEL (1)
ANALOG INPUT CHARACTERISTICS
zin
Input resistance
f = dc, differential
Cin
Input capacitance
Differential
Single-ended input resistance
f = dc
0.6
67.5
Single-ended input
capacitance
75
82.5
1.2
–0.2
0.2
Ω
A
pF
C
Ω
A
pF
C
VICM
Input common-mode voltage
Internally biased to mid-supply
V
A
VIL
Low-level input voltage range
Differential gain shift < 1 dB
(VS–) + 1.5
V
C
VIH
High-level input voltage range
Differential gain shift < 1 dB
(VS+) – 1.5
V
C
20
Ω
C
V
A
V
A
ANALOG OUTPUT CHARACTERISTICS
zo
Output resistance
Differential
VOL
Low-level output voltage
range
VS = 5 V, GND = 0 V
VOH
High-level output voltage
range
VS = 5 V, GND = 0 V
VOM
Maximum output voltage
swing
CMRR
Common-mode rejection ratio
TA = 25°C
1.15
3.75
3.85
5
5.4
TA = –40°C to +85°C
5.4
1.25
6.4
56
V
A
B
dB
C
V
A
POWER SUPPLY
VS
Supply voltage
Default current, default bias setting
IQ
±PSRR
4.75
5.0
5.25
102
105
108
Quiescent current per channel Min current, lowest power setting
90
Max current, highest bias setting
108
Power-supply rejection ratio (3) Gain = 30 dB
A
mA
C
C
–48
dB
C
POWER-DOWN (4)
Power-down quiescent current TA = 25°C
(per channel)
TA = –40°C to +85°C
Power-down bias current
2.5
6
6.5
–2
mA
A
B
–1
µA
A
55
ns
C
Turn-on time delay
Time to VO = 90% of final value,
gain = 0 dB, VI = 2 V
Turn-off time delay
Time to VO = 10% of original value,
gain = 0 dB, VI = 2 V
110
ns
C
Forward isolation in PD mode
f = 300 MHz
–67
dB
C
DIGITAL INPUTS/OUTPUTS
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
VOL
Low-level output voltage
(3)
(4)
1.4
2
V
A
–0.3
0.8
V
A
IOH = –100 µA
1.65
IOH = –2 mA
1.55
V
IOL = 100 µA
0.1
IOL = 2 mA
0.2
V
A
A
A
A
PSRR is defined with respect to a differential output.
The device power-down function can be controlled by the PDx pins or by the power-down register accessible from the SPI interface.
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7.6 Timing Requirements: SPI
MIN
TYP
MAX
UNIT
0
25
50
MHz
fS_C
SCLK frequency (1)
tPH
SCLK pulse duration, high
10
ns
tPL
SCLK pulse duration, low
10
ns
tSU
SDI setup
3
ns
tH
SDO hold
3
ns
tIZ
SDO tri-state
3
ns
(2)
tODZ
SDO driven to tri-state
0
10
20
ns
tOZD
SDO tri-state to driven
0
2
5
ns
tOD
SDO output delay (2)
0
10
12
ns
tCSS
CS setup
(3)
3
5
ns
tCSH
CS hold
3
ns
tIAG
Inter-access gap
20
ns
(1)
(2)
(3)
8
Tested on the automated test equipment (ATE) only up to 25 MHz.
Referenced to the negative edge of SCLK.
Referenced to the positive edge of SCLK.
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7.7 Typical Characteristics
Voltage Gain (dB)
at TA = 25°C, VS+ = 5 V, Ri = 75 Ω, RL = 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to
300 MHz, VO converted to single-ended (SE) measurement with transformer, and default current setting (unless otherwise
noted); upon power-up, gain is set to mid-range
32
31
28
30.8
24
30.6
20
30.4
16
30.2
Gain (dB)
12
8
4
f = 50 MHz
f = 100 MHz
f = 200 MHz
f = 300 MHz
f = 400 MHz
f = 500 MHz
30
29.8
29.6
0
-4
29.4
-8
29.2
-12
29
-16
28.8
-40
1
10
100
Frequency (MHz)
1000
8000
-20
0
D001
20
40
60
Temperature (°C)
80
100 110
D025
VO = 2 VPP
Figure 1. Voltage Gain vs Frequency (1-dB Gain Steps)
Figure 2. Gain Flatness vs Temperature
0
0.1
0.2
Gain Matching Error (dB)
-10
Input Return Loss (dB)
-15
-20
-25
-30
-35
-40
-45
0.05
0.1
0
0
-0.05
-0.1
Phase Matching Error (q)
Gain Matching Error (dB)
Phase Matching Error (°)
-5
-50
-55
-60
1
10
100
Frequency (MHz)
1000
3000
-0.1
-9
-6
D008
Differential input impedance (ZIN) = 150 Ω, all gain settings
0
3
-0.2
6
9 12 15 18 21 24 27 30
Voltage Gain (dB)
D034
f = 200 MHz
Figure 3. Input Return Loss vs Frequency
Figure 4. Channel-to-Channel Mismatch Error
60
60
50
45
40
-40'C
27'C
90'C
105'C
55
50
OIP3 (dBm)
Av = 30 dB
Av = 22 dB
Av = 14 dB
Av = 6 dB
Av = 2 dB
Av = -2 dB
55
OIP3 (dBm)
-3
45
40
35
35
30
30
25
25
0
50 100 150 200 250 300 350 400 450 500 550 600
Frequency (MHz)
D002
0
50 100 150 200 250 300 350 400 450 500 550 600
Frequency (MHz)
D004
POUT = 0 dBm per tone
POUT = 0 dBm per tone
Figure 5. OIP3 vs Frequency and Voltage Gain
Figure 6. OIP3 vs Frequency and Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS+ = 5 V, Ri = 75 Ω, RL = 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to
300 MHz, VO converted to single-ended (SE) measurement with transformer, and default current setting (unless otherwise
noted); upon power-up, gain is set to mid-range
60
60
Av = 30 dB
Av = 22 dB
Av = 14 dB
Av = 6 dB
Av = 2 dB
Av = -2 dB
OIP3 (dBm)
50
Channel A
Channel B
55
50
OIP3 (dBm)
55
45
40
45
40
35
35
30
30
25
25
0
2
4
6
8
10
POUT per tone (dBm)
12
14
0
D003
50 100 150 200 250 300 350 400 450 500 550 600
Frequency (MHz)
D005
f = 200 MHz
POUT = 0 dBm per tone
Figure 7. OIP3 vs Output Power
Figure 8. OIP3 Channel Comparison
46
58
VS = 4.5 V
VS = 4.75 V
VS = 5 V
VS = 5.25 V
57
44
55
OIP3 (dBm)
OIP3 (dBm)
56
VS = 4.5 V
VS = 4.75 V
VS = 5 V
VS = 5.25 V
45
54
53
43
42
52
41
51
50
-40
-20
0
20
40
60
Temperature (°C)
80
40
-40
100 110
-20
POUT = 0 dBm per tone
55
Intermodulation Distortion (dBc)
0
-10
54
OIP3 (dBm)
53
52
51
50
Bias Setting = 00h
Bias Setting = 02h
Bias Setting = 08h
Bias Setting = 20h
Bias Setting = 80h
47
46
-40
100 110
D007
IMD2 (dBc)
IMD3 (dBc)
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-20
0
20
40
60
Temperature (°C)
80
100 110
0
D038
POUT = 0 dBm per tone
50
100
150
200 250 300 350
Frequency (MHz)
400
450
500
D039
POUT = 0 dBm per tone
Figure 11. OIP3 vs Temperature and Bias Setting
(f = 200 MHz)
10
80
Figure 10. OIP3 vs Temperature and Supply Voltage
(f = 300 MHz)
56
48
20
40
60
Temperature (°C)
POUT = 0 dBm per tone
Figure 9. OIP3 vs Temperature and Supply Voltage
(f = 200 MHz)
49
0
D006
Figure 12. Intermodulation Distortion vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS+ = 5 V, Ri = 75 Ω, RL = 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to
300 MHz, VO converted to single-ended (SE) measurement with transformer, and default current setting (unless otherwise
noted); upon power-up, gain is set to mid-range
50
12
f = 50 MHz
f = 100 MHz
f = 200 MHz
f = 300 MHz
45
10
Noise Figure (dB)
Noise Figure (dB)
40
25°C
11
35
30
25
20
9
8
7
6
15
5
10
5
-9
4
-6
-3
0
3
6
9 12 15 18 21 24 27 30
Voltage Gain (dB)
D011
0
50
100
150
200 250 300 350
Frequency (MHz)
400
450
500
D022
ZIN = 150 Ω
Figure 13. Noise Figure vs Voltage Gain
Figure 14. Noise Figure vs Frequency
0
0
Gain = 30 dB
Gain = 22 dB
Gain = 14 dB
Gain = 6 dB
Gain = 2 dB
Gain = -2 dB
-20
HD2 (dBc)
-30
-40
Gain = 30 dB
Gain = 22 dB
Gain = 14 dB
Gain = 6 dB
Gain = 2 dB
Gain = -2 dB
-10
-20
-30
-40
HD3 (dBc)
-10
-50
-60
-50
-60
-70
-80
-70
-90
-80
-100
-90
-110
-100
-120
0
50
100
150
200 250 300 350
Frequency (MHz)
400
450
500
0
50
100
150
D012
VO = 2 VPP
400
450
500
D013
VO = 2 VPP
Figure 15. HD2 vs Frequency and Gain Settings
Figure 16. HD3 vs Frequency and Gain Settings
0
0
-40°C
25°C
90°C
105°C
-10
-20
-40°C
25°C
90°C
105°C
-10
-20
-30
-30
-40
HD3 (dBc)
HD2 (dBc)
200 250 300 350
Frequency (MHz)
-40
-50
-60
-50
-60
-70
-80
-70
-90
-80
-100
-90
-110
-100
-120
0
50
100
150
200 250 300 350
Frequency (MHz)
400
450
500
0
50
D014
VO = 2 VPP
100
150
200 250 300 350
Frequency (MHz)
400
450
500
D015
VO = 2 VPP
Figure 17. HD2 vs Frequency and Temperature
Figure 18. HD3 vs Frequency and Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS+ = 5 V, Ri = 75 Ω, RL = 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to
300 MHz, VO converted to single-ended (SE) measurement with transformer, and default current setting (unless otherwise
noted); upon power-up, gain is set to mid-range
0
-50
Channel A (HD2)
Channel A (HD3)
Channel B (HD2)
Channel B (HD3)
Harmonic Distortion (dBc)
-20
-30
VS = 4.5 V (HD2)
VS = 4.5 V (HD3)
VS = 5 V (HD2)
VS = 5 V (HD3)
VS = 5.25 V (HD2)
VS = 5.25 V (HD3)
-55
Harmonic Distortion (dBc)
-10
-40
-50
-60
-70
-80
-90
-100
-60
-65
-70
-75
-80
-85
-90
-95
-110
-120
0
50
100
150
200 250 300 350
Frequency (MHz)
400
450
-100
-40
500
-20
0
D040
20
40
60
Temperature (°C)
80
100 110
D016
VO = 2 VPP
Figure 19. Harmonic Distortion Between Channels
Figure 20. Harmonic Distortion vs Temperature and
Supply Voltage (100 MHz)
-40
-50
VS = 4.5 V (HD2)
VS = 4.5 V (HD3)
VS = 5 V (HD2)
VS = 5 V (HD3)
VS = 5.25 V (HD2)
VS = 5.25 V (HD3)
-60
-65
-70
-50
-60
HD2 (dBc)
Harmonic Distortion (dBc)
-55
-75
-80
Gain = 30 dB
Gain = 22 dB
Gain = 14 dB
Gain = 6 dB
Gain = 2 dB
-70
-80
-85
-90
-90
-95
-100
-40
-20
0
20
40
60
Temperature (°C)
80
-100
0.5
100 110
1
1.5
D017
2
2.5
3
3.5
4
4.5
Differential Output Swing (VPP)
5
5.5
D018
VO = 2 VPP
Figure 21. Harmonic Distortion vs Temperature and
Supply Voltage (200 MHz)
Figure 22. HD2 vs Differential Output Swing (100 MHz)
-40
HD3 (dBc)
-60
-40
-50
HD2 (dBc)
-50
-30
Gain = 30 dB
Gain = 22 dB
Gain = 14 dB
Gain = 6 dB
Gain = 2 dB
-70
-80
-70
-90
1
1.5
2
2.5
3
3.5
4
4.5
Differential Output Swing (VPP)
5
5.5
-100
0.5
D019
Figure 23. HD3 vs Differential Output Swing (100 MHz)
12
-60
-80
-90
-100
0.5
Gain = 30 dB
Gain = 22 dB
Gain = 14 dB
Gain = 6 dB
Gain = 2 dB
1
1.5
2
2.5
3
3.5
4
4.5
Differential Output Swing (VPP)
5
5.5
D020
Figure 24. HD2 vs Differential Output Swing (200 MHz)
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Typical Characteristics (continued)
at TA = 25°C, VS+ = 5 V, Ri = 75 Ω, RL = 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to
300 MHz, VO converted to single-ended (SE) measurement with transformer, and default current setting (unless otherwise
noted); upon power-up, gain is set to mid-range
-30
HD3 (dBc)
-50
Output P1dB Compression (dBm)
-40
22
Gain = 30 dB
Gain = 22 dB
Gain = 14 dB
Gain = 6 dB
Gain = 2 dB
-60
-70
-80
-90
-100
-110
0.5
20
18
16
14
12
10
1
1.5
2
2.5
3
3.5
4
4.5
Differential Output Swing (VPP)
5
5.5
0
50
100
150
200 250 300 350
Frequency (MHz)
D021
Figure 25. HD3 vs Differential Output Swing (200 MHz)
400
450
500
D023
Figure 26. Output P1dB Compression vs Frequency
20
80
VS = 4.5 V
VS = 5 V
VS = 5.25 V
19
Common Mode Rejection Ratio (dB)
Output P1dB Compression (dBm)
VS = 4.5 V
VS = 5 V
VS = 5.25 V
18
17
16
15
14
-40
70
60
50
40
30
20
10
0
-20
0
20
40
60
Temperature (°C)
80
100 110
1
10
100
Frequency (MHz)
D024
1000
8000
D033
Sdd21 / Scc21
Figure 27. Output P1dB Compression vs Temperature
Figure 28. CMRR vs Frequency
0
Channel-to-Channel Isolation (dBc)
-40
Output Balance Error (dB)
-10
-20
-30
-40
-50
-60
-70
-80
Channel A to B
Channel B to A
-50
-60
-70
-80
-90
-100
-110
1
10
100
Frequency (MHz)
1000
8000
0
D035
50
100
150
200 250 300 350
Frequency (MHz)
400
450
500
D037
Scd21 / Sdd21
Figure 29. Output Balance Error vs Frequency
Figure 30. Channel-to-Channel Isolation vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS+ = 5 V, Ri = 75 Ω, RL = 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to
300 MHz, VO converted to single-ended (SE) measurement with transformer, and default current setting (unless otherwise
noted); upon power-up, gain is set to mid-range
6
f = 100 MHz
f = 200 MHz
f = 300 MHz
0.1
Cumulative Phase Step Error (dB)
0.05
0
-0.05
-0.1
2
0
-2
-4
-6
-6
-3
0
3
-9
6
9 12 15 18 21 24 27 30
Voltage Gain (dB)
D009
Figure 31. Cumulative Gain Step Error vs Voltage Gain
R (:)
jX (:)
|Z| (:)
Power Down Pin (V)
100
50
0
-50
3
6
9 12 15 18 21 24 27 30
Voltage Gain (dB)
D010
2
2.5
Power Down Pin
Output
2
1.6
1.5
1.2
1
0.8
0.5
0.4
0
-0.5
-0.4
1
10
100
Frequency (MHz)
Time (50 ns/div)
D036
D026
Figure 34. Power-Down Transition Response
2.4
SCLK
Output
-1
1000 2000
Figure 33. Output Impedance vs Frequency
2.4
2.4
2
2
2.4
SCLK
Output
2
1.6
1.6
1.6
1.2
1.2
1.2
1.2
0.8
0.8
0.8
0.8
0.4
0.4
0
0
SCLK (V)
1.6
Output (V)
SCLK (V)
0
0
-100
0.4
0.4
0
0
-0.4
-0.4
-0.4
-0.4
-0.8
-0.8
-0.8
-0.8
-1.2
-1.2
-1.2
Time (10 ns/div)
-1.2
Time (10 ns/div)
D027
Figure 35. Gain Switching Response (AV = 30 dB to 22 dB)
14
-3
2.4
150
2
-6
Figure 32. Cumulative Phase Step Error vs Voltage Gain
200
Output Impedance (:)
4
Output (V)
-0.15
-9
f = 100 MHz
f = 200 MHz
f = 300 MHz
Output (V)
Cumulative Gain Step Error (dB)
0.15
D028
Figure 36. Gain Switching Response (AV = 22 dB to 30 dB)
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Typical Characteristics (continued)
at TA = 25°C, VS+ = 5 V, Ri = 75 Ω, RL = 150 Ω, maximum gain (1:2-Ω ratio transformer plus 30-dB DVGA gain), f = 5 MHz to
300 MHz, VO converted to single-ended (SE) measurement with transformer, and default current setting (unless otherwise
noted); upon power-up, gain is set to mid-range
2.4
2
2.4
SCLK
Output
2
1.6
1.6
1.6
1.2
1.2
1.2
1.2
0.8
0.8
0.8
0.8
0.4
0.4
0.4
0.4
0
SCLK (V)
1.6
0
0
0
-0.4
-0.4
-0.4
-0.4
-0.8
-0.8
-0.8
-0.8
-1.2
-1.2
-1.2
-1.2
Time (10 ns/div)
Time (10 ns/div)
D029
D030
Figure 37. Gain Switching Response (AV = 30 dB to 14 dB)
2.4
2.4
2
2
2.4
SCLK
Output
2
1.6
1.6
1.6
1.2
1.2
1.2
1.2
0.8
0.8
0.8
0.8
0.4
0.4
0.4
0.4
0
0
SCLK (V)
1.6
Output (V)
SCLK (V)
2
Figure 38. Gain Switching Response (AV = 14 dB to 30 dB)
2.4
SCLK
Output
0
0
-0.4
-0.4
-0.4
-0.4
-0.8
-0.8
-0.8
-0.8
-1.2
-1.2
-1.2
Output (V)
2
Output (V)
SCLK (V)
2
2.4
SCLK
Output
Time (10 ns/div)
Output (V)
2.4
-1.2
Time (10 ns/div)
D031
Figure 39. Gain Switching Response (AV = 30 dB to 6 dB)
D032
Figure 40. Gain Switching Response (AV = 6 dB to 30 dB)
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8 Parameter Measurement Information
8.1 Setup Diagrams
Figure 41 to Figure 44 illustrate various test setup diagrams using the LMH2832 evaluation module (EVM).
LMH2832EVM-50
VS+ = 5 V
Vector Network
Analyzer
50
Vector Network
Analyzer
0.1 µF
Port 1 SMA
10
INPx
½ LMH2832
50
Port 3 SMA
0.1 µF
OUTPx 15
+
OUT_AMP
-
0.1 µF INMx
SMA
Port 2
50
Port 4
50
+
OUT_LOAD
SMA
OUTMx 15
10
0.1 µF
Test Equipment
with 50-Ÿ ,QSXWV/Outputs
Test Equipment
with 50-Ÿ ,QSXWV/Outputs
SPI
GND
USB
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Figure 41. Frequency Response Differential Test Setup
LMH2832EVM-75
VS+ = 5 V
zo = 50 Ÿ, 1:2
F-Connector
0º
50
180º
Signal Generator
with 50-Ÿ 2XWSXWV
Band-Pass
Filter
0.1 µF
10-
INPx
BMP5075
OUTPx 40
0.1 µF
+
½ LMH2832 OUT_AMP
-
BMP5075
F-Connector
0.1 µF INMx
50
SMA
OUTMx 40
10-
ETC1-1-13T
(1:1, zo = 50 Ÿ)
Spectrum Analyzer
with 50-Ÿ ,QSXWV
0.1 µF
ZFSCJ-2-1-S+
SPI
75-Ÿ 5HIHUHQFH
50-Ÿ 5HIHUHQFH
GND
USB
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Figure 42. Single-Tone Harmonic Distortion Test Setup
LMH2832EVM-75
VS+ = 5 V
50
Signal Generator
with 50-Ÿ 2XWSXWV
F-Connector
6-dB
Band-Pass
Attenuation
Filter
Pads
ZFSCJ-2-1
or
ZFSCJ-2-4
BMP5075
MABA011033
(1:2, zo = 75 Ÿ)
0.1 µF
10
INPx
0.1 µF INMx
50
OUTPx 40
0.1 µF
+
½ LMH2832 OUT_AMP
10
ETC1-1-13T
(1:1, zo = 50 Ÿ)
50
SMA
OUTMx 40
0.1 µF
Spectrum Analyzer
with 50-Ÿ ,QSXWV
50-Ÿ 5HIHUHQFH
75-Ÿ 5HIHUHQFH
Signal Generator
with 50-Ÿ 2XWSXWV
SPI
GND
USB
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Figure 43. Two-Tone Linearity Test Setup (OIP3, OIP2)
16
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Setup Diagrams (continued)
LMH2832EVM-50
VS+ = 5 V
50
346B
Noise Source
Agilent E4443A
with 50-Ÿ 2XWSXWV
MABA011038
(1:3, zo = 50 Ÿ)
0.1 µF
10
INPx
OUTPx 40
0.1 µF
0.1 µF INMx
50
SMA
½ LMH2832
SMA
ETC1-1-13T
(1:1, zo = 50 Ÿ)
10
OUTMx 40
0.1 µF
Agilent E4443A
with 50-Ÿ ,QSXWV
SPI
GND
USB
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Figure 44. Noise Figure Test Setup
8.2 ATE Testing and DC Measurements
All production testing and dc parameters are measured on automated test equipment (ATE) capable of dc
measurements only. Some measurements (such as voltage gain) are referenced to the output of the internal
amplifier and do not include losses attributed to the on-chip output resistors. The Electrical Characteristics values
specify these conditions. When the measurement is referred to the amplifier output, the output resistors are not
included in the measurement. If the measurement is referred to the device pins, then the output resistor loss is
included in the measurement.
8.3 Frequency Response
This test is done by running an S-parameter sweep on a 4-port differential network analyzer using the standard
EVM with no baluns; see Figure 41. The inputs and outputs of the EVM are connected to the network analyzer
using 75-Ω coaxial cables with the input ports set to a characteristic impedance of 75 Ω, and the output ports set
to a characteristic impedance of 50 Ω.
The frequency response test with capacitive load is done by soldering the capacitor across the LMH2832 output
pins. In this configuration, the on-chip, 10-Ω resistors on each output leg isolate the capacitive load from the
amplifier output pins.
8.4 Distortion
The standard EVM is used for measuring both the single-tone harmonic distortion and two-tone intermodulation
distortion; see Figure 42 and Figure 43, respectively. The distortion is measured with differential input signals to
the LMH2832. In order to interface with 50-Ω, single-ended test equipment, 50-Ω to 75-Ω impedance matching
pads followed by external baluns (1:2, zo = 75 Ω) are required between the EVM output ports and the test
equipment. These baluns are used to combine two single tones in the two-tone test plots as well as to convert
the single-ended input to differential output for harmonic distortion tests. The use of 6-dB attenuator pads on both
the inputs and outputs is recommended to provide a balanced match between the external balun and the EVM.
8.5 Noise Figure
This test is done by matching the input of the LMH2832 to a 50-Ω noise source using a 50-Ω to 75-Ω impedance
transformation pad followed by a 1:2 balun (Figure 44), with the noise figure being referred to the input
impedance (RS = 150 Ω). As noted in Figure 44, a Keysight Technologies™ E4443A with NF features is used for
the testing.
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8.6 Pulse Response, Slew Rate, and Overdrive Recovery
For time-domain measurements, the standard EVM is driven through an impedance transformation pad and a
balun again to convert a single-ended output from the test equipment to the differential inputs of the LMH2832.
The differential outputs are directly connected to the oscilloscope inputs, with the differential signal response
calculated using trace math from the two separate oscilloscope inputs.
8.7 Power-Down
The standard EVM is used for this test by completely removing the shorting block on jumper JPD. A high-speed,
50-Ω pulse generator is used to drive the PDx pin that toggles the output signal on or off depending upon the
PDx pin voltage.
8.8 Crosstalk, Gain Matching, and Phase Matching
The standard EVM is used for these tests with both channels enabled. For gain and phase matching, the
responses of both channels are measured on a network analyzer and the gain and phase values are compared.
For crosstalk, a single channel is driven with a signal on the network analyzer when the other channel is
measured.
8.9 Output Measurement Reference Points
The LMH2832 has two on-chip, 10-Ω output resistors on each channel. When matching the output to a 100-Ω
load, the evaluation module (EVM) uses an external 40-Ω resistor on each output leg to complete the output
matching. The inclusion of on-chip output resistors creates two potential reference points for measuring the
output voltage. The first reference point is at the internal amplifier output (OUT_AMP), and the second reference
point is at the externally-matched 100-Ω load (OUT_LOAD). The measurements in the Electrical Characteristics
table and in the Typical Characteristics section are referred to the (OUT_AMP) reference point unless otherwise
specified. The conversion between reference points is a straightforward correction of 3 dB for power and 6 dB for
voltage, as shown in Equation 1 and Equation 2. The measurements are referenced to OUT_AMP when not
specified.
VOUT_LOAD = (VOUT_AMP – 6 dB)
POUT_LOAD = (POUT_AMP – 3 dB)
18
(1)
(2)
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9 Detailed Description
9.1 Overview
Each channel of the LMH2832 consists of an input attenuator block followed by a fully differential amplifier that
has a gain of 30 dB. The attenuator has a range of 0 dB to –39 dB in 1-dB steps that is controlled by an SPI
interface. The two channels can be controlled independently using the digital interface including power-down and
bias settings. A separate analog power-down pin (PDA, PDB) is also included for each channel so that the
device can bet set to a low-power state without waiting for a serial write to a register. The internal registers also
include a power-on-reset (POR) that ensures the device starts in a known state after the power is reset.
9.2 Functional Block Diagram
1-dB Attenuator Steps:
0 dB to -39 dB
OUTPA
INPA
FDA
G = 30 dB
150
OUTMA
INMA
PDA
CS
SCLK
SDI
SDO
SPI
POR
Channel A Control Logic
Channel B Control Logic
PDB
INMB
OUTMB
FDA
G = 30 dB
150
INPB
OUTPB
1-dB Attenuator Steps:
0 dB to -39 dB
9.3 Feature Description
9.3.1 Analog Input Characteristics
The LMH2832 is a dual-channel device with two identical channels (A and B) that each have differential input
pins (INP and INM) that denote the positive and negative inputs, respectively. The inputs are expected to be accoupled only, typically through a transformer or capacitor. The amplifier self-biases the input common-mode to
mid-supply for the maximum input voltage range. The inputs of the LMH2832 can only be driven differentially. For
single-ended input source applications, use a balun or fully differential amplifier (such as the LMH3401 or
LMH5401) that can convert single-ended to differential signals before the LMH2832.
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Feature Description (continued)
At maximum gain, the digital attenuator is set to 0 dB of attenuation, causing the input signal to be much larger
than the output signal and forcing the maximum output voltage swing to be limited by the outputs of the device.
However at minimum gain, the maximum voltage swing is limited by the inputs of the device because the
attenuator causes the output voltage to be 9 dB lower than the input voltage. In minimum gain, the input voltage
limits against the electrostatic discharge (ESD) devices before the output reaches the maximum swing limits. For
linear operation, the input voltage must be kept within the maximum input voltage ratings described in the
Electrical Characteristics table.
The input impedance of the LMH2832 is set by internal termination resistors to a nominal value of 150 Ω,
differential. Process variations result in a range of values, as described in the Electrical Characteristics table. The
input impedance is also affected by device parasitic effects at higher frequencies that cause the impedance to
shift away from the nominal value.
9.3.2 Analog Output Characteristics
The LMH2832 has series, 10-Ω, on-chip resistors on each output to provide isolation from board parasitics that
can cause instability. When designing a filter following the LMH2832, the filter source impedance calculation
must include the two 10-Ω, on-chip resistors. Table 2 shows the calculated external source impedance values
required for various matched filter loads.
Table 2. Output Resistor Values for Matched Loads
MATCHED FILTER IMPEDANCE (Ω)
EXTERNAL SERIES RESISTOR PER OUTPUT (Ω)
100
80
150
130
200
180
300
280
9.3.3 Driving Low Insertion-Loss Filters
When driving high-speed ADCs, a filter is commonly driven with a matched impedance to the ADC. This
impedance is matched by the amplifier by setting the combination of the output resistors to the same impedance
as the ADC inputs. Impedance matching is often done to minimize any transmission reflections caused by the
physical signal path. The drawback to using a matched impedance is that a voltage swing is required from the
amplifier outputs that is twice the desired ADC input voltage swing, which can cause output voltage limitation
issues.
To avoid using a matched impedance, a low insertion loss filter can be driven where there is little to no
resistance added at the amplifier outputs. The amplifier outputs then only must swing to the value of the ADC
full-scale input voltage, thus eliminating most of the potential amplifier output headroom issues. The requirements
of this technique are that the amplifier must be able to provide enough current to the load of the ADC and that
the path between the amplifier outputs and ADC inputs must be minimized to prevent any reflections.
9.3.4 Input Impedance Matching
The LMH2832 has a differential input impedance of 150 Ω that can be easily matched to single-ended, 50-Ω or
75-Ω systems using baluns. For a single-ended, 50-Ω input, a 1:3-Ω ratio balun can be used to create a 150-Ω
differential source impedance to the device with a balun gain of 4.8 dB. For a single-ended, 75-Ω input, a 1:2-Ω
ratio balun creates a 150-Ω differential source impedance to the device with a voltage gain of 3 dB.
9.3.5 Power-On Reset (POR)
The LMH2832 has a built-in, power-on-reset (POR) that sets the device registers to their default state (see the
Register Maps section) on power-up. Note that the LMH2832 register information is lost when power is removed.
When power is reapplied, the POR ensures that the device enters a default state. Power glitches (of sufficient
duration) can also initiate the POR and return the device to a default state.
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9.4 Device Functional Modes
9.4.1 Power-Down (PD)
The device supports power-down control using an external power-down (PDx) pin or by writing a logic high to bit
6 of SPI register 2h (see the Register Maps section). The external PDx pins are active high; when left floating,
the device defaults to an on condition resulting from the internal pulldown resistors that cause a logic low on the
PDx pins. The device PDx thresholds are noted in the Electrical Characteristics table. The device consumes
approximately 7 mA in power-down mode. Note that the SPI register contents are preserved in power-down
mode.
9.4.2 Gain Control
The LMH2832 gain can be controlled from 30-dB gain (0-dB attenuation) to –9-dB gain in 1-dB steps by digitally
programming the SPI register 2h; see the Register Maps section for more details.
9.5 Programming
9.5.1 Details of the Serial Interface
The LMH2832 has a set of internal registers that can be accessed by the serial interface formed by the CS
(serial interface enable), SCLK (serial interface clock), SDI (serial interface input data), and SDO (serial interface
read-back data) pins. Serially shifting bits into the device is enabled when CS is low. SDI serial data are latched
at every SCLK rising edge when CS is active (low). The serial data are loaded into the register at every 16th
SCLK rising edge when CS is low. When the word length exceeds a multiple of 16 bits, the excess bits are
ignored. Data can be loaded in multiples of 16-bit words within a single active CS pulse. The first eight bits form
the register address and the remaining eight bits are the register data. The interface can function with SCLK
frequencies from 25 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle. A
summary of the LMH2832 SPI protocol is:
1. SPI-1.1 interface
2. Independent channel A, B attenuation programming (6-bit gain control)
3. SPI register contents are preserved in power-down mode
4. SPI-controlled power modes (3-bit control for eight options to step down the power)
5. Powered for the main 5-V power supply
6. 1.8-V logic
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Programming (continued)
9.5.2 Timing Diagrams
Figure 45 and Figure 46 show timing diagrams for the SPI write and read bus cycles, respectively. Figure 47
shows an example timing diagram for a streaming write cycle and Figure 48 shows an example timing diagram
for a streaming read cycle. Figure 49, Figure 50, Figure 51, and Figure 52 illustrate timing diagrams and
requirements for the clock, data input, data output, and chip select, respectively. See the Timing Requirements:
SPI table for SPI timing requirements.
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SDI
SDO
Figure 45. SPI Write Bus Cycle Timing Diagram
CS
1
2
3
4
5
6
7
8
A6
A5
A4
A3
A2
A1
A0
9
10
11
12
13
14
15
16
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SDI
SDO
Figure 46. SPI Read Bus Cycle Timing Diagram
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
D3
D2
D1
D0
21
22
23
24
D2
D1
D0
SCLK
Addr N
A6
SDI
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
Addr N+1
D2
D1
D0
D7
D6
D5
D4
SDO
Figure 47. SPI Streaming Write Example Timing Diagram
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SCLK
Addr N+1
Addr N
SDI
A6
A5
A4
A3
A2
A1
A0
D7
SDO
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
Figure 48. SPI Streaming Read Example Timing Diagram
tPH
tPL
SCLK
tPL
Figure 49. SPI Clock Timing Diagram
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Programming (continued)
SCLK
tSU
tH
SDI
Figure 50. SPI Data Input Timing Diagram
CS
CS
tODZ
CS
tOD
tODZ
SDOen
SDOen
a) Need Title
SDO
b) Need Title
c) Need Title
Figure 51. SPI Data Output Timing Diagrams
SCLK
tCSS
tCSH
tIAG
CS
CS
a) Need Title
b) Need Title
Figure 52. SPI Chip Select Timing Diagrams
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9.6 Register Maps
Table 3 shows the SPI registers for the LMH2832.
Table 3. SPI Register Map
REGISTER DATA
ADDRESS
(A[6:0])
R/W
DEFAULT
(Hex)
0
R
B3
1
R
23
2
R/W
00
SW reset
Reserved
Reset B
Reserved
Reset A
3
R/W
00
Power-down
Reserved
PD B
Reserved
PD A
4
R/W
20
Channel A RW0, bias control
Channel A RW0
5
R/W
14
Channel A RW1, attenuator control
Channel A RW1
6
R/W
20
Channel B RW0, bias control
Channel B RW0
7
R/W
14
Channel B RW1, attenuator control
8-127
R
00
Reserved
24
REGISTER NAME
7
6
5
4
3
2
1
0
Revision ID
1
0
1
1
0
0
1
1
Product ID
0
0
1
0
0
0
1
1
Channel B RW1
0
0
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0
0
0
0
0
0
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9.6.1 Register Descriptions
Exercising the SW reset function returns all registers to the default values of the respective channel.
9.6.1.1 SW Reset Register (address = 2)
Figure 53. SW Reset Register
7
6
Reserved
R-0h
5
4
Reset B
R/W-0h
3
2
Reserved
R-0h
1
0
Reset A
R/W-0h
1
0
PD A
R/W-0h
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4. SW Reset Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
Reserved
R
0h
Reserved.
Reset B
R/W
0h
This bit is a self-clearing bit.
0 = No action
1 = Reset
Reserved
R
0h
Reserved.
Reset A
R/W
0h
This bit is a self-clearing bit.
0 = No action
1 = Reset
4
3-1
0
9.6.2 Power-Down Control Register (address = 3)
Figure 54. Power-Down Control Register
7
6
Reserved
R-0h
5
4
PD B
R/W-0h
3
2
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5. Power-Down Control Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
Reserved
R
0h
Reserved.
PD B
R/W
0h
0 = Active
1 = PD
Reserved
R
0h
Reserved.
PD A
R/W
0h
0 = Active
1 = PD
4
3-1
0
9.6.3 Channel A RW0 Register (address = 4)
Figure 55. Channel A RW0 Register
7
6
5
4
3
2
Channel A RW0
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. Channel A RW0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Channel A RW0
R/W
0h
These bits drive the output CHA_RW0[7:0] and are reset by a
device reset or Reset A. Table 10 lists controls for this register.
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9.6.4 Channel A RW1 Register (address = 5)
Figure 56. Channel A RW1 Register
7
6
5
4
3
2
1
0
Channel A RW1
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. Channel A RW1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Channel A RW1
R/W
0h
These bits drive the output CHA_RW1[7:0] and are reset by a
device reset or Reset A. Table 11 lists controls for this register.
9.6.5 Channel B RW0 Register (address = 6)
Figure 57. Channel B RW0 Register
7
6
5
4
3
2
1
0
Channel B RW0
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. Channel B RW0 Register Field Descriptions
26
Bit
Field
Type
Reset
Description
7-0
Channel B RW0
R/W
0h
These bits drive the output CHB_RW0[7:0] and are reset by a
device reset or Reset B. Table 10 lists controls for this register.
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9.6.6 Channel B RW1 Register (address = 7)
Figure 58. Channel B RW1 Register
7
6
5
4
3
2
1
0
Channel B RW1
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. Channel B RW1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Channel B RW1
R/W
0h
These bits drive the output CHB_RW1[7:0] and are reset by a
device reset or Reset B. Table 11 lists controls for this register.
Table 10. Bias Control Register Bit Settings (Channels A, B) (1)
(1)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
X
0
0
0
0
0
1
X
X
0
0
0
0
1
X
X
X
0
0
0
1
X
X
X
X
0
0
1
X
X
X
X
X
0
1
X
X
X
X
X
X
1
X
X
X
X
X
X
X
Default value: 001xxxxx. Highest power: 1xxxxxxx. Lower power: 00000000.
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Table 11. Attenuator Control Register Bit Settings (Channels A, B) (1)
7
(1)
28
5
4
3
2
1
0
Reserved, always read 0
6
0
0
0
0
0
0
Reserved, always read 0
0
0
0
0
0
1
Reserved, always read 0
0
0
0
0
1
0
Reserved, always read 0
0
0
0
0
1
1
Reserved, always read 0
0
0
0
1
0
0
Reserved, always read 0
0
0
0
1
0
1
Reserved, always read 0
0
0
0
1
1
0
Reserved, always read 0
0
0
0
1
1
1
Reserved, always read 0
0
0
1
0
0
0
Reserved, always read 0
0
0
1
0
0
1
Reserved, always read 0
0
0
1
0
1
0
Reserved, always read 0
0
0
1
0
1
1
Reserved, always read 0
0
0
1
1
0
0
Reserved, always read 0
0
0
1
1
0
1
Reserved, always read 0
0
0
1
1
1
0
Reserved, always read 0
0
0
1
1
1
1
Reserved, always read 0
0
1
0
0
0
0
Reserved, always read 0
0
1
0
0
0
1
Reserved, always read 0
0
1
0
0
1
0
Reserved, always read 0
0
1
0
0
1
1
Reserved, always read 0
0
1
0
1
0
0
Reserved, always read 0
0
1
0
1
0
1
Reserved, always read 0
0
1
0
1
1
0
Reserved, always read 0
0
1
0
1
1
1
Reserved, always read 0
0
1
1
0
0
0
Reserved, always read 0
0
1
1
0
0
1
Reserved, always read 0
0
1
1
0
1
0
Reserved, always read 0
0
1
1
0
1
1
Reserved, always read 0
0
1
1
1
0
0
Reserved, always read 0
0
1
1
1
0
1
Reserved, always read 0
0
1
1
1
1
0
Reserved, always read 0
0
1
1
1
1
1
Reserved, always read 0
1
0
0
0
0
0
Reserved, always read 0
1
0
0
0
0
1
Reserved, always read 0
1
0
0
0
1
0
Reserved, always read 0
1
0
0
0
1
1
Reserved, always read 0
1
0
0
1
0
0
Reserved, always read 0
1
0
0
1
0
1
Reserved, always read 0
1
0
0
1
1
0
Reserved, always read 0
1
0
0
1
1
1
Default attenuation setting: xx001011. Maximum attenuation (lowest gain setting): xx100111. Minimum attenuation (highest gain setting):
xx000000.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The LMH2832 is designed as a general-purpose, analog-to-digital converter (ADC) driver that also meets the
performance requirements for DOCSIS 3.X upstream CMTS solutions. This section describes various
requirements and considerations for using the LMH2832 and also some design examples.
10.1.1 Driving ADCs
When the amplifier is driving an ADC, the key points to consider for implementation are the signal-to-noise ratio
(SNR), spurious-free dynamic range (SFDR), and ADC input considerations, as described in this section.
A typical application of the LMH2832 involves driving a wideband, 14-bit ADC (such as the ADS54J40), as
shown in Figure 59. The LMH2832 can drive the full Nyquist bandwidth of ADCs with sampling rates up to
900 MSPS. If the front-end bandwidth of the ADC is more than 450 MHz, then use a simple noise filter to
improve SNR. Otherwise, the ADC can be connected directly to the amplifier output pins with appropriate
matching resistors to limit the full-scale input of the ADC. Note that the LMH2832 inputs must be driven
differentially using a balun or fully differential amplifiers (FDAs). For dc-coupled applications, an FDA (such as
the LMH3401 or LMH5401) that can convert a single-ended input to a differential output with low distortion is
preferred.
VS+ = 5V
ZS = 50-Ÿ
10
1:3
INPx
½ LMH2832
INMx
OUTPx
RO
+
OUT_AMP
10
LPF
OUTMx
ADC
RO
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SPI
GND
Figure 59. ADC Driver with a 50-Ω Source
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Application Information (continued)
10.1.1.1 SNR Considerations
When using the LMH2832 with a filter, the signal-to-noise ratio (SNR) of the amplifier and filter can be calculated
from the amplitude of the signal and the bandwidth of the filter. The noise from the amplifier is band-limited by
the filter with the equivalent brick-wall filter bandwidth. The amplifier and filter noise can be calculated using
Equation 3:
SNRAMP+FILTER = 10 × log
V2O
e
= 20 × log
2
FILTEROUT
VO
eFILTEROUT
where:
•
•
•
•
eFILTEROUT = eNAMPOUT • √ENB
eNAMPOUT = the output noise density of the LMH2832 (50.4 nV/√Hz) at AV = 30 dB
ENB = the brick-wall equivalent noise bandwidth of the filter
VO = the amplifier output signal
(3)
For example, with a first-order (N = 1) band-pass or low-pass filter with a 1000-MHz cutoff, ENB is 1.57 • f–3dB =
1.57 • 1000 MHz = 1570 MHz. For second-order (N = 2) filters, ENB is 1.22 • f–3dB. When the filter order
increases, ENB approaches f–3dB (N = 3 → ENB = 1.15 • f–3dB; N = 4 → ENB = 1.13 • f–3dB). Both VO and
eFILTEROUT are in RMS voltages. For example, with a 2-VPP (0.707 VRMS) output signal and a 300-MHz, first-order,
low-pass filter, the SNR of the amplifier and filter is 56 dB with eFILTEROUT = 50.4 nV/√Hz • √471 MHz = 1.09
mVRMS.
The SNR of the amplifier, filter, and ADC sum in RMS fashion, as shown in Equation 4 (SNR values in dB):
-SNRAMP+FILTER
SNRSYSTEM = -20 × log
10
10
-SNRADC
+ 10
10
(4)
This formula shows that if the SNR of the amplifier and filter equals the SNR of the ADC, then the combined
SNR is 3 dB lower (worse). Thus, for minimal degradation (< 1 dB) on the ADC SNR, the SNR of the amplifier
and filter must be 10 dB greater than the ADC SNR. The combined SNR calculated in this manner is usually
accurate to within ±1 dB of the actual implementation.
10.1.1.2 SFDR Considerations
The SFDR of the amplifier is usually set by the second- or third-order harmonic distortion for single-tone inputs,
and by the second-order or third-order intermodulation distortion for two-tone inputs. Harmonics and secondorder intermodulation distortion can be filtered to some degree, but third-order intermodulation spurs cannot be
filtered. The ADC generates the same distortion products as the amplifier, but also generates additional spurs
(not harmonically related to the input signal) as a result of sampling and clock feed through.
When the spurs from the amplifier and filter are known, each individual spur can be directly added to the same
spur from the ADC, as shown in Equation 5, to estimate the combined spur (spur amplitudes in dBc):
-HDxADC
-HDxAMP+FILTER
HDxSYSTEM = -20 × log 10
20
+ 10
20
(5)
This calculation assumes that the spurs are in phase, but usually provides a good estimate of the final combined
distortion.
For example, if the spur of the amplifier and filter equals the spur of the ADC, then the combined spur is 6 dB
higher. To minimize the amplifier contribution (< 1 dB) to the overall system distortion, the spur from the amplifier
and filter must be approximately 15 dB lower in amplitude than that of the converter. The combined spur
calculated in this manner is usually accurate to within ±6 dB of the actual implementation; however, higher
variations can be detected as a result of phase shift in the filter, especially in second-order harmonic
performance.
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Application Information (continued)
This worst-case spur calculation assumes that the amplifier and filter spur of interest is in phase with the
corresponding spur in the ADC, such that the two spur amplitudes can be added linearly. There are two phaseshift mechanisms that cause the measured distortion performance of the amplifier-ADC chain to deviate from the
expected performance calculated using Equation 5; one mechanism is the common-mode phase shift and the
other is the differential phase shift.
Common-mode phase shift is the phase shift detected equally in both branches of the differential signal path
including the filter. Common-mode phase shift nullifies the basic assumption that the amplifier, filter, and ADC
spur sources are in phase. This phase shift can lead to better performance than predicted when the spurs
become phase shifted, and there is the potential for cancellation when the phase shift reaches 180°. However,
there is a significant challenge in designing an amplifier-ADC interface circuit to take advantage of a commonmode phase shift for cancellation: the phase characteristics of the ADC spur sources are unknown, thus the
necessary phase shift in the filter and signal path for cancellation is also unknown.
Differential phase shift is the difference in the phase response between the two branches of the differential filter
signal path. Differential phase shift in the filter is a result of mismatched components caused by nominal
tolerances and can severely degrade the even harmonic distortion of the amplifier-ADC chain. This effect has the
same result as mismatched path lengths for the two differential traces, and causes more phase shift in one path
than the other. Ideally, the phase responses over frequency through the two sides of a differential signal path are
identical, such that even harmonics remain optimally out of phase and cancel when the signal is taken
differentially. However, if one side has more phase shift than the other, then the even harmonic cancellation is
not as effective.
Single-order, resistor-capacitor (RC) filters cause very little differential phase shift with nominal tolerances of 5%
or less, but higher-order, inductor-capacitor (LC) filters are very sensitive to component mismatch. For instance,
a third-order Butterworth band-pass filter with a 100-MHz center frequency and a 20-MHz bandwidth displays as
much as 20° of differential phase imbalance in a SPICE Monte Carlo analysis with 2% component tolerances.
Therefore, although a prototype may work, production variance is unacceptable. For ac-coupled or dc-coupled
applications where a transformer or balun cannot be used, using first- or second-order filters is recommended to
minimize the effect of differential phase shift.
10.1.1.3 ADC Input Common-Mode Voltage Considerations (AC-Coupled Input)
When interfacing to an ADC, the input common-mode voltage range of the ADC must be taken into account for
proper operation. In an ac-coupled application between the amplifier and the ADC, the input common-mode
voltage bias of the ADC can be accomplished in different ways. Some ADCs use internal bias networks such that
the analog inputs are automatically biased to the required input common-mode voltage if the inputs are accoupled with capacitors (or if the filter between the amplifier and ADC is a band-pass filter). Other ADCs supply
the required input common-mode voltage from a reference voltage output pin (often termed CM or VCM). With
these ADCs, the ac-coupled input signal can be re-biased to the input common-mode voltage by connecting
resistors from each input to the CM output of the ADC, as shown in Figure 60. AC coupling provides dc commonmode isolation between the amplifier and the ADC; thus, the output common-mode voltage of the amplifier is a
don’t care for the ADC.
RO
RCM
AIN+
Amp
ADC
RCM
AIN-
CM
RO
Figure 60. Biasing AC-Coupled ADC Inputs Using the ADC CM Output
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Application Information (continued)
10.1.1.4 ADC Input Common-Mode Voltage Considerations (DC-Coupled Input)
The LMH2832 is designed to primarily be used in ac-coupled applications only. However, the LMH2832 can be
dc-coupled if certain strict conditions are met. The LMH2832 has an internal common-mode bias equal to the
mid-supply voltage, so any dc coupling on the input or output must have a common-mode voltage that is also set
to mid-supply. To dc couple to an ADC input, the mid-supply voltage of the LMH2832 must be centered around
the ADC input common-mode. This common-mode matching can be accomplished by shifting the supplies to
center the mid-supply voltage around the ADC input common-mode voltage. However, shifting the supplies also
changes the ground reference for the digital inputs, which then likely requires a voltage-shifted interface as well.
The LMH2832 is not recommended to be operated as dc-coupled unless absolutely necessary.
10.2 Typical Applications
10.2.1 DOCSIS 3.X Driver
The LMH2832 is designed to perform best when driving differential input ADCs in high-speed applications.
Figure 61 shows an example diagram of the LMH2832 driving an ADC with a fifth-order, low-pass filter for a 75-Ω
impedance, data over cable service interface specification (DOCSIS) 3.X upstream receiver return path
application. The primary interface between the amplifier and the ADC is usually an antialiasing filter to suppress
high-frequency harmonics that otherwise alias back into the ADC FFT spectrum. Filters range from single-order
real RC poles to higher-order, resistor-inductor-capacitor (RLC) filters, depending on the application
requirements. Series output resistors (RO) help isolate the amplifier from any capacitive load presented by the
filter, and can also be used to create a matched impedance to drive transmission lines.
VS+ = 5V
ZS = 75-Ÿ
1:2 O
10
0.1 µF
64.9
INPx
½ LMH2832
0.1 µF INMx
+
OUT_AMP
-
0.1 µF
24 nH
82 nH
24 nH
OUTPx
5.5 pF
5.5 pF
½ ADS54J40
100
OUTMx
10
5.1
100
64.9
0.1 µF
24 nH
SPI
82 nH
24 nH
5.1
VOCM
Copyright © 2016, Texas Instruments Incorporated
GND
Figure 61. DOCSIS 3.X Driver with the ADS54J40 and a 300-MHz, 4th-Order, Butterworth, Low-Pass Filter
10.2.1.1 Design Requirements
Table 12 shows example design requirements for the LMH2832 in an upstream receiver application.
Table 12. Example Design Requirements
32
SPECIFICATION
DESIGN REQUIREMENTS
Supply voltage
4.75 to 5.25 V
Usable input frequency range
300 MHz
System voltage gain and range
33-dB voltage gain with 30-dB range
Source impedance
75 Ω, single-ended
Signal path SNR at 175 MHz (measured at ADC)
> 50 dBFS
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10.2.1.2 Detailed Design Procedure
To begin the design process, make sure that none of the following design parameters exceed the limits listed in
the Electrical Characteristics table, such as:
•
•
•
•
•
Supply voltage
Temperature range
Input voltage range across gain
Output current requirements
Digital I/O voltages and currents
10.2.1.2.1 Source Resistance Matching
Standard DOCSIS systems use a characteristic single-ended impedance of 75 Ω that must be properly matched
to the 150-Ω differential impedance of the LMH2832. The circuit in Figure 61 uses a transformer with a 1:2-Ω
ratio to convert the signal from single-ended to differential, and also to match the differential impedance. The
transformer also adds a signal gain of approximately 3 dB to the system with some insertion loss depending on
the chosen transformer.
10.2.1.2.2 Output Impedance Matching
For the circuit in Figure 61, the output impedance is matched to a 150-Ω characteristic impedance filter to
maximize the performance of the LMH2832. On the amplifier output side, the output impedance is matched to
150 Ω by including a 65-Ω series resistor on each output. Combined with the internal 10-Ω resistors on each
output, the total differential impedance becomes 150 Ω. The ADS54J40 has an input impedance of
approximately 600 Ω that is reduced to 150 Ω by using two 5-Ω series input resistors in parallel with two 100-Ω
series resistors. The 5-Ω series resistors are included to isolate the input capacitance of the ADC so that the
response of the filter is not affected. With both the amplifier and ADC impedances matched, any transmission
line effects of the connection are minimized.
If the ADC is physically located close enough to the amplifier, a matched impedance may not be needed; see
Driving Low Insertion-Loss Filters section for more information on driving non-matched filters.
10.2.1.2.3 Voltage Headroom Considerations
Because of the series resistors included on both the amplifier outputs and ADC inputs, the amplifier must drive a
voltage that is significantly higher than the ADC full-scale input. For the circuit in Figure 61, the ADS54J40 fullscale input voltage is 1.9 VPP, so the required voltage at the amplifier output pins is 3.6 VPP. This voltage is less
than the specified output voltage of 5 VPP for the LMH2832, thus system performance is not limited. If the
required output voltage is higher than what the amplifier can support, then the matched resistance value can be
reduced. However, this reduction can have performance implications because more current output is required
from the amplifier.
The input voltage swing can be larger than the output voltage swing because the LMH2832 can operate as an
attenuator. To maintain the full-scale voltage of the ADS54J40 input in this application, the amplifier cannot
attenuate more than 1 dB from input to output; otherwise, the maximum input voltage swing is exceeded. If the
amplifier must be operated with more attenuation, then the output voltage must be reduced.
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10.2.1.3 Application Curve
Channel-to-Channel Isolation (dBc)
-40
Channel A to B
Channel B to A
-50
-60
-70
-80
-90
-100
-110
0
50
100
150
200 250 300 350
Frequency (MHz)
400
450
500
D037
Figure 62. Amplifier Dual Channel Isolation Presented to ADC Interface
10.2.2 IQ Receiver
The LMH2832 is a dual-channel device; therefore, the device has excellent gain and phase matching between
channels A and B. This matching makes the LMH2832 an excellent choice for systems that require two matched
channels (such as an IQ demodulation receiver), as shown in Figure 63. For an IQ system, both the gain and
phase must match for the real and imaginary channel. When using two single-channel amplifiers, the matching
characteristics are subject to process lot and packaging variations for two individual devices, and there is often
no way to make sure that the amplifiers match without testing each amplifier. However, the dual-channel
architecture of the LMH2832 allows for much tighter gain and phase matching with minimal crosstalk effects. For
more matching information, see the Electrical Characteristics table.
I Channel
RF IN
LPF
LMH2832
ADS54J60
LPF
Q Channel
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Figure 63. IQ Receiver Block Diagram
34
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10.3 Do's and Don'ts
10.3.1 Do:
•
•
•
•
•
Include a thermal analysis at the beginning of the project
Use well-terminated transmission lines for all signals
Maintain symmetrical input and output trace layouts
Use solid metal layers for the power supplies
Keep signal lines as straight as possible
10.3.2 Don't:
•
•
•
Use a lower power-supply voltage than necessary
Forget about the common-mode response of filters and transmission lines
Rout digital line traces close to the analog signals and supply line traces
11 Power Supply Recommendations
The LMH2832 is designed to be used with a single supply with a range of 4.75 V to 5.25 V. The ideal supply
voltage is a 5.0-V total single-ended supply. If the supply is reduced to the minimum voltage, then the maximum
input and output voltage range is reduced by 0.25 V.
11.1 Split Supplies
Ideally, the LMH2832 uses a single-ended, 5-V supply, but the device can be operated on a split supply if
necessary. However, the digital logic is referenced to the GND pins, meaning that the logic reference shifts with
the GND supply if connected to a negative voltage and must be accounted for in the logic connections. In
general, the LMH2832 is not suggested to be operated with a split-supply configuration.
11.2 Supply Decoupling
Power-supply decoupling is critical to high-frequency performance. Onboard bypass capacitors are used on the
LMH2832EVM; however, the most important component of the supply bypassing is provided by the printed circuit
board (PCB). As illustrated in Figure 64, there are multiple vias connecting the LMH2832 power planes to the
power-supply traces. These vias connect the internal power planes to the LMH2832. Both VCC and GND must be
connected to the internal power planes with several square centimeters of continuous plane in the immediate
vicinity of the amplifier. The capacitance between these power planes provides the bulk of the high-frequency
bypassing for the LMH2832.
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12 Layout
12.1 Layout Guidelines
With a small bandwidth greater than 1 GHz, layout for the LMH2832 is critical and nothing can be neglected. In
order to simplify board design, the LMH2832 has on-chip resistors that reduce the affect of off-chip capacitance.
For this reason, make sure that the ground layer below the LMH2832 is not cut. The recommendation to not cut
the ground plane under the amplifier input and output pins is different than many other high-speed amplifiers, but
the reason is that parasitic inductance is more harmful to the LMH2832 performance than parasitic capacitance.
By leaving the ground layer under the device intact, parasitic inductance of the output and power traces is
minimized. The DUT portion of the evaluation board layout is shown in Figure 64.
The EVM uses long-edge capacitors for the decoupling capacitors, which reduces series resistance and
increases the resonant frequency. Vias are also placed to the power planes before the bypass capacitors.
Although not evident in the top layer, two vias are used at the capacitor in addition to the two vias underneath the
device.
The output-matching resistors are 0402 size and are placed very close to the amplifier output pins, which
reduces both parasitic inductance and capacitance. The use of 0603 output-matching resistors produces a
measurable decrease in bandwidth.
When the signal is on a 50-Ω or 75-Ω controlled impedance transmission line, the layout then becomes much
less critical. The transition from the 50-Ω or 75-Ω transmission line to the amplifier pins is the most critical area.
12.2 Layout Example
Figure 64. Layout Example
36
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Device Nomenclature
Legend:
LMH2832
= Pin 1 Designator
LMH2832 = Device Name
IRHA
TI = Texas Instruments
TI YMS
YM = Year Month Date Code
LLLL
S = Assembly Site Code
LLLL = Assembly Lot Code
Figure 65. Device Marking Information
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• ADS54J40 Dual-Channel, 14-Bit, 1.0-GSPS Analog-to-Digital Converter Data Sheet (SBAS714)
• LMH3401 7-GHz, Ultra-Wideband, Fixed-Gain, Fully-Differential Amplifier Data Sheet (SBOS695)
• LMH5401 8-GHz, Low-Noise, Low-Power, Fully-Differential Amplifier Data Sheet (SBOS710)
• LMH6521 High Performance Dual DVGA Data Sheet (SNOSB47)
• LMH3404 Dual-Channel, 7-GHz, Low-Noise, Low-Power, Fully Differential Amplifier Data Sheet (SBOS739)
• LMH3402 Dual, Selectable-Gain, 7-GHz, Low-Noise, Low-Power, Fully Differential Amplifier Data Sheet
(SBOS744)
• LMH2832EVM-50 Evaluation Module User's Guide (SLOU454)
• LMH2832EVM-75 Evaluation Module User's Guide (SLOU438)
• LMH2832 TINA-TI Reference Design (SBOMA21)
• LMH2832 TINA-TI Spice Model (SBOMA22)
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
Keysight Technologies is a trademark of Keysight Technologies.
SPI is a trademark of Motorola Mobility LLC.
All other trademarks are the property of their respective owners.
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13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
38
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMH2832IRHAR
ACTIVE
VQFN
RHA
40
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
LMH2832
IRHA
LMH2832IRHAT
ACTIVE
VQFN
RHA
40
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
LMH2832
IRHA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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