LMH6504
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SNOSA96D – NOVEMBER 2003 – REVISED MARCH 2013
LMH6504 Wideband, Low Power, Variable Gain Amplifier
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FEATURES
DESCRIPTION
•
The LMH™6504 is a wideband DC coupled voltage
controlled gain stage followed by a high-speed
current feedback Op Amp which can directly drive a
low impedance load. Gain adjustment range is 80 dB
for up to 10 MHz by varying the gain control input
voltage, VG.
1
23
•
•
•
•
•
•
•
•
•
•
•
•
•
•
VS = ±5V, TA = 25°C, RF = 1 KΩ, RG = 100Ω, RL
= 100Ω, AV = AVMAX = 9.7V/V, Typical values
unless specified.
−3 dB BW 150 MHz
Gain control BW 150 MHz
Adjustment range ( 1500 V/μs) and
can also drive a heavy load current (60 mA). Near
ideal input characteristics (i.e. low input bias current,
low offset, low pin 3 resistance) enable the device to
be easily configured as an inverting amplifier as well
(see Application Information section for details).
Variable attenuator
AGC
Voltage controlled filter
Video imaging processing
Typical Application
30
12
20
11
10
10
GAIN (dB)
25°C
7
-40
-50
125°C
125°C
6
5
(V/V)
25°C
V
+
8
6
3
7
RG
100:
4
5
V
-
RF
1 k:
RL
100:
4
-55°C
-60
3
-70
2
-80
1
-90
-0.5
2
8
-20
-30
VIN
9
-55°C
dB
1
GAIN (V/V)
0
-10
VG
0
0
0.5
1
1.5
2
VG (V)
Figure 1. Gain vs. VG
Figure 2. AVMAX = 9.7 V/V
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LMH is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
LMH6504
SNOSA96D – NOVEMBER 2003 – REVISED MARCH 2013
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DESCRIPTION CONTINUED
LMH6504 gain control is linear in dB for a large portion of the total gain control range. This makes the device
suitable for AGC applications. For linear gain control applications, see the LMH6503 data sheet.
The combination of minimal external components and small outline packages (SOIC and VSSOP) allows the
LMH6504 to be used in space-constrained applications.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
ESD Tolerance
(1)
(2)
:
Human Body Model
1000V
Machine Model
100V
Input Current
±10 mA
Output Current
120 mA
−
+
Supply Voltages (V - V )
(3)
12.6V
Voltage at Input/ Output pins
V+ +0.8V, V− −0.8V
Storage Temperature Range
−65°C to 150°C
Junction Temperature
150°C
Soldering Information:
(1)
(2)
(3)
Infrared or Convection (20 sec)
235°C
Wave Soldering (10 sec)
260°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical
Characteristics.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
The maximum output current (IOUT) is determined by device power dissipation limitations or value specified, whichever is lower.
Operating Ratings
Supply Voltages (V+ - V−)
Temperature Range
Thermal Resistance:
(1)
2
7V to 12V
(1)
−40°C to +85°C
(θJC)
(θJA)
8-Pin SOIC
60
165
8-Pin VSSOP
65
235
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
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Electrical Characteristics (1)
Unless otherwise specified, all limits are specified for TA = 25°C, VS = ±5V, AVMAX = 9.7 V/V, RF = 1 kΩ, RG = 100Ω,
VIN = ±0.1V, RL = 100Ω, VG = +2V. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(2)
Typ
(2)
Max
(2)
Units
Frequency Domain Response
VOUT < 1 VPP
150
VOUT < 4 VPP, AVMAX = 100
58
VOUT < 1 VPP
0.9V ≤ VG ≤ 2V, ±0.2 dB
40
BW
-3dB Bandwidth
GF
Gain Flatness
Att Range
Flat Band (Relative to Max Gain)
Attenuation Range (3)
±0.2 dB Flatness, f < 30 MHz
26
±0.1 dB Flatness, f < 30 MHz
9.5
BW
Control
Gain control Bandwidth
VG = 1V
CT (dB)
Feed-through
VG = 0V, 30 MHz
(Output/Input)
−53
GR
Gain Adjustment Range
f < 10 MHz
80
f < 30 MHz
73
(4)
MHz
MHz
dB
150
MHz
dB
dB
Time Domain Response
tr, tf
Rise and Fall Time
OS %
Overshoot
SR
Slew Rate
0.5V Step
(5)
2.1
ns
20
%
4V Step, Non Inverting
800
4V Step, Inverting
1500
V/μs
Distortion & Noise Performance
HD2
2nd Harmonic Distortion
HD3
3rd Harmonic Distortion
THD
Total Harmonic Distortion
En tot
Total Equivalent Input Noise
f > 1 MHz, RSOURCE = 50Ω
4.4
nV/√Hz
IN
Input Noise Current
f > 1 MHz
2.6
pA/√Hz
DG
Differential Gain
f = 4.43 MHz, RL = 100Ω
0.45
%
DP
Differential Phase
0.13
deg
(1)
(2)
(3)
(4)
−47
2VPP, 20 MHz
–55
dBc
−45
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No parametric performance is indicated in the electrical tables under conditions of
internal self-heating where TJ > TA.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested on shipped production material.
Flat Band Attenuation (Relative To Max Gain) Range Definition: Specified as the attenuation range from maximum which allows gain
flatness specified (either ±0.2dB or ±0.1dB), relative to AVMAX gain. For example, for f < 30 MHz, here are the Flat Band Attenuation
ranges:±0.2 dB: 19.7 dB down to -6.3 dB = 26 dB range±0.1 dB: 19.7 dB down to 10.2 dB = 9.5 dB range
Gain control frequency response schematic:
RF
1 k:
+0.2 VDC
+VIN
ROUT
50:
+
R1
50:
LMH6504
VG
RG
100:
PORT 1
(5)
+5V
C1
0.01 PF
RF IN
RT
50:
PORT 2
RL
50:
RP1
10 k:
1V DC
-5V
Slew rate is the average of the rising and falling slew rates.
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Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are specified for TA = 25°C, VS = ±5V, AVMAX = 9.7 V/V, RF = 1 kΩ, RG = 100Ω,
VIN = ±0.1V, RL = 100Ω, VG = +2V. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(2)
Typ
(2)
Max
(2)
Units
DC & Miscellaneous Performance
GACCU
Gain Accuracy
(See Application Note)
VG = 2.0V
G Match
Gain Matching
(See Application Note
VG = 2.0V
—
±0.42
0.8V < VG < 2V
—
+2.8/−4.2
K
Gain Multiplier
(See Application Notes)
0.965
1.01
1.02
0.8V < VG < 2V
0.920
0.916
VIN NL
RG Open
Input Voltage Range
VIN L
±3.2
±6.8
mA
Pin 2
(6)
(7) (8)
TC IBIAS
Bias Current Drift
Pin 2
RIN
Input Resistance
CIN
Input Capacitance
IVG
VG Bias Current
Pin 1, VG = 2V
TC IVG
VG Bias Drift
Pin 1
R VG
VG Input Resistance
C VG
VG Input Capacitance
−1.4
−3.5
−3.7
µA
±200
pA/°C
Pin 2
7
MΩ
Pin 2
2.8
pF
0.9
µA
10
pA/°C
Pin 1
25
MΩ
Pin 1
2.8
pF
(6)
(7)
RL = 100Ω
±2.0
±1.7
±2.2
V
RL = Open
±3.1
0.12
Ω
±80
mA
ROUT
Output Impedance
DC
IOUT
Output Current
VOUT = ±4V from Rails
VO
Output Offset Voltage
0V < VG < 2V
±60
±40
±10
+PSRR
+Power Supply Rejection Ratio
(9)
Input Referred, 1V change, VG =
2.2V
–65
–76
−PSRR
−Power Supply Rejection Ratio
(9)
Input Referred, 1V change, VG =
2.2V
–65
–88
IS
Supply Current
No Load
8.5
6.5
11
4
V/V
±4.8
±4.0
Bias Current
(6)
(7)
(8)
(9)
dB
V
IBIAS
OFFSET
dB
±0.68
Pin 3
VOUT NL
±3.9
±0.48
±0.40
RG Current
Output Voltage Range
±0.45
RG = 100Ω
I RG_MAX
VOUT L
0
±0.33
±55
±70
mV
dB
dB
15
16
mA
Positive current corresponds to current flowing into the device.
Drift determined by dividing the change in parameter distribution at temperature extremes by the total temperature change.
Input bias current drift with temperature can be either positive or negative for a given sample.
+PSRR definition: [|ΔVOUT/ΔV+| / AV], −PSRR definition: [|ΔVOUT/ΔV−| / AV] with 0.1V input voltage. ΔVOUT is the change in output
voltage with offset shift subtracted out.
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SNOSA96D – NOVEMBER 2003 – REVISED MARCH 2013
CONNECTION DIAGRAM
8-Pin Package
(Top View)
VG
1
8
2
7
VIN
+
V
I
-
X1
RG
GND
3
4
6
+
5
VOUT
V-
See Package Number D0008A (SOIC)
and DGK008A (VSSOP)
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Typical Performance Characteristics
Unless otherwise specified: VS = ±5V, TA = 25°C, VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL
= 100Ω, Typical values.
Frequency Response Over Temperature
1
-1
100
0
50
-1
0
-2
150
85°C
VG = 0.90V
GAIN
25°C
PHASE
-100
85°C
-5
-150
0
-3
-200
-7
PIN = -22 dBm
SEE NOTE 10
-9
100k
10k
1M
10M
100M
VG = 0.90V
-200
-250
-7
-300
-8
-350
-9
PIN = -22 dBm
-350
1k
1G
-300
SEE NOTE 11
10k
100k
1M
100M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 3.
Figure 4.
1G
Inverting Frequency Response
4
150
2
100
3
-60
GAIN
4 VPP
GAIN
50
0
-180
-6
-100
AVMAX = 2
-150
RF = 1k:
RG = 510:
-200
-12
PIN = 4 dBm
-250
-14
0.6V < VG < 2.0V
SEE NOTE 11
-300
1k
100k
10k
1M
10M
100M
PHASE
5 VPP
-6
-420
SEE NOTE 11
-9
-350
-16
-300
-540
0
1G
50
Figure 5.
Figure 6.
Frequency Response for Various VG (AVMAX = 100)
(Large Signal)
2
RF = 2.4 k:
20
0
0.8V
RG = 27:
0
-2
PIN = -24 dBm
SEE NOTE 11
-2
-20
-4
-40
-3
0.6V
PHASE
0
1 VPP
-60
-4
GAIN (dB)
-1
50
GAIN
AVMAX = 100V/V
PHASE (°)
0.6V
Frequency Response for Various Amplitudes
40
1
0
-50
-100
PHASE
-150
-6
-8
-200
2 VPP
0.8V
-80
-5
1.0V
-100
-6
-250
-10
4 VPP
-12
-300
SEE NOTE 11
2.0V
-120
-7
200
FREQUENCY (MHz)
FREQUENCY (Hz)
GAIN
150
100
PHASE (°)
-8
-10
2 VPP
-3
PHASE (°)
-50
PHASE (°)
PHASE
-4
GAIN (dB)
0
-2
GAIN (dB)
-150
-6
-250
0
GAIN (dB)
-100
VG = 1.0V
-5
Frequency Response (AVMAX = 2)
-350
-14
f (20 MHz/DIV)
f (10 MHz/DIV)
Figure 7.
6
-50
VG = 2.0V
-4
25°C
-6
1k
50
VG = 2.0V
VG = 1.0V
PHASE (°)
-50
-40°C
-4
GAIN (dB)
-3
-8
100
PHASE
PHASE (°)
GAIN (dB)
1
-40°C
GAIN
0
-2
Frequency Response for Various VG
150
Figure 8.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, TA = 25°C, VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL
= 100Ω, Typical values.
Gain Control Frequency Response
20
10
80
18
5
40
16
25°C
40°C
85°C
40°C
-80
25°C
-15
-120
12
10
85°C
-160
-25
VG (AC) = -13.7 dBm
-200
6
-30
VIN = 0.2V (DC)
-240
4
-35
VG = 0.98 AVERAGE
SEE NOTE 12
-280
2
-320
0
10M
1M
100M
25°C
8
-20
-40
100k
RL = OPEN
14
-40
IS (mA)
-5
-10
VG = VG_MIN
85°C
0
PHASE
ANGLE S21
MAG
0
|S21| (dB)
IS vs. VS
120
15
-40°C
1G
3
3.5
FREQUENCY (Hz)
4
Figure 9.
5
5.5
6
Figure 10.
IS vs. VS
Input Bias Current vs. VS
-1.26
20
-1.28
RL = OPEN
18
-1.3
16
85°C
-1.32
14
-1.34
12
10
IB (PA)
IS (mA)
4.5
±SUPPLY VOTLAGE (V)
25°C
-40°C
-1.36
-1.38
8
25°C
-1.4
6
-1.42
-40°C
4
-1.44
2
-1.46
85°C
-1.48
0
3
3.5
4
4.5
5
5.5
3.5
3
6
4
4.5
5
5.5
6
±SUPPLY VOLTAGE (V)
±SUPPLY VOTLAGE (V)
Figure 11.
Figure 12.
PSRR
AVMAX vs. Supply Voltage
0
12
SEE NOTE 9
-10
85°C
10
-20
AVMAX (V/V)
PSRR (dB)
-30
-40
+PSRR
-50
-60
8
25°C
6
-40°C
4
-70
-80
2
-PSRR
-90
-100
100
0
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
2.5
3
3.5
4
4.5
5
5.5
6
±SUPPLY VOLTAGE
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, TA = 25°C, VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL
= 100Ω, Typical values.
Feed through Isolation for Various AVMAX
Gain Variation Over entire Temp Range vs. VG
60
100
20
GAIN (dB)
0
-20
AVMAX = 100
-40
TEMP RANGE: -55°C TO 125°C
|GAINCOLD - GAINHOT|
OVER TEMP. GAIN CHANGE (dB)
40
AVMAX = 2
AVMAX = 10
-60
10
1
-80
-100
100
0
10k 100k 1M
10M 100M 1G
0
0.5
1
FREQUENCY (Hz)
Figure 15.
IRG vs. VIN
SEE NOTE 7
-6
-4
12
20
11
10
10
-2
0
+2
dB
+6
-0.5
-1
0
0.5
1
1.5
7
-30
125°C
-40
25°C
125°C
4
-55°C
-60
3
-70
2
-80
1
-90
-0.5
0
0
0.5
1
1.5
2
VG (V)
Figure 17.
Figure 18.
Gain vs. VG Including Limits
Output Offset Voltage vs. VG (Typical Unit #1)
10
30
VIN = 0.1V
-40°C
5
10
-10
VO_OFFSET (mV)
0
GAIN (dB)
6
5
(V/V)
VIN (V)
MAX/MIN VALUE = ±5
SIGMA FROM TYPICAL
-20
MAX
-30
-40
0
25°C
-5
85°C
MIN
-10
-50
TYPICAL
-15
-70
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0
0.5
1
1.5
2
2.5
VG (V)
VG (V)
Figure 19.
8
8
25°C
-20
-50
+4
9
-55°C
-10
GAIN (dB)
IR G (mA)
30
0
+8
-1.5
2.5
Gain vs. VG
-8
-60
2
Figure 16.
-10
20
1.5
VG (V)
GAIN (V/V)
1k
Figure 20.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, TA = 25°C, VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL
= 100Ω, Typical values.
Output Offset Voltage vs. VG (Typical Unit #2)
Output Offset Voltage vs. VG (Typical Unit #3)
30
30
25°C
25°C
25
85°C
VO_OFFSET (mV)
VO_OFFSET (mV)
25
20
15
10
85°C
20
15
-40°C
10
5
85°C
5
25°C
-40°C
0
0
0
0.5
1
1.5
2
2.5
0
0.5
1
VG (V)
2
2.5
VG (V)
Figure 21.
Figure 22.
Distribution of Output Offset Voltage
Output Noise Density vs. Frequency
10000
26
24
22
RSOURCE - 50:
20
18
16
14
eno (nV/ Hz)
RELATIVE FREQUENCY (%)
1.5
12
10
8
VG_MAX
1000
VG_MID
VG_MIN
100
6
4
2
0
10
1
10
1k
100
-60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60
10k 100k
1M
10M
FREQUENCY (Hz)
OFFSET VOLTAGE (mV)
Figure 23.
Figure 24.
Output Noise Density vs. Frequency
Output Noise Density vs. Frequency
100000
10000
AVMAX = 100
VG_MAX
RG = 510:
RG = 22:
RSOURCE = 50:
RSOURCE = 50:
eno (nV/ Hz)
eno (nV/ Hz)
10000
AVMAX = 2
RF = 2.4 k:
VG_MID
1000
VG_MAX
1000
VG_MID
100
100
VG_MIN
VG_MIN
10
10
1
10
100
1k
10k
100k
1M 10M
1
10
100
1k
10k 100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 25.
Figure 26.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, TA = 25°C, VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL
= 100Ω, Typical values.
Input Referred Noise Density vs. Frequency
1000
Output Voltage vs. Output Current (Sinking)
5
1000
25°C
-40°C
85°C
Hz)
10
10
-
100
VOLTAGE
VOUT FROM V (V)
100
Ini (pA/
eni (nV/ Hz)
4
3
2
1
1
0
1
10
100
25°C
85°C
CURRENT
1
-40°C
10k 100k
1k
1M
20
0
10M
80
FREQUENCY (Hz)
Figure 27.
Figure 28.
100
120
Distortion vs. Frequency
-30
5
85°C
VG = VG_MAX
-40°C
-40
VOUT = 1 VPP
25°C
4
-50
THD
3
HD (dBc)
VOUT FROM V (V)
60
IOUT (mA)
Output Voltage vs. Output Current (Sourcing)
+
40
-40°C
2
-60
-70
HD3
85°C
-80
HD2
1
-90
-100
100k
0
20
0
40
60
80
100
120
1M
IOUT (mA)
Figure 29.
-80
THD (dBc)
HD (dBc)
-80
-70
HD2, 2 MHz
-50
-70
2 MHz
-60
20 MHz
-50
-40
HD2, 25 MHz
HD3, 25 MHz
-30
-15
-10
-5
0
5
10
25 MHz
-40
VG = VGMAX
-20
15
-30
20
POUT (dBm)
Figure 31.
10
1 MHz
HD3, 2 MHz
-60
VG = VG_MAX
100 kHz
-90
HD2, 100 kHz
-100
-90
THD vs. POUT
-100
HD3, 100 kHz
-110
30M
Figure 30.
HD vs. POUT
-120
10M
FREQUENCY (Hz)
-15
-10
-5
0
5
POUT (dBm)
10
15
20
Figure 32.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, TA = 25°C, VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL
= 100Ω, Typical values.
THD vs. POUT
THD vs. Gain
80
-100
-90
70
100 kHz
-80
1 MHz
60
20 MHz
40
30
2 MHz
-60
THD (dBc)
|THD (dBc)|
-70
50
-50
-40
25 MHz
-30
20
-20
10
VG = VGMID
0
-10
-5
VOUT = 0.25 VPP
-10
0
10
5
15
VG VARIED
0
-15 -10
20
-5
0
POUT (dBm)
10
15
THD vs. Gain
Differential Gain & Phase
0.6
-80
25
Figure 34.
-90
0.19
f = 4.43 MHz
100 kHz
VOUT = 1 VPP
20
GAIN (dB)
Figure 33.
VG VARIED
RL = 100:
0.5
0.16
VG = VGMAX
-70
0.4
DG (%)
-50
-40
-30
0.13
0.3
0.1
DP
0.2
0.07
25 MHz
DG
0.1
DP (°)
2 MHz
-60
THD (dBc)
5
0.04
-20
0
-10
0
-5
0
5
10
15
20
0.01
-0.1
-1.4
-1
-0.6 -0.2
0.2
0.6
1
-0.02
1.4
VOUT DC (V)
GAIN (dB)
Figure 35.
Figure 36.
VG Bias Current vs. VG
Output Impedance
100
940
920
IMPEDANCE (:)
10
IG (nA)
900
880
860
1
0.1
840
0.01
820
0
0.5
1
1.5
2
2.5
3
1k
10k
100k
1M
10M
FREQUENCY (Hz)
VG (V)
Figure 37.
Figure 38.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VS = ±5V, TA = 25°C, VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL
= 100Ω, Typical values.
Step Response Plot
Step Response Plot
VG = VG_MID
0.5 VPP SMALL SIGNAL
SS REF
SS REF
0.5 VPP SMALL SIGNAL
LS REF
LS REF
4 VPP LARGE SIGNAL
4 VPP LARGE SIGNAL
10 ns/DIV
10 ns/DIV
Figure 39.
Figure 40.
Gain vs. VG Step
2.5
10
GAIN
2
8
7
6
1.5
5
1
4
GAIN (V/V)
VG
VG (V)
9
3
0.5
2
VIN = 0.3V
0
1
0
t (10 ns/DIV)
Figure 41.
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APPLICATION INFORMATION
GENERAL DESCRIPTION
The key features of the LMH6504 are:
• Low power
• Broad voltage controlled gain and attenuation range (From AVMAX down to complete cutoff)
• Bandwidth independent, resistor programmable gain range (RG)
• Broad signal and gain control bandwidths
• Frequency response may be adjusted with RF
• High impedance signal and gain control inputs
Refer to Figure 42 below. The LMH6504 combines a closed loop input buffer (“X1” Block), a voltage controlled
variable gain cell (“MULT” Block) and an output amplifier (“CFA” Block). The input buffer is a transconductance
stage whose gain is set by the gain setting resistor, RG. The output amplifier is a current feedback op amp and is
configured as a transimpedance stage whose gain is set by, and is equal to, the feedback resistor, RF. The
maximum gain, AVMAX, of the LMH6504 is defined by the ratio: K · RF / RG where “K” is the gain multiplier with a
nominal value of 0.965. As the gain control input (VG) changes over its 0 to 2V range, the gain is adjusted over a
range of about 80 dB relative to the maximum set gain.
INPUT
SIGNAL
GAIN
CONTROL
5V
+VCC
VG
MULT
VIN
RX
50:
IX1
RIN
50:
-
RO OUTPUT
50:
CFA
GND
0.1 µF
RF
1 k:
VO
RG
+
6.8 µF
-VCC
+
RG
100:
0.1 µF
6.8 µF
+
-5V
Figure 42. LMH6504 Typical Application and Block Diagram
SETTING THE LMH6504 MAXIMUM GAIN
AVMAX =
RF
RG
·K
(1)
Although the LMH6504 is specified at AVMAX = 9.7V/V, the recommended AVMAX varies between 2 and 100.
Higher gains are possible but usually impractical due to output offsets, noise and distortion. When varying AVMAX
several tradeoffs are made:
RG: determines the input voltage range
RF: determines overall bandwidth
The amount of current which the input buffer can source/sink into RG is limited and is specified in the IRG_MAX
spec. This sets the maximum input voltage:
VIN (MAX) = IR G MAX · RG
(2)
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As the IRG_MAX limit is approached (with increasing input voltage or with lowering of RG), the device harmonic
distortion will increase. Changes in RF will have a dramatic effect on the small signal bandwidth. The output
amplifier of the LMH6504 is a current feedback amplifier (CFA) and its bandwidth is determined by RF. As with
any CFA, doubling the feedback resistor will roughly cut the bandwidth of the device in half. For more about
CFA’s, see the basic tutorial, OA-20, “Current Feedback Myths Debunked” (SNOA376), or a more rigorous
analysis, OA-13, “Current Feedback Amplifier Loop Gain Analysis and Performance Enhancements” (SNOA366).
OTHER CONFIGURATIONS
1) Single Supply Operation
The LMH6504 can be configured for use in a single supply environment. Doing so requires the following:
a. Bias pin 4 and RG to a “virtual half supply” somewhere close to the middle of V+ and V-range. The other end
of RG is tied to pin 3. The “virtual half supply” needs to be capable of sinking and sourcing the expected
current flow through RG.
b. Ensure that VG can be adjusted from 0V to 2V above the “virtual half supply”.
c. Bias the input (pin 2) to make sure that it stays within the range of 1.8V above V-to 1.8V below V+ (see “Input
voltage Range” specification in the Electrical Characteristics table). This can be accomplished by either DC
biasing the input and AC coupling the input signal, or alternatively, by direct coupling if the output of the
driving stage is also biased to half supply.
Arranged this way, the LMH6504 will respond to the current flowing through RG. The gain control relationship will
be similar to the split supply arrangement with VG measured referenced to pin 4. Keep in mind that the circuit
described above will also center the output voltage to the “virtual half supply voltage”.
2) Arbitrarily Referenced Input Signal
Having a wide input voltage range on the input (pin 2) (+/-3.2V typical), the LMH6504 can be configured to
control the gain on signals which are not referenced to ground (e.g. Half Supply biased circuits, etc.). We will call
this node the “reference node”. In such cases, the other end of RG (the side not tied to pin 3) can be tied to this
reference node so that RG will “look at” the difference between the signal and this reference only. Keep in mind
that the reference node needs to source and sink the current flowing through RG.
Application Information
GAIN ACCURACY
Gain accuracy is defined as the actual gain compared against the theoretical gain at a certain VG (results
expressed in dB) (See Figure 43).
Theoretical gain is given by:
A(V/V) = K x
RF
RG
1
N - VG
x
1+e
VC
(3)
Where K = 0.965 (nominal) N = 0.96V & VC = 80mV @ room temperature
For a VG range, the value specified in the tables represents the worst case accuracy over the entire range. The
"Typical" value would be the worst case difference between the "Typical gain" and the "Theoretical gain". The
"Max" value would be the worst case difference between the actual gain and the "Theoretical gain" for the entire
population.
GAIN MATCHING
Gain matching as the limit on gain variation at a certain VG (expressed in dB) (see Figure 43) and is specified as
"Max" only (no "Typical"). For a VG range, the value specified represents the worst case matching over the entire
range. The "Max" value would be the worst case difference between the actual gain and the typical gain for the
entire population.
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MAX GAIN LIMIT
THEORETICAL GAIN
GAIN (dB)
MIN GAIN LIMIT
D
TYPICAL GAIN
C
B
PARAMETER:
A
GAIN ACCURACY (TYPICAL) = B-C
GAIN ACCURACY (MAX/MIN) = (D-C)/(A-C)
GAIN MATCHING (MAX/MIN) = (D-B)/(A-B)
VG (V)
Figure 43. LMH6504 Gain Accuracy & Gain Matching Defined
GAIN PARTITIONING
If high levels of gain are needed, gain partitioning should be considered:
VG
VIN
+
25:
1
2
LMH6624
6
RC
-
LMH6504
VO
3
7
4
R2
R1
RF
RG
Figure 44. Gain Partitioning
The maximum gain range for this circuit is given by the following equation:
R2
MAXIMUM GAIN =
1+
R1
RF
·
RG
·K
(4)
The LMH6624 is a low noise wideband voltage feedback amplifier. Setting R2 at 909Ω and R1 at 100Ω produces
a gain of 20 dB. Setting RF at 1000Ω as recommended and RG at 50Ω, produces a gain of about 26 dB in the
LMH6504. The total gain of this circuit is therefore approximately 46 dB. It is important to understand that when
partitioning to obtain high levels of gain, very small signal levels will drive the amplifiers to full scale output. For
example, with 46 dB of gain, a 20 mV signal at the input will drive the output of the LMH6624 to 200 mV, the
output of the LMH6504 to 4V. Accordingly, the designer must carefully consider the contributions of each stage
to the overall characteristics. Through gain partitioning the designer is provided with an opportunity to optimize
the frequency response, noise, distortion, settling time, and loading effects of each amplifier to achieve improved
overall performance.
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LMH6504 GAIN CONTROL RANGE AND MINIMUM GAIN
Before discussing Gain Control Range, it is important to understand the issues which limit it. The minimum gain
of the LMH6504, theoretically, is zero, but in practical circuits is limited by the amount of feedthrough, here
defined as the gain when VG = 0V. Capacitive coupling through the board and package as well as coupling
through the supplies will determine the amount of feedthrough. Even at DC, the input signal will not be
completely rejected. At high frequencies feedthrough will get worse because of its capacitive nature. At
frequencies below 10 MHz, the feed through will be less than −60 dB and therefore, it can be said that with
AVMAX = 20 dB, the gain control range is 80 dB.
LMH6504 GAIN CONTROL FUNCTION
In the plot, Gain vs. VG, we can see the gain as a function of the control voltage. The “Gain (V/V)” plot,
sometimes referred to as the S-curve, is the linear (V/V ) gain. This is a hyperbolic tangent relationship and is
given by Equation 3. The “Gain (dB)” plots the gain in dB and is linear over a wide range of gains. Because of
this, the LMH6504 gain control is referred to as “linear-in-dB.”
For applications where the LMH6504 will be used at the heart of a closed loop AGC circuit, the S-curve control
characteristic provides a broad linear (in dB) control range with soft limiting at the highest gains where large
changes in control voltage result in small changes in gain. For applications requiring a fully linear (in dB) control
characteristic, use the LMH6504 at half gain and below (VG ≤ 1V).
AVOIDING OVERDRIVE OF THE LMH6504 GAIN CONTROL INPUT
There is an additional requirement for the LMH6504 Gain Control Input (VG): VG must not exceed +2.3V (with
±5V supplies). The gain control circuitry may saturate and the gain may actually be reduced. In applications
where VG is being driven from a DAC, this can easily be addressed in the software. If there is a linear loop
driving VG, such as an AGC loop, other methods of limiting the input voltage should be implemented. One simple
solution is to place a 2.2:1 resistive divider on the VG input. If the device driving this divider is operating off of
±5V supplies as well, its output will not exceed 5V and through the divider VG can not exceed 2.3V.
IMPROVING THE LMH6504 LARGE SIGNAL PERFORMANCE
Figure 45 illustrates an inverting gain scheme for the LMH6504.
VG
1
2
6
LMH6504
25:
VO
3
VIN
7
RG
4
RF
Figure 45. Inverting Amplifier
The input signal is applied through the RG resistor. The VIN pin should be grounded through a 25Ω resistor. The
maximum gain range of this configuration is given in the following equation:
AVMAX = -
RF
·K
RG
(5)
The inverting slew rate of the LMH6504 is much higher than that of the non-inverting slew rate. This 2X
performance improvement comes about because in the non-inverting configuration, the slew rate of the overall
amplifier is limited by the input buffer. In the inverting circuit, the input buffer remains at a fixed voltage and does
not affect slew rate.
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TRANSMISSION LINE MATCHING
One method for matching the characteristic impedance of a transmission line is to place the appropriate resistor
at the input or output of the amplifier. Figure 46 shows a typical circuit configuration for matching transmission
lines.
VG
CO
ZO
1
2
ZO
6
RS
SIGNAL
INPUT
RI
+-
OUTPUT
LMH6504
3
RO
7
RT
4
RG
RF
Figure 46. TRANSMISSION LINE MATCHING
The resistors RS, RI, RO, and RT are equal to the characteristic impedance, ZO, of the transmission line or cable.
Use CO to match the output transmission line over a greater frequency range. It compensates for the increase of
the op amp’s output impedance with frequency.
MINIMIZING PARASITIC EFFECTS ON SMALL SIGNAL BANDWIDTH
The best way to minimize parasitic effects is to use surface mount components and to minimize lead lengths and
component distance from the LMH6504. For designs utilizing through-hole components, specifically axial
resistors, resistor self-capacitance should be considered. Example: the average magnitude of parasitic
capacitance of RN55D 1% metal film resistors is about 0.15 pF with variations of as much as 0.1 pF between
lots. Given the LMH6504’s extended bandwidth, these small parasitic reactance variations can cause
measurable frequency response variations in the highest octave. We therefore recommend the use of surface
mount resistors to minimize these parasitic reactance effects.
RECOMMENDATIONS
Here are some recommendations to avoid problems and to get the best performance:
• Do not place a capacitor across RF. However, an appropriately chosen series RC combination could be used
to shape the frequency response.
• Keep traces connecting RF separated and as short as possible
• Place a small resistor (20-50Ω) between the output and CL
• Cut away the ground plane, if any, under RG
• Keep decoupling capacitors as close as possible to the LMH6504.
• Connect pin 2 through a minimum resistance of 25Ω.
ADJUSTING OFFSETS AND DC LEVEL SHIFTING
Offsets can be broken into two parts: an input-referred term and an output-referred term. These errors can be
trimmed using the circuit in Figure 47. First set VG to 0V and adjust the trim pot R4 to null the offset voltage at the
output. This will eliminate the output stage offsets. Next set VG to 2V and adjust the trim pot R1 to null the offset
voltage at the output. This will eliminate the input stage offsets.
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VG
1
2
VIN
6
VO
LMH6504
3
RF
7
+5V
4
R2
10 k:
R1
10 k:
+5V
RG
R3
10 k:
R4
10 k:
0.1 µF
0.1 µF
-5V
-5V
Figure 47. OFFSET ADJUST CIRCUIT
DIGITAL GAIN CONTROL
Digitally variable gain control can be easily realized by driving the LMH6504’s gain control input with a digital-toanalog converter (DAC). Figure 48 illustrates such an application. This circuit employs Texas Instruments' eightbit DAC0830, the LMC8101 MOS input op-amp (Rail-to-Rail Input/Output), and the LMH6504 VGA. With VREF set
to 2V, the circuit provides up to 80 dB of gain control in 256 steps with up to 0.05% full scale resolution. The
maximum gain of this circuit is 20 dB.
DIGITAL
INPUT
RFB
Io1
VREF
LMC8101
DAC0830
Io2
+
VIN
2
1
6
VO
LMH6504
3
7
4
RG
100:
RF
1 k:
Figure 48. Digital Gain Control
USING THE LMH6504 IN AGC APPLICATIONS
In AGC applications, the control loop forces the LMH6504 to have a fixed output amplitude. The input amplitude
will vary over a wide range and this can be the issue that limits dynamic range. At high input amplitudes, the
distortion due to the input buffer driving RG may exceed that which is produced by the output amplifier driving the
load. In the plot, Distortion vs. Gain, total harmonic distortion (THD) is plotted over a gain range of nearly 35 dB
for a fixed output amplitude of 0.25 VPP in the specified configuration, RF = 1k, RG = 100Ω. When the gain is
adjusted to -15 dB (i.e. 35 dB down from AVMAX), the input amplitude would be 1.41 VPP and we can see the
distortion is at its worst at this gain. If the output amplitude of the AGC were to be raised above 0.25 VPP, the
input amplitudes for gains 40 dB down from AVMAX would be even higher and the distortion would degrade
further. It is for this reason that we recommend lower output amplitudes if wide gain ranges are desired. Using a
post-amp like the LMH6714/ 6720/ 6722 family or LMH6702 would be the best way to preserve dynamic range
and yield output amplitudes much higher than 100 mVPP. Another way of addressing distortion performance and
its limitations on dynamic range, would be to raise the value of RG. Just like any other high-speed amplifier, by
increasing the load resistance, and therefore decreasing the demanded load current, the distortion performance
will be improved in most cases. With an increased RG, RF will also have to be increased to keep the same AVMAX
and this will decrease the overall bandwidth. It may be possible to insert a series RC combination across RF in
order to counteract the negative effect on BW when a large RF is used.
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AUTOMATIC GAIN CONTROL (AGC) #1
Fast Response AGC Loop
The AGC circuit shown in Figure 49 will correct a 6 dB input amplitude step in 100 ns. The circuit includes a two
op-amp precision rectifier amplitude detector (U1 and U2), and an integrator (U3) to provide high loop gain at low
frequencies. The output amplitude is set by R9. Some notes on building fast AGC loops: Precision rectifiers work
best with large output signals. Accuracy is improved by blocking DC offsets, as shown in Figure 49.
INCLUDES SCOPE
PROBE CAPACITANCE
C3
40 pF
1
2
VIN
+
U4
LMH6504
0.1 VPP
-
7
3
R10
500:
RG
100:
OUTPUT
20 MHz,
6
C1
1.0 µF
RF
4
R1
20:
C2
680 pF
R8
500:
-
R5
25:
R3
300:
+
U2
LMH6714
U3
LMH6609
-
+
R4
300:
R6
300:
R9
4.22 k:
R7
300:
U1
LMH6714
1N5712
SCHOTTKY
+
-5V
R2
25:
Figure 49. Automatic Gain Control Circuit #1
Signal frequencies must not reach the gain control port of the LMH6504, or the output signal will be distorted
(modulated by itself). A fast settling AGC needs additional filtering beyond the integrator stage to block signal
frequencies. This is provided in Figure 49 by a simple R-C filter (R10 and C3); better distortion performance can
be achieved with a more complex filter. These filters should be scaled with the input signal frequency. Loops with
slower response time (longer integration time constants) may not need the R10 – C3 filter.
Checking the loop stability can be done by monitoring the VG voltage while applying a step change in input signal
amplitude. Changing the input signal amplitude can be easily done with an arbitrary waveform generator.
AUTOMATIC GAIN CONTROL (AGC) #2
Figure 50 illustrates an automatic gain control circuit that employs two LMH6504’s. In this circuit, U1 receives the
input signal and produces an output signal of constant amplitude. U2 is configured to provide negative feedback.
U2 generates a rectified gain control signal that works against an adjustable bias level which may be set by the
potentiometer and RB. CI integrates the bias and negative feedback. The resultant gain control signal is applied
to the U1 gain control input VG. The bias adjustment allows the U1 output to be set at an arbitrary level less than
the maximum output specification of the amplifier. Rectification is accomplished in U2 by driving both the
amplifier input and the gain control input with the U1 output signal. The voltage divider that is formed by R1 and
R2, sets the rectifier gain.
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+5V
RC
100:
RB
2 k:
LEVEL ADJ
R2
100:
150:
CI
100 pF
-5V
2
SIGNAL
INPUT
R1
100:
1
U1
LMH6504
3
6
25:
RG2
100:
4
RG1
100:
RF1
1 k:
6
U2
LMH6504
50:
2.2 µF
7
1
2
7
3
4
RF2
1 k:
OUTPUT
Figure 50. Automatic Gain Control Circuit #2
CIRCUIT LAYOUT CONSIDERATIONS & EVALUATION BOARD
A good high frequency PCB layout including ground plane construction and power supply bypassing close to the
package are critical to achieving full performance. The amplifier is sensitive to stray capacitance to ground at the
I-input (pin 7); keep node trace area small. Shunt capacitance across the feedback resistor should not be used to
compensate for this effect. Capacitance to ground should be minimized by removing the ground plane from
under the body of RG. Parasitic or load capacitance directly on the output (pin 6) degrades phase margin leading
to frequency response peaking.
The LMH6504 is fully stable when driving a 100Ω load. With reduced load (e.g. 1k.) there is a possibility of
instability at very high frequencies beyond 400 MHz especially with a capacitive load. When the LMH6504 is
connected to a light load as such, it is recommended to add a snubber network to the output (e.g. 100Ω and 39
pF in series tied between the LMH6504 output and ground). CL can also be isolated from the output by placing a
small resistor in series with the output (pin 6).
Component parasitics also influence high frequency results. Therefore it is recommended to use metal film
resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not
recommended.
Texas Instruments suggests the following evaluation board as a guide for high frequency layout and as an aid in
device testing and characterization:
Device
Package
Evaluation Board
Part Number
LMH6504
SOIC
CLC730066
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REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMH6504MA/NOPB
NRND
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LMH65
04MA
LMH6504MAX/NOPB
NRND
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LMH65
04MA
LMH6504MM/NOPB
NRND
VSSOP
DGK
8
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
A93A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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