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LMH6521
SNOSB47E – MAY 2011 – REVISED AUGUST 2016
LMH6521 High Performance Dual DVGA
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The LMH6521 contains two high performance,
digitally controlled variable gain amplifiers (DVGA).
•
•
OIP3 of 48.5 dBm at 200 MHz
Maximum Voltage Gain of 26 dB
Gain Range: 31.5 dB with 0.5-dB Step Size
Channel Gain Matching of ±0.04 dB
Noise Figure: 7.3 dB at Maximum Gain
–3-dB Bandwidth of 1200 MHz
Low Power Dissipation
Independent Channel Power Down
Three Gain Control Modes:
– Parallel Interface
– Serial Interface (SPI)
– Pulse Mode Interface
Temperature Range: –40°C to +85°C
Thermally-Enhanced, 32-Pin WQFN Package
2 Applications
•
•
•
•
•
Both channels of the LMH6521 have an independent,
digitally controlled attenuator followed by a high
linearity, differential output amplifier. Each block has
been optimized for low distortion and maximum
system design flexibility. Each channel has a high
speed power down mode.
The internal digitally controlled attenuator provides
precise 0.5-dB gain steps over a 31.5-dB range.
Serial and parallel programming options are provided.
Serial mode programming uses the SPI interface. A
pulse mode is also offered where simple up or down
commands can change the gain one step at a time.
The output amplifier has a differential output allowing
10-VPPD signal swings on a single 5-V supply. The
low impedance output provides maximum flexibility
when driving filters or analog to digital converters.
Device Information(1)
Cellular Base Stations
Wideband and Narrowband IF Sampling
Receivers
Wideband Direct Conversion
Digital Pre-Distortion
ADC Drivers
PART NUMBER
LMH6521
ATTEN_A
OUTA-
0 dB to 31.5 dB
6
LATCH _A
EN_A
PULSE_A
2
4
SPI
ATTEN_B
6
Digital
Control
LATCH _B
INB+
0.20
2.0
0.15
1.5
0.10
2
Attenuator
1.0
Gain Matching Error
0.05
0.5
0.00
0.0
-0.05
-0.5
-0.10
Phase Matching Error
-1.0
-0.15
-1.5
-0.20
-2.0
0
EN_B
PULSE_B
GAIN MATCHING ERROR (dB)
OUTA+
26 dB
INA-
5.00 mm × 5.00 mm
Channel Matching Error (Ch A – Ch B)
+5 V
INA+
WQFN (32)
BODY SIZE (NOM)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
LMH6521 Block Diagram
Attenuator
PACKAGE
4
PHASE MATCHING ERROR (degrees)
1
8 12 16 20 24 28 32
ATTENUATION (dB)
OUTB+
26 dB
INB-
0 dB to 31.5 dB
OUTB-
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6521
SNOSB47E – MAY 2011 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6
6
6
6
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
13
15
7.5 Programming........................................................... 16
8
Application and Implementation ........................ 25
8.1 Application Information............................................ 25
8.2 Typical Application .................................................. 25
9 Power Supply Recommendations...................... 28
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 28
10.3 Thermal Considerations ........................................ 29
11 Device and Documentation Support ................. 30
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
30
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2013) to Revision E
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision C (March 2013) to Revision D
•
2
Page
Page
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1
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SNOSB47E – MAY 2011 – REVISED AUGUST 2016
5 Pin Configuration and Functions
A2/CS/S1A
A1/SDO/S0A
INA+
INA±
GND
+5V
GND
A0
32
31
30
29
28
27
26
25
RTV Package
32-Pin WQFN
Top View
A3/SDI/DNA
1
24
OUTA+
A4/CLK/UPA
2
23
OUTA±
A5
3
22
ENA
MOD0
4
21
LATA
MOD1
5
20
LATB
B5
6
19
ENB
B4/UPB
7
18
OUTB±
B3/DNB
8
17
OUTB+
9
10
11
12
13
14
15
16
B2/S1B
B1/S0B
INB+
INB±
GND
+5V
GND
B0
GND
Not to scale
Pin Functions
PIN
NO.
1
NAME
A3/SDI/DNA
TYPE (1)
DESCRIPTION
I
A3: Attenuation bit three = 4-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1).
SDI: Serial data in. Digital inputs serial mode (MOD1 = 1, MOD0 = 0) SPI compatible. See
Application Information for more details.
DNA: Down pulse pin. A logic 0 pulse decreases gain one step. Digital inputs pulse mode
(MOD1 = 0, MOD0 = 1).
Pulsing this pin together with pin 2 resets the gain to maximum gain.
2
A4/CLK/UPA
I
A4: Attenuation bit four = 8-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1).
CLK: Serial clock. Digital inputs serial mode (MOD1 = 1, MOD0 = 0) SPI compatible.
UPA: Up pulse pin. A logic 0 pulse increases gain one step. Digital inputs pulse mode
(MOD1 = 0, MOD0 = 1).
Pulsing this pin together with pin 1 resets the gain to maximum gain.
3
A5
I
Attenuation bit five = 16-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1). Pins
unused in serial mode, connect to DC ground. Pins unused in pulse mode, connect to DC
ground.
4
MOD0
I
Digital mode control pins. These pins float to the logic hi state if left unconnected. Pins unused in
serial mode, connect to DC ground. See Application Information for mode settings.
5
MOD1
I
Digital mode control pins. These pins float to the logic hi state if left unconnected. Pins unused in
pulse mode, connect to DC ground. See Application Information for mode settings.
6
B5
I
Attenuation bit five = 16-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1). Pins
unused in serial mode, connect to DC ground. Pins unused in pulse mode, connect to DC
ground.
(1)
I = Input, O = Output, P = Power
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Pin Functions (continued)
PIN
NO.
7
8
9
NAME
B4/UPB
B3/DNB
B2/S1B
TYPE (1)
DESCRIPTION
I
B4: Attenuation bit four = 8-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1).
UPB: Up pulse pin. A logic 0 pulse increases gain one step. Digital inputs pulse mode
(MOD1 = 0, MOD0 = 1).
Pulsing this pin together with pin 8 resets the gain to maximum gain. Pins unused in serial mode,
connect to DC ground.
I
B3: Attenuation bit three = 4-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1).
DNB: Down pulse pin. A logic 0 pulse decreases gain one step. Digital inputs pulse mode
(MOD1 = 0, MOD0 = 1).
Pulsing this pin together with pin 7 resets the gain to maximum gain. Pins unused in serial mode,
connect to DC ground.
I
B2: Attenuation bit two = 2-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1).
S1B: Step size zero and step size 1. (0,0) = 0.5 dB; (0, 1)= 1 dB; (1,0) = 2 dB, and (1, 1)= 6 dB.
Digital inputs pulse mode (MOD1 = 0, MOD0 = 1).
Pins unused in serial mode, connect to DC ground.
10
B1/S0B
I
B1: Attenuation bit one = 1-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1).
S0B: Step size zero and step size 1. (0,0) = 0.5 dB; (0, 1)= 1 dB; (1,0) = 2 dB, and (1, 1)= 6 dB.
Digital inputs pulse mode (MOD1 = 0, MOD0 = 1).
Pins unused in serial mode, connect to DC ground.
11
INB+
I
Amplifier noninverting input. Internally biased to mid supply. Input voltage must not exceed V+ or
go below GND by more than 0.5 V.
12
INB–
I
Amplifier inverting input. Internally biased to mid supply. Input voltage must not exceed V+ or go
below GND by more than 0.5 V.
13
GND
P
Ground pin. Connect to low impedance ground plane. All pin voltages are specified with respect
to the voltage on these pins. The exposed thermal pad is internally bonded to the ground pins.
14
+5V
P
Power supply pins. Valid power supply range is 4.75 V to 5.25 V.
15
GND
P
Ground pin. Connect to low impedance ground plane. All pin voltages are specified with respect
to the voltage on these pins. The exposed thermal pad is internally bonded to the ground pins.
16
B0
I
Attenuation bit zero = 0.5-dB step. Gain steps down from maximum gain (000000 = Maximum
Gain). Digital inputs parallel mode (MOD1 = 1, MOD0 = 1). Pins unused in serial mode, connect
to DC ground. Pins unused in pulse mode, connect to DC ground.
17
OUTB+
O
Amplifier noninverting output. Externally biased to 0 V.
18
OUTB–
O
Amplifier inverting output. Externally biased to 0 V.
19
ENB
I
Enable pins. Logic 1 = enabled state. See Application Information for operation in serial mode.
20
LATB
I
Latch pins. Logic zero = active, logic 1 = latched. Gain does not change once latch is high.
Connect to ground if the latch function is not desired. Digital inputs parallel mode (MOD1 = 1,
MOD0 = 1). Pins unused in serial mode, connect to DC ground.
21
LATA
I
Latch pins. Logic zero = active, logic 1 = latched. Gain does not change once latch is high.
Connect to ground if the latch function is not desired. Digital inputs parallel mode (MOD1 = 1,
MOD0 = 1). Pins unused in serial mode, connect to DC ground.
22
ENA
I
Enable pins. Logic 1 = enabled state. See Application Information for operation in serial mode.
23
OUTA–
O
Amplifier inverting output. Externally biased to 0 V.
24
OUTA+
O
Amplifier noninverting output. Externally biased to 0 V.
25
A0
I
Attenuation bit zero = 0.5-dB step. Gain steps down from maximum gain (000000 = Maximum
Gain). Digital inputs parallel mode (MOD1 = 1, MOD0 = 1). Pins unused in serial mode, connect
to DC ground. Pins unused in pulse mode, connect to DC ground.
26
GND
P
Ground pin. Connect to low impedance ground plane. All pin voltages are specified with respect
to the voltage on these pins. The exposed thermal pad is internally bonded to the ground pins.
27
+5V
P
Power supply pins. Valid power supply range is 4.75 V to 5.25 V.
28
GND
P
Ground pin. Connect to low impedance ground plane. All pin voltages are specified with respect
to the voltage on these pins. The exposed thermal pad is internally bonded to the ground pins.
29
INA–
I
Amplifier inverting input. Internally biased to mid supply. Input voltage must not exceed V+ or go
below GND by more than 0.5 V.
30
INA+
I
Amplifier noninverting input. Internally biased to mid supply. Input voltage must not exceed V+ or
go below GND by more than 0.5 V.
4
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Pin Functions (continued)
PIN
NO.
31
32
GND
NAME
TYPE (1)
DESCRIPTION
I
A1: Attenuation bit one = 1-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1).
SDO: Serial data out. Digital inputs serial mode (MOD1 = 1, MOD0 = 0) SPI compatible.
S0A: Step size zero and step size 1. (0,0) = 0.5 dB; (0, 1)= 1 dB; (1,0) = 2 dB, and (1, 1)= 6 dB.
Digital inputs pulse mode (MOD1 = 0, MOD0 = 1).
A2/CS/S1A
I
A2: Attenuation bit two = 2-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1).
CS: Serial chip select (active low). Digital inputs serial mode (MOD1 = 1, MOD0 = 0) SPI
compatible.
S1A: Step size zero and step size 1. (0,0) = 0.5 dB; (0, 1)= 1 dB; (1,0) = 2 dB, and (1, 1)= 6 dB.
Digital inputs pulse mode (MOD1 = 0, MOD0 = 1).
GND
P
Ground plane. Connect to low impedance ground plane. All pin voltages are specified with
respect to the voltage on these pins. The exposed thermal pad is internally bonded to the ground
pins.
A1/SDO/S0A
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
Positive supply voltage (pin 14 and 27)
MIN
MAX
UNIT
–0.6
5.5
V
Differential voltage between any two grounds
< 200
mV
Analog input voltage
–0.6
V+
V
Digital input voltage
–0.6
5.5
V
Soldering temperature, infrared or convection (30 s)
260
°C
Junction temperature, TJ
150
°C
150
°C
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
6.2 ESD Ratings
VALUE
Human-body model (HBM)
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
(1) (2)
UNIT
±2000
Charged-device model (CDM) (3)
±750
Machine model (MM)
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Human-body model, applicable std. MIL-STD-883, Method 3015.7. Field-induced Charge-device model, applicable std. JESD22-C101-C
(ESD FICDM std. of JEDEC). Machine model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC).
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage (pin 14 and 27)
MIN
MAX
UNIT
4.75
5.25
V
80 dB at 300 MHz
• Noise voltage < 0 nV/rt Hz
8.2.2 Detailed Design Procedure
A voltage between 4.75 V and 5.25 V must be applied to the supply pin labeled 5 V. Each supply pin must be
decoupled with a additional capacitance along with some low inductance, surface-mount ceramic capacitor of
0.01 µF as close to the device as possible where space allows.
The outputs of the LMH6521 are low impedance devices that requires connection to ground with 1-µH RF
chokes and require AC-coupling capacitors of 0.01 µF. The input pins are self biased to 2.5 V and must be accoupled with 0.01-µF capacitors as well. The output RF inductors and AC-coupling capacitors are the main
limitations for operating at low frequencies.
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Typical Application (continued)
Each channel of the LMH6521 consists of a digital step attenuator followed by a low-distortion, 26-dB fixed gain
amplifier and a low impedance output stage. The gain is digitally controlled over a 31.5-dB range from 26 dB to
−5.5 dB. The LMH6521 has a 200-Ω differential input impedance and a low 20-Ω differential output impedance.
To enable each channel of the LMH6521, the ENA and ENB pins can be left to float, which internally is
connected high with a weak pullup resistor. Externally connecting ENA and ENB to ground disables the channels
of the LMH6521 and reduce the current consumption to 17.5 mA per channel.
+5 V
+
0.01 PF
50 :
0.01 PF
OUT+
IN+
40.2 :
0.01 PF
½
LMH6521
AC
100 :
OUT-
50 :
0.01 PF IN-
40.2 :
1 PH
6
0.01 PF
1 PH
A0 - A5
Copyright © 2016, Texas Instruments Incorporated
Figure 39. Basic Operating Connection
The LMH6521 meets the SFDR and output voltage swing requirements with no additional design details.
However, the noise requires an additional filter as shown in Figure 38. The filter termination reduces the
LMH6521 output noise voltage from 33 nV/rt Hz to 16.5 nV/rt Hz. A simple third order filter reduces out of band
noise that would alias into the signal path. For filter details, see Interface to ADC.
1P
0.01P
90
100 n
+ IN
+
100
LMH6521
2.5 p
2.5 p
100
90
.
1P
VRM
ADC16DV160
-IN
0.01P
100 n
Copyright © 2016, Texas Instruments Incorporated
Figure 40. Filter Schematic
For further design assistance, see SP16160CH1RB Reference Design Board User’s Guide (SNAU079).
26
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Typical Application (continued)
8.2.3 Application Curve
30
15
Voltage (V)
0
-15
-30
-45
-60
-75
-90
100000
1000000
1E+7
1E+8
Frequency (Hz)
1E+9
1E+10
D001
Figure 41. Filter Frequency Response
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9 Power Supply Recommendations
The LMH6521 was designed primarily to be operated on 5-V power supplies. The voltage range for VCC is 4.75 V
to 5.25 V. When operated on a board with high-speed digital signals, it is important to provide isolation between
digital signal noise and the LMH6521 inputs. 700-2700 MHZ Dual-Channel Receiver with 16-Bit ADC and 100
MHz IF Bandwidth Reference Design (TIDA-00360) provides an example of good board layout.
10 Layout
10.1 Layout Guidelines
Layout for the LMH6521 is critical to achieve specified performance. Circuit symmetry is necessary for good HD2
performance. Input traces must be 200-Ω impedance transmission lines. To reduce output to input coupling, use
ground plane fill between the amplifier input and output traces as shown in Figure 42. The output inductors
contribute to crosstalk if placed too closely together. See Figure 42 for recommended placement of the output
bias inductors. Output termination resistors and coupling capacitors must be placed as closely to the output
inductors as possible.
10.2 Layout Example
Coupling
Capacitors
RF Bias
Inductors
Termination
Resistors
Inputs
Outputs
Figure 42. LMH6521 Layout Example
28
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10.3 Thermal Considerations
The LMH6521 is packaged in a thermally enhanced WQFN package and features an exposed pad that is
connected to the GND pins. TI recommends attaching the exposed pad directly to a large power supply ground
plane for maximum heat dissipation. The thermal advantage of the WQFN package is fully realized only when the
exposed die attach pad is soldered down to a thermal land on the PCB board with the through vias planted
underneath the thermal land. The thermal land can be connected to any ground plane within the PCB. However,
it is also very important to maintain good high-speed layout practices when designing a system board.
The LMH6521EVAL evaluation board implemented an eight metal layer PCB with (a) 4 oz. copper inner ground
planes (b) additonal through vias and (c) maximum bottom layer metal coverage to assist with device heat
dissipation. These PCB design techniques assist with the heat dissipation of the LMH6521 to optimize distortion
performance. See AN–2045 LMH6521EVAL Evaluation Board (SNOA551) for suggested layout techniques.
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• AN-2045 LMH6521EVAL Evaluation Board (SNOA551)
• SP16160CH1RB Reference Design Board User’s Guide (SNAU079)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMH6521SQ/NOPB
ACTIVE
WQFN
RTV
32
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
L6521SQ
LMH6521SQE/NOPB
ACTIVE
WQFN
RTV
32
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
L6521SQ
LMH6521SQX/NOPB
ACTIVE
WQFN
RTV
32
4500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
L6521SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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