LMP7711MK

LMP7711 www.ti.com SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 Single and Dual Precision, 17 MHz, Low Noise, CMOS Input Amplifiers Check for Samples: LMP7711 FEATURES DESCRIPTION • The LMP7711/LMP7712 are single and dual low noise, low offset, CMOS input, rail-to-rail output precision amplifiers with a high gain bandwidth product and an enable pin. The LMP7711/LMP7712 are part of the LMP™ precision amplifier family and are ideal for a variety of instrumentation applications. 1 23 • • • • • • • • • • • • Unless Otherwise Noted, Typical Values at VS = 5V. Input Offset Voltage ±150 μV (Max) Input Bias Current 100 fA Input Voltage Noise 5.8 nV/√Hz Gain Bandwidth Product 17 MHz Supply Current (LMP7711) 1.15 mA Supply Current (LMP7712) 1.30 mA Supply Voltage Range 1.8V to 5.5V THD+N @ f = 1 kHz 0.001% Operating Temperature Range −40°C to 125°C Rail-to-rail Output Swing Space Saving SOT Package (LMP7711) 10-pin VSSOP Package (LMP7712) APPLICATIONS • • • Active Filters and Buffers Sensor Interface Applications Transimpedance Amplifiers Utilizing a CMOS input stage, the LMP7711/LMP7712 achieve an input bias current of 100 fA, an input referred voltage noise of 5.8 nV/√Hz, and an input offset voltage of less than ±150 μV. These features make the LMP7711/LMP7712 superior choices for precision applications. Consuming only 1.15 mA of supply current, the LMP7711 offers a high gain bandwidth product of 17 MHz, enabling accurate amplification at high closed loop gains. The LMP7711/LMP7712 have a supply voltage range of 1.8V to 5.5V, which makes these ideal choices for portable low power applications with low supply voltage requirements. In order to reduce the already low power consumption the LMP7711/LMP7712 have an enable function. Once in shutdown, the LMP7711/LMP7712 draw only 140 nA of supply current. The LMP7711/LMP7712 are built with TI's advanced VIP50 process technology. The LMP7711 is offered in a 6-pin SOT package and the LMP7712 is offered in a 10-pin VSSOP. TYPICAL PERFORMANCE Offset Voltage Distribution PERCENTAGE (%) 20 Input Referred Voltage Noise 100 VS = 5V VS = 5.5V VCM = VS/2 UNITS TESTED: 10,000 VOLTAGE NOISE (nV/ Hz) 25 15 10 5 0 -200 VS = 2.5V 10 1 -100 0 100 200 1 10 100 1k OFFSET VOLTAGE (PV) FREQUENCY (Hz) Figure 1. Figure 2. 10k 100k 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LMP is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated LMP7711 SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) ESD Tolerance (3) Human Body Model 2000V Machine Model 200V Charge-Device Model 1000V VIN Differential ±0.3V Supply Voltage (VS = V+ – V−) 6.0V Voltage on Input/Output Pins V+ +0.3V, V− −0.3V Storage Temperature Range −65°C to 150°C Junction Temperature (4) +150°C Soldering Information Infrared or Convection (20 sec) 235°C Wave Soldering Lead Temp. (10 sec) (1) (2) (3) (4) 260°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC Board. OPERATING RATINGS (1) Temperature Range (2) −40°C to 125°C + − Supply Voltage (VS = V – V ) Package Thermal Resistance (θJA (2)) (1) (2) 2 0°C ≤ TA ≤ 125°C 1.8V to 5.5V −40°C ≤ TA ≤ 125°C 2.0V to 5.5V 6-Pin SOT 170°C/W 10-Pin VSSOP 236°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC Board. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 LMP7711 www.ti.com SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 2.5V ELECTRICAL CHARACTERISTICS Unless otherwise noted, all limits are ensured for TA = 25°C, V+ = 2.5V, V− = 0V ,VO = VCM = V+/2, VEN = V+. Boldface limits apply at the temperature extremes. Symbol Parameter VOS Input Offset Voltage TC VOS Input Offset Voltage Temperature Drift (3) (4) LMP7711 Input Bias Current VCM = 1.0V (5) (4) IB Typ (2) Max (1) Units ±20 ±180 ±480 μV –1 ±4 μV/°C −40°C ≤ TA ≤ 85°C 0.05 1 25 −40°C ≤ TA ≤ 125°C 0.05 1 100 0.006 0.5 50 Conditions Min (1) –1.75 LMP7712 IOS Input Offset Current VCM = 1.0V (4) CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 1.4V 83 80 100 PSRR Power Supply Rejection Ratio 2.0V ≤ V+ ≤ 5.5V V− = 0V, VCM = 0 85 80 100 1.8V ≤ V+ ≤ 5.5V V− = 0V, VCM = 0 85 98 CMVR Common Mode Voltage Range CMRR ≥ 80 dB CMRR ≥ 78 dB AVOL Open Loop Voltage Gain LMP7711, VO = 0.15 to 2.2V RL = 2 kΩ to V+/2 88 82 98 LMP7712, VO = 0.15 to 2.2V RL = 2 kΩ to V+/2 84 80 92 LMP7711, VO = 0.15 to 2.2V RL = 10 kΩ to V+/2 92 88 114 LMP7712, VO = 0.15 to 2.2V RL = 10 kΩ to V+/2 90 86 95 VOUT Output Voltage Swing High Output Voltage Swing Low IOUT IS SR (1) (2) (3) (4) (5) (6) Output Current Supply Current Slew Rate −0.3 –0.3 pA pA dB dB 1.5 1.5 dB RL = 2 kΩ to V+/2 25 70 77 RL = 10 kΩ to V+/2 20 60 66 RL = 2 kΩ to V+/2 30 70 73 RL = 10 kΩ to V+/2 15 60 62 Sourcing to V− VIN = 200 mV (6) 36 30 52 Sinking to V+ VIN = −200 mV (6) 7.5 5.0 15 V mV from either rail mA LMP7711 Enable Mode VEN ≥ 2.1 0.95 1.30 1.65 LMP7712 (per channel) Enable Mode VEN ≥ 2.1 1.10 1.50 1.85 Shutdown Mode (per channel) VEN ≤ 0.4 0.03 1 4 AV = +1, Rising (10% to 90%) 8.3 AV = +1, Falling (90% to 10%) 10.3 mA μA V/μs Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the Statistical Quality Control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change. This parameter is specified by design and/or characterization and is not tested in production. Positive current corresponds to current flowing into the device. The short circuit test is a momentary open loop test. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 3 LMP7711 SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 www.ti.com 2.5V ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted, all limits are ensured for TA = 25°C, V+ = 2.5V, V− = 0V ,VO = VCM = V+/2, VEN = V+. Boldface limits apply at the temperature extremes. Symbol Parameter GBW Gain Bandwidth en Input Referred Voltage Noise Density in Input Referred Current Noise Density ton Turn-on Time toff Turn-off Time VEN Enable Pin Voltage Range Min (1) Conditions Enable Pin Input Current THD+N Total Harmonic Distortion + Noise Max (1) 14 Units MHz f = 400 Hz 6.8 f = 1 kHz 5.8 f = 1 kHz 0.01 pA/√Hz 140 ns 1000 ns Enable Mode 2.1 Shutdown Mode IEN Typ (2) VEN = 2.5V (5) nV/√Hz 2 - 2.5 0 - 0.5 0.4 1.5 3.0 VEN = 0V (5) 0.003 0.1 f = 1 kHz, AV = 1, RL = 100 kΩ VO = 0.9 VPP 0.003 f = 1 kHz, AV = 1, RL = 600Ω VO = 0.9 VPP 0.004 V μA % 5V ELECTRICAL CHARACTERISTICS Unless otherwise noted, all limits are ensured for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, VEN = V+. Boldface limits apply at the temperature extremes. Symbol Parameter VOS Input Offset Voltage TC VOS Input Offset Voltage Temperataure Drift (3) (4) LMP7711 Input Bias Current VCM = 2.0V (5) (4) IB Input Offset Current VCM = 2.0V (4) CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 3.7V CMVR (1) (2) (3) (4) (5) 4 Power Supply Rejection Ratio Common Mode Voltage Range Typ (2) Max (1) Units ±10 ±150 ±450 μV –1 ±4 μV/°C −40°C ≤ TA ≤ 85°C 0.1 1 25 −40°C ≤ TA ≤ 125°C 0.1 1 100 0.01 0.5 50 –1.75 LMP7712 IOS PSRR Min (1) Conditions 85 82 100 2.0V ≤ V ≤ 5.5V V− = 0V, VCM = 0 85 80 100 1.8V ≤ V+ ≤ 5.5V V− = 0V, VCM = 0 85 98 + CMRR ≥ 80 dB CMRR ≥ 78 dB −0.3 –0.3 pA pA dB dB 4 4 V Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the Statistical Quality Control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change. This parameter is specified by design and/or characterization and is not tested in production. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 LMP7711 www.ti.com SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 5V ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted, all limits are ensured for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, VEN = V+. Boldface limits apply at the temperature extremes. Symbol AVOL VOUT Open Loop Voltage Gain Output Voltage Swing High Output Voltage Swing Low IOUT Output Current IS Supply Current SR Min (1) Typ (2) LMP7711, VO = 0.3 to 4.7V RL = 2 kΩ to V+/2 88 82 107 LMP7712, VO = 0.3 to 4.7V RL = 2 kΩ to V+/2 84 80 90 LMP7711, VO = 0.3 to 4.7V RL = 10 kΩ to V+/2 92 88 114 LMP7712, VO = 0.3 to 4.7V RL = 10 kΩ to V+/2 90 86 95 Parameter Slew Rate GBW Gain Bandwidth en Input Referred Voltage Noise Density Conditions Max (1) dB RL = 2 kΩ to V+/2 32 70 77 RL = 10 kΩ to V+/2 22 60 66 RL = 2 kΩ to V+/2 (LMP7711) 42 70 73 RL = 2 kΩ to V+/2 (LMP7712) 50 75 78 RL = 10 kΩ to V+/2 20 60 62 Sourcing to V− VIN = 200 mV (6) 46 38 66 Sinking to V+ VIN = −200 mV (6) 10.5 6.5 23 1.15 1.40 1.75 LMP7712 (per channel) Enable Mode VEN ≥ 4.6 1.30 1.70 2.05 Shutdown Mode VEN ≤ 0.4 (per channel) 0.14 1 4 6.0 9.5 AV = +1, Falling (90% to 10%) 7.5 11.5 mV from either rail mA LMP7711 Enable Mode VEN ≥ 4.6 AV = +1, Rising (10% to 90%) Units mA μA V/μs 17 MHz f = 400 Hz 7.0 f = 1 kHz 5.8 f = 1 kHz 0.01 pA/√Hz nV/√Hz in Input Referred Current Noise Density ton Turn-on Time 114 ns toff Turn-off Time 800 ns VEN Enable Pin Voltage Range Enable Mode Shutdown Mode IEN Enable Pin Input Current THD+N (6) (7) Total Harmonic Distortion + Noise 4.6 4.5 – 5 0 – 0.5 0.4 VEN = 5V (7) 5.6 10 VEN = 0V (7) 0.005 0.2 f = 1 kHz, AV = 1, RL = 100 kΩ VO = 4 VPP 0.001 f = 1 kHz, AV = 1, RL = 600Ω VO = 4 VPP 0.004 V μA % The short circuit test is a momentary open loop test. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 5 LMP7711 SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 www.ti.com CONNECTION DIAGRAM 6 1 + V OUTPUT 5 V - -IN A 2 +IN A - 3 1 4 V -IN +IN - EN A Figure 3. 6-Pin SOT - Top View See Package Number DDC 6 10 + V 9 OUT B 8 -IN B 4 7 +IN B 5 6 EN B - EN 2 + OUT A 3 + + - Figure 4. 10-Pin VSSOP-Top View See Package Number DGS Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 LMP7711 www.ti.com SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+. Offset Voltage Distribution PERCENTAGE (%) 20 TCVOS Distribution (LMP7711) 25 VS = 2.5V -40°C d TA d 125qC VS = 2.5V, 5V VCM = VS/2 UNITS TESTED:10,000 20 PERCENTAGE (%) 25 15 10 5 VCM = VS/2 UNITS TESTED: 10,000 15 10 5 0 -200 -100 0 100 0 200 -4 -3 -2 -1 0 TCVOS (PV/°C) OFFSET VOLTAGE (PV) Figure 5. TCVOS Distribution (LMP7712) 25 -40°C d TA d 125°C VS = 5V VCM = VS/2 UNITS TESTED: 10,000 PERCENTAGE (%) PERCENTAGE (%) 20 15 10 5 VS = 2.5V, 5V 20 VCM = VS/2 UNITS TESTED: 10,000 15 10 5 0 -200 0 -100 0 100 200 -4 -3 OFFSET VOLTAGE (PV) -2 -1 Figure 8. Offset Voltage vs. VCM Offset Voltage vs. VCM 200 VS = 1.8V VS = 2.5V 150 -40°C OFFSET VOLTAGE (PV) OFFSET VOLTAGE (PV) 150 100 50 25°C 0 -50 125°C -100 -150 -200 -0.3 0 TCVOS (PV/°C) Figure 7. 200 2 Figure 6. Offset Voltage Distribution 25 1 -40°C 100 50 25°C 0 125°C -50 -100 -150 0 0.3 0.6 0.9 1.2 1.5 VCM (V) -200 -0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 VCM (V) Figure 9. Figure 10. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 7 LMP7711 SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+. Offset Voltage vs. VCM Offset Voltage vs. Supply Voltage 200 200 VS = 5V 150 100 -40°C 50 25°C OFFSET VOLTAGE (PV) OFFSET VOLTAGE (PV) 150 0 125°C -50 -100 100 -40°C 50 25°C 0 125°C -50 -100 -150 -150 -200 -0.3 -200 0.7 1.7 2.7 3.7 1.5 4.7 2.5 3.5 4.5 VS (V) VCM (V) Figure 11. CMRR vs. Frequency 120 100 100 VS = 2.5V 50 VS = 2.5V 0 80 CMRR (dB) OFFSET VOLTAGE (PV) 6 Figure 12. Offset Voltage vs. Temperature 150 5.5 LMP7711 -50 -100 VS = 5V 60 40 VS = 5V 20 -150 LMP7712 -200 -40 -20 0 20 40 60 0 10 80 100 120 125 Figure 13. Input Bias Current Over Temperature Input Bias Current Over Temperature VS = 5V 25°C VS = 5V 40 INPUT BIAS CURRENT (pA) INPUT BIAS CURRENT (fA) 50 0 -500 -40°C -1500 -2000 -2500 30 20 125°C 10 0 -10 85°C -20 -30 -40 -3000 -50 0 8 1M Figure 14. 1000 -1000 100k FREQUENCY (Hz) TEMPERATURE (°C) 500 10k 1k 100 1 2 3 4 0 1 2 VCM (V) VCM (V) Figure 15. Figure 16. Submit Documentation Feedback 3 4 Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 LMP7711 www.ti.com SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+. Supply Current vs. Supply Voltage (LMP7711) Supply Current vs. Supply Voltage (LMP7712) 2 2 1.6 1.6 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 125°C 125°C 25°C 1.2 0.8 -40°C 0.4 25°C 1.2 -40°C 0.8 0.4 0 0 1.5 2.5 3.5 4.5 5.5 1.5 2.5 3.5 VS (V) Figure 17. 5.5 Figure 18. Supply Current vs. Supply Voltage (Shutdown) Crosstalk Rejection Ratio (LMP7712) 160 CROSSTALK REJECTION RATIO (dB) 1.8 1.6 SUPPLY CURRENT (PA) 4.5 VS (V) 125°C 1.4 1.2 1 0.8 0.6 25°C 0.4 0.2 -40°C 0 1.5 2.5 3.5 4.5 140 120 100 80 60 40 20 0 1k 5.5 10k 100k 1M 10M 100M FREQUENCY (Hz) VS (V) Figure 19. Figure 20. Supply Current vs. Enable Pin Voltage (LMP7711) Supply Current vs. Enable Pin Voltage (LMP7711) 1.5 2.4 125°C VS = 2.5V VS = 5V 1.1 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 1.3 25°C 0.9 -40°C 0.7 0.5 0.3 125°C 1.9 25°C 1.4 -40°C 0.9 -40°C 0.4 125°C 0.1 -0.1 -0.1 0 0.5 1 1.5 2 2.5 ENABLE PIN VOLTAGE (V) 0 1 2 3 4 5 ENABLE PIN VOLTAGE (V) Figure 21. Figure 22. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 9 LMP7711 SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+. Supply Current vs. Enable Pin Voltage (LMP7712) 1.7 VS = 2.5V 2.4 VS = 5V 125°C 25°C 1.3 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 1.5 Supply Current vs. Enable Pin Voltage (LMP7712) 125°C 1.1 0.9 -40°C 0.7 0.5 0.3 1.9 1.4 25°C 0.9 -40°C -40°C 25°C 0.4 125°C 0.1 -0.1 -0.1 0 0.5 1 1.5 2 2.5 0 ENABLE PIN VOLTAGE (V) 1 2 Figure 23. 4 5 Figure 24. Sourcing Current vs. Supply Voltage Sinking Current vs. Supply Voltage 80 35 125°C 70 30 60 125°C 25 50 ISINK (mA) ISOURCE (mA) 3 ENABLE PIN VOLTAGE (V) -40°C 25°C 40 30 25°C 20 15 10 20 -40°C 5 10 0 1.5 2.5 3.5 4.5 0 1.5 5.5 2.5 3.5 VS (V) 4.5 5.5 VS (V) Figure 25. Figure 26. Sourcing Current vs. Output Voltage Sinking Current vs. Output Voltage 30 70 125°C 60 50 20 ISINK (mA) ISOURCE (mA) 125°C 25 -40°C 40 25°C 30 25°C 15 10 -40°C 20 5 10 0 0 0 10 1 2 3 4 5 0 1 2 3 VOUT (V) VOUT (V) Figure 27. Figure 28. Submit Documentation Feedback 4 5 Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 LMP7711 www.ti.com SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+. Output Swing High vs. Supply Voltage Output Swing Low vs. Supply Voltage 50 50 40 30 25°C 125°C 20 -40°C 10 RL =10 k: 40 VOUT FROM RAIL (mV) VOUT FROM RAIL (mV) RL = 10 k: 30 -40°C 20 125°C 10 0 25°C 0 1.5 2.5 3.5 4.5 5.5 1.5 2.5 3.5 VS (V) 4.5 5.5 VS (V) Figure 29. Figure 30. Output Swing High vs. Supply Voltage Output Swing Low vs. Supply Voltage 50 50 RL = 2 k: 125°C 25°C 30 20 40 VOUT FROM RAIL (mV) VOUT FROM RAIL (mV) -40°C 40 -40°C 125°C 30 25°C 20 10 10 RL = 2 k: 0 1.5 2.5 3.5 4.5 0 1.5 5.5 2.5 VS (V) 3.5 Figure 31. 5.5 Figure 32. Output Swing High vs. Supply Voltage Output Swing Low vs. Supply Voltage 150 150 RL = 600: RL = 600: 120 VOUT FROM RAIL (mV) VOUT FROM RAIL (mV) 4.5 VS (V) 90 125°C 25°C 60 120 30 25°C 125°C 90 -40°C 60 30 -40°C 0 0 1.5 2.5 3.5 4.5 5.5 VS (V) 1.5 2.5 3.5 4.5 5.5 VS (V) Figure 33. Figure 34. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 11 LMP7711 SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+. Open Loop Frequency Response CL = 50 pF GAIN (dB) GAIN 40 CL = 100 pF 100 100 80 80 80 60 60 60 40 20 20 0 -20 CL = 50 pF -40 CL = 100 pF 10k 100k 1M 40 GAIN 20 20 0 0 -20 -20 -40 -40 -20 -40 RL = 600: 10 k: 10 M: -60 100M -60 1k 10M -60 10k 1M FREQUENCY (Hz) Figure 36. -60 100M Phase Margin vs. Capacitive Load 50 RL = 600: 40 40 PHASE MARGIN (°) RL = 600: 30 RL = 10 k: RL = 10 M: 20 10 RL = 10 k: 30 20 RL = 10 M: 10 VS = 2.5V VS = 5V 0 0 10 100 1000 10 CAPACITIVE LOAD (pF) 100 1000 CAPACITIVE LOAD (pF) Figure 37. Figure 38. Overshoot and Undershoot vs. Capacitive Load Slew Rate vs. Supply Voltage 70 12 UNDERSHOOT% 60 FALLING EDGE 11 50 SLEW RATE (V/Ps) OVERSHOOT AND UNDERSHOOT (%) 10M Figure 35. Phase Margin vs. Capacitive Load PHASE MARGIN (°) 100k FREQUENCY (Hz) 50 OVERSHOOT % 40 30 20 10 9 RISING EDGE 8 10 0 0 20 40 60 80 100 120 CAPACITIVE LOAD (pF) 7 1.5 2.5 3.5 4.5 5.5 6 VS (V) Figure 39. 12 100 40 0 CL = 20 pF PHASE PHASE (°) CL = 20 pF 80 120 120 GAIN (dB) 100 60 Open Loop Frequency Response 120 PHASE PHASE (°) 120 Figure 40. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 LMP7711 www.ti.com SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+. Large Signal Step Response 10 mV/DIV 200 mV/DIV Small Signal Step Response VIN = 20 mVPP VIN = 1 VPP f = 1 MHz, AV = +1 f = 200 kHz, AV = +1 VS = 2.5V, CL = 10 pF VS = 2.5V, CL = 10 pF 800 ns/DIV Figure 41. Figure 42. Small Signal Step Response Large Signal Step Response 10 mV/DIV 200 mV/DIV 200 ns/DIV VIN = 20 mVPP VIN = 1 VPP f = 200 kHz, AV = +1 VS = 5V, CL = 10 pF f = 1 MHz, AV = +1 VS = 5V, CL = 10 pF 200 ns/DIV 800 ns/DIV Figure 43. Figure 44. THD+N vs. Output Voltage THD+N vs. Output Voltage 0 0 -20 AV = +2 VS = 5.5V f = 1 kHz AV = +2 -40 -40 THD+N (dB) THD+N (dB) -20 VS = 1.8V f = 1 kHz -60 RL = 600: -60 RL = 600: -80 -80 -100 -100 -120 RL = 100 k: -120 0.01 0.1 1 10 -140 0.01 OUTPUT AMPLITUDE (VPP) RL = 100 k: 0.1 1 10 OUTPUT AMPLITUDE (VPP) Figure 45. Figure 46. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 13 LMP7711 SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+. THD+N vs. Frequency 0.006 THD+N vs. Frequency 0.006 VS = 1.8V VS = 5V VO = 0.9 VPP 0.005 AV = +2 0.004 THD+N (%) 0.004 THD+N (%) VO = 4 VPP 0.005 RL = 600: AV = +2 RL = 100 k: 0.003 RL = 600: 0.003 0.002 0.002 0.001 0.001 0 0 RL = 100 k: 10 100 1k 10k 10 100k 100 FREQUENCY (Hz) 1k 10k Figure 47. Figure 48. PSRR vs. Frequency Time Domain Voltage Noise 120 VS = ±2.5V VS = 5.5V, -PSRR VCM = 0.0V VS = 1.8V, -PSRR 100 400 nV/DIV PSRR (dB) 80 VS = 5.5V, +PSRR 60 100k FREQUENCY (Hz) 40 VS = 1.8V, +PSRR 20 0 10 100 1k 10k 100k 1M 1 s/DIV 10M FREQUENCY (Hz) Figure 49. Figure 50. Closed Loop Frequency Response 100 5 VS = 2.5V GAIN (dB) VOLTAGE NOISE (nV/ Hz) VS = 5.5V 10 4 RL = 2 k: 180 3 CL = 20 pF 135 2 VO = 2 VPP 90 AV = +1 1 45 0 0 -45 -1 PHASE -2 GAIN -5 1 10 100 1k 10k 100k -90 -135 -3 -4 1 100 FREQUENCY (Hz) 1k 10k 100 k 1M -180 -225 10M FREQUENCY (Hz) Figure 51. 14 225 VS = 5V PHASE (°) Input Referred Voltage Noise vs. Frequency Figure 52. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 LMP7711 www.ti.com SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+. Closed Loop Output Impedance vs. Frequency OUTPUT IMPEDANCE (:) 100 10 1 0.1 0.01 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 53. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 15 LMP7711 SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 www.ti.com APPLICATION NOTES LMP7711/LMP7712 The LMP7711/LMP7712 are single and dual, low noise, low offset, rail-to-rail output precision amplifiers with a wide gain bandwidth product of 17 MHz and low supply current. The wide bandwidth makes the LMP7711/LMP7712 ideal choices for wide-band amplification in portable applications. The low supply current along with the enable feature that is built-in on the LMP7711/LMP7712 allows for even more power efficient designs by turning the device off when not in use. The LMP7711/LMP7712 are superior for sensor applications. The very low input referred voltage noise of only 5.8 nV/√Hz at 1 kHz and very low input referred current noise of only 10 fA/ √Hz mean more signal fidelity and higher signal-to-noise ratio. The LMP7711/LMP7712 have a supply voltage range of 1.8V to 5.5V over a wide temperature range of 0°C to 125°C. This is optimal for low voltage commercial applications. For applications where the ambient temperature might be less than 0°C, the LMP7711/LMP7712 are fully operational at supply voltages of 2.0V to 5.5V over the temperature range of −40°C to 125°C. The outputs of the LMP7711/LMP7712 swing within 25 mV of either rail providing maximum dynamic range in applications requiring low supply voltage. The input common mode range of the LMP7711/LMP7712 extends to 300 mV below ground. This feature enables users to utilize this device in single supply applications. The use of a very innovative feedback topology has enhanced the current drive capability of the LMP7711/LMP7712, resulting in sourcing currents as much as 47 mA with a supply voltage of only 1.8V. The LMP7711 is offered in the space saving SOT package and the LMP7712 is offered in a 10-pin VSSOP. These small packages are ideal solutions for applications requiring minimum PC board footprint. Texas Instruments is heavily committed to precision amplifiers and the market segments they serves. Technical support and extensive characterization data is available for sensitive applications or applications with a constrained error budget. CAPACITIVE LOAD The unity gain follower is the most sensitive configuration to capacitive loading. The combination of a capacitive load placed directly on the output of an amplifier along with the output impedance of the amplifier creates a phase lag which in turn reduces the phase margin of the amplifier. If phase margin is significantly reduced, the response will be either underdamped or the amplifier will oscillate. The LMP7711/LMP7712 can directly drive capacitive loads of up to 120 pF without oscillating. To drive heavier capacitive loads, an isolation resistor, RISO in Figure 54, should be used. This resistor and CL form a pole and hence delay the phase lag or increase the phase margin of the overall system. The larger the value of RISO, the more stable the output voltage will be. However, larger values of RISO result in reduced output swing and reduced output current drive. Figure 54. Isolating Capacitive Load INPUT CAPACITANCE CMOS input stages inherently have low input bias current and higher input referred voltage noise. The LMP7711/LMP7712 enhance this performance by having the low input bias current of only 50 fA, as well as, a very low input referred voltage noise of 5.8 nV/√Hz. In order to achieve this a larger input stage has been used. This larger input stage increases the input capacitance of the LMP7711/LMP7712. Figure 55 shows typical input common mode input capacitance of the LMP7711/LMP7712. 16 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 LMP7711 www.ti.com SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 25 VS = 5V CCM (pF) 20 15 10 5 0 0 1 2 3 4 VCM (V) Figure 55. Input Common Mode Capacitance This input capacitance will interact with other impedances such as gain and feedback resistors, which are seen on the inputs of the amplifier to form a pole. This pole will have little or no effect on the output of the amplifier at low frequencies and under DC conditions, but will play a bigger role as the frequency increases. At higher frequencies, the presence of this pole will decrease phase margin and also causes gain peaking. In order to compensate for the input capacitance, care must be taken in choosing feedback resistors. In addition to being selective in picking values for the feedback resistor, a capacitor can be added to the feedback path to increase stability. The DC gain of the circuit shown in Figure 56 is simply −R2/R1. CF R2 R1 - + CIN VIN + + - - AV = - VOUT VIN =- VOUT R2 R1 Figure 56. Compensating for Input Capacitance For the time being, ignore CF. The AC gain of the circuit in Figure 56 can be calculated as follows: VOUT -R2/R1 (s) = VIN s2 s 1+ + § A0 § A0 R 1 ¨ ¨C R © IN 2 © R1 + R2 (1) § ¨ © § ¨ © This equation is rearranged to find the location of the two poles: 1 1 + r R1 R2 §1 1 + ¨ R2 © R1 § ¨ © -1 P1,2 = 2CIN 2 - 4 A0CIN R2 (2) Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 17 LMP7711 SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 www.ti.com As shown in Equation 2, as the values of R1 and R2 are increased, the magnitude of the poles are reduced, which in turn decreases the bandwidth of the amplifier. Figure 57 shows the frequency response with different value resistors for R1 and R2. Whenever possible, it is best to chose smaller feedback resistors. 15 AV = -1 10 GAIN (dB) 5 0 -5 R1, R2 = 30 k: -10 R1, R2 = 10 k: -15 R1, R2 = 1 k: -20 -25 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 57. Closed Loop Frequency Response As mentioned before, adding a capacitor to the feedback path will decrease the peaking. This is because CF will form yet another pole in the system and will prevent pairs of poles, or complex conjugates from forming. It is the presence of pairs of poles that cause the peaking of gain. Figure 58 shows the frequency response of the schematic presented in Figure 56 with different values of CF. As can be seen, using a small value capacitor significantly reduces or eliminates the peaking. 20 R1, R2 = 30 k: 10 CF = 0 pF AV = -1 GAIN (dB) 0 CF = 5 pF -10 CF = 2 pF -20 -30 -40 10k 100k 1M 10M FREQUENCY (Hz) Figure 58. Closed Loop Frequency Response TRANSIMPEDANCE AMPLIFIER In many applications, the signal of interest is a very small amount of current that needs to be detected. Current that is transmitted through a photodiode is a good example. Barcode scanners, light meters, fiber optic receivers, and industrial sensors are some typical applications utilizing photodiodes for current detection. This current needs to be amplified before it can be further processed. This amplification is performed using a current-tovoltage converter configuration or transimpedance amplifier. The signal of interest is fed to the inverting input of an op amp with a feedback resistor in the current path. The voltage at the output of this amplifier will be equal to the negative of the input current times the value of the feedback resistor. Figure 59 shows a transimpedance amplifier configuration. CD represents the photodiode parasitic capacitance and CCM denotes the common-mode capacitance of the amplifier. The presence of all of these capacitances at higher frequencies might lead to less stable topologies at higher frequencies. Care must be taken when designing a transimpedance amplifier to prevent the circuit from oscillating. 18 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LMP7711 LMP7711 www.ti.com SNOSAP4F – SEPTEMBER 2005 – REVISED MAY 2013 With a wide gain bandwidth product, low input bias current and low input voltage and current noise, the LMP7711/LMP7712 are ideal for wideband transimpedance applications. CF RF IIN CCM + + VOUT CD - VB CIN = CD + CCM VOUT = - RF IIN Figure 59. Transimpedance Amplifier A feedback capacitance CF is usually added in parallel with RF to maintain circuit stability and to control the frequency response. To achieve a maximally flat, 2nd order response, RF and CF should be chosen by using Equation 3 CF = CIN GBWP 2 S RF (3) Calculating CF from Equation 3 can sometimes result in capacitor values which are less than 2 pF. This is especially the case for high speed applications. In these instances, its often more practical to use the circuit shown in Figure 60 in order to allow more sensible choices for CF. The new feedback capacitor, C′F, is (1+ RB/RA) CF. This relationship holds as long as RA