Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
LMP91002
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
LMP91002 Sensor AFE System: Configurable AFE Potentiostat for Low-Power Chemical
Sensing Applications
1 Features
3 Description
•
•
•
•
•
The LMP91002 device is a programmable Analog
Front End (AFE) for use in micro-power
electrochemical-sensing applications. It provides a
complete signal path solution between a not biased
gas sensor and a microcontroller generating an
output voltage proportional to the cell current.
1
•
•
•
•
•
•
•
•
Typical Values, TA = 25°C
Supply Voltage 2.7 V to 3.6 V
Supply Current (Average Over Time) < 10 µA
Cell Conditioning Current Up to 10 mA
Reference Electrode Bias Current (85°C) 900-pA
(Maximum)
Output Drive Current 750 µA
Complete Potentiostat Circuit to Interface to Most
Not Biased Gas Sensors
Low Bias Voltage Drift
Programmable TIA Gain 2.75 kΩ to 350 kΩ
I2C-Compatible Digital Interface
Ambient Operating Temperature –40°C to 85°C
Package 14-pin WSON
Supported by Webench Sensor AFE Designer
The LMP91002’s programmability enables it support
not biased electro-chemical gas sensor with a single
design. The LMP91002 supports gas sensitivities
over a range of 0.5 nA/ppm to 9500 nA/ppm. It also
allows for an easy conversion of current ranges from
5 μA to 750 μA full scale. The LMP91002’s
transimpedance amplifier (TIA) gain is programmable
through the I2C interface. The I2C interface can also
be used for sensor diagnostics. The LMP91002 is
optimized for micro-power applications and operates
over a voltage range of 2.7 V to 3.6 V. The total
current consumption can be less than 10 μA. Further
power savings are possible by switching off the TIA
amplifier and shorting the reference electrode to the
working electrode with an internal switch.
2 Applications
•
•
•
Gas Detectors
Amperometric Applications
Electrochemical Blood Glucose Meters
Device Information(1)
PART NUMBER
LMP91002
PACKAGE
WSON (14)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
VDD
VREF
SCL
LMP91002
3-Lead
Electrochemical
Cell
+
CE
A1
DIAGNOSTIC
VREF
DIVIDER
I2C INTERFACE
AND
CONTROL
REGISTERS
SDA
MSP430
MENB
-
CE
RE
RE
DGND
WE
+
WE
-
RLoad
VOUT
TIA
RTIA
C1
C2
AGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMP91002
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Interface ..............................................................
Timing Characteristics...............................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 12
7.5 Programming........................................................... 12
7.6 Register Maps ......................................................... 14
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 19
9
Power Supply Recommendations...................... 22
9.1 Power Consumption................................................ 22
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (March 2013) to Revision B
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Original (March 2013) to Revision A
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 18
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: LMP91002
LMP91002
www.ti.com
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
5 Pin Configuration and Functions
NHL Package
14-Pin WSON
Top View
DGND 1
14 CE
MENB
RE
SCL
WE
SDA
VREF
DAP
NC
C1
VDD
C2
AGND 7
8
VOUT
Pin Functions (1)
PIN
I/O
DESCRIPTION
NO.
NAME
1
DGND
G
Connect to ground
2
MENB
D
Module Enable. Active Low
3
SCL
D
I2C Clock
4
SDA
D
I2C Data
5
NC
—
Do not connect. Not internally connected
6
VDD
P
Voltage supply
7
AGND
GND
8
VOUT
A
Analog voltage representing sensor output
9
C2
A
Optional External component node 2 for TIA (filter capacitor or gain resistor)
10
C1
A
Optional External component node 1 for TIA (filter capacitor or gain resistor)
11
VREF
A
External Reference voltage input
12
WE
A
Working Electrode of the sensor.
13
RE
A
Reference Electrode of the sensor.
14
CE
A
Counter Electrode of the sensor.
—
DAP
GND
(1)
Analog GND
Die attached pad. Connect to GND.
A = analog, D = digital, P = power, G = GND
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: LMP91002
3
LMP91002
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
(1) (2) (3)
See
MAX
UNIT
Voltage between any two pins
MIN
6
V
Current through VDD or VSS
50
mA
Current sunk and sourced by CE pin
10
mA
Current out of other pins (4)
5
mA
150
°C
150
°C
Junction temperature
(5)
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For soldering specifications, see SNOA549.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
All non-power pins of this device are protected against ESD by snapback devices. Voltage at such pins will rise beyond absmax if
current is forced into pin.
The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PCB.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
(3)
Electrostatic
discharge
(1) (2)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (3)
±1000
Machine Model (MM)
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field- Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
Supply voltage VS = (VDD - AGND)
2.7
3.6
V
Temperature (1)
–40
85
°C
(1)
UNIT
The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PCB.
6.4 Thermal Information
LMP91002
THERMAL METRIC (1)
NHL (WSON)
UNIT
14 PINS
RθJA
(1)
(2)
4
Junction-to-ambient thermal resistance
(2)
44
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PCB.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: LMP91002
LMP91002
www.ti.com
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
6.5 Electrical Characteristics
Unless otherwise specified, all limits ensured for TA = 25°C, VS= (VDD – AGND), VS= 3.3 V and AGND = DGND = 0 V, VREF =
2.5 V, Internal Zero = 20% VREF. (1)
PARAMETER
TEST CONDITIONS
MIN (2)
TYP (3)
MAX (2)
10
13.5
UNIT
POWER SUPPLY SPECIFICATION
3-lead amperometric cell
mode
MODECN = 0x03
IS
Supply current
Standby mode
MODECN = 0x02
Deep sleep mode
MODECN = 0x00
TA = 25ºC
At the temperature
extremes
15
TA = 25ºC
6.5
At the temperature
extremes
8
10
TA = 25ºC
0.6
At the temperature
extremes
µA
0.85
1
POTENTIOSTAT
VDD = 2.7 V;
Internal zero 50% VDD
IRE
Input bias current at RE pin
VDD = 3.6 V;
Internal zero 50% VDD
TA = 25ºC
At the temperature
extremes
TA = 25ºC
At the temperature
extremes
–90
90
–800
800
–90
90
–900
900
Minimum operating current
capability
Sink
750
Source
750
Minimum charging
capability (4)
Sink
10
Source
10
AOL_A1
Open-loop voltage gain of
control loop operational
amplifier (A1)
300 mV ≤ VCE ≤
Vs – 300 mV, –750 µA ≤
ICE ≤ 750 µA
en_RW
Low frequency integrated
noise between RE pin and
WE pin
0.1 Hz to 10 Hz (5)
ICE
VOS_RW
TcVOS_RW
(1)
(2)
(3)
(4)
(5)
(6)
WE voltage offset referred to
RE
WE voltage offset drift
referred to RE from –40°C to
85°C (6)
TA = 25ºC
At the temperature
extremes
pA
µA
mA
120
dB
104
3.4
µVpp
0% VREF, internal zero = 20% VREF,
at the temperature extremes
–550
550
0% VREF, internal zero = 50% VREF,
at the temperature extremes
–550
550
0% VREF, internal zero = 67% VREF,
at the temperature extremes
–550
550
0% VREF, internal zero = 20% VREF
–4
4
0% VREF, internal zero = 50% VREF
–4
4
0% VREF, internal zero = 67% VREF
–4
4
µV
µV/°C
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
At such currents no accuracy of the output voltage can be expected.
This parameter includes both A1 and TIA's noise contribution.
Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.Starting from the measured voltage offset at temperature T1 (VOS_RW(T1)), the voltage offset at temperature T2 (VOS_RW(T2)) is
calculated according the following formula: VOS_RW(T2)=VOS_RW(T1)+ABS(T2–T1)* TcVOS_RW.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: LMP91002
5
LMP91002
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
www.ti.com
Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TA = 25°C, VS= (VDD – AGND), VS= 3.3 V and AGND = DGND = 0 V, VREF =
2.5 V, Internal Zero = 20% VREF.(1)
PARAMETER
MIN (2)
TEST CONDITIONS
Transimpedance gain
accuracy
2.75
3.5
7
14
35
120
350
7 programmable gain resistors
Maximum external gain resistor
3 programmable percentages of VREF
3 programmable percentages of VDD
20%
50%
67%
Internal zero voltage
accuracy
±0.04%
Load resistor
Power supply rejection ratio
at RE pin
Ω
10
Load accuracy
PSRR
kΩ
350
20%
50%
67%
Internal zero voltage
RL
UNIT
±0.05%
TIA_GAIN
TIA_ZV
MAX (2)
5%
Linearity
Programmable TIA gains
TYP (3)
5%
2.7 V ≤ VDD ≤ 5.25 V
Internal zero 20% VREF
80
110
Internal zero 50% VREF
80
110
Internal zero 67% VREF
80
110
dB
EXTERNAL REFERENCE SPECIFICATION (7)
VREF
External voltage reference
range
1.5
VDD
Input impedance
(7)
10
V
MΩ
In case of external reference connected, the noise of the reference has to be added.
6.6 I2C Interface
Unless otherwise specified, all limits ensured for at TA = 25°C, VS= (VDD – AGND), 2.7 V TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
This parameter is specified by design or characterization.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: LMP91002
LMP91002
www.ti.com
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
6.7 Timing Characteristics
Unless otherwise specified, all limits ensured for TA = 25°C, VS= (VDD – AGND), VS= 3.3 V and AGND = DGND = 0 V, VREF
= 2.5 V, Internal Zero= 20% VREF. All limits apply at the temperature extremes. Refer to timing diagram in Figure 1 (1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100
kHz
fSCL
Clock Frequency
At the temperature extremes
10
tLOW
Clock Low Time
At the temperature extremes
4.7
µs
tHIGH
Clock High Time
At the temperature extremes
4
µs
tHD;STA
Data valid
After this period, the first clock pulse is
generated at the temperature extremes
4
µs
tSU;STA
Set-up time for a repeated START
condition
At the temperature extremes
4.7
µs
tHD;DAT
Data hold time
(2)
At the temperature extremes
0
ns
tSU;DAT
Data Set-up time
At the temperature extremes
250
ns
IL ≤ 3 mA, CL ≤ 400 pF,
at the temperature extremes
(3)
tf
SDA fall time
tSU;STO
Set-up time for STOP condition
At the temperature extremes
4
µs
tBUF
Bus free time between a STOP and
START condition
At the temperature extremes
4.7
µs
tVD;DAT
Data valid time
At the temperature extremes
3.45
µs
tVD;ACK
Data valid acknowledge time
At the temperature extremes
3.45
µs
tSP
Pulse width of spikes that must be
suppressed by the input filter (3)
At the temperature extremes
50
ns
t_timeout
SCL and SDA Timeout
At the temperature extremes
25
100
ms
2
250
ns
tEN;START
I C Interface Enabling
At the temperature extremes
600
ns
tEN;STOP
I2C Interface Disabling
At the temperature extremes
600
ns
tEN;HIGH
time between consecutive I2C
interface enabling and disabling
At the temperature extremes
600
ns
(1)
(2)
(3)
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
LMP91002 provides an internal 300ns minimum hold time to bridge the undefined region of the falling edge of SCL.
This parameter is specified by design or characterization.
MENB
70%
30%
tEN;START
tEN;HIGH
tEN;STOP
70%
SDA
30%
tf
tVD;DAT
tLOW
tBUF
tHD;STA
tSP
SCL
70%
30%
tSU;STA
tHD;STA
tHIGH
tHD;DAT
START
1/fSCL
tSU;STO
tSU;DAT
tVD;ACK
REPEATED
START
STOP
START
Figure 1. I2C Interface Timing Diagram
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: LMP91002
7
LMP91002
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
www.ti.com
6.8 Typical Characteristics
Unless otherwise specified, TA = 25°C, VS= (VDD – AGND), 2.7 V VWE), VRW= 0 V.
LMP91000 OUTPUT
TEST PULSE
INPUT PULSE (50mV/DIV)
OUTPUT VOLTTAGE (500mV/DIV)
The width of the pulse is simply the time between the two writing operation.
TIME (25ms/DIV)
Figure 23. Test Procedure Example
18
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: LMP91002
LMP91002
www.ti.com
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
8.2 Typical Application
VDD
VREF
SCL
LMP91002
3-Lead
Electrochemical
Cell
+
CE
A1
DIAGNOSTIC
VREF
DIVIDER
I2C INTERFACE
AND
CONTROL
REGISTERS
SDA
MSP430
MENB
-
CE
RE
RE
DGND
WE
+
WE
-
RLoad
VOUT
TIA
RTIA
C1
C2
AGND
Figure 24. AFE Gas Detector
8.2.1 Design Requirements
The primary design requirement is selecting the appropriate TIA gain for the expected range of current over the
operating range of the sensor. This gain should set the VOUT range to fall within the limits of the full-scale
voltage for the ADC that is sampling the signal. For example, assume the current output range of the sensor is 0
to 100,000 nA, and the full scale ADC input range is 0 to 1 V. Because Gain = RTIA, the appropriate relationship
is:
ISENSOR × Gain = RTIA × 10 – 4 A ≤ 1 V
(1)
4
Hence, RTIA < 10 Ω. In this case, the closest programmed gain value is 7 kΩ (see Table 4). However, if
optimization of the full-scale range is desired, then alternatively, RTIA can be programmed to 350 kΩ, and a 10kΩ resistor connected between pins C1 and C2. This will give an equivalent resistance of 9.7 kΩ.
8.2.2 Detailed Design Procedure
8.2.2.1 Smart Gas Sensor Analog Front End
The LMP91002 together with an external EEPROM represents the core of a SMART GAS SENSOR AFE. In the
EEPROM it is possible to store the information related to the GAS sensor type, calibration and LMP91002's
configuration (content of registers 10h, 11h, 12h). At startup the microcontroller reads the EEPROM's content
and configures the LMP91002. A typical smart gas sensor AFE is shown in Figure 25. The connection of MENB
to the hardware address pin A0 of the EEPROM allows the microcontroller to select the LMP91002 and its
corresponding EEPROM when more than one smart gas sensor AFE is present on the I2C bus.
NOTE
Only EEPROM I2C addresses with A0 = 0 should be used in this configuration.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: LMP91002
19
LMP91002
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
www.ti.com
Typical Application (continued)
SCL
A0
SDA
SCL
MENB
MENB
SCL
SDA
I2C EEPROM
LMP91000
SDA
Figure 25. Smart Gas Sensor AFE
8.2.2.2 Smart Gas Sensor AFES on I2C Bus
The connection of Smart gas sensor AFEs on the I2C bus is the natural extension of the previous concepts. Also
in this case the microcontroller starts communication asserting 1 out of N MENB signals where N is the total
number of smart gas sensor AFE connected to the I2C bus. Only one of the devices (either LMP91002 or its
corresponding EEPROM) in the smart gas sensor AFE enabled will acknowledge the I2C commands. When the
communication with this particular module ends, the microcontroller de-asserts the corresponding MENB and
repeats the procedure for other modules. Figure 26 shows the typical connection when several smart gas sensor
AFEs are connected to the I2C bus.
SMART SENSOR AFE
SMART SENSOR AFE
SCL
SDA
A0
SCL
I2C EEPROM
SMART SENSOR AFE
GPIO 2
GPIO 1
SDA
LMP91000
MENB
SCL
SDA
I2C EEPROM
A0
SDA
SCL
LMP91000
MENB
SDA
A0
I2C EEPROM
SCL
SCL
SDA
MENB
LMP91000
GPIO N
µC
SCL
SDA
Figure 26. Smart Gas Sensor AFEs on I2C Bus
20
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: LMP91002
LMP91002
www.ti.com
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
Typical Application (continued)
NORMALIZED OUTPUT TIA (200mV/DIV)
2.75k
3.5k
7k
14k
35k
120k
350k
TIME (200 s/DIV)
Figure 27. IWE Step Current Response (Rise)
2.0
IWE
2.75k
3.5k
7k
14k
35k
120k
350k
IWE(50 A/DIV)
IWE
IWE(50 A/DIV)
NORMALIZED OUTPUT (200mV/DIV)
8.2.3 Application Curves
TIME (200 s/DIV)
Figure 28. IWE Step Current Response (Fall)
LMP91000
1.9
1.8
VOUT (V)
1.7
1.6
1.5
1.4
1.3
1.2
RTIA=35k ,
Rload=10 ,
1.1
1.0
0
25
50
75
100
TIME (s)
125
150
Figure 29. A VOUT Step Response 100 ppm to 400 ppm CO
(CO Gas Sensor Connected to LMP91002)
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: LMP91002
21
LMP91002
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
www.ti.com
9 Power Supply Recommendations
9.1 Power Consumption
The LMP91002 is intended for use in portable devices, so the power consumption is as low as possible in order
to ensure a long battery life. The total power consumption for the LMP91002 is below 10 µA at 3.3-V average
over time, (this excludes any current drawn from any pin). A typical usage of the LMP91002 is in a portable gas
detector and its power consumption is summarized in Table 7. This has the following assumptions:
• Power On only happens a few times over life, so its power consumption can be ignored
• Deep Sleep mode is not used
• The system is used about 8 hours a day, and 16 hours a day it is in Standby mode.
This results in an average power consumption of approximately 7.8 µA. This can potentially be further reduced,
by using the Standby mode between gas measurements. It may even be possible, depending on the sensor
used, to go into deep sleep for some time between measurements, further reducing the average power
consumption.
Table 7. Power Consumption Scenario
DEEP SLEEP
STANDBY
3-LEAD AMPEROMETRIC
CELL
Current consumption (µA) typical value
0.6
6.5
10
Time ON (%)
0
60
39
Average (µA)
0
3.9
3.9
A1
OFF
ON
ON
TIA
OFF
OFF
ON
ON
ON
ON
TOTAL
7.8
Notes
2
I C interface
10 Layout
10.1 Layout Guidelines
Figure 30 and Figure 31 show an example layout for the LMP91002. Figure 30 shows the top layer, and
Figure 31 shows the bottom layer. Figure 30 shows that the sensor electrodes may be arranged around the
LMP91002 so that the sensor sets directly over the LMP91002, creating a compact layout. There are very few
components needed for the LMP91002: one or more bypass capacitors attached to VDD, and one or two
optional external components attached to pins C1 or C2 of the TIA that can provide extra filtering or gain. In the
layout shown here, the VDD bypass capacitor is on the top layer, close to the LMP91002, while the optional
components for the TIA are placed on the bottom layer. However, these components may also be placed on the
top layer.
22
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: LMP91002
LMP91002
www.ti.com
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
10.2 Layout Example
CE
WE
LMP91002
RE
Figure 30. Layout Example – Top Layer
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: LMP91002
23
LMP91002
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
www.ti.com
Layout Example (continued)
CE
WE
Node C2
Node C1
RE
Optional external
components
Figure 31. Layout Example – Bottom Layer
24
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: LMP91002
LMP91002
www.ti.com
SNIS163B – APRIL 2012 – REVISED OCTOBER 2015
11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: LMP91002
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMP91002SD/NOPB
ACTIVE
WSON
NHL
14
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
L91002
LMP91002SDE/NOPB
ACTIVE
WSON
NHL
14
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
L91002
LMP91002SDX/NOPB
ACTIVE
WSON
NHL
14
4500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
L91002
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
