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LMP91050MME/NOPB

LMP91050MME/NOPB

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    VSSOP10

  • 描述:

    IC AFE INTERFACE 10VSSOP

  • 数据手册
  • 价格&库存
LMP91050MME/NOPB 数据手册
Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMP91050 SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 LMP91050 Configurable AFE for Nondispersive Infrared (NDIR) Sensing Applications 1 Features 3 Description • • • • • The LMP91050 device is a programmable integrated Sensor Analog Front End (AFE) optimized for thermopile sensors, as typically used in NDIR applications. It provides a complete signal path solution between a sensor and microcontroller that generates an output voltage proportional to the thermopile voltage. The programmability of the LMP91050 enables it to support multiple thermopile sensors with a single design as opposed to the multiple discrete solutions. 1 Programmable Gain Amplifier Dark Signal Offset Cancellation Supports External Filtering Common-Mode Generator and 8-Bit DAC Key Specifications – Programmable Gain 167 to 7986 V/V – Low Noise (0.1 to 10 Hz) 0.1 μVRMS – Gain Drift 100 ppm/°C (Maximum) – Phase Delay Drift 500 ns (Maximum) – Power Supply Voltage Range 2.7 to 5.5 V The LMP91050 features a programmable gain amplifier (PGA), dark phase offset cancellation, and an adjustable common-mode generator (1.15 V or 2.59 V) which increases output dynamic range. The PGA offers a low-gain range of 167 V/V to 1335 V/V plus a high-gain range of 1002 V/V to 7986 V/V which enables the user to use thermopiles with different sensitivities. The PGA is highlighted by low-gain drift (100 ppm/°C), output offset drift (1.2 mV/°C at G = 1002 V/V), phase delay drift (500 ns) and noise specifications (0.1 μVRMS 0.1 to 10Hz). 2 Applications • • • • • • • NDIR Sensing Demand Control Ventilation Building Monitoring CO2 Cabin Control — Automotive Alcohol Detection — Automotive Industrial Safety and Security GHG and Freons Detection Platforms Device Information(1) PART NUMBER LMP91050 PACKAGE VSSOP (10) BODY SIZE (NOM) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit 10 µF 6.8 nF 160 k VDD 10 µF CMOUT 10 nF VDD Thermopile 160 k A0 A1 OUT IN 1 kO û ADC 10 nF LMP91050 1 µF CSB CMOUT SCLK SDIO 10 nF GND Configurable AFE for NDIR 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMP91050 SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 3 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 3 4 4 4 4 6 6 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... SPI Interface ............................................................. Timing Characteristics ............................................. Typical Characteristics .............................................. Detailed Description ............................................ 12 8.1 Overview ................................................................. 12 8.2 Functional Block Diagram ....................................... 12 8.3 8.4 8.5 8.6 9 Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ......................................................... 12 14 14 16 Application and Implementation ........................ 18 9.1 Application Information............................................ 18 9.2 Typical Application ................................................. 18 10 Power Supply Recommendations ..................... 21 11 Layout................................................................... 21 11.1 Layout Guidelines ................................................. 21 11.2 Layout Example .................................................... 21 12 Device and Documentation Support ................. 22 12.1 12.2 12.3 12.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 13 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (March 2013) to Revision E • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision C (April 2012) to Revision D • 2 Page Page Changed layout of National Data Sheet to TI format ........................................................................................................... 17 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 LMP91050 www.ti.com SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 5 Description (continued) The offset cancellation circuitry compensates for the dark signal by adding an equal and opposite offset to the input of the second stage, thus removing the original offset from the output signal. This offset cancellation circuitry allows optimized usage of the ADC full scale and relaxes ADC resolution requirements. The LMP91050 allows extra signal filtering (high-pass, lowpass or bandpass) through dedicated pins A0 and A1, in order to remove out of band noise. The user can program through the on board SPI interface. Available in a small form factor 10-pin package, the LMP91050 operates from –40 to 105°C. 6 Pin Configuration and Functions DGS Package 10-Pin VSSOP Top View VDD IN SDIO CMOUT A0 LMP91050 SCLK A1 CSB GND OUT Pin Functions PIN NO. NAME TYPE DESCRIPTION 1 IN Analog Input 2 CMOUT Analog Output Signal Input Common-Mode Voltage Output 3 A0 Analog Output First Stage Output 4 A1 Analog Input 5 GND Power 6 OUT Analog Output 7 CSB Digital Input Chip Select, active low 8 SCLK Digital Input Interface Clock 9 SDIO 10 VDD Second Stage Input Ground Signal Output, reference to the same potential as CMOUT Digital Input / Output Serial Data Input / Output Power Positive Supply 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN MAX UNIT Supply Voltage (VDD) –0.3 6 V Voltage at Any Pin –0.3 VDD + 0.3 V 5 mA 150 °C 150 °C Input Current at Any Pin Junction Temperature (4) Storage Temperature, Tstg (1) (2) (3) (4) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. For soldering specifications: see product folder at www.ti.com and SNOA549. The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PC board. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 3 LMP91050 SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1250 Machine Model ±250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN MAX Supply Voltage 2.7 5.5 V Junction Temperature (2) –40 105 °C (1) (2) UNIT Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PC board. 7.4 Thermal Information LMP91050 THERMAL METRIC (1) DGS (VSSOP) UNIT 10 PINS RθJA (1) Junction-to-ambient thermal resistance 176 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics The following specifications apply for VDD = 3.3 V, VCM = 1.15 V, unless otherwise specified. All other limits apply to TA = TJ = +25°C. (1) PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT POWER SUPPLY VDD Supply voltage 2.7 3.3 5.5 V IDD Supply current All analog block ON 3.1 3.7 4.2 mA Power-down supply current All analog block OFF 45 85 121 μA OFFSET CANCELLATION (OFFSET DAC) Resolution LSB 256 All gains DNL -1 Error Output referred offset error, all gains Offset adjust range Output referred, all gains DAC settling time steps 33.8 mV 2 ±100 0.2 LSB mV VDD – 0.2 V μs 480 PROGRAMMABLE GAIN AMPLIFIER (PGA) 1ST STAGE, RL = 10 kΩ, CL = 15 pF 5 IBIAS (1) (2) (3) 4 Bias current TA = –40°C to +85°C 200 pA Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 LMP91050 www.ti.com SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 Electrical Characteristics (continued) The following specifications apply for VDD = 3.3 V, VCM = 1.15 V, unless otherwise specified. All other limits apply to TA = TJ = +25°C.(1) PARAMETER VINMAX _HGM Max input signal high-gain mode VINMAX _LGM Max input signal low-gain mode VOS Input offset voltage G _HGM G_LGM GE Gain error VOUT Output voltage range TEST CONDITIONS MIN (2) Referenced to CMOUT voltage, it refers to the maximum voltage at the IN pin before clipping; It includes dark voltage of the thermopile and signal voltage. TYP (3) MAX (2) UNIT ±2 mV ±12 mV -165 µV Gain high-gain mode 250 V/V Gain low-gain mode 42 V/V Both HGM and LGM 2.5% 0.5 PhDly Phase delay 1-mV input step signal, HGM, VOUT measured at Vdd/2 TCPhDly Phase delay variation with temperature 1-mV input step signal, HGM, VOUT measured at Vdd/2, SSBW Small signal bandwidth Vin = 1mVpp, Gain = 250 V/V Cin Input capacitance VDD – 0.5 V 6 μs 416 ns 18 kHz 100 pF 1.65 V 0.82 V PROGRAMMABLE GAIN AMPLIFIER (PGA) 2ND STAGE, RS = 1 kΩ, CL = 1 µF VINMAX Max input signal VINMIN Min input signal GAIN = 4 V/V G Gain Programmable in 4 steps GE Gain error Any gain VOUT Output voltage range 4 32 V/V 2.5 0.2 % VDD – 0.2 V PhDly Phase delay 100-mV input sine 35-kHz signal, Gain = 8, VOUT measured at 1.65 V, RL = 10 kΩ TCPhDly Phase delay variation with temperature 250-mV input step signal, Gain = 8, VOUT measured at Vdd/2 SSBW Small signal bandwidth Gain = 32 V/V Cin Input capacitance CLOAD, OUT OUT pin load capacitance Series RC 1 µF RLOAD, OUT OUT pin load resistance Series RC 1 kΩ Combination of both current and voltage noise, with a 86kΩ source impedance at 5Hz, Gain = 7986 30 nV/√Hz Combination of both current and voltage Input-referred integrated noise noise, with a 86kΩ source impedance 0.1Hz to 10Hz, Gain = 7986 0.1 1 µs 84 ns 360 kHz 5 pF COMBINED AMPLIFIER CHAIN SPECIFICATION en G GE (4) Input-referred noise density Gain Gain error PGA1 GAIN = 42, PGA2 GAIN = 4 167 PGA1 GAIN = 42, PGA2 GAIN = 8 335 PGA1 GAIN = 42, PGA2 GAIN = 16 669 PGA1 GAIN = 42, PGA2 GAIN = 32 1335 PGA1 GAIN = 250, PGA2 GAIN = 4 1002 PGA1 GAIN = 250, PGA2 GAIN = 8 2004 PGA1 GAIN = 250, PGA2 GAIN = 16 4003 PGA1 GAIN = 250, PGA2 GAIN = 32 7986 Any gain 0.12 (4) µVrms V/V 5% Specified by design and characterization. Not tested on shipped production material. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 5 LMP91050 SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com Electrical Characteristics (continued) The following specifications apply for VDD = 3.3 V, VCM = 1.15 V, unless otherwise specified. All other limits apply to TA = TJ = +25°C.(1) PARAMETER TEST CONDITIONS (5) TCCGE Gain temp coefficient PSRR Power supply rejection ratio DC, 3-V to 3.6-V supply, gain = 1002 V/V PhDly Phase delay 1-mV input step signal, Gain = 1002, VOUT measured at Vdd/2 TCPhDly Phase delay variation with temperature (6) 1-mV input step signal, Gain=1002, VOUT measured at Vdd/2, TA = –40°C to +85°C TCVOS Output offset voltage temperature drift (5) MIN (2) TYP (3) TA = –40°C to +85°C MAX (2) 100 90 UNIT ppm/°C 110 dB 9 µs 500 Gain = 167 V/V, TA = –40°C to +85°C –0.525 0.525 Gain = 335 V/V, TA = –40°C to +85°C –0.6 0.6 Gain = 669 V/V, TA = –40°C to +85°C –0.9 0.9 Gain = 1335 V/V, TA = –40°C to +85°C –1.5 1.5 Gain = 1002 V/V, TA = –40°C to +85°C –1.2 1.2 Gain = 2004 V/V, TA = –40°C to +85°C –1.9 1.9 Gain = 4003 V/V, TA = –40°C to +85°C –3.7 3.7 Gain = 7986V/V, TA = –40°C to +85°C –7.1 7.1 ns mV/°C COMMON-MODE GENERATOR VCM Common-mode voltage Programmable, see Common-Mode Generation 1.15 or 2.59 VCM accuracy CLOAD (5) (6) V 2% CMOut load capacitance 10 nF TCCGE and TCVOS are calculated by taking the largest slope between -40°C and 25°C linear interpolation and 25°C and 85°C linear interpolation. TCPhDly is largest change in phase delay between -40°C and 25°C measurements and 25°C and 85°C measurements. 7.6 SPI Interface The following specifications apply for VDD = 3.3 V, VCM = 1.15 V, CL = 15 pF, unless otherwise specified. All other limits apply to TA = TJ = +25°C. (1) PARAMETER VIH Logic input high VIL Logic input low VOH Logic output high VOL Logic output low IIH/IIL (1) (2) (3) Input digital leakage current TEST CONDITIONS MIN (2) TYP (3) MAX (2) 0.7 × VDD V 0.8 2.6 V V 0.4 TA = –40°C to +85°C UNIT –100 100 –200 200 V nA Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. 7.7 Timing Characteristics The following specifications apply for VDD = 3.3 V, VCM = 1.15 V, CL = 15 pF, unless otherwise specified. All other limits apply to TA = TJ = +25°C. (1) (1) 6 Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 LMP91050 www.ti.com SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 Timing Characteristics (continued) The following specifications apply for VDD = 3.3 V, VCM = 1.15 V, CL = 15 pF, unless otherwise specified. All other limits apply to TA = TJ = +25°C.(1) PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) Wake-up time fSCLK Serial clock frequency tPH SCLK pulse width high 0.4 / fSCLK ns tPL SCLK pulse width low 0.4 / fSCLK ns tCSS CSB set-up time 10 ns tCSH CSB hold time 10 ns tSU SDI set-up time prior to rise edge of SCLK 10 ns tSH SDI hold time prior to rise edge of SCLK 10 ns tDOD1 SDO disable time after rise edge of CSB 45 ns tDOD2 SDO disable time after 16th rise edge of SCLK 45 ns tDOE SDO enable time from the fall edge of 8th SCLK 35 ns tDOA SDO access time after the fall edge of SCLK 35 ns tDOH SDO hold time after the fall edge of SCLK tDOR SDO rise time 5 ns tDOF SDO fall time 5 ns (2) (3) 1 UNIT tWU ms 10 5 MHz ns Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Figure 1. SPI Timing Diagram tPL tPH 16th clock SCLK tH tSU SDI Valid Data Valid Data Figure 2. SPI Set-Up Hold Time Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 7 LMP91050 SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com Figure 3. SDO Disable Time After 16th Rise Edge of SCLK Figure 4. SDO Access Time (tDOA) and SDO Hold Time (tDOH) After the Fall Edge of SCLK Figure 5. SDO Enable Time from the Fall Edge of 8th SCLK Figure 6. SDO Disable Time after Rise Edge of CSB Figure 7. SDO Rise and Fall Times 8 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 LMP91050 www.ti.com SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 7.8 Typical Characteristics 168.4 336.0 168.3 335.9 168.2 335.8 GAIN (V/V) GAIN (V/V) VDD = +3.3 V, VCM = 1.15 V, and TA = 25°C unless otherwise noted 168.1 168.0 335.6 167.9 335.5 167.8 -50 335.7 -25 0 25 50 75 TEMPERATURE (°C) 335.4 -50 100 Figure 8. Gain = 167 V/V vs. Temperature -25 0 25 50 75 TEMPERATURE (°C) 100 Figure 9. Gain = 335 V/V vs. Temperature 672.5 1011 672.4 GAIN (V/V) GAIN (V/V) 672.3 672.2 672.1 672.0 1010 1009 671.9 671.8 671.7 -50 1008 -25 0 25 50 75 TEMPERATURE (°C) 100 -50 2014 9.3 2013 9.2 2012 2011 2010 9.1 9.0 8.9 8.8 2009 8.7 2008 8.6 -50 -25 0 25 50 75 TEMPERATURE (°C) 100 Figure 11. Gain = 1002 V/V vs. Temperature PHASE DELAY (s) GAIN (V/V) Figure 10. Gain = 669 V/V vs. Temperature -25 0 25 50 75 TEMPERATURE (°C) 100 Figure 12. Gain = 2004 V/V vs. Temperature -50 -25 0 25 50 TEMPERATURE (°C) 75 100 Figure 13. Phase Delay vs. Temperature Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 9 LMP91050 SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) VDD = +3.3 V, VCM = 1.15 V, and TA = 25°C unless otherwise noted 1.160 100 COMMON MODE VOLTAGE (V) OUTPUT OFFSET (mV) 90 80 70 60 50 40 30 G = 1002 V/V 20 10 0 -50 -25 0 25 50 TEMPERATURE (°C) 75 1.154 1.152 0 5 -1 4 -2 -3 -25 0 25 50 75 TEMPERATURE (°C) 100 Figure 15. Common-Mode Voltage vs. Temperature IDD (mA) IBIAS (pA) 1.156 1.150 -50 100 Figure 14. Output Offset vs. Temperature 1.158 3 2 G = 1002 V/V -4 1 -5 0 -50 -25 0 25 50 TEMPERATURE (°C) 75 100 -50 Figure 16. Input Bias Current vs. Temperature -25 0 25 50 TEMPERATURE (°C) 75 100 Figure 17. Supply Current vs. Temperature 4.5 120 4.0 110 3.5 100 IDD (A) IDD (mA) 3.0 2.5 2.0 1.5 80 PGA ALL ON PGA2 ON PGA1 ON 1.0 0.5 70 0.0 2.5 60 3.0 3.5 4.0 4.5 VDD (V) 5.0 5.5 Figure 18. Supply Current vs. Supply Voltage 10 90 2.5 3.0 3.5 4.0 4.5 VDD (V) 5.0 5.5 Figure 19. Power-Down Supply Current vs. Supply Voltage Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 LMP91050 www.ti.com SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 Typical Characteristics (continued) VDD = +3.3 V, VCM = 1.15 V, and TA = 25°C unless otherwise noted OUTPUT OFFSET (mV) 70 G = 1002 V/V 65 60 55 50 2.5 3.0 3.5 4.0 4.5 VDD (V) 5.0 5.5 Figure 20. Output Offset vs. Supply Voltage Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 11 LMP91050 SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com 8 Detailed Description 8.1 Overview The input channel of the LMP91050 features two programmable gain stages that give the user flexibility in optimizing the system gain. Access to the inter-stage connection between the gain blocks also allows the inclusion of appropriate filtering if needed. The internal DAC allows the DC offset of the output voltage to be adjusted independently of the common-mode voltage supplied to the sensor, enabling the sampled signal to be centered within the ADC full-scale input range. The following paragraphs discuss the LMP91050’s features in more detail. 8.2 Functional Block Diagram CMOUT VDD A0 A1 LMP91050 G2=4,8,16,32 G1=250,42 IN SPI OUT PGA2 PGA1 DAC CMOUT SPI CM GEN VREF GND CSB SCLK SDIO 8.3 Feature Description 8.3.1 Programmable Gain Amplifier The LMP91050 offers two programmable gain modes (low or high) with four programmable gain settings each. The purpose of the gain mode is to enable thermopiles with larger dark voltage levels. All gain settings are accessible through bits GAIN1 and GAIN2[1:0]. The low-gain mode has a range of 167 V/V to 1335 V/V while the high-gain mode has a range of 1002 V/V to 7986 V/V. The PGA is referenced to the internally generated VCM. Input signal, referenced to this VCM voltage, should be within ±2 mV (see VINMAX_HGM specification) in highgain mode. In the low gain mode the first stage will provide a gain of 42 V/V instead of 250 V/V, thus allowing a larger maximum input signal up to ±12 mV (VINMAX_LGM). Table 1. Gain Modes BIT SYMBOL 0: 250 (default) GAIN1 12 GAIN 1: 42 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 LMP91050 www.ti.com SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 Feature Description (continued) Table 1. Gain Modes (continued) BIT SYMBOL GAIN 00: 4 (default) 01: 8 GAIN2 [1:0] 10: 16 11: 32 8.3.2 External Filter The LMP91050 offers two different measurement modes selectable through EXT_FILT bit. EXT_FILT bit is present in the Device configuration register and is programmable through SPI. Table 2. Measurement Modes BIT SYMBOL EXT_FILT MEASUREMENT MODE 0: The signal from the thermopile is being processed by the internal PGAs, without additional external decoupling or filtering (default). 1: The signal from the thermopile is being processed by the first internal PGA and fed to the A0 pin. An external low pass, high pass or band pass filter can be connected through pins A0, A1. An external filter can be applied when EXT_FILT = 1. A typical band pass filter is shown in the picture below. Resistor and capacitor can be connected to the CMOUT pin of the LMP91050 as shown. Discrete component values have been added for reference. 10 µF 160 k A1 A0 6.8 nF 160 k CMOUT Figure 21. Typical Bandpass Filter 8.3.3 Offset Adjust Procedure of the offset adjust is to first measure the dark signal, program the DAC to adjust, and then measure in a second cycle the residual of the dark signal for further signal manipulation within the µC. The signal source is expected to have an offset component (dark signal) larger than the actual signal. During the dark phase, the time when no light is detected by the sensor, the µC can program LMP91050 internal DAC to compensate for a measured offset. A low output offset voltage temperature drift (TCVOS) ensures system accuracy over temperature. See Figure 22 below which plots the maximum TCVOS allowed over a given temperature drift in order to achieve n bit system accuracy. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 13 LMP91050 SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com MAX TCVOS (mV/°C) 100 12 bit Accuracy 11 bit Accuracy 10 bit Accuracy 9 bit Accuracy 8 bit Accuracy 10 1 100m 10m 1 2 3 4 5 6 7 8 9 TEMPERATURE DRIFT (°C) 10 Figure 22. System Accuracy vs. TCVOS and Temperature Drift 8.3.4 Common-Mode Generation As the offset of the sensor is bipolar, there is a need to supply a VCM to the sensor. This can be programmed as 1.15 V or 2.59 V (approximately mid rail of 3.3-V or 5-V supply). TI does not recommend to use 2.59-V VCM with a 3.3-V supply 8.3.5 CSB Chip Select is a active-low signal. CSB needs to be asserted throughout a transaction. That is, CSB should not pulse between the Instruction Byte and the Data Byte of a single transaction. NOTE CSB de-assertion always terminates an on-going transaction, if it is not already complete. Likewise, CSB assertion will always bring the device into a state, ready for next transaction, regardless of the termination status of a previous transaction. CSB may be permanently tied low for a 2-wire SPI communication protocol. 8.3.5.1 SCLK SCLK can idle High or Low for a write transaction. However, for a READ transaction, SCLK must idle high. SCLK features a Schmitt-triggered input and although it has hysterisis, TI recommends to keep SCLK as clean as possible to prevent glitches from inadvertently spoiling the SPI frame. 8.4 Device Functional Modes To read the registers of the LMP91050, the SDIO mode enable register must be written using a special sequence, as described in the SDIO Mode section. During the reading process, the analog OUT pin is still active, as normal. There are no other special modes for the device. 8.5 Programming 8.5.1 SPI Interface An SPI interface is available in order to program the device parameters like PGA gain of two stages, enabling external filter, enabling power for PGAs, offset adjust and common-mode (VCM) voltage. 8.5.1.1 Interface Pins The Serial Interface consists of SDIO (Serial Data Input / Output), SCLK (Serial Interface Clock) and CSB (Chip Select Bar). The serial interface is write-only by default. Read operations are supported after unlocking the SDIO_MODE_PASSWD. This is discussed in detail later in the document. 14 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 LMP91050 www.ti.com SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 Programming (continued) 8.5.1.2 Communication Protocol Communication on the SPI normally involves Write and Read transactions. Write transaction consists of single Write Command Byte, followed by single Data byte. The following figure shows the SPI Interface Protocol for write transaction. CSB 1 2 3 4 5 6 7 8 9 11 10 12 13 14 15 16 SCK COMMAND FIELD DATA FIELD MSB c7 Wb=0 c6 c5 c4 c3 Reserved to 0 c2 c1 c0 d7 LSB d6 d5 Address (4 bits) d4 d3 d2 d1 d0 Write Data (8-bits) Figure 23. SPI Interface Protocol For Read transactions, user first needs to write into a SDIO mode enable register for enabling the SPI read mode. Once the device is enabled for Reading, the data is driven out on the SDIO pin during the Data field of the Read Transaction. SDIO pin is designed as a bidirectional pin for this purpose. Figure 24 shows the Read transaction. The sequence of commands that need to be issued by the SPI Master to enable SPI read mode is shown in Figure 25. Figure 24. Read Transaction Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 15 LMP91050 SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com Programming (continued) Sequence of transactions for unlocking SDIO_MODE CSB SDI Write cmd (sdio_mod e_en reg) Write data Write cmd Write (0xFE first (sdio_mode data byte of _en reg) (0xED) sdio_mode _en reg) Read cmd (to read contents of any register specified by the address bits) SDO Read data Bus turnaround time = half cycle Note: 1. Once the SDIO_mode is unlocked. The user can read as many registers as long as nothing else is written to sdio_mode_en register to disturb the state of SDIO_mode 2. The separate signals SDI and SDO are given in the figure for the sake of understanding. However, only one signal SDIO exists in the design Figure 25. Enable SDIO Mode for Reading SPI Registers 8.5.1.3 Registers Organization Configuring the device is achieved using Write of the designated registers in the device. All the registers are organized into individually addressable byte-long registers that have a unique address. The format of the Write/ Read instruction is as shown below. Table 3. Write / Read Instruction Format Bit[7] 0 : Write Instruction 1 : Read Instruction Bit[6:4] Reserved to 0 Bit[3:0] Address 8.6 Register Maps This section describes the programmable registers and the associated programming sequence, if any, for the device. Table 4 shows the summary listing of all the registers that are available to the user and their power-up values. Table 4. Register Descriptions Title Address (Hex) Device Configuration 0x0 DAC Configuration 0x1 SDIO Mode Enable 0xF 16 Power-up/Reset Value (Hex) Type Read-Write (Read allowed in SDIO Mode) Read-Write (Read allowed in SDIO Mode) Write-only Submit Documentation Feedback 0x0 0x80 0x0 Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 LMP91050 www.ti.com SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 8.6.1 Device Configuration Table 5. Device Configuration Register (Address 0x0) Bit Bit Symbol 7 RESERVED Description Reserved to 0. 00: PGA1 OFF PGA2 OFF (default) [6:5] EN 01: PGA1 OFF, PGA2 ON 10: PGA1 ON, PGA2 OFF 11: PGA1 ON, PGA2 ON 4 EXT_FILT 3 CMN_MODE 0: PGA1 to PGA2 direct (default) 1: PGA1 to PGA2 via external filter 0 : 1.15V (default) 1 : 2.59V 00: 4 (default) [2:1] GAIN2 01: 8 10: 16 11: 32 0 GAIN1 0: 250 (default) 1: 42 8.6.2 DAC Configuration The output DC level will shift according to the formula Vout_shift = -33.8mV * (NDAC - 128). Table 6. DAC Configuration Register (Address 0x1) Bit Bit Symbol [7:0] NDAC Description 128 (0x80): Vout_shift = -33.8mV * (128 - 128) = 0mV (default) 8.6.3 SDIO Mode Write-only Table 7. SDIO Mode Enable Register (Address 0xf) Bit [7:0] Bit Symbol SDIO_MODE_EN Description To enter SDIO Mode, write the successive sequence 0xFE and 0xED. Write anything other than this sequence to get out of mode. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 17 LMP91050 SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information Figure 26 shows a typical NDIR sensing circuit with a bandpass filter with a high frequency cutoff of approximately 100 Hz. The lowpass filter at the output has a cutoff of approximately 110 Hz. 9.2 Typical Application 10 µF 6.8 nF 160 k VDD 10 µF CMOUT 10 nF VDD Thermopile 160 k A0 A1 OUT IN 1 kO û ADC 10 nF LMP91050 1 µF CSB CMOUT SCLK SDIO 10 nF GND Figure 26. Typical NDIR Sensing Application Circuit 9.2.1 Design Requirements The design requirements for using the LMP91050 in an application basically include the following: • Determine the characteristics of the thermopile and the appropriate gain and common mode voltage that will maximize the dynamic range of the sensor. Consult the manufacturer’s data sheet. • Selecting an analog-to-digital converter that supports the needed resolution and update rate. • Determining the bandwidth of the inter-stage low-pass filter to limit the noise imposed on the signal • An SPI interface to a microcontroller or other logic device is required in order to configure the LMP91050. 9.2.2 Detailed Design Procedure The basic design procedure is as follows: • Select the appropriate inter-stage bandpass filter bandwidth. Note that the common mode voltage (CMOUT) is connected to both the thermopile and the bandpass filter, as shown in Figure 26. • TI recommends that a lowpass filter be inserted between the OUT pin and the input to the ADC, to further reduce noise on the signal and prevent aliasing. • Power supply bypassing as shown in figure 32 is recommended. • Based on the thermopile characteristics, select the common-mode voltage and gain to be programmed into the LMP91050. CMOUT should be selected to center the expected dynamic range of the thermopile within the full scale range of the ADC to the best extent possible. The gain should be selected to maximize the 18 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 LMP91050 www.ti.com SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 Typical Application (continued) • signal range at the ADC input, but should allow some headroom below full scale to prevent clipping. The gain should also compensate, if possible, for any loss due to the filters in the signal path. The internal DAC can be programmed to further optimize the signal range on the OUT pin. See Offset Adjust for further information. 9.2.3 Application Curves 60 40 G = 32 V/V G = 16 V/V G = 8 V/V G = 4 V/V G = 250 V/V G = 42 V/V 50 GAIN (dB) GAIN (dB) 30 40 30 20 20 10 10 0 0 1k 10k 100k FREQUENCY (Hz) 1M 10k Figure 27. PGA1 Small Signal Bandwidth 140 G = 7986 V/V G = 4003 V/V G = 2004 V/V G = 1002 V/V NOISE DENSITY (nV/¥+]) PSRR (dB) 10M Figure 28. PGA2 Small Signal Bandwidth 120 110 100k 1M FREQUENCY (Hz) 100 90 80 70 120 100 60 80 60 40 20 0 10 100 FREQUENCY (Hz) 1k Figure 29. Power Supply Rejection Ratio vs. Frequency 100m 1 10 100 1k FREQUENCY (Hz) 10k Figure 30. Input-Referred Noise Density vs. Frequency Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 19 LMP91050 SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com Typical Application (continued) 3.5 5.50 G = 1002 V/V G = 2004 V/V G = 4003 V/V G = 7986 V/V 2.5 2.0 1.5 VDD = 3.3V 1.0 0.5 0.0 4.00 3.25 2.50 VDD = 5V 1.75 1.00 0.25 -0.5 -0.50 0 50 100 150 200 DAC CODE 250 300 Figure 31. DAC DC Sweep With VDD = 3.3 V 20 G = 1002 V/V G = 2004 V/V G = 4003 V/V G = 7986 V/V 4.75 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 3.0 0 50 100 150 200 DAC CODE 250 300 Figure 32. DAC DC Sweep With VDD = 5 V Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 LMP91050 www.ti.com SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 10 Power Supply Recommendations Because the LMP91050 is used in a sampled data system, care must be taken to maintain power supply noise below an acceptable level, which will depend on the requirements of the application. In all cases, follow the manufacturer’s design recommendations for the power conditioning device used in the system. The LMP91050 offers excellent power supply rejection over a wide range of frequencies, but adequate power supply bypassing should always be used (see Figure 26). If using a switching supply, additional filtering may be required particularly if the switcher harmonics fall within the passband of the filters used in the system. Ensure that the selected power conditioning device is capable of sourcing the current required by the LMP91050. 11 Layout 11.1 Layout Guidelines Figure 33 shows a layout example for the LMP91050. All components should be placed as close as possible to the device, especially the bypass capacitors to VDD (CBypass1 and CBypass2). 11.2 Layout Example Figure 33. LMP91050 Layout Example Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 21 LMP91050 SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com 12 Device and Documentation Support 12.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: LMP91050 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LMP91050MM/NOPB ACTIVE VSSOP DGS 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 AN8A LMP91050MME/NOPB ACTIVE VSSOP DGS 10 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 AN8A LMP91050MMX/NOPB ACTIVE VSSOP DGS 10 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 AN8A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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