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LMR10510
SNVS727C – OCTOBER 2011 – REVISED JUNE 2019
LMR10510 5.5-VIN, 1-A Step-Down Voltage Regulator
in SOT-23 and WSON Packages
1 Features
3 Description
•
•
•
•
The LMR10510 regulator is a monolithic, high
frequency, PWM step-down DC/DC converter in a 5pin SOT-23 and a 6-pin WSON package. It provides
all the active functions to provide local DC/DC
conversion with fast transient response and accurate
regulation in the smallest possible PCB area. The
LMR10510 is internally compensated, so it is simple
to use and requires few external components. The
ability to drive 1-A loads with an internal 130-mΩ
PMOS switch results in the best power density
available. The world-class control circuitry allows ontimes as low as 30 ns, thus supporting exceptionally
high frequency conversion over the entire 3-V to 5.5V input operating range down to the minimum output
voltage of 0.6 V.
1
•
•
•
•
•
•
•
•
Input Voltage Range of 3 V to 5.5 V
Output Voltage Range of 0.6 V to 4.5 V
Output Current up to 1 A
1.6-MHz (LMR10510X) and 3-MHz (LMR10510Y)
Switching Frequencies
Low Shutdown IQ, 30 nA Typical
Internal Soft Start
Internally Compensated
Current-Mode PWM Operation
Thermal Shutdown
SOT-23 (2.92 × 2.84 × 1 mm) and WSON
(3 × 3 × 0.8 mm) Packaging
Tiny Overall Solution Reduces System Cost
Create a custom design using the LMR10510 with
the WEBENCH® Power Designer
•
•
•
•
•
PART NUMBER
LMR10510
2 Applications
•
Device Information(1)
Point-of-Load Conversions from 3.3-V- and 5-V
Rails
Space Constrained Applications
Battery Powered Equipment
Industrial Distributed Power Applications
Power Meters
Portable Hand-Held Instruments
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
WSON (6)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
space
space
Simplified Application
FB
EN
LMR10510
R3
VIN
GND
L1
VOUT
SW
VIN
R1
C1
D1
C2
C3
R2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR10510
SNVS727C – OCTOBER 2011 – REVISED JUNE 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description, continued ..........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
4
4
5
6
Absolute Maximum Ratings ......................................
Recommended Operating Ratings............................
Electrical Characteristics...........................................
Typical Performance Characteristics ........................
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Layout................................................................... 20
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Example ....................................................
Thermal Definitions ...............................................
WSON Package ....................................................
20
20
20
22
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2013) to Revision C
•
Editorial changes only; add WEBENCH links and top navigator icon for reference design................................................... 1
Changes from Revision A (April 2013) to Revision B
•
2
Page
Page
Changed layout of National Semiconductor data sheet to TI format...................................................................................... 1
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5 Description, continued
The LMR10510 is a constant frequency PWM buck regulator IC that delivers a 1-A load current. The regulator
has a preset switching frequency of 1.6 MHz or 3 MHz. This high frequency allows the LMR10510 to operate
with small surface mount capacitors and inductors, resulting in a DC/DC converter that requires a minimum
amount of board space. Even though the operating frequency is high, efficiencies up to 93% are easy to achieve.
External shutdown is included, featuring an ultra-low stand-by current of 30 nA. The LMR10510 utilizes currentmode control and internal compensation to provide high-performance regulation over a wide range of operating
conditions. Additional features include internal soft-start circuitry to reduce inrush current, pulse-by-pulse current
limit, thermal shutdown, and output overvoltage protection.
6 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
EN
3
4
NGG Package
6-Pin WSON
Top View
FB
2 GND
VIN
1
5
SW
FB
1
GND
2
SW
3
6 EN
DAP
5 VINA
4 VIND
Pin Description: 5-Pin SOT-23
PIN
NO.
DESCRIPTION
NAME
1
SW
2
GND
Switch node. Connect to the inductor and catch diode.
3
FB
Feedback pin. Connect to external resistor divider to set output voltage.
4
EN
Enable control input. Logic high enables operation. Do not allow this pin to float or be greater than VIN
+ 0.3V.
5
VIN
Input supply voltage.
Signal and power ground pin. Place the bottom resistor of the feedback network as close as possible
to this pin.
Pin Descriptions 6-Pin WSON
PIN
NO.
DESCRIPTION
NAME
1
FB
2
GND
3
SW
4
VIND
Power Input supply.
5
VINA
Control circuitry supply voltage. Connect VINA to VIND on PC board.
6
EN
DAP
Die Attach Pad
Feedback pin. Connect to external resistor divider to set output voltage.
Signal and power ground pin. Place the bottom resistor of the feedback network as close as
possible to this pin.
Switch node. Connect to the inductor and catch diode.
Enable control input. Logic high enables operation. Do not allow this pin to float or be greater than
VINA + 0.3V.
Connect to system ground for low thermal impedance, but it cannot be used as a primary GND
connection.
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7 Specifications
7.1 Absolute Maximum Ratings (1) (2)
VIN
-0.5V to 7V
FB Voltage
-0.5V to 3V
EN Voltage
-0.5V to 7V
SW Voltage
-0.5V to 7V
ESD Susceptibility
2kV
Junction Temperature (3)
150°C
−65°C to +150°C
Storage Temperature
For soldering specifications: http://www.ti.com/lit/SNOA549C
(1)
(2)
(3)
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for
which the device is intended to be functional, but does not ensure specfic performance limits. For specific specifications and test
conditions, see Electrical Characteristics
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Thermal shutdown will occur if the junction temperature exceeds the maximum junction temperature of the device.
7.2 Recommended Operating Ratings
VIN
3V to 5.5V
−40°C to +125°C
Junction Temperature
4
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7.3 Electrical Characteristics
VIN = 5 V unless otherwise indicated under the Conditions column. Limits in standard type are for TJ = 25°C only; limits in
boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified
through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are
provided for reference purposes only. (1) (2)
PARAMETER
VFB
ΔVFB/VIN
IB
UVLO
TEST CONDITIONS
Feedback Voltage
Feedback Voltage Line Regulation
MIN
TYP
MAX
0.588
0.600
0.612
VIN = 3V to 5V
0.02
Feedback Input Bias Current
Undervoltage Lockout
VIN Rising
VIN Falling
1.85
UVLO Hysteresis
FSW
Switching Frequency
DMAX
Maximum Duty Cycle
DMIN
Minimum Duty Cycle
RDS(ON)
ICL
VEN_TH
(2)
(3)
Switch Current Limit
100
nA
2.73
2.90
V
2.3
0.43
1.2
1.6
1.95
LMR10510-Y
2.25
3.0
3.75
LMR10510-X
86
94
LMR10510-Y
82
90
LMR10510-X
5
LMR10510-Y
7
WSON Package
150
SOT-23 Package
130
1.2
Switch Leakage
Enable Pin Current
Quiescent Current (switching)
MHz
%
%
195
1.75
mΩ
A
0.4
Enable Threshold Voltage
IEN
V
LMR10510-X
VIN = 3.3V
V
%/V
0.1
Shutdown Threshold Voltage
ISW
IQ
(1)
Switch On Resistance
UNIT
1.8
100
V
nA
Sink/Source
100
LMR10510X VFB = 0.55
3.3
5
mA
6.5
mA
LMR10510Y VFB = 0.55
4.3
Quiescent Current (shutdown)
All Options VEN = 0V
30
θJA
Junction to Ambient
0 LFPM Air Flow (3)
WSON Package
80
SOT-23 Package
118
θJC
Junction to Case
WSON Package
18
SOT-23 Package
80
TSD
Thermal Shutdown Temperature
nA
165
nA
°C/W
°C/W
°C
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate TI’s Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely parametric norm.
Applies for packages soldered directly onto a 3” × 3” PC board with 2-oz. copper on 4 layers in still air.
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7.4 Typical Performance Characteristics
100
100
90
90
EFFICIENCY (%)
EFFICIENCY (%)
Unless stated otherwise, all curves taken at VIN = 5 V with configuration in typical application circuit shown in Figure 15. TJ =
25°C, unless otherwise specified.
80
70
60
50
80
70
60
50
1.8Vout
3.3Vout
40
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
VIN = 5 V
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
VOUT = 1.8 V and 3.3 V
VIN = 5 V
Figure 1. Η vs Load "X"
OSCILLATOR FREQUENCY (MHz)
1.81
90
EFFICIENCY (%)
VOUT = 1.8 V and 3.3 V
Figure 2. Η vs Load "Y"
100
80
70
60
50
LMR10510Y
LMR10510X
40
VIN = 3.3 V
1.76
1.71
1.66
1.61
1.56
1.51
1.46
1.41
1.36
-45 -40
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
-10
20
50
80 110 125 130
TEMPERATURE (ºC)
VOUT = 1.8 V
Figure 3. Η vs Load "X And Y"
Figure 4. Oscillator Frequency vs Temperature - "X"
3.45
2000
3.35
1950
3.25
1900
CURRENT LIMIT (mA)
OSCILLATOR FREQUENCY (MHz)
1.8Vout
3.3Vout
40
3.15
3.05
2.95
2.85
2.75
1850
1800
1750
1700
1650
1600
2.65
1550
2.55
-45 -40
1500
-10
20
50
80 110 125 130
-45 -40
TEMPERATURE (ºC)
-10
20
50
80 110 125 130
TEMPERATURE (oC)
VIN = 3.3 V
Figure 5. Oscillator Frequency vs Temperature - "Y"
6
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Figure 6. Current Limit vs Temperature
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Typical Performance Characteristics (continued)
Unless stated otherwise, all curves taken at VIN = 5 V with configuration in typical application circuit shown in Figure 15. TJ =
25°C, unless otherwise specified.
Figure 8. RDSON vs Temperature (Sot-23 Package)
3.6
4.6
3.5
4.5
3.4
4.4
IQ (mA)
IQ (mA)
Figure 7. RDSON vs Temperature (WSON Package)
3.3
4.3
3.2
4.2
3.1
4.1
3.0
-45
-40 -10
20
50
80
4.0
-45
110 125 130
-40 -10
20
50
80
110 125 130
TEMPERATURE (ºC)
TEMPERATURE (ºC)
Figure 9. LMR10510X IQ (Quiescent Current)
Figure 10. LMR10510Y IQ (Quiescent Current)
FEEBACK VOLTAGE (V)
0.610
0.605
0.600
0.595
0.590
-45 -40 -10
20
50
80
110 125 130
TEMPERATURE (ºC)
VIN = 5 V
Figure 11. VFB vs Temperature
VOUT = 1.2 V at 1 A
Figure 12. Gain vs Frequency
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Typical Performance Characteristics (continued)
Unless stated otherwise, all curves taken at VIN = 5 V with configuration in typical application circuit shown in Figure 15. TJ =
25°C, unless otherwise specified.
VIN = 5 V
VOUT = 1.2 V at 1 A
Figure 13. Phase Plot vs Frequency
8
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8 Detailed Description
8.1 Overview
The following operating description of the LMR10510 refers to Functional Block Diagram and to the waveforms in
Figure 14. The LMR10510 supplies a regulated output voltage by switching the internal PMOS control switch at
constant frequency and variable duty cycle. A switching cycle begins at the falling edge of the reset pulse
generated by the internal oscillator. When this pulse goes low, the output control logic turns on the internal
PMOS control switch. During this on-time, the SW pin voltage (VSW) swings up to approximately VIN, and the
inductor current (IL) increases with a linear slope. IL is measured by the current sense amplifier, which generates
an output proportional to the switch current. The sense signal is summed with the regulator’s corrective ramp and
compared to the error amplifier’s output, which is proportional to the difference between the feedback voltage
and VREF. When the PWM comparator output goes high, the output switch turns off until the next switching cycle
begins. During the switch off-time, inductor current discharges through the Schottky catch diode, which forces the
SW pin to swing below ground by the forward voltage (VD) of the Schottky catch diode. The regulator loop
adjusts the duty cycle (D) to maintain a constant output voltage.
VSW
D = TON/TSW
VIN
SW
Voltage
TOFF
TON
0
t
VD
IL
TSW
IPK
Inductor
Current
0
t
Figure 14. Typical Waveforms
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8.2 Functional Block Diagram
EN
VIN
+
ENABLE and UVLO
ThermalSHDN
I SENSE
-
+
-
I LIMIT
-
1 .15 x VREF
+
OVPSHDN
Ramp Artificial
Control Logic
cv
I SENSE
R
R
Q
+
FB
S
1.6 MHz
PFET
-
+
DRIVER
Internal - Comp
SW
VREF = 0.6V
SOFT - START
Internal - LDO
GND
10
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8.3 Feature Description
8.3.1 Soft Start
This function forces VOUT to increase at a controlled rate during start up. During soft-start, the error amplifier’s
reference voltage ramps from 0V to its nominal value of 0.6 V in approximately 600 µs. This forces the regulator
output to ramp up in a controlled fashion, which helps reduce inrush current.
8.3.2 Output Overvoltage Protection
The overvoltage comparator compares the FB pin voltage to a voltage that is 15% higher than the internal
reference VREF. Once the FB pin voltage goes 15% above the internal reference, the internal PMOS control
switch is turned off, which allows the output voltage to decrease toward regulation.
8.3.3 Undervoltage Lockout
Undervoltage lockout (UVLO) prevents the LMR10510 from operating until the input voltage exceeds 2.73 V
(typical). The UVLO threshold has approximately 430 mV of hysteresis, so the device operates until VIN drops
below 2.3 V (typical). Hysteresis prevents the part from turning off during power up if VIN is non-monotonic.
8.3.4 Current Limit
The LMR10510 uses cycle-by-cycle current limiting to protect the output switch. During each switching cycle, a
current limit comparator detects if the output switch current exceeds 1.75A (typical), and turns off the switch until
the next switching cycle begins.
8.3.5 Thermal Shutdown
Thermal shutdown limits total power dissipation by turning off the output switch when the IC junction temperature
exceeds 165°C. After thermal shutdown occurs, the output switch doesn’t turn on until the junction temperature
drops to approximately 150°C.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMR10510 is internally compensated, so it is simple to use and requires few external components. The
regulator has a preset switching frequency of 1.6 MHz or 3 MHz. This high frequency allows the LMR10510 to
operate with small surface mount capacitors and inductors, resulting in a DC/DC converter that requires a
minimum amount of board space
9.2 Typical Application
EN
R3
3.3 PH
(³;´ YHUVLRQ)
U1
6
VIN
4, 5
2
EN
SW
1.0 PH
VINA/VIND
GND
VOUT
L1
3
FB
1
1.8V
R1
20k
C3
22 PF
C2
C1
2.2 PF
R2
10k
D1
2.2 PF
GND
C4
22 PF
Chf
22 nF
(opt.)
GND
Figure 15. Typical Application Schematic
9.2.1 Detailed Design Procedure
9.2.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR10510 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
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Typical Application (continued)
9.2.1.2 Inductor Selection
The duty cycle (D) can be approximated quickly using the ratio of output voltage (VO) to input voltage (VIN):
D=
VOUT
VIN
The catch diode (D1) forward voltage drop and the voltage drop across the internal PMOS must be included to
calculate a more accurate duty cycle. Calculate D by using the following formula:
D=
VOUT + VD
VIN + VD - VSW
VSW can be approximated by:
VSW = IOUT x RDSON
The diode forward drop (VD) can range from 0.3 V to 0.7 V depending on the quality of the diode. The lower the
VD, the higher the operating efficiency of the converter. The inductor value determines the output ripple current.
Lower inductor values decrease the size of the inductor, but increase the output ripple current. An increase in the
inductor value will decrease the output ripple current.
One must ensure that the minimum current limit (1.2 A) is not exceeded, so the peak current in the inductor must
be calculated. The peak current (ILPK) in the inductor is calculated by:
ILPK = IOUT + ΔiL
'i L
I OUT
VIN - VOUT
VOUT
L
L
DTS
TS
t
Figure 16. Inductor Current
VIN - VOUT
L
=
2'iL
DTS
In general,
ΔiL = 0.1 x (IOUT) → 0.2 x (IOUT)
If ΔiL = 20% of 1 A, the peak current in the inductor will be 1.2 A. The minimum specified current limit over all
operating conditions is 1.2 A. One can either reduce ΔiL, or make the engineering judgment that zero margin will
be safe enough. The typical current limit is 1.75 A.
The LMR10510 operates at frequencies allowing the use of ceramic output capacitors without compromising
transient response. Ceramic capacitors allow higher inductor ripple without significantly increasing output ripple.
See the Output Capacitor section for more details on calculating output voltage ripple. Now that the ripple current
is determined, the inductance is calculated by:
L=
DTS
x (VIN - VOUT)
2'iL
where
TS =
•
1
fS
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Typical Application (continued)
When selecting an inductor, make sure that it is capable of supporting the peak output current without saturating.
Inductor saturation will result in a sudden reduction in inductance and prevent the regulator from operating
correctly. Because of the speed of the internal current limit, the peak current of the inductor need only be
specified for the required maximum output current. For example, if the designed maximum output current is 1 A
and the peak current is 1.25 A, then the inductor should be specified with a saturation current limit of > 1.25A.
There is no need to specify the saturation or peak current of the inductor at the 1.75 A typical switch current limit.
The difference in inductor size is a factor of 5. Because of the operating frequency of the LMR10510, ferrite
based inductors are preferred to minimize core losses. This presents little restriction since the variety of ferritebased inductors is huge. Lastly, inductors with lower series resistance (RDCR) will provide better operating
efficiency. For recommended inductors see examples in Other System Examples.
9.2.1.3 Input Capacitor
An input capacitor is necessary to ensure that VIN does not drop excessively during switching transients. The
primary specifications of the input capacitor are capacitance, voltage, RMS current rating, and ESL (Equivalent
Series Inductance). The recommended input capacitance is 22 µF.The input voltage rating is specifically stated
by the capacitor manufacturer. Make sure to check any recommended deratings and also verify if there is any
significant change in capacitance at the operating input voltage and the operating temperature. The input
capacitor maximum RMS input current rating (IRMS-IN) must be greater than:
IRMS_IN D IOUT2 (1-D) +
'i2
3
Neglecting inductor ripple simplifies the above equation to:
IRMS_IN = IOUT x D(1 - D)
It can be shown from the above equation that maximum RMS capacitor current occurs when D = 0.5. Always
calculate the RMS at the point where the duty cycle D is closest to 0.5. The ESL of an input capacitor is usually
determined by the effective cross sectional area of the current path. A large leaded capacitor will have high ESL
and a 0805 ceramic chip capacitor will have very low ESL. At the operating frequencies of the LMR10510,
leaded capacitors may have an ESL so large that the resulting impedance (2πfL) will be higher than that required
to provide stable operation. As a result, surface mount capacitors are strongly recommended.
Sanyo POSCAP, Tantalum or Niobium, Panasonic SP, and multilayer ceramic capacitors (MLCC) are all good
choices for both input and output capacitors and have very low ESL. For MLCCs it is recommended to use X7R
or X5R type capacitors due to their tolerance and temperature characteristics. Consult capacitor manufacturer
datasheets to see how rated capacitance varies over operating conditions.
9.2.1.4 Output Capacitor
The output capacitor is selected based upon the desired output ripple and transient response. The initial current
of a load transient is provided mainly by the output capacitor. The output ripple of the converter is:
'VOUT = 'IL RESR +
1
8 x FSW x COUT
When using MLCCs, the ESR is typically so low that the capacitive ripple may dominate. When this occurs, the
output ripple will be approximately sinusoidal and 90° phase shifted from the switching action. Given the
availability and quality of MLCCs and the expected output voltage of designs using the LMR10510, there is really
no need to review any other capacitor technologies. Another benefit of ceramic capacitors is their ability to
bypass high frequency noise. A certain amount of switching edge noise will couple through parasitic
capacitances in the inductor to the output. A ceramic capacitor will bypass this noise while a tantalum will not.
Since the output capacitor is one of the two external components that control the stability of the regulator control
loop, most applications will require a minimum of 22 µF of output capacitance. Capacitance often, but not always,
can be increased significantly with little detriment to the regulator stability. Like the input capacitor, recommended
multilayer ceramic capacitors are X7R or X5R types.
14
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Typical Application (continued)
9.2.1.5 Catch Diode
The catch diode (D1) conducts during the switch off-time. A Schottky diode is recommended for its fast switching
times and low forward voltage drop. The catch diode should be chosen so that its current rating is greater than:
ID1 = IOUT x (1-D)
The reverse breakdown rating of the diode must be at least the maximum input voltage plus appropriate margin.
To improve efficiency, choose a Schottky diode with a low forward voltage drop.
9.2.1.6 Output Voltage
The output voltage is set using the following equation where R2 is connected between the FB pin and GND, and
R1 is connected between VO and the FB pin. A good value for R2 is 10 kΩ. When designing a unity gain
converter (Vo = 0.6V), R1 must be between 0 Ω and 100 Ω, and R2 must be equal or greater than 10 kΩ.
R1 =
VOUT
VREF
- 1 x R2
VREF = 0.60V
9.2.1.7 Calculating Efficiency, and Junction Temperature
The complete LMR10510 DC/DC converter efficiency can be calculated in the following manner.
K=
POUT
PIN
Or
K=
POUT
POUT + PLOSS
Calculations for determining the most significant power losses are shown below. Other losses totaling less than
2% are not discussed.
Power loss (PLOSS) is the sum of two basic types of losses in the converter: switching and conduction.
Conduction losses usually dominate at higher output loads, whereas switching losses remain relatively fixed and
dominate at lower output loads. The first step in determining the losses is to calculate the duty cycle (D):
D=
VOUT + VD
VIN + VD - VSW
VSW is the voltage drop across the internal PFET when it is on, and is equal to:
VSW = IOUT x RDSON
VD is the forward voltage drop across the Schottky catch diode. It can be obtained from the diode manufactures
Electrical Characteristics section. If the voltage drop across the inductor (VDCR) is accounted for, the equation
becomes:
D=
VOUT + VD + VDCR
VIN + VD + VDCR - VSW
The conduction losses in the free-wheeling Schottky diode are calculated as follows:
PDIODE = VD × IOUT × (1-D)
Often this is the single most significant power loss in the circuit. Take care to choose a Schottky diode that has a
low forward-voltage drop.
Another significant external power loss is the conduction loss in the output inductor. The equation can be
simplified to:
PIND = IOUT2 × RDCR
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Typical Application (continued)
The LMR10510 conduction loss is mainly associated with the internal PFET:
PCOND = (IOUT2 x D) 1 +
'iL
1
x
3
IOUT
2
RDSON
If the inductor ripple current is fairly small, the conduction losses can be simplified to:
PCOND = IOUT2 × RDSON x D
Switching losses are also associated with the internal PFET. They occur during the switch on and off transition
periods, where voltages and currents overlap resulting in power loss. The simplest means to determine this loss
is to empirically measuring the rise and fall times (10% to 90%) of the switch at the switch node.
Switching Power Loss is calculated as follows:
PSWR = 1/2(VIN x IOUT x FSW x TRISE)
PSWF = 1/2(VIN x IOUT x FSW x TFALL)
PSW = PSWR + PSWF
Another loss is the power required for operation of the internal circuitry:
PQ = IQ x VIN
IQ is the quiescent operating current, and is typically around 3.3mA for the 1.6MHz frequency option.
Typical Application power losses are:
Table 1. Power Loss Tabulation
VIN
5V
VOUT
3.3 V
IOUT
1A
VD
0.45 V
FSW
1.6 MHz
IQ
TRISE
POUT
3.3 W
PDIODE
150 mW
3.3 mA
PQ
17 mW
4 ns
PSWR
16 mW
TFALL
4 ns
PSWF
16 mW
RDS(ON)
150 mΩ
PCOND
100 mW
INDDCR
70 mΩ
PIND
70 mW
D
0.667
PLOSS
369 mW
η
88%
PINTERNAL
149 mW
ΣPCOND + PSW + PDIODE + PIND + PQ = PLOSS
ΣPCOND + PSWF + PSWR + PQ = PINTERNAL
PINTERNAL = 149 mW
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9.2.2 Application Curves
VOUT = 1.8 V
IOUT = 500 mA
VIN = 3.3 V
Figure 17. Line Regulation
VIN = 5 V
VOUT = 1.8 V (All Options)
VOUT = 1.8 V (All Options)
Figure 18. Load Regulation
VIN = 5 V
Figure 19. Load Regulation
VOUT = 3.3 V (All Options)
Figure 20. Load Regulation
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9.2.3 Other System Examples
9.2.3.1 LMR10510x Design Example 1
FB
EN
R3
VIN = 5V
C1
LMR10510
100k
GND
L1
VIN
SW
3.3 PH
1.5A
22 PF
10V
D1
1.5A
20V
VO = 1.2V @ 1.0A
R1
15k
R2
15k
C2
22 PF
6.3V
Figure 21. LMR10510X (1.6 MHz): VIN = 5 V, VOUT = 1.2 V at 1 A
9.2.3.2 Lmr10510X Design Example 2
FB
EN
R3
VIN = 5V
LMR10510
100k
GND
L1
VIN
SW
2.2 PH
1.8A
C1
22 PF
10V
D1
1.5A
20V
VO = 3.3V @ 1.0A
R1
45.3k
R2
100k
C2
22 PF
6.3V
Figure 22. LMR10510X (1.6 MHz): VIN = 5 V, VOUT = 3.3 V at 1 A
9.2.3.3 LMR10510Y Design Example 3
FB
EN
R3
VIN = 5V
LMR10510
100k
VIN
GND
L1
SW
1.6 PH
2.0A
C1
22 PF
10V
D1
1.5A
20V
VO = 3.3V @ 1.0A
R1
45.3k
R2
100k
C2
22 PF
6.3V
Figure 23. LMR10510Y (3 MHz): VIN = 5 V, VOUT = 3.3 V at 1 A
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9.2.3.4 LMR10510Y Design Example 4
FB
EN
R3
VIN = 5V
C1
LMR10510
100k
VIN
22 PF
10V
GND
L1
SW
1.6 PH
2.0A
D1
1.5A
20V
VO = 1.2V @ 1.0A
R1
10k
R2
10k
C2
22 PF
6.3V
Figure 24. LMR10510Y (3 MHz): VIN = 5 V, VOUT = 1.2 V at 1 A
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10 Layout
10.1 Layout Guidelines
When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The
most important consideration is the close coupling of the GND connections of the input capacitor and the catch
diode D1. These ground ends should be close to one another and be connected to the GND plane with at least
two through-holes. Place these components as close to the IC as possible. Next in importance is the location of
the GND connection of the output capacitor, which should be near the GND connections of CIN and D1. There
should be a continuous ground plane on the bottom layer of a two-layer board except under the switching node
island. The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise
pickup and inaccurate regulation. Place he feedback resistors as close as possible to the IC, with the GND of R1
placed as close as possible to the GND of the IC. The VOUT trace to R2 should be routed away from the inductor
and any other traces that are switching. High AC currents flow through the VIN, SW and VOUT traces, so they
should be as short and wide as possible. However, making the traces wide increases radiated noise, so the
designer must make this trade-off. Radiated noise can be decreased by choosing a shielded inductor. Place the
remaining componentsas close as possible to the IC. See Application Note AN-1229 for further considerations
and the LMR10510 demo board as an example of a good layout.
10.2 Layout Example
FB
GND
6 EN
1
2
GND
PLANE
SW 3
5 VINA
4 VIND
Figure 25. 6-Lead WSON PCB Dog Bone Layout
10.3 Thermal Definitions
TJ = Chip junction temperature
TA = Ambient temperature
RθJC = Thermal resistance from chip junction to device case
RθJA = Thermal resistance from chip junction to ambient air
Heat in the LMR10510 due to internal power dissipation is removed through conduction and/or convection.
Conduction: Heat transfer occurs through cross sectional areas of material. Depending on the material, the
transfer of heat can be considered to have poor to good thermal conductivity properties (insulator vs. conductor).
Heat Transfer goes as:
Silicon → package → lead frame → PCB
Convection: Heat transfer is by means of airflow. This could be from a fan or natural convection. Natural
convection occurs when air currents rise from the hot device to cooler air.
Thermal impedance is defined as:
RT =
'T
Power
Thermal impedance from the silicon junction to the ambient air is defined as:
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Thermal Definitions (continued)
RTJA =
TJ - TA
Power
The PCB size, weight of copper used to route traces and ground plane, and number of layers within the PCB can
greatly effect RθJA. The type and number of thermal vias can also make a large difference in the thermal
impedance. Thermal vias are necessary in most applications. They conduct heat from the surface of the PCB to
the ground plane. Four to six thermal vias should be placed under the exposed pad to the ground plane if the
WSON package is used.
Thermal impedance also depends on the thermal properties of the application operating conditions (Vin, Vo, Io
etc), and the surrounding circuitry.
Silicon Junction Temperature Determination Method 1:
To accurately measure the silicon temperature for a given application, two methods can be used. The first
method requires the user to know the thermal impedance of the silicon junction to case temperature.
RθJC is approximately 18°C/Watt for the 6-pin WSON package with the exposed pad. Knowing the internal
dissipation from the efficiency calculation given previously, and the case temperature, which can be empirically
measured on the bench we have:
RTJC =
TJ - TC
Power
where TC is the temperature of the exposed pad and can be measured on the bottom side of the PCB.
Therefore:
Tj = (RθJC x PLOSS) + TC
From the previous example:
Tj = (RθJC x PINTERNAL) + TC
Tj = 18°C/W x 0.149W + TC
The second method can give a very accurate silicon junction temperature.
The first step is to determine RθJA of the application. The LMR10510 has over-temperature protection circuitry.
When the silicon temperature reaches 165°C, the device stops switching. The protection circuitry has a
hysteresis of about 15°C. Once the silicon temperature has decreased to approximately 150°C, the device will
start to switch again. Knowing this, the RθJA for any application can be characterized during the early stages of
the design one may calculate the RθJA by placing the PCB circuit into a thermal chamber. Raise the ambient
temperature in the given working application until the circuit enters thermal shutdown. If the SW-pin is monitored,
it will be obvious when the internal PFET stops switching, indicating a junction temperature of 165°C. Knowing
the internal power dissipation from the above methods, the junction temperature, and the ambient temperature
RθJA can be determined.
RTJA =
165° - Ta
PINTERNAL
Once this is determined, the maximum ambient temperature allowed for a desired junction temperature can be
found.
An example of calculating RθJA for an application using the LMR10510 is shown below.
A sample PCB is placed in an oven with no forced airflow. The ambient temperature was raised to 147°C, and at
that temperature, the device went into thermal shutdown.
From the previous example:
PINTERNAL = 149 mW
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Thermal Definitions (continued)
RTJA =
165°C - 147°C
149 mW
= 121°C/W
Since the junction temperature must be kept below 125°C, then the maximum ambient temperature can be
calculated as:
Tj - (RθJA x PLOSS) = TA
125°C - (121°C/W x 149 mW) = 107°C
10.4 WSON Package
Figure 26. Internal WSON Connection
For certain high power applications, the PCB land may be modified to a "dog bone" shape (see Figure 25). By
increasing the size of ground plane, and adding thermal vias, the RθJA for the application can be reduced.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR10510 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMR10510XMF/NOPB
ACTIVE
SOT-23
DBV
5
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SH7B
LMR10510XMFE/NOPB
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SH7B
LMR10510XMFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SH7B
LMR10510YMF/NOPB
ACTIVE
SOT-23
DBV
5
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SH9B
LMR10510YMFE/NOPB
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SH9B
LMR10510YMFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SH9B
LMR10510YSD/NOPB
ACTIVE
WSON
NGG
6
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
L268B
LMR10510YSDE/NOPB
ACTIVE
WSON
NGG
6
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
L268B
LMR10510YSDX/NOPB
ACTIVE
WSON
NGG
6
4500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
L268B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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