LMR14206
SNVS733D – OCTOBER 2011 – REVISED APRIL 2013
LMR14206 SIMPLE SWITCHER® 42Vin, 0.6A Step-Down Voltage Regulator in SOT-23
Check for Samples: LMR14206
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1 Features
4 Description
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The LMR14206 is a PWM DC/DC buck (step-down)
regulator. With a wide input range from 4.5V-42V,
they are suitable for a wide range of applications
such as power conditioning from unregulated
sources. They feature a low RDSON (0.9Ω typical)
internal switch for maximum efficiency (85% typical).
Operating frequency is fixed at 1.25 MHz allowing the
use of small external components while still being
able to have low output voltage ripple. Soft-start can
be implemented using the shutdown pin with an
external RC circuit allowing the user to tailor the softstart time to a specific application.
1
Input Voltage Range of 4.5V to 42V
Output Voltage Range of 0.765V to 34V
Output Vurrent up to 0.6A
1.25 MHz Switching Frequency
Low Shutdown Iq, 16 µA Typical
Short Circuit Protected
Internally Compensated
Soft-Start Function
Thin 6-Pin SOT Package (2.97 x 1.65 x 1mm)
Fully Enabled for WEBENCH® Power Designer
2 Performance Benefits
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Tight Accuracy for Powering Digital ICs
Extremely Easy to Use
Tiny Overall Solution Reduces System Cost
The LMR14206 is optimized for up to 600 mA load
current with a 0.765V nominal feedback voltage.
Additional features include: thermal shutdown, VIN
under-voltage lockout, and gate drive under-voltage
lockout. The LMR14206 is available in a low profile 6pin SOT package.
3 Applications
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Point-of-Load Conversions from 5V, 12V, and 24V
Rails
Space Constrained Applications
Battery Powered Equipment
Industrial Distributed Power Applications
Power Meters
Portable Hand-Held Instruments
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR14206
SNVS733D – OCTOBER 2011 – REVISED APRIL 2013
www.ti.com
4.1 System Performance
Efficiency vs Load Current
VIN = 24V, VOUT = 1.2V and 3.3V
100
100
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs Load Current
VIN = 12V, VOUT = 1.2V and 3.3V
70
60
50
40
30
20
60
50
40
30
20
10
10
1.2Vout
3.3Vout
0
0.0
70
0.1
1.2Vout
3.3Vout
0
0.2
0.3
0.4
0.5
LOAD CURRENT (A)
0.6
0.0
CBOOT
0.1
L1
0.2
0.3
0.4
0.5
LOAD CURRENT (A)
0.6
VOUT
LMR14206
VIN
VIN
CB
SHDN
SW
GND
FB
D1
R1
R2
CIN
COUT
Figure 1.
4.2 Connection Diagram
LMR14206
CB
1
GND
2
6
SW
5
VIN
4
SHDN
PIN 1 ID
FB
3
Figure 2. 6-Pin SOT (Top View)
See DDC Package
2
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Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMR14206
LMR14206
www.ti.com
SNVS733D – OCTOBER 2011 – REVISED APRIL 2013
Connection Diagram (continued)
PIN DESCRIPTIONS
Pin
Name
1
CB
2
GND
3
FB
4
SHDN
Function
SW FET gate bias voltage. Connect CBOOT cap between CB and SW.
Ground connection.
Feedback pin: Set feedback voltage divider ratio with VOUT = VFB (1+(R1/R2)). Resistors should be
in the 100-10K range to avoid input bias errors.
Logic level shutdown input. Pull to GND to disable the device and pull high to enable the device. If
this function is not used tie to VIN or leave open.
5
VIN
Power input voltage pin: 4.5V to 42V normal operating range.
6
SW
Power FET output: Connect to inductor, diode, and CBOOT cap.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMR14206
3
LMR14206
SNVS733D – OCTOBER 2011 – REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
5 Absolute Maximum Ratings (1) (2)
VIN
-0.3V to +45V
SHDN
-0.3V to (VIN+0.3V)
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