LMR36510ADDAR

Order Now Product Folder Technical Documents Support & Community Tools & Software LMR36510 ZHCSKB5A – OCTOBER 2019 – REVISED FEBRUARY 2020 LMR36510 SIMPLE SWITCHER ®4.2V 至 65V、 、1A 同步降压转换器 1 特性 • 1 • • • • 3 说明 专为可靠耐用的应用 设计 – 高达 70V 的输入瞬态保护 – 保护 功能：热关断、输入欠压锁定、逐周期电 流限制和断续短路保护 非常适合可扩展的工业电源 – 与以下器件引脚兼容： – LMR36520（65V、2A） – LMR33610/LMR33620/LMR33630/ LMR33640（36V、1A、2A、3A 或 4A） – 内部补偿有助于减小解决方案尺寸、降低成本和 设计复杂性 – 频率为 400kHz 宽转换范围 – 输入电压范围：4.2V 至 65V – 输出电压范围：1V 至 95% 的 VIN 在整个负载范围内具有低功率耗散 – 在 400kHz（24VIN、5VOUT、1A）下效率为 90% – 在 PFM 模式中提高了轻负载效率 – 低至 26µA 的工作静态电流 具有滤波器和延迟释放功能的电源正常状态输出 2 应用 • • • • • • IP 网络摄像头 模拟安防摄像头 HVAC 阀门和传动器控制 交流驱动器和伺服驱动控制模块 模拟输入模块和混合 I/O 模块 通用宽输入电压电源 LMR36510 稳压器是一款易于使用的同步降压直流/直 流 SIMPLE SWITCHER 转换器。借助集成式高侧和低 侧功率 MOSFET，在 4.2V 至 65V 宽输入电压范围内 的输出电流可高达 1A。高达 70V 的瞬态电压耐受能力 有助于缩小解决方案尺寸和降低成本，以提供过压保护 并满足 IEC 61000-4-5 的浪涌抗扰度要求。 LMR36510 采用峰值电流模式控制机制来提供出色的 效率和输出电压精度。利用精密使能功能，您可以灵活 地直接连接到宽输入电压，或对器件启动和关断进行精 确控制。附带内置滤波和延迟功能的电源正常状态标志 可提供系统状态的真实指示，免去了使用外部监控器的 麻烦。 通过集成和内部补偿，该器件减少了很多外部组件，并 提供专为实现简单 PCB 布局而设计的引脚排列方式。 该器件的功能集旨在简化各种终端设备的实施。 LMR36510 与 LMR36520（65V、2A）、 LMR33610、LMR33620、LMR33630 和 LMR33640 （36V、1A/2A/3A/4A）引脚对引脚兼容，完善了 SIMPLE SWITCHER 转换器的最新系列。这提高了宽 输入电压转换器在各种常用电压和电流额定值范围内的 易用性和可扩展性，无需重新设计电路板布局。因此， 不仅降低了总体成本和设计工作量，而且缩短了上市时 间。 LMR36510 采用 8 引脚 HSOIC 封装。 器件信息(1) 器件型号 封装 LMR36510 封装尺寸（标称值） HSOIC (8) 5.00mm × 4.00mm (1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附 录。 效率与输出电流间的关系 VOUT = 5V， ，400kHz 简化原理图 BOOT 100 VIN VIN CBOOT 95 CIN 90 SW L1 VOUT COUT 85 Efficiency (%) EN PGND 80 75 VCC 70 65 VIN = 8V VIN = 12V VIN = 24V VIN = 36V VIN = 48V 60 55 50 45 0.001 0.002 PG RFBT CVCC 0.005 0.01 0.02 0.05 0.1 Load Current (A) 0.2 0.3 0.5 FB RFBB 1 Effi 1 本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确 性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。 English Data Sheet: SNVSBD7 LMR36510 ZHCSKB5A – OCTOBER 2019 – REVISED FEBRUARY 2020 www.ti.com.cn 目录 1 2 3 4 5 6 7 特性 .......................................................................... 应用 .......................................................................... 说明 .......................................................................... 修订历史记录 ........................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 4 4 4 5 5 6 6 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Switching Characteristics .......................................... System Characteristics ............................................. Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 Overview ................................................................... 9 7.2 Functional Block Diagram ......................................... 9 7.3 Feature Description................................................... 9 7.4 Device Functional Modes........................................ 13 8 Application and Implementation ........................ 16 8.1 Application Information............................................ 16 8.2 Typical Application .................................................. 17 8.3 What to Do and What Not to Do ............................. 26 9 Power Supply Recommendations...................... 27 10 Layout................................................................... 28 10.1 Layout Guidelines ................................................. 28 10.2 Layout Example .................................................... 30 11 器件和文档支持 ..................................................... 31 11.1 11.2 11.3 11.4 11.5 11.6 11.7 器件支持 ............................................................... 文档支持................................................................ 接收文档更新通知 ................................................. 支持资源................................................................ 商标 ....................................................................... 静电放电警告......................................................... Glossary ................................................................ 31 31 31 31 31 31 31 12 机械、封装和可订购信息 ....................................... 31 4 修订历史记录 注：之前版本的页码可能与当前版本有所不同。 Changes from Original (October 2019) to Revision A Page • 将器件状态从“预告信息”更改为“生产数据” ............................................................................................................................. 1 2 Copyright © 2019–2020, Texas Instruments Incorporated LMR36510 www.ti.com.cn ZHCSKB5A – OCTOBER 2019 – REVISED FEBRUARY 2020 5 Pin Configuration and Functions DDA Package 8-Pin HSOIC Top View PGND 1 VIN 2 8 SW 7 BOOT THERMAL PAD EN 3 6 VCC PG 4 5 FB Not to scale Pin Functions PIN I/O DESCRIPTION NAME NO. PGND 1 G Power and analog ground terminal. Connect to bypass capacitor with short, wide traces. Ground reference for internal references and logic. All electrical parameters are measured with respect to this pin. VIN 2 P Input supply to regulator. Connect a high-quality bypass capacitor or capacitors directly to this pin and PGND. EN 3 A Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN; Do not float. PG 4 A Open-drain power-good flag output. Connect to suitable voltage supply through a current limiting resistor. High = power OK, low = power bad. Flag pulls low when EN = Low. Can be left open when not used. FB 5 A Feedback input to regulator. Connect to tap point of feedback voltage divider. Do not float. Do not ground. VCC 6 P Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect to external loads. Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this pin to PGND. BOOT 7 P Bootstrap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor from this pin to the SW pin. SW 8 P Regulator switch node. Connect to a power inductor. PAD THERMAL PAD Therm Major heat dissipation path of the device. A direct thermal connection to a ground plane is required. al The PAD is not meant as an electrical interconnect. Electrical characteristics are not ensured. A = Analog, P = Power, G = Ground Copyright © 2019–2020, Texas Instruments Incorporated 3 LMR36510 ZHCSKB5A – OCTOBER 2019 – REVISED FEBRUARY 2020 www.ti.com.cn 6 Specifications 6.1 Absolute Maximum Ratings Over junction temperature range of -40°C to 150°C (unless otherwise noted) (1) MIN MAX Input voltage VIN to PGND –0.3 70 UNIT V Input voltage EN to PGND –0.3 70.3 V Input voltage FB to PGND –0.3 5.5 V Input voltage PG to PGND –0.3 20 V Output voltage SW to PGND –0.3 70.3 V Output voltage SW to PGND less than 10-ns transients –3.5 70 V Output voltage CBOOT to SW –0.3 5.5 V Output voltage VCC to PGND –0.3 5.5 V Junction Temperature TJ -40 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM) (1) ±2500 Charged-device model (CDM) (2) ±750 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions Over the recommended operating junction temperature range of –40 ℃ to 125 ℃ (unless otherwise noted) (1) MIN MAX 4.2 65 V EN to PGND (2) 0 65 V PG to PGND (2) 0 18 V Output voltage VOUT 1 28 V Output current IOUT 0 1 A VIN to PGND Input voltage (1) (2) 4 UNIT Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical Characteristics. The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V. Copyright © 2019–2020, Texas Instruments Incorporated LMR36510 www.ti.com.cn ZHCSKB5A – OCTOBER 2019 – REVISED FEBRUARY 2020 6.4 Thermal Information LMR36510 THERMAL METRIC (1) DDA (HSOIC) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter 4.3 °C/W ψJB Junction-to-board characterization parameter 13.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 4.3 °C/W (1) 42.9 °C/W 54 °C/W 13.6 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics Limits apply over operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated. Minimum and Maximum limits (1) are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX 36 UNIT SUPPLY VOLTAGE (VIN PIN) IQ-nonSW Operating quiescent current (nonswitching) (2) VEN = 3.3 V (PFM variant only) 26 ISD Shutdown quiescent current; measured at VIN pin VEN = 0 V 5.3 µA µA ENABLE (EN PIN) VEN-VCC-H Enable input high level for VCC output VENABLE rising VEN-VCC-L Enable input low level for VCC output VENABLE falling 0.3 1.14 V VEN-VOUT-H Enable input high level for VOUT VENABLE rising 1.157 VEN-VOUT-HYS Enable input hysteresis for VOUT Hysteresis below VENABLE-H; falling 110 mV ILKG-EN Enable input leakage current VEN = 3.3V 2.7 nA V 1.231 1.3 V INTERNAL LDO (VCC PIN) VCC VCC-UVLORising VCC-UVLOFalling Internal VCC voltage 6 V ≤ VIN ≤ 65 V Internal VCC undervoltage lockout Internal VCC undervoltage lockout 4.75 5 5.25 V VCC rising 3.6 3.8 4.0 V VCC falling 3.1 3.3 3.5 V 1 1.015 VOLTAGE REFERENCE (FB PIN) VFB Feedback voltage ILKG-FB Feedback leakage current 0.985 FB = 1 V 2.1 V nA CURRENT LIMITS AND HICCUP High-side current limit (3) ISC ILS-LIMIT Low-side current limit IL-ZC Zero cross detector threshold IPEAK-MIN Minimum inductor peak current (3) (1) (2) (3) 1.6 (3) 1 PFM variants only 2 2.4 A 1.3 1.6 A 0.04 A 0.28 A MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). This is the current used by the device open loop. It does not represent the total input current of the system when in regulation. The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application. Copyright © 2019–2020, Texas Instruments Incorporated 5 LMR36510 ZHCSKB5A – OCTOBER 2019 – REVISED FEBRUARY 2020 www.ti.com.cn Electrical Characteristics (continued) Limits apply over operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated. Minimum and Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER GOOD (PGOOD PIN) VPG-HIGH-UP Power-Good upper threshold - rising % of FB voltage 105% 107% 110% VPG-LOW-DN Power-Good lower threshold - falling % of FB voltage 90% 93% 95% VPG-HYS Power-Good hysteresis (rising & falling) % of FB voltage VPG-VALID Minimum input voltage for proper Power-Good function RPG Power-Good on-resistance VEN = 2.5 V RPG Power-Good on-resistance VEN = 0 V RDS-ON-HS High-side MOSFET ON-resistance RDS-ON-LS Low-side MOSFET ON-resistance 1.5% 2 V 80 165 Ω 35 90 Ω IOUT = 0.5 A 245 465 mΩ IOUT = 0.5 A 165 310 mΩ MOSFETS 6.6 Timing Requirements Limits apply over operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated. Minimum and Maximum limits (1) are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V. MIN NOM MAX UNIT tON-MIN Minimum switch on-time 92 tOFF-MIN Minimum switch off-time 80 102 ns tON-MAX Maximum switch on-time 7 12 µs tSS Internal soft-start time 4.5 6 ms (1) 3 ns MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). 6.7 Switching Characteristics TJ = -40°C to 125°C, VIN = 24 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 340 400 460 kHz OSCILLATOR FOSC 6 Internal oscillator frequency 400-kHz variant Copyright © 2019–2020, Texas Instruments Incorporated LMR36510 www.ti.com.cn ZHCSKB5A – OCTOBER 2019 – REVISED FEBRUARY 2020 6.8 System Characteristics The following specifications apply to a typical application circuit with nominal component values. Specifications in the typical (TYP) column apply to TJ = 25℃ only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case of typical components over the temperature range of TJ = –40℃ to 125℃. These specifications are not ensured by production testing. PARAMETER TEST CONDITIONS MIN TYP MAX Operating input voltage range VOUT Adjustable output voltage regulation (1) PFM operation ISUPPLY Input supply current when in regulation VIN = 24 V, VOUT = 3.3 V, IOUT = 0 A, RFBT = 1 MΩ, PFM variant DMAX Maximum switch duty cycle (2) VHC FB pin voltage required to trip short-circuit hiccup mode tD Switch voltage dead time 2 ns TSD Thermal shutdown temperature Shutdown temperature 170 °C TSD Thermal shutdown temperature Recovery temperature 158 °C (1) (2) 4.2 65 –1.5% 2.5% UNIT VIN 26 V µA 98% 0.4 V Deviation in VOUT from nominal output voltage value at VIN = 24 V, IOUT = 0 A to full load In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: FMIN = 1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN). 版权 © 2019–2020, Texas Instruments Incorporated 7 LMR36510 ZHCSKB5A – OCTOBER 2019 – REVISED FEBRUARY 2020 www.ti.com.cn 6.9 Typical Characteristics Unless otherwise specified the following conditions apply: TA = 25°C and VIN = 24 V. 12 500 475 Peak Inductor Current (mA) Input Current (PA) 10 8 6 4 25qC 125qC -40qC 425 400 375 350 25qC 125qC -40qC 325 2 300 5 10 15 20 25 30 35 40 45 Input Voltage (V) 50 55 EN = 0 V 图 1. Shutdown Supply Current 8 450 60 65 5 10 Shut IOUT = 0 A 15 20 25 30 35 40 45 Input Voltage (V) VOUT = 3.3 V See 图 34 50 55 60 65 Imin ƒSW = 400 kHz 图 2. IPEAK-MIN 版权 © 2019–2020, Texas Instruments Incorporated LMR36510 www.ti.com.cn ZHCSKB5A – OCTOBER 2019 – REVISED FEBRUARY 2020 7 Detailed Description 7.1 Overview The LMR36510 is a synchronous peak-current mode buck regulator designed for a wide variety of industrial applications. The regulator automatically switches modes between PFM and PWM, depending on load. At heavy loads, the device operates in PWM at a constant switching frequency. At light loads, the mode changes to PFM with diode emulation, allowing DCM. This reduces the input supply current and keeps efficiency high. The device features internal loop compensation, which reduces design time and requires fewer external components than externally compensated regulators. 7.2 Functional Block Diagram VCC INT. REG. BIAS OSCILLATOR EN VIN ENABLE LOGIC BOOT HS CURRENT SENSE 1.0 V Reference ERROR AMPLIFIER FB + ± + ± PWM COMP CONTROL LOGIC PFM MODE CONTROL PG DRIVER SW LS CURRENT SENSE POWER GOOD CONTROL PGND 7.3 Feature Description 7.3.1 Power-Good Flag Output The power-good flag function (PG output pin) of the LMR36510 can be used to reset a system microprocessor whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation for short excursions of the output voltage, such as during line and load transients. Output voltage excursions lasting less than tPG do not trip the power-good flag. Power-good operation can best be understood by referencing 图 3 and 图 4. Note that during initial power-up, a delay of about 4 ms (typical) is inserted from the time that EN is asserted to the time that the power-good flag goes high. This delay only occurs during start-up and is not encountered during normal operation of the power-good function. The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic supply. It can also be pulled up to either VCC or VOUT through an appropriate resistor, as desired. If this function is not needed, the PG pin must be grounded. When EN is pulled low, the flag output is also forced low. With EN low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into this pin to ≤ 4 mA. 版权 © 2019–2020, Texas Instruments Incorporated 9 LMR36510 ZHCSKB5A – OCTOBER 2019 – REVISED FEBRUARY 2020 www.ti.com.cn Feature Description (接 接下页) Glitches do not cause false operation nor reset timer VOUT VPG-LOW-UP (95%) VPG-LOW-DN (93%)