LMS3655MMRNLR

Order Now Product Folder Support & Community Tools & Software Technical Documents LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 LMS3655 5.5-A, 36-V Synchronous, 400-kHz DC-DC Step-Down Converter 1 Features 3 Description • • The LMS3655 synchronous buck regulators are optimized for high performance applications, providing an adjustable output of 1 V to 20 V. Seamless transition between PWM and PFM modes, along with a low quiescent current, ensures high efficiency and superior transient responses at all loads. 1 • • • • • • • • • • • • • 96% Peak Efficiency While Converting 12 V to 5 V Low EMI and Switch Noise – Minimized Switch Node Ringing – Pseudo-Random Spread Spectrum 400-kHz (±10%) Fixed Switching Frequency –40°C to +150°C Junction Temperature Range External Frequency Synchronization RESET Output With Internal Filter and 3-ms Release Timer Automatic Light Load Mode for Improved Efficiency Pin-Selectable Forced PWM Mode Built-In Compensation, Soft Start, Current Limit, Thermal Shutdown, and UVLO 0.35-V Dropout With 3.5-A Load at 25°C (Typical) 32-µA IQ_VIN: Quiescent Current at 3.3 VOUT and No Load (Typical) 5.5-A Continuous Load Current Adjustable Output Voltage (1 V to 20 V) ±1.5% Reference Voltage Tolerance 4-mm × 5-mm, 0.5-mm Pitch SON Package An open-drain reset output, with built-in filtering and delay, provides a true indication of system status. This feature negates the requirement for an additional supervisory component, saving cost and board space. Device Information(1) DEVICE NAME LMS3655 PACKAGE VQFN-HR (22) BODY SIZE 4.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • Advanced high-speed circuitry allows the LMS3655 to regulate an input of 24 V to an output of 3.3 V at a fixed frequency of 400 kHz while also enabling a continuous load current of 5.5 A. An innovative frequency foldback architecture allows this device to regulate a 3.3-V output from an input voltage of only 3.5 V. The input voltage can range up to 36 V, with transient tolerance up to 42 V, easing input surge protection design. Noise-Sensitive Medical Applications Telecom High Performance Industrial Typical Application Circuit LMS3655 Efficiency: VOUT = 5 V 100% VIN 3.5 V to 36 V 98% 10 µF PVIN 1 PVIN 2 PGND1 PGND2 10 µF 96% 10 µF RESET VCC SYNC 4.7 µF AGND LMS3655 94% Efficiency AVIN BIAS 0.1 µF NC FB EN CBOOT 90% 88% 86% CFF RFBB FPWM 92% RFBT 84% 470 nF SW L1=10 µH VOUT 3 X 47 µF Copyright © 2017, Texas Instruments Incorporated VIN = 12 VIN = 24 82% 80% 0.001 0.01 0.1 Output Current (A) 1 10 LMS3 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 8 1 1 1 2 3 4 5 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 6 Thermal Information (for Device Mounted on PCB).. 6 Electrical Characteristics........................................... 6 System Characteristics ............................................. 8 Timing Requirements ................................................ 9 Typical Characteristics ............................................ 10 Detailed Description ............................................ 12 8.1 Overview ................................................................. 12 8.2 Functional Block Diagram ....................................... 13 8.3 Feature Description................................................. 14 8.4 Device Functional Modes........................................ 19 9 Application and Implementation ........................ 23 9.1 Application Information............................................ 23 9.2 Typical Applications ................................................ 23 9.3 Do's and Don't's ...................................................... 40 10 Power Supply Recommendations ..................... 40 11 Layout................................................................... 40 11.1 Layout Guidelines ................................................. 40 11.2 Layout Example .................................................... 42 12 Device and Documentation Support ................. 43 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Device Support...................................................... Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 43 43 43 43 43 43 43 13 Mechanical, Packaging, and Orderable Information ........................................................... 44 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (October 2017) to Revision B Page • Changed maximum adjustable output voltage from: 15 V to: 20 V ....................................................................................... 1 • Changed maximum extended output adjustment from: 15 V to: 20 V .................................................................................. 5 • Added new extended output adjustment tablenote to the Recommended Operating Conditions.......................................... 5 Changes from Original (July 2017) to Revision A Page • Changed symbol from: IB to: IB_NSW ....................................................................................................................................... 6 • Added IB spec to System Characteristics ............................................................................................................................... 8 • Added System Characteristics crossreference links for the IB spec..................................................................................... 18 2 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 5 Device Comparison Table Table 1. LMS3655 Devices (5.5-A Output) PART NUMBER OUTPUT VOLTAGE SPREAD SPECTRUM PACKAGE QTY LMS3655AMRNLR Adjustable No 3000 LMS3655AMRNLT Adjustable No 250 LMS3655MMRNLR Adjustable Yes 3000 LMS3655MMRNLT Adjustable Yes 250 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 3 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com 6 Pin Configuration and Functions RNL Package 22-Pin VQFN Top View Pin Functions PIN NO. NAME TYPE (1) DESCRIPTION 1 VCC A Internal 3.1-V LDO output. Used as supply to internal control circuits. Connect a high-quality 4.7-µF capacitor from this pin to AGND. 2 CBOOT P Bootstrap capacitor connection for gate drivers. Connect a high quality 470-nF capacitor from this pin to the SW pin. 3 SYNC I Synchronization input to regulator. Used to synchronize the device switching frequency to a system clock. Triggers on rising edge of external clock; frequency must be in the range of 250 kHz and 500 kHz. 4 PVIN1 P Input supply to regulator. Connect input bypass capacitors directly to this pin and PGND pins. Connect PVIN1 and PVIN2 pins directly together at PCB. PGND1 G Power ground to internal low-side MOSFET. These pins must be tied together on the PCB. Connect PGND1 and PGND2 directly together at PCB. Connect to AGND and system ground. SW P Regulator switch node. Connect to power inductor. PGND2 G Power ground to internal low-side MOSFET. These pins must be tied together. Connect PGND1 and PGND2 directly together at PCB. Connect to AGND and system ground. PVIN2 P Input supply to regulator. Connect input bypass capacitors directly to this pin and PGND pins. Connect PVIN1 and PVIN2 pins directly together at PCB. 15 AVIN A Analog VIN. Connect to PVIN1 and PVIN2 on PCB. 16 FPWM I Mode control input of regulator. High = FPWM, low = Automatic light load mode. Do not float. 17 NC — 18 EN I Enable input to regulator. High = on, Low = off. Can be connected to VIN. Do not float. 19 RESET O Open-drain reset output flag. Connect to suitable voltage supply through a current limiting resistor. High = regulator OK, Low = regulator fault. Goes low when EN = low. 20 AGND G Analog ground for regulator and system. All electrical parameters are measured with respect to this pin. Connect to PGND on PCB. 21 FB A Feedback input to regulator. Connect to feedback voltage divider. 22 BIAS P Input to auxiliary bias regulator. Connect to output voltage node. 5 6 7 8 9 10 11 12 13 14 (1) 4 No internal connection. A = Analog, O = Output, I = Input, G = Ground, P = Power Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 7 Specifications 7.1 Absolute Maximum Ratings Over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted). (1) PARAMETER MIN MAX UNIT VIN (AVIN, PVIN1, and PVIN2) to AGND, PGND (2) –0.3 40 V SW to AGND, PGND (3) –0.3 VIN + 0.3 V CBOOT to SW –0.3 3.6 V EN to AGND, PGND (2) –0.3 40 V BIAS to AGND, PGND –0.3 16 V FB to AGND, PGND –0.3 16 V RESET to AGND, PGND –0.3 8 V RESET sink current (4) 10 mA SYNC to AGND, PGND (2) –0.3 40 V FPWM to AGND, PGND (2) –0.3 40 V VCC to AGND, PGND –0.3 3.6 V Junction temperature –40 150 °C Storage temperature, Tstg –40 150 °C (1) (2) (3) (4) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. A maximum of 42 V can be sustained at this pin for a duration of ≤ 500 ms at a duty cycle of ≤ 0.01%. A voltage of 2 V below PGND and 2 V above VIN can appear on this pin for ≤ 200 ns with a duty cycle of ≤ 0.01%. Do not exceed the voltage rating on this pin. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions Over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted). MIN Input voltage after start-up (1) 3.9 Output adjustment for LMS3655 (2) Extended output adjustment for LMS3655 (3) (4) Operating ambient temperature (1) (2) (3) (4) (5) MAX UNIT 36 V 3.3 6 V 1 20 V 5.5 A 125 °C Load current for LMS3655 (5) NOM –40 An extended input voltage range to 3.5 V is possible; see System Characteristics table. See Input UVLO for start-up conditions. The output voltage must not be allowed to fall below zero volts during normal operation. Operation below 3.3 V and above 6 V may require changes to the typical application schematic, operation may not be possible over the full input voltage range, and some system specifications will not be achieved for this extended output voltage range. Consult the factory for further information. Operation above 15 V requires the BIAS pin grounded or powered by an external source. A maximum of 16 V can be sustained on the BIAS pin. High junction temperatures degrade operating lifetime. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 5 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com 7.4 Thermal Information LMS3655 THERMAL METRIC (1) RNL (VQFN) UNIT 22 PINS RθJA Junction-to-ambient thermal resistance 38.5 °C/W RθJC Junction-to-case (top) thermal resistance 16.3 °C/W RθJB Junction-to-board thermal resistance 16.4 °C/W ψJT Junction-to-top characterization parameter 2.0 °C/W ψJB Junction-to-board characterization parameter 16.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 4.6 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.5 Thermal Information (for Device Mounted on PCB) LMS3655 THERMAL METRIC (1) RNL (VQFN) UNIT 22 PINS RθJA Junction-to-ambient thermal resistance 29.4 °C/W RθJC Junction-to-case (top) thermal resistance 14.2 °C/W RθJB Junction-to-board thermal resistance 5.4 °C/W ψJT Junction-to-top characterization parameter 1.2 °C/W ψJB Junction-to-board characterization parameter 5.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.4 °C/W (1) Mounted on a thermally optimized FR4 four layer EVM with a size of 4000 mill × 3000 mill. 7.6 Electrical Characteristics Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5 V. PARAMETER VFB Initial reference voltage for 5-V and 3.3-V options IQ Operating quiescent current; measured at VIN pin when enabled and not switching (1) IB_NSW Bias current into BIAS pin, enabled, not switching Shutdown quiescent current; measured at VIN pin ISD VIN-OPERATE VRESET (1) 6 Minimum input voltage to operate TEST CONDITIONS VIN = 3.8 V to 36 V, TJ = 25°C VIN = 3.8 V to 36 V MIN TYP MAX –1% 1% –1.5% 1.5% VIN = 13.5 V, VBIAS = 5 V 7.5 16 VIN = 13.5 V, VBIAS = 5 V, FPWM = 0V 53 62 VIN = 13.5 V, VBIAS = 3.3 V, FPWM =0V 53 62 2 3 Rising 3.2 3.55 3.90 Falling 2.95 3.25 3.55 Hysteresis 0.28 0.3 0.4 105% 107% 110% 92% 94% 96.5% Rising, % of VOUT RESET lower threshold voltage Falling, % VOUT Magnitude of RESET lower threshold from steady state output voltage Steady-state output voltage and RESET falling threshold read at the same TJ and VIN µA µA EN ≤ 0.4 V RESET upper threshold voltage UNIT µA V 96% This is the current used by the device while not switching, open loop on the ATE. It does not represent the total input current from the regulator system. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 Electrical Characteristics (continued) Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5 V. PARAMETER VRESET_HYST RESET hysteresis as a percent of output voltage setpoint VRESET_VALID Minimum input voltage for proper RESET function Low level RESET function output voltage VOL FSW Switching frequency FSYNC Sync frequency range DSYNC Sync input duty cycle range VFPWM FPWM input threshold voltage TEST CONDITIONS MIN TYP MAX UNIT ±1% 50-µA pullup to RESET pin, EN = 0 V, TJ= 25°C 1.5 50-µA pullup to RESET pin, VIN = 1.5 V, EN = 0 V 0.4 0.5-mA pullup to RESET pin, VIN = 13.5 V, EN = 0 V 0.4 1-mA pullup to RESET pin, VIN = 13.5 V, EN = 3.3 V 0.4 VIN = 13.5 V, center frequency with spread spectrum, PWM operation 360 400 440 VIN = 13.5 V, without spread spectrum, PWM operation 360 400 440 250 400 V kHz High state input < 5.5 V and > 2.3 V 25% FPWM input high (MODE = FPWM) 1.5 500 kHz 75% FPWM input low (MODE = AUTO with diode emulation) FPWM input hysteresis V 0.4 0.15 V 1 FSSS Frequency span of spread spectrum operation FPSS Spread-spectrum pattern frequency (2) IFPWM FPWM leakage current ISYNC SYNC leakage current IL-HS High-side switch current limit LMS3655 6.7 8.5 9.5 A IL-LS Low-side switch current limit LMS3655 6 7 7.7 A IL-ZC Zero-cross current limit FPWM = low IL-NEG Negative current limit FPWM = high RDSON Power switch on-resistance VEN Enable input threshold voltage rising VEN_HYST Enable threshold hysteresis VEN_WAKE Enable wake-up threshold IEN EN pin input current VCC Internal VCC voltage VCC_UVLO Internal VCC input undervoltage lockout (2) ±3% 1.2 VIN = 13.5 V, VFPWM = 3.3 V 1 VIN = VFPWM = 13.5 V 1 VIN = 13.5 V, VSYNC = 3.3 V 1 VIN = VSYNC = 13.5 V 1 Hz µA µA –0.02 A –1.5 High-side MOSFET RDSON, VIN = 13 V, IL = 1 A 60 130 Low-side MOSFET RDSON, VIN = 13 V, IL = 1 A 40 80 Enable rising mΩ 1.7 2 V 0.45 0.55 V 3 µA 0.4 VIN = VEN = 13.5 V V 2 VIN = 13.5 V, VBIAS = 0 V 3.05 VIN = 13.5 V, VBIAS = 3.3 V 3.15 V VIN rising 2.7 V Hysteresis below VCC-UVLO 185 mV Ensured by Design, Not tested at production. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 7 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com Electrical Characteristics (continued) Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5 V. PARAMETER IFB Input current from FB to AGND VREF Reference voltage RRESET RDSON of RESEToutput TEST CONDITIONS MIN MAX 20 TJ = 25°C TJ = –40°C to 125°C UNIT nA 0.993 1 1.007 0.99 1 1.01 50 120 Ω 0.4 V Pull FB pin low. Sink 1-mA at RESET pin VIH VSYNC TYP FB = 1 V V 1.5 VIL VHYST TSD Thermal shutdown thresholds (2) DMAX Maximum switch duty cycle Rising 0.15 1 160 185 Hysteresis 15 Fsw = 400 kHz °C 96% While in dropout (2) 98% 7.7 System Characteristics The following specifications are ensured by design provided that the component values in the typical application circuit are used. These parameters are not ensured by production testing. Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5 V. PARAMETER VIN-MIN VOUT FSW IQ_VIN VOUT = 3.3 V +2% or –3% regulation 3.8 Output voltage VIN = VOUT + 1 V to 36 V, IOUT = 3.5 A Switching frequency VIN = 24 V, FPWM = 24V, VOUT = 3.3 V, IOUT = 200 mA Minimum input to output voltage differential to maintain FSW ≥ 330 kHz without inductor DCR drop Efficiency 8 Minimum input voltage for full functionality at maximum rated load 5.5 A after start-up. Minimum input to output voltage differential to maintain regulation accuracy without inductor DCR drop VDROP2 TYP 3.5 Bias current in AUTO mode at no load VDROP1 MIN VOUT = 3.3 V +2% or –3% regulation Input current to VIN pin IB TEST CONDITIONS Minimum input voltage for full functionality at 3.5-A load, after start-up. Typical efficiency MAX UNIT V –2.25% 2.25% 400 VIN = 13.5 V, VOUT = 3.3 V, IOUT = 0 A , FPWM = 0, RFBT = 49.9 kΩ, RFBB = 21.7 kΩ 32 VIN = 13.5 V, VOUT = 5.0 V, IOUT = 0 A, FPWM = 0, RFBT = 49.9 kΩ, RFBB = 12.4 kΩ 57 VIN = 13.5 V, IOUT = 0 A, FPWM = 0 kHz µA 32 42 µA VOUT = 3.3 V or 5 V, IOUT= 3.5 A, +2% or –3% output accuracy 0.35 0.6 V VOUT = 3.3 V or 5 V, IOUT= 5.5 A, +2% or –3% output accuracy 0.65 0.85 V VOUT = 3.3 V or 5 V, IOUT = 3.5 A, FSW = 330 kHz, 2% regulation accuracy 0.5 0.7 V VOUT = 3.3 V or 5 V, IOUT = 5.5 A, FSW = 330 kHz, 2% regulation accuracy 0.7 1.2 V VIN = 13.5 V, VOUT = 5 V, IOUT = 3.5 A 94% VIN = 13.5 V, VOUT = 3.3 V, IOUT = 3.5 A 92% VIN = 13.5 V, VOUT = 5 V, IOUT = 100 mA 92% Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 7.8 Timing Requirements Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted. Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 13.5 V. NOM MAX tON Minimum switch on-time, VIN = 18 V, IL = 1 A MIN 60 84 tOFF Minimum switch off-time, VIN = 3.8 V, IL = 1 A 65 80 ns tRESET-act Delay time to RESET high signal 3 4 ms tRESET-filter Glitch filter time for RESET function (1) tSS Soft-start time from first switching pulse to VREF at 90% 5 ms tEN Turnon delay, CVCC = 4.7 µF (2) tW Short-circuit wait time (hiccup time) (3) tFPWM (1) (2) (3) 2 UNIT 24 2.5 4 ns µs 0.8 ms 6 ms Change transition time from AUTO to FPWM MODE, 10-mA load, VIN = 13.5 V 250 Change transition time from FPWM to AUTO MODE, 10-mA load, VIN = 13.5 V 450 µs See Detailed Description. This is the time from the rising edge of EN to the time that the soft-start ramp begins. Tw is the wait time between current limit trip and restart. Tw is proportional to the soft-start time. However, provision must be made to make Tw longer to ensure survivability during an output short circuit. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 9 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com 7.9 Typical Characteristics Unless otherwise specified the following conditions apply: VIN = 12 V, TA = 25ºC. Specified temperatures are ambient. 104% 450000 440000 Switching Frequency (Hz) Reference Voltage Drift 103% 102% 101% 100% 430000 420000 410000 400000 390000 380000 370000 360000 99% -50 -25 0 25 50 75 100 Temperature (qC) 125 150 175 350000 -40 10 LMS3 VIN = 12 V 60 Temperature (qC) 110 160 LMS3 VIN = 12 V Figure 1. Reference Voltage Drift Figure 2. Switching Frequency vs Temperature 10 8 7 8 Current (A) Current (A) 6 6 4 5 4 3 2 2 1 LMS3655 0 -50 0 50 100 Temperature (qC) 150 LMS3655 0 -50 200 0 VIN = 12 V Figure 3. High-Side/Peak Current Limit for LMS3655 200 LMS3 Figure 4. Low-Side/Valley Current Limit for LMS3655 25 3.8 VIN 5.5 VIN 13.5 VIN 18 VIN 20 Current (PA) 0.2 Current (A) 150 VIN = 12V 0.25 0.15 0.1 0.05 15 10 5 0 0 5 10 15 20 25 Temperature (qC) 30 35 40 0 -50 0 LMS3 VIN = 12 V 50 100 Temperature (qC) 150 200 LMS3 VIN = 12 V Figure 5. Short Circuit Average Input Current for LMS3655 10 50 100 Temperature (qC) LMS3 Submit Documentation Feedback Figure 6. Shutdown Current Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 Typical Characteristics (continued) Unless otherwise specified the following conditions apply: VIN = 12 V, TA = 25ºC. Specified temperatures are ambient. 5.4 108% VRESET_UPPER VRESET_UPPER 5.3 VRESET_UPPER_FALLING % of Vout at no load 5.2 106% Voltage (V) 5.1 VOUT 5 4.9 4.8 4.7 VRESET_LOWER_RISING 102% 100% 98% VRESET_LOWER 96% 4.6 4.5 -40 104% -20 0 20 40 60 80 100 Termperature (qC) 120 140 160 94% -40 D026 Figure 7. RESET Threshold 5-V Output VRESET_LOWER -20 0 20 40 60 80 100 Temperature (qC) 120 140 160 D027 Figure 8. RESET Threshold as Percentage of Output Voltage Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 11 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com 8 Detailed Description 8.1 Overview The LMS3655 devices are wide-input voltage range, low quiescent current, high-performance regulators with internal compensation. This device is designed to minimize end-product cost and size while operating in demanding high-performance industrial environments. Normal operating frequency is 400 kHz allowing the use of small passive components. This device has a low unloaded current consumption, eliminating the need for an external backup LDO. The LMS3655 low shutdown current and high maximum operating voltage also allow for the elimination of an external load switch. To further reduce system cost, an advanced reset output is provided, which can often eliminate the use of an external reset or supervisor device. The LMS3655 family is designed with a flip-chip or HotRod™ technology, greatly reducing the parasitic inductance of the pins. In addition, the layout of the device allows for partial cancellation of the current generated magnetic field which reduces the radiated noise generated by the switching action. As a result the switch-node waveform exhibits less overshoot and ringing. Figure 9. Switch Node Waveform (VIN = 13.5 V, IOUT = 5.5 A) The LMS3655 is available in a VQFN package with wettable flanks which allows easy inspection of the soldering without the requirement of x-ray checks. 12 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 8.2 Functional Block Diagram SYNC VCC BIAS VIN * = not used in -ADJ Oscillator Enable Logic EN FB HS Current Sense ¯ 1.0-V Reference * + - CBOOT Int. Reg. Bias Error Amplifier PWM Comp. + - Control Logic Driver SW * RESET Reset Control Mode Logic LS Current Sense FPWM AGND PGND Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 13 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com Functional Block Diagram (continued) 8.2.1 Control Scheme The LMS3655 control scheme allows this device to operate under a wide range of conditions with a low number of external components. Peak current mode control allows a wide range of input voltages and output capacitance values while maintaining a constant switching frequency. Stable operation is maintained while output capacitance is changed during operation as well. This allows use in systems that require high performance during load transients and which have load switches that remove loads as the operating state changes. Short minimum on and off times ensure constant frequency regulation over a wide range of conversion ratios. This architecture uses frequency spreading to achieve low dropout voltage maintaining output regulation as the input voltage falls close to output voltage. The frequency spreading is smooth and continuous, and activated as the off time approaches its minimum. Under these conditions, the LMS3655 operates like a constant off-time converter, allowing the maximum duty cycle to reach 98% and output voltage regulation with 650-mV dropout. As load current is reduced, the LMS3655 transitions to light load mode. In this mode, diode emulation is used to reduce RMS inductor current and switching frequency. Average output voltage increases slightly while lightly loaded as well. 8.3 Feature Description 8.3.1 RESET Flag Output While the LMS3655 reset function resembles a standard Power-Good function, its functionality is designed to replace a discrete reset device, reducing additional component cost. There are three major differences between the reset function and the normal power good function seen in most regulators. • A delay has been added between the point at which the output voltage is within specified limits and the flag asserts Power Good. A glitch filter prevents false flag operation for short excursions in the output voltage, such as during line and load transients. See Figure 11 and Figure 12 for more detail. • RESET output signals a fault (pulls its output to ground) while the part is disabled. • RESET continues to operate with input voltage as low as 1.5 V. Below this input voltage, RESET output may be high impedance. Because the RESET comparator and the regulation loop share the same reference, the thresholds track with the output voltage. When EN is pulled low, the RESET flag output is forced low. When the device is disabled, RESET remains valid as long as the input voltage is ≥ 1.5 V. RESET operation can best be understood by reference to Figure 10 and Figure 11. Output voltage excursions lasting less than TRESET-filter do not trip RESET. Once the output voltage is within the prescribed limits, a delay of TRESET-act is imposed before RESET goes high. This enables tighter tolerance than is possible with an external supervisor device while also expanding the system allowance for transient response without the need for extremely accurate internal circuitry. This output consists of an open-drain NMOS; requiring an external pullup resistor to a suitable logic supply. It can also be pulled up to either VCC or VOUT, through an appropriate resistor, as desired. The pin can be left floating or grounded if the RESET function is not used in the application. The maximum current into this pin must be limited to 10 mA, and the maximum voltage must be less than 8 V. 14 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 Feature Description (continued) Figure 10. Static RESET Operation Figure 11. RESET Timing Behavior Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 15 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com Feature Description (continued) The threshold voltage for the RESET function takes advantage of the availability of the LMS3655 internal feedback threshold to the RESET circuit. This allows a maximum threshold of 96.5% of selected output voltage to be specified at the same time as 96% of actual set point. 8.3.2 Enable and Start-Up Start-up and shutdown of the LMS3655 are controlled by the EN input. Applying a voltage of ≥ 2 V activates the device, while a voltage of ≤ 1.45 V is required for shutdown. The EN input may also be connected directly to the input voltage supply. This input must not be left floating. The LMS3655 uses a reference-based soft start that prevents output voltage overshoots and large inrush currents as the regulator is starting up. A typical start-up waveform is shown in Figure 12 along with timing definitions. This waveform indicates the sequence and timing between the enable input, output voltage, and RESET. From the figure, the user can define several different start-up times depending on what is relevant to the application. Table 2 lists the timing definitions and typical values. tRESET-UP tPOWER-UP tEN tSS tRESET-ACT 2 ms/div Figure 12. Typical Start-Up Waveform Table 2. Typical Start-Up Times PARAMETER DEFINITION tRESET-READY Total start-up sequence time Time from EN to RESET released tPOWER-UP Start-up time Time from EN to 90% of VOUT tSS Soft-start time tEN tRESET-ACT VALUE UNIT 7.5 ms 4 ms Rise time of VOUT from 10% to 90% 3.2 ms Delay time Time from EN to start of VOUT rising 1 ms RESET time Time from output voltage within 94% and RESET released 3 ms 8.3.3 Soft-Start Function Soft-start time is fixed internally at about 4 ms. Soft start is achieved by ramping the internal reference. The LMS3655 operates correctly even if there is a voltage present on the output before activation of the LMS3655 (prebiased start-up). The device operates in AUTO mode during soft start, and the state of the FPWM pin is ignored during that period. 8.3.4 Current Limit The LMS3655 incorporates a valley current limit for normal overloads and for short-circuit protection. A precision low-side current limit prevents excessive average output current from the buck converter of the LMS3655. A high-side peak-current limit is employed for protection of the top N MOSFET and inductors. The two current limits enable use of smaller inductors than a system with a single current limit. This scheme allows use of inductors with saturation current rated less than twice the operating current of the LMS3655. 16 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 During overloads the low-side current limit, IL-LS (see Electrical Characteristics), determines the maximum load current that the LMS3655 can supply. When the low-side switch turns on, the inductor current begins to ramp down. If the current does not fall below IL-LS before the next turnon cycle, then that cycle is skipped, and the lowside FET is left on until the current falls below IL-LS. This is different than the more typical peak current limit, and results in Equation 1 for the maximum load current. IOUT max ILS VIN VOUT VOUT ˜ 2 ˜ FS ˜ L VIN (1) If the converter continues triggering valley current limit for more than about 64 clock cycles, the device turns off both high and low side switches for approximately 6 ms (see TW in Timing Requirements). If the overload is still present after the hiccup time, another 64 cycles is counted, and the process is repeated. If the current limit is not tripped for two consecutive clock cycles, the counter is reset. The hiccup time allows the inductor current to fall to zero, resetting the inductor volt-second balance. Of course the output current is greatly reduced in this condition (see Typical Characteristics). A typical short-circuit transient and recovery is shown in Figure 13. SPACE Figure 13. Short-Circuit Transient and Recovery SPACE The high-side current limit trips when the peak inductor current reaches IL-HS (see Electrical Characteristics). This is a cycle-by-cycle current limit and does not produce any frequency or current foldback. It is meant to protect the high-side MOSFET from excessive current. Under some conditions, such as high input voltage, this current limit may trip before the low-side protection. The peak value of this current limit varies with duty cycle. In response to a short circuit, the peak current limit prevents excessive peak current while valley current limit prevents excessive average inductor current and keeps the power dissipation low during a fault. After a small number of cycles of valley current limit triggers, hiccup mode is activated. In addition, the INEG current limit also protects the low-side switch from excessive negative current when the device is in FPWM mode. If this current exceeds INEG, the low-side switch is turned off until the next clock cycle. When the device is in AUTO mode, the negative current limit is increased to about IZC (about 0 A). This allows the device to operate in DCM. 8.3.5 Hiccup Mode Hiccup mode prevents excessive heating and power consumption under sustained short-circuit conditions. If an overcurrent condition is maintained, the LMS3655 shuts off its output and waits for TW (approximately 6 ms), after which the LMS3655 restarts operation by activating soft start. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 17 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com Vout Figure 14. Hiccup Operation During hiccup mode operation, the switch node of the LMS3655 is high impedance after a short circuit or overcurrent persists for a short duration. Periodically, the LMS3655 attempts to restart. If the short has been removed before one of these restart attempts, the LMS3655 operates normally. 8.3.6 Synchronizing Input It is often desirable to synchronize the operation of multiple regulators in a single system. This technique results in better-defined EMI and can reduce the need for capacitance on some power rails. The LMS3655 provides a SYNC input which allows synchronization with an external clock. The LMS3655 implements an in-phase locking scheme—the rising edge of the clock signal provided to the SYNC input corresponds to turning on the high-side device within the LMS3655. The SYNC mode operation is implemented using phase locking over a limited frequency range eliminating large glitches upon initial application of an external clock. The clock fed into the LMS3655 replaces the internal free running clock but does not affect frequency foldback operation. Output voltage continues to be well regulated with duty factors outside of the normal 4% through 96% range though at reduced frequency. The SYNC input recognizes a valid high level as that ≥ 1.5 V, and a valid low as that ≤ 0.4 V. The frequency synchronization signal must be in the range of 250 kHz to 500 kHz with a duty cycle of 10% to 90%. The internal clock is synced to the rising edge of the external clock. Ground this input if not used; this input must not be allowed to float. See Device Functional Modes to determine which modes are valid for synchronizing the clock. The device remains in FPWM mode and operates in CCM for light loads when a synchronization input is provided. To prevent frequency foldback behavior at low duty cycles, provide a 200-mA load. 8.3.7 Undervoltage Lockout (UVLO) and Thermal Shutdown (TSD) The LMS3655 incorporates an input UVLO function. The device accepts an EN command when the input voltage rises above about 3.64 V and shuts down when the input falls below about 3.3 V. See Electrical Characteristics under VIN-OPERATE for detailed specifications. TSD is provided to protect the device from excessive temperature. When the junction temperature reaches about 165°C, the device shuts down; restart occurs at a temperature of about 150°C. 8.3.8 Input Supply Current The LMS3655 is designed to have very low input supply current when regulating light loads. This is achieved by powering much of the internal circuitry from the output. The BIAS pin is the input to the LDO that powers the majority of the control circuits. By connecting the BIAS input to the output of the regulator, this current acts as a small load on the output. This current is reduced by the ratio of VOUT / VIN, just like any other load. 18 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 IQ_VIN is defined as the current consumed by a converter using a LMS3655 device while regulating without a load. To calculate the theoretical total quiescent current, the below equation can be used with parameters from the Electrical Characteristics and System Characteristics tables. While operating without a load, the LMS3655 only powers itself. The device draws power from three sources: the VIN pin (IQ), the EN pin (IEN), and the BIAS pin (IB). Because the BIAS input is connected to the output of the circuit, the power consumed is converted from input power with an effective efficiency, ηeff. Here, effective efficiency is the added input power needed when lightly loading the converter of the LMS3655 device and is divided by the corresponding additional load. This allows unloaded current to be calculated in Equation 2: Output Voltage IQ _ VIN IQ IEN IB Idiv Keff u Input Voltage where • • • • • • IQ_VIN is the current consumed by the operating (switching) buck converter while unloaded. IQ is the current drawn by the LMS3655 from its VIN terminal. See IQ in Electrical Characteristics. IEN is current drawn by the LMS3655 from its EN terminal. Include this current if EN is connected to VIN. See IEN in Electrical Characteristics. Note that this current drops to a very low value if connected to a voltage less than 5 V. IB is bias current drawn by the unloaded LMS3655. See IB in System Characteristics. Idiv is the current drawn by the feedback voltage divider used to set output voltage. ηeff is the light load efficiency of the Buck converter with IQ_VIN removed from the input current of the buck converter. (2) NOTE The EN pin consumes a few micro-amperes when tied to high; see IEN. Add IEN to IQ as shown in Equation 2 if EN is tied to VIN. If EN is tied to a voltage less than 5 V, virtually no current is consumed allowing EN to be used as an UVLO pin once a voltage divider is added. 8.4 Device Functional Modes Refer to Table 3 and the following paragraphs for a detailed description of the functional modes for the LMS3655. These modes are controlled by the FPWM input as listed in Table 3. This input can be controlled by any compatible logic while the regulator is operating. If it is desired to fix the mode for a given application, the input can be either connected to ground, a logic supply, the VIN pin, or the VCC pin, as desired. The FPWM pin must not be allowed to float. Table 3. Mode Selection FPWM INPUT VOLTAGE OPERATING MODE > 1.5 V Forced PWM: The regulator operates as a constant frequency, current mode, fullsynchronous converter for all loads; without diode emulation. < 0.4 V AUTO: The regulator moves between PFM and PWM as the load current changes, using diode-emulation mode to allow DCM (see the Glossary). 8.4.1 AUTO Mode In AUTO mode the device moves between PWM and PFM as the load changes. At light loads, the regulator operates in PFM. At higher loads, the mode changes to PWM. The load currents at which the mode changes can be found in the Application Curves. In PWM, the converter operates as a constant frequency, current mode, full synchronous converter using PWM to regulate the output voltage. While operating in this mode the output voltage is regulated by switching at a constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line and load regulation and low output voltage ripple. When in PWM, the converter synchronizes to any valid clock signal on the SYNC input (see Synchronizing Input); during PFM operation, the SYNC input is ignored. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 19 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com In PFM, the high-side FET is turned on in a burst of one or more cycles to provide energy to the load. The frequency of these bursts is adjusted to regulate the output, while diode emulation is used to maximize efficiency (see the Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current required to regulate the output voltage at small loads. A small increase in the output voltage occurs in PFM. This trades off very good light load efficiency for larger output voltage ripple and variable switching frequency. The actual switching frequency and output voltage ripple depend on the input voltage, output voltage, and load. See the Application Curves for output voltage variation in AUTO mode. A typical switching waveform for PFM is shown in Figure 15. A unique feature of this device is that a minimum input voltage is required for the regulator to switch from PWM to PFM at light load. This feature is a consequence of the advanced architecture employed to provide high efficiency at light loads. Figure 16 indicates typical values of input voltage required to switch modes at no load. Also, once the regulator switches to PFM at light load, it remains in that mode if the input voltage is reduced. SPACE 4.2 Inductor Current: 250 mA/div Light Load Deactivation Threshold (Falling) Light Load Activation Threshold (Rising) Input Voltage (V) 4 SW: 5V/div 3.8 3.6 3.4 VOUT: 5V/div 3.2 -50 10 µs/div Figure 15. Typical PFM Switching Waveforms 0 50 Temperature (qC) 100 150 LMS3 Figure 16. Input Voltage for Mode Change — 3.3-V Output, 10-µH Inductor 6 Light Load Deactivation Threshold (Falling) Light Load Activation Threshold (Rising) 5.9 Input Voltage (V) 5.8 5.7 5.6 5.5 5.4 5.3 5.2 5.1 5 -50 0 50 Temperature (qC) 100 150 LMS3 Figure 17. Input Voltage for Mode Change — 5-V Output, 10-µH Inductor 8.4.2 FPWM Mode With a logic high on the FPWM input, the device is locked in PWM mode. CCM operation is maintained, even at no load, by allowing the inductor current to reverse its normal direction. To prevent frequency foldback behavior at low duty cycles, provide a 200-mA load. This mode trades off reduced light load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching frequency. In this mode, a negative current limit of INEG is imposed to prevent damage to the low-side FET of the regulator. When in PWM, the converter synchronizes to any valid clock signal on the SYNC input (see Synchronizing Input). When constant frequency operation is more important than light load efficiency, pull the LMS3655 FPWM input high or provide a valid synchronization input. Once activated, the diode emulation feature is turned off in this mode. This means that the device remains in CCM under light loads. Under conditions where the device must reduce the on time or off time below the ensured minimum, the frequency reduces to maintain the effective duty cycle required for regulation. This can occur for high input or output voltage ratios. With the FPWM pin pulled low (normal mode), the diode emulation feature is activated. Device operation is the same as above; however, the regulator goes into DCM operation when the valley of the inductor current reaches zero. 20 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 This feature may be activated and deactivated while the part is regulating without removing the load. This feature activates and deactivates gradually preventing perturbation of output voltage. When in FPWM mode, a limited reverse current is allowed through the inductor allowing power to pass from the regulator's output to its input. In this case, ensure that a large enough input capacitor is used to absorb the reverse current. NOTE While FPWM is activated, larger currents pass through the inductor than in AUTO mode when lightly loaded. This may result in more EMI, though at a predictable frequency. Once loads are heavy enough to necessitate CCM operation, FPWM has no measurable effect on the operation of the regulator. 8.4.3 Dropout The minimum off time influences the dropout performance of the buck regulator. As the input voltage is reduced, to near the output voltage, the off time of the high-side switch starts to approach the minimum value (see Electrical Characteristics). Beyond this point the switching may become erratic or the output voltage falls out of regulation. To avoid this problem, the LMS3655 automatically reduces the switching frequency to increase the effective duty cycle. This results in two specifications regarding dropout voltage, as shown in System Characteristics. One specification indicates when the switching frequency drops to 330 kHz. The other specification indicates when the output voltage has fallen to 3% of nominal. See the Application Curves for typical dropout values. Figure 18 and Figure 19 show the overall dropout characteristic for the 5-V option. Additional dropout information is discussed in Application Curves for 5-V output and in Application Curves for 3.3-V output. SPACE 450000 5.2 0A 2A 4A 5.5 A 400000 5 4.8 Frequency (Hz) Output Voltage (V) 350000 4.6 4.4 0A 2A 4A 5.5 A 4.2 4.5 5 Input Voltage (V) 250000 200000 150000 100000 50000 4 4 300000 5.5 0 4 LMS3 Figure 18. Overall Dropout Characteristics (VOUT = 5 V) 4.2 4.4 4.6 4.8 5 5.2 5.4 Input Voltage (V) 5.6 5.8 6 LMS3 Figure 19. Frequency Dropout Characteristics (VOUT = 5 V) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 21 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com 8.4.4 Spread-Spectrum Operation The spread spectrum is a factory option. In order to find which parts have spread spectrum enabled, see Device Comparison Table. The purpose of the spread spectrum is to eliminate peak emissions at specific frequencies by spreading emissions across a wider range of frequencies. In most systems containing the LMS3655 devices, low frequency conducted emissions from the first few harmonics of the switching frequency can be easily filtered. A more difficult design criterion is reduction of emissions at higher harmonics which fall in the FM band. These harmonics often couple to the environment through electric fields around the switch node. The LMS3655 devices use a ±3% spread of frequencies which spread energy smoothly across the FM band but is small enough to limit subharmonic emissions below its switching frequency. Peak emissions at the switching frequency of the part are only reduced by slightly less than 1 dB, while peaks in the FM band are typically reduced by more than 6 dB. The LMS3655 devices use a cycle-to-cycle frequency hopping method based on a linear feedback shift register (LFSR). Intelligent pseudo random generator limits cycle to cycle frequency changes to limit output ripple. Pseudo random pattern repeats by approximately 1.2 Hz which is below the audio band. The spread spectrum is only available while the clock of the LMS3655 devices is free running at its natural frequency. Any of the following conditions overrides spread spectrum, turning it off: • An external clock is applied to the SYNC/MODE terminal. • The clock is slowed due to operation at low input voltage; this is operation in dropout. • The clock is slowed under light load in AUTO mode; this is normally not seen above 200 mA of load. In FPWM mode, spread spectrum is active even if there is no load. 22 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LMS3655 is a step-down DC-DC converter, typically used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 5.5 A. The following design procedures can be used to select components for the LMS3655. Alternately, the WEBENCH® Design Tool may be used to generate a complete design. This tool uses an iterative design procedure and has access to a comprehensive database of components. This allows the tool to create an optimized design and allows the user to experiment with various design options. 9.2 Typical Applications 9.2.1 General Application Figure 20 shows a general application schematic. FPWM, SYNC, and EN are digital inputs. RESET is an opendrain output. • The FPWM pin can be connected to GND to enable light-load PFM operation. Select this option if current consumption at light load is critical. The pin can be connected to VCC or VIN for forced 400-kHz operation. Select this option if constant switching frequency is critical. The pin can also be driven by an external signal and can be toggled while the part is in operation (by an MCU, for example). Refer to the Device Functional Modes for more details on the operation and signal requirements of the FPWM pin. • The SYNC pin can be used to control the switching frequency and the phase of the converter. If the function is not needed, tie the SYNC pin to GND, VCC, or VIN. • The RESET pin can be left floating or tied to ground if the function is not required. If the function is needed, the pin must be connected to a DC rail through a pullup resistor (100 kΩ is the typical recommended value). Check RESET Flag Output for the details of the RESET pin function. • Connect the output to the FB pin through a voltage divider. See Detailed Design Procedure for details on component selection. • The BIAS pin can be connected directly to the output voltage. In applications that can experience inductive shorts (such as cases with long leads on the output), a 3 Ω or so is necessary between the output and the BIAS pin, and a small capacitor to GND is necessary close to the BIAS pin (CBIAS). Alternatively, a Schottky diode can be connected between OUT and GND to limit the negative voltage that can arise on the output during inductive shorts. In addition, BIAS can also be connected to an external rail if necessary and if available. The typical current into the bias pin is 15 mA when the device is operating in PWM mode at 400 kHz. • Power components must be chosen carefully for proper operation of the converter. Detailed Design Procedure discusses the details of the process of choosing the input capacitors, output capacitors, and inductor for the application. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 23 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com Typical Applications (continued) VIN 3.5 V to 36 V 10 µF PVIN 1 PVIN 2 PGND1 PGND2 10 µF 10 µF AVIN RESET VCC SYNC 4.7 µF AGND LMS3655 BIAS 0.1 µF FB NC CFF RFBB FPWM CBOOT RFBT 470 nF SW EN L1=10 µH VOUT 3 X 47 µF Copyright © 2017, Texas Instruments Incorporated Figure 20. General Application Circuit 9.2.1.1 Design Requirements Three sets of application-specific design requirements are outlined in Table 8, Table 9, and Table 10. The minimum input voltage shown in Figure 20 is not the minimum operating voltage of the LMS3655. Rather, it is a typical operating range for the systems. For the complete information regarding minimum input voltage see Electrical Characteristics. 9.2.1.2 Detailed Design Procedure 9.2.1.2.1 External Components Selection The device requires input capacitors and an output inductor-capacitor filter. These components are critical to the performance of the device. 9.2.1.2.1.1 Input Capacitors The input capacitor supplies the AC switching current drawn from the switching action of the internal power FETs. The input current of a buck converter is discontinuous, so the ripple current supplied by the input capacitor is large. The input capacitor must be rated to handle both the RMS current and the dissipated power. The device is designed to be used with ceramic capacitors on the input of the buck regulator. The recommended dielectric type of these capacitors is X5R, X7R, or of comparable material to maintain proper tolerances over voltage and temperature. The device requires a minimum of 20 µF of ceramic capacitance at the input. TI recommends 2 × 10 µF, 10 µF for PVIN1 and 10 µF for PVIN2. Place these capacitors close to the PVIN1, PGND1, PVIN2, and the PGND2 pads. The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying ripple current and isolating switching noise from other circuits. Table 4 shows the nominal and minimum values of total input capacitance recommended for the LMS3655. Also shown are the measured values of effective capacitance for the indicated capacitor. 24 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 Typical Applications (continued) In addition, it is especially important to have small ceramic bypass capacitors of 10 nF to 100 nF very close to the PVIN1 and PVIN2 inputs to minimize ringing and EMI generation due to the high-speed switching of the device coupled with trace inductance. TI recommends that a small case size 10-nF ceramic capacitor be placed across the input, as close to the device as possible. Additional high-frequency capacitors can be used to help manage conducted EMI or voltage spike issues that may be encountered. Many times it is desirable to use an additional electrolytic capacitor on the input, in parallel with the ceramics. This is especially true if long leads or traces are used to connect the input supply to the regulator. The moderate ESR of this capacitor can help damp any ringing on the input supply caused by long power leads. The use of this additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance. Table 4. Recommended Input Capacitors NOMINAL INPUT CAPACITANCE MINIMUM INPUT CAPACITANCE RATED CAPACITANCE MEASURED CAPACITANCE (1) RATED CAPACITANCE MEASURED CAPACITANCE (1) PART NUMBER 3 × 10 μF 22.5 μF 2 × 10 μF 15 μF CL32B106KBJNNNE (1) Measured at 14 V and 25°C. 9.2.1.2.1.2 Output Inductors and Capacitors There are several design considerations related to the selection of output inductors and capacitors: • Load transient response • Stability • Efficiency • Output ripple voltage • Overcurrent ruggedness The device has been optimized for use with LC values as shown in the Figure 20. 9.2.1.2.1.2.1 Inductor Selection The LMS3655 devices run in current mode and with internal compensation. The compensation of the adjustable 5-V and 3.3-V configurations is stable with inductance between 6.5 µH and 20 µH. For most applications, the adjustable 5-V and 3.3-V configurations of the LMS3655 devices are optimized for a nominal inductance of 10 μH. This gives a ripple current that is approximately 20% to 30% of the full load current of 5.5 A. If applying a synchronization clock signal, the designer should appropriately size the inductor for the converter's operating switching frequency. For output voltages greater than 5 V, a proportionally larger inductor can be used, thus keeping the ratio of inductor current slope to internal compensating slope constant. Inductance that is too high is not recommended because it can result in poor load transient behavior and instability. The inductor must be rated to handle the peak load current plus the ripple current—carefully review the different saturation current ratings specified by different manufacturers. Saturation current ratings are typically specified at 25°C, so ratings at maximum ambient temperature of the application should be requested from the manufacturer. For the LMS3655, TI recommends a saturation current of 10 A or higher. Carefully review the inductor parasitic resistance; the inductor parasitic resistance must be as low as possible to minimize losses at heavy loads. The best way to obtain an optimum design is to use the Texas Instruments WEBENCH Design Tool. Table 5 gives a list of several possible inductors that can be used with the LMS3655. The designer should choose the inductors that best match the system requirements. A very wide range of inductors are available as regarding physical size, height, maximum current (thermally limited, and inductance loss limited), series resistance, maximum operating frequency, losses, and so forth. In general, inductors of smaller physical size have higher series resistance (DCR) and implicitly lower overall efficiency is achieved. Very low-profile inductors may have even higher series resistance. TI recommends finding the best compromise between system performance and cost. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 25 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com Table 5. Recommended Inductors MANUFACTURER PART NUMBER SATURATION CURRENT DC RESISTANCE Würth 7443251000 8.5 A 16 mΩ Würth 7447709100 10.5 A 21 mΩ Vishay IHLP4040DZER100M01 12 A 36.5 mΩ 9.2.1.2.1.2.2 Output Capacitor Selection The output capacitor of a switching converter absorbs the AC ripple current from the inductor, reduces the output voltage ripple, and provides the initial response to a load transient. The ripple voltage at the output of the converter is the product of the ripple current flowing through the output capacitor and the impedance of the capacitor. The impedance of the capacitor can be dominated by capacitive, resistive, or inductive elements within the capacitor, depending on the frequency of the ripple current. Ceramic capacitors have very low ESR and remain capacitive up to high frequencies. Their inductive component can be usually neglected at the operating frequency range of the converter. The LMS3655 is designed to work with low-ESR ceramic capacitors. TI recommends X5R and X7R type capacitors. The effective value of these capacitors is defined as the actual capacitance under voltage bias and temperature. All ceramic capacitors have a large voltage coefficient, in addition to normal tolerances and temperature coefficients. Under DC bias, the capacitance value drops considerably. Larger case sizes or higher voltage capacitors are better in this regard. To help mitigate these effects, multiple small capacitors can be used in parallel to bring the minimum effective capacitance up to the desired value. This can also ease the RMS current requirements on a single capacitor. Table 6 shows the nominal and minimum values of total output ceramic capacitance recommended for the LMS3655.The values shown also provide a starting point for other output voltages. More output capacitance can be used to improve transient performance and reduce output voltage ripple. In order to minimize ceramic capacitance, a low-ESR electrolytic capacitor can be used in parallel with minimal ceramic capacitance. As a starting point for designing with an output electrolytic capacitor, Table 7 shows the minimum ceramic capacitance recommended when paired with a 120-µF Aluminum-polymer (ESR = 25 mΩ) in order to maintain stable operation. Depending on load transient design requirements, the designer may choose to add additional capacitance. In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load transient testing and bode plots are the best way to validate any given design and should always be completed before the application goes into production. Make a careful study of temperature and bias voltage variation of any candidate ceramic capacitor in order to ensure that the minimum value of effective capacitance is provided. The best way to obtain an optimum design is to use the Texas Instruments WEBENCH Design Tool. In adjustable applications the feed-forward capacitor, CFF, provides another degree of freedom when stabilizing and optimizing the design. Refer to Optimizing Transient Response of Internally Compensated DC-DC Converters With Feedforward Capacitor (SLVA289) for helpful information when adjusting the feed-forward capacitor. In addition to the capacitance shown in Table 6, a small ceramic capacitor placed on the output can help to reduce high frequency noise. Small case-size ceramic capacitors in the range of 1 nF to 100 nF can be very helpful in reducing spikes on the output caused by inductor parasitics. Limit the maximum value of total output capacitance to between 800 μF and 1200 μF. Large values of output capacitance can prevent the regulator from starting up correctly and adversely effect the loop stability. If values greater than the given range are to be used, then a careful study of start-up at full load and loop stability must be performed. Table 6. Recommended Output Ceramic Capacitors OUTPUT VOLTAGE (1) 26 NOMINAL OUTPUT CERAMIC CAPACITANCE MINIMUM OUTPUT CERAMIC CAPACITANCE RATED CAPACITANCE RATED CAPACITANCE (1) PART NUMBER 3.3 V 4 × 47 µF 3 x 47µF GRM32ER71A476KE15L 5V 4 × 47 µF 3 × 47µF GRM32ER71A476KE15L L = 10 μH Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 Table 6. Recommended Output Ceramic Capacitors OUTPUT VOLTAGE (2) () (continued) NOMINAL OUTPUT CERAMIC CAPACITANCE MINIMUM OUTPUT CERAMIC CAPACITANCE RATED CAPACITANCE RATED CAPACITANCE PART NUMBER 6V 4× 47 μF 3 × 47μF GRM32ER71A476KE15L 10 V (2) 4 × 47 μF 3 × 47 μF GRM32ER71A476KE15L L = 20 μH Table 7. Recommended Output Al-Polymer and Ceramic Capacitors OUTPUT VOLTAGE OUTPUT AL-POLYMER CAPACITANCE PART NUMBER RATED CAPACITANCE (1) (1) MINIMUM OUTPUT CERAMIC CAPACITANCE RATED CAPACITANCE 3.3 V 120 µF APXE160ARA121MH70G 1 × 47µF + 1 x 20µF 5V 120 µF APXE160ARA121MH70G 1 × 47µF L = 10 μH Consult Output Ripple Voltage for Buck Switching Regulator (SLVA630) for more details on the estimation of the output voltage ripple for this converter. 9.2.1.2.2 FB for Adjustable Output The LMS3655 devices regulate output voltage to a level that results in the FB node being VREF, which is approximately 1 V (see Electrical Characteristics). Output voltage given a specific feedback divider can be calculated using Equation 3: R RFBT Output Voltage Vref u FBB RFBB (3) To ensure proper behavior for all modes of operation, a 50-kΩ resistor is recommended for RFBT. RFBB can then be determined using Equation 4: Vref u RFBT RFBB Output Voltage Vref (4) In addition, a feed-forward capacitor CFF may be required to optimize the transient response. For output voltages greater than 6 V, the WEBENCH Design Tool can be used to optimize the design. 9.2.1.2.3 VCC The VCC pin is the output of the internal LDO used to supply the control circuits of the LMS3655. This output requires a 4.7-µF, 10-V ceramic capacitor connected from VCC to GND for proper operation. X7R type is recommended. In general, this output must not be loaded with any external circuitry. However, the output can be used to supply a logic level to the FPWM input or for the pullup resistor used with the RESET output. The nominal output of the LDO is 3.15 V. 9.2.1.2.4 BIAS The BIAS pin is the input to the internal LDO. As detailed in Input Supply Current, this input is connected directly to VOUT to provide the lowest possible supply current at light loads. Because this input is connected directly to the output, it must be protected from negative voltage transients. Such transients may occur when the output is shorted at the end of a long PCB trace or cable. If this is likely in a given application, then place a small resistor in series between the BIAS input and VOUT as shown in Figure 23. Size the resistor to limit the current out of the BIAS pin to < 100 mA. Values in the range of 2 Ω to 5 Ω are typically sufficient. Values greater than 5 Ω are not recommended. As a rough estimate, assume that the full negative transient appears across RBIAS and design for a current of < 100 mA. In severe cases, a Schottky diode can be placed in parallel with the output to limit the transient voltage and current. When a resistor is used between the output and the BIAS pin, a 0.1-µF capacitor is required close to the BIAS pin. In general, TI recommends having a 0.1-µF capacitor near the BIAS pin, regardless of the presence of the resistor, unless the trace between the output capacitors and the BIAS pin is very short. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 27 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com The typical current into the bias pin is 15 mA when the device is operating in PWM mode at 400 kHz. 9.2.1.2.5 CBOOT The LMS3655 requires a boot-strap capacitor between the CBOOT pin and the SW pin. This capacitor stores energy that is used to supply the gate drivers for the power MOSFETs. A ceramic capacitor of 0.47 µF, ≥ 6.3 V is required. 9.2.1.2.6 Maximum Ambient Temperature As with any power conversion device, the LMS3655 dissipates internal power while operating. The effect of this power dissipation is to raise the internal temperature of the converter above ambient. The internal die temperature (TJ) is a function of the ambient temperature, the power loss, and the effective thermal resistance, RθJA of the device and PCB combination. The maximum internal die temperature for the LMS3655 is 150°C, thus establishing a limit on the maximum device power dissipation and therefore load current at high ambient temperatures. Equation 5 shows the relationships between the important parameters. IOUT TJ TA K 1 ˜ ˜ R TJA 1 K VOUT (5) The device uses an advanced package technology that uses the pads and pins as heat spreading paths. As a result, the pads must be connected to large copper areas to dissipate the heat from the IC. All pins provide some heat relief capability but the PVINs, PGNDs, and SW pins are of particular importance for proper heat dissipation. Utilization of all the board layers for heat dissipation and using vias as heat pipes is recommended. The Layout Guidelines includes an example that shows layout for proper heat management. 28 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 9.2.1.3 Application Curves These parameters are not tested and represent typical performance only. Unless otherwise stated, the following conditions apply: VIN = 12 V, TA = 25°C. For the purpose of offering more information to the designer, information for the application with FPWM pin high (FPWM mode) and FPWM pin low (AUTO mode) is included, although the schematic shows the application running specifically in FPWM mode. The mode is specified under each following graph. 3.5 3.5 8.0 VIN 12.0 VIN 13.5 VIN 18.0 VIN 24.0 VIN 36.0 VIN 2.5 4.0 VIN 6.0 VIN 12.0 VIN 13.5 VIN 24.0 VIN 36.0 VIN 3 Power Dissipation (W) Power Dissipation (W) 3 2 1.5 1 0.5 2.5 2 1.5 1 0.5 0 0 0 1 2 3 4 Output Current (A) 5 6 0 LMS3 Figure 21. Power Dissipation 5-V Output 1 2 3 4 Output Current (A) 5 Figure 22. Power Dissipation 3.3-V Output Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 6 LMS3 29 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com 9.2.2 Adjustable 5-V Output VIN 5.5 V ± 36 V PVIN 1 PVIN 2 10 µF PGND1 0.1 µF 10 µF PGND2 0.1 µF RESET/PG OUT RESET AVIN 100 NŸ VCC 4.7 µF AGND NC LMS3655 BIAS 3Ÿ 0.1 µF FPWM FB 21.7 NŸ EN CBOOT 49.9 NŸ 22 pF 470 nF VOUT = 5 V SYNC IN SYNC SW L1 = 10 µF 100 NŸ 1 X 47 µF 1 X 120 µF ESR = 25 PŸ Copyright © 2017, Texas Instruments Incorporated Figure 23. 5-V, 5.5-A Output Power Supply 9.2.2.1 Design Requirements Example requirements for a typical 5-V application. The input voltages are here for illustration purposes only. See Electrical Characteristics for minimum operating input voltage. The minimum input voltage necessary to achieve proper output regulation depends on the components used. See Figure 29 for typical drop-out behavior. Table 8. Example Requirements for 5-V Typical Application DESIGN PARAMETER EXAMPLE VALUE Input voltage range 8 V to 18 V steady-state, 5.5 V to 36 V transients Output current 0 A to 5.5 A Switching Frequency at 0-A load Critical: must have > 250 kHz Current Consumption at 0-A load Not critical: < 100 mA acceptable Synchronization Yes: 300 kHz supplied by MCU 9.2.2.2 Detailed Design Procedure • BIAS is connected to the output. This example assumes that the load is connected to the output through long wires so a 3-Ω resistor is inserted to minimize risks of damage to the part during load shorts. In addition 0.1µF capacitor is required close to the bias pin. • FB is connected to the output through a voltage divider in order to create a voltage of 1 V at the FB pin when the output is at 5 V. A 22-pF capacitance is added in parallel with the top feedback resistor in order to improve transient behavior. BIAS and FB are connected to the output through separate traces. This is important to reduce noise and achieve good performance. See Layout Guidelines for more details on the proper layout method. • SYNC is connected to ground through a pulldown resistor, and an external synchronization signal can be 30 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com • • • • • • • SNAS744B – JULY 2017 – REVISED MARCH 2018 applied. The pulldown resistor ensures that the pin is not floating when the SYNC pin is not driven by any source. EN is connected to VIN so the device operates as soon as the input voltage rises above the VIN-OPERATE threshold. FPWM is connected to VIN. This causes the device to operate in FPWM mode. In this mode, the device remains in CCM operation regardless of the output current and is ensured to be within the boundaries set by FSW. To prevent frequency foldback behavior at low duty cycles, provide a 200-mA load. The drawback is that the efficiency is not optimized for light loads. See Device Functional Modes for more details. A 4.7-µF capacitor is connected between VCC and GND close to the VCC pin. This ensures stable operation of the internal LDO. RESET is biased to the output in this example. A pullup resistor is necessary. A 100-kΩ is selected for this application and is generally sufficient. The value can be selected to match the needs of the application but must not lead to excessive current into the RESET pin when RESET is in a low state. Consult Absolute Maximum Ratings for the maximum current allowed. In addition, a low pullup resistor could lead to an incorrect logic level due to the value of RRESET. Consult Electrical Characteristics for details on the RESET pin. Input capacitor selection is detailed in Input Capacitors. It is important to connect small high-frequency capacitors CIN_HF1 and CIN_HF2 as close to both inputs PVIN1 and PVIN2 as possible. Output capacitor selection is detailed in Output Capacitor Selection. Inductor selection is detailed in Inductor Selection. In general, a 10-µH inductor is recommended for the nominal adjustable output range of 3.3 V to 5 V. The inductance can vary with the output voltage due to ripple and current limit requirements. 9.2.2.3 Application Curves The following characteristics apply only to the circuit of Adjustable 5-V Output. These parameters are not tested and represent typical performance only. Unless otherwise stated, the following conditions apply: VIN = 12 V, TA = 25°C. For the purpose of offering more information to the designer, information for the application with FPWM pin high (FPWM mode) and FPWM pin low (AUTO mode) is included, although the schematic shows the application running specifically in FPWM mode. The mode is specified under each following graph. 100% 100% 95% 95% 90% 90% Efficiency Efficiency 85% 85% 80% 75% 8.0 VIN 12.0 VIN 13.5 VIN 18.0 VIN 24.0 VIN 36.0 VIN 70% 65% 60% 0.001 80% 75% 70% 8.0 VIN 12.0 VIN 13.5 VIN 18.0 VIN 24.0 VIN 36.0 VIN 65% 60% 55% 50% 0.01 VOUT = 5 V 0.1 Output Current (A) AUTO 1 10 0 1 LMS3 VOUT = 5 V Figure 24. Efficiency 2 3 4 Output Current (A) 5 6 LMS3 FPWM Figure 25. Efficiency Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 31 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com 5.12 5.05 8.0 VIN 12.0 VIN 13.5 VIN 18.0 VIN 24.0 VIN 36.0 VIN Output Voltage (V) 5.1 5.09 5.08 5.03 Output Voltage (V) 5.11 5.07 5.06 5.05 5.04 5.01 4.99 8.0 VIN 12.0 VIN 13.5 VIN 18.0 VIN 24.0 VIN 36.0 VIN 4.97 5.03 5.02 5.01 4.95 0 0.5 1 1.5 2 2.5 3 3.5 Output Current (A) VOUT = 5 V 4 4.5 5 5.5 0 1 AUTO VOUT = 5 V Figure 26. Load and Line Regulation 3 4 Output Current (A) 5 6 LMS3 FPWM Figure 27. Load and Line Regulation 1.2 1000 40qC 25qC 105qC 900 1 Dropout Voltage (V) 800 Output Current (mA) 2 LMS3 700 600 500 400 300 200 0.8 0.6 0.4 0.2 100 0 0 0 10 20 Input Voltage (V) 30 0 40 1 LMS3 5 6 LMS3 Figure 29. Dropout for –3% Regulation Figure 28. Load Current for PFM-to-PWM Transition 450000 1.2 40qC 25qC 105qC 400000 Switching Frequency (Hz) 1 Dropout Voltage (V) 3 4 Output Current (A) VOUT = 5 V VOUT = 5 V 0.8 0.6 0.4 0.2 350000 300000 250000 200000 150000 8 VIN 12 VIN 18 VIN 24 VIN 100000 50000 0 0 1 2 3 4 Output Current (A) 5 6 LMS3 VOUT = 5 V Figure 30. Dropout for ≥ 330 kHz 32 2 0 0.001 0.01 VOUT = 5 V 0.1 Output Current (A) 1 10 LMS3 AUTO Figure 31. Switching Frequency vs Load Current Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 9 8 Output Current (A) 7 6 5 4 3 2 1 LMS3655 0 0 5 10 VOUT = 5 V 15 20 25 30 Input Voltage (V) 35 40 45 LMS3 L = 10 µH AUTO COUT = 170 µF Figure 32. Output Current Level Limit Before Overcurrent Protection FPWM COUT = 170 µF VOUT = 5 V IOUT = 0 A to 3.5 A VOUT = 5 V IOUT = 10 mA to 3.5 A L = 10 µH TR = TF = 1 µs Figure 33. Load Transients L = 10 µH TR = TF = 1 µs Figure 34. Load Transient Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 33 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com 9.2.3 Adjustable 3.3-V Output VIN 3.8 V to 36 V VDD PVIN 1 PVIN 2 10 µF 0.1 µF 4.7 µF PGND1 10 µF 100 NŸ PGND2 0.1 µF AVIN RESET VCC NC AGND LMS3655 RESET/PG OUT BIAS 0.1 µF FPWM FB 21.7 NŸ EN CBOOT 49.9 NŸ 22 pF 470 nF VOUT = 3.3 V SYNC SW L1 = 10 µH 1 X 67 µF 1 X 120 µF ESR = 25 PŸ Copyright © 2017, Texas Instruments Incorporated Figure 35. Adjustable 3.3-V, 5.5-A Output Power Supply 9.2.3.1 Design Requirements Example requirements for a typical 3.3-V application. The input voltages are here for illustration purposes only. See Electrical Characteristics for minimum operating input voltage. The minimum input voltage necessary to achieve proper output regulation depends on the components used. See Figure 41 for typical drop-out behavior. Table 9. Example Requirements for 3.3-V Application DESIGN PARAMETER EXAMPLE VALUE Input voltage range 8-V to 18-V steady-state, 4.0-V to 36-V transients Output current 0 A to 5.5 A Switching Frequency at 0-A load Not critical: Need >330 kHz at high load only Current Consumption at 0-A load Critical: Need to ensure low current consumption to reduce battery drain Synchronization No 9.2.3.2 Detailed Design Procedure • BIAS is connected to the output. This example assumes that the load is close to the output so no bias resistance is necessary. A 0.1-µF capacitor is still recommended close to the bias pin. • FB is connected to the output through a voltage divider in order to create a voltage of 1 V at the FB pin when the output is at 3.3 V. A 22-pF capacitance is added in parallel with the top feedback resistor in order to improve transient behavior. BIAS and FB are connected to the output through separate traces. This is important to reduce noise and achieve good performance. See Layout Guidelines for more details on the proper layout method. • SYNC is connected to ground directly as there is no need for this function in this application. • EN is connected to VIN so the device operates as soon as the input voltage rises above the VIN-OPERATE threshold. 34 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com • • • • • • SNAS744B – JULY 2017 – REVISED MARCH 2018 FPWM is connected to GND. This causes the device to operate in AUTO mode. In this mode, the switching frequency is adjusted at light loads to optimize efficiency. As a result the switching frequency changes with the output current until medium load is reached. The part will then switch at the frequency defined by FSW. See Device Functional Modes for more details. A 4.7-µF capacitor is connected between VCC and GND close to the VCC pin. This ensures stable operation of the internal LDO. RESET is biased to an external rail in this example. A pullup resistor is necessary. A 100-kΩ pullup resistor is selected for this application and is generally sufficient. The value can be selected to match the needs of the application but must not lead to excessive current into the RESET pin when RESET is in a low state. Consult Absolute Maximum Ratings for the maximum current allowed. In addition, a low pullup resistor could lead to an incorrect logic level due to the value of RRESET. Consult Electrical Characteristics for details on the RESET pin. It is important to connect small high frequency capacitors CIN_HF1 and CIN_HF2 as close to both inputs PVIN1 and PVIN2 as possible. For the detailed process of choosing input capacitors, refer to Input Capacitors. Output capacitor selection is detailed in Output Capacitor Selection. Inductor selection is detailed in Inductor Selection. In general, a 10-µH inductor is recommended for the nominal adjustable output range of 3.3 V to 5 V. The inductance can vary with the output voltage due to ripple and current limit requirements. 9.2.3.3 Application Curves 100% 95% 90% 85% 80% 75% 70% 65% 60% 55% 50% 45% 40% 35% 30% 25% 20% 0.0001 1.1 1 0.9 Output Voltage (V) Efficiency The following characteristics apply only to the circuit of Figure 35. These parameters are not tested and represent typical performance only. Unless otherwise stated, the following conditions apply: VIN = 12 V, TA = 25°C. For the purpose of offering more information to the designer, information for the application with FPWM pin high (FPWM mode) and FPWM pin low (AUTO mode) is included, although the schematic shows the application running specifically in AUTO mode. The mode is specified under each of the following graphs. 6.0 VIN 12.0 VIN 13.5 VIN 18.0 VIN 24.0 VIN 36.0 VIN 0.001 VOUT = 3.3 V 0.01 0.1 Output Current (A) AUTO 1 0.8 0.7 0.6 0.5 6.0 VIN 12.0 VIN 13.5 VIN 18.0 VIN 24.0 VIN 36.0 VIN 0.4 0.3 0.2 10 0.1 0.0001 1.0001 LMS3 VOUT = 3.3 V Figure 36. Efficiency 2.0001 3.0001 Output Current (A) 4.0001 5.0001 LMS3 FPWM Figure 37. Efficiency Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 35 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com 3.4 3.4 6.0 VIN 12.0 VIN 13.5 VIN 18.0 VIN 24.0 VIN 36.0 VIN Output Voltage (V) 3.36 3.34 3.32 6.0 VIN 12.0 VIN 13.5 VIN 18.0 VIN 24.0 VIN 36.0 VIN 3.38 3.36 Output Voltage (V) 3.38 3.3 3.28 3.26 3.34 3.32 3.3 3.28 3.26 3.24 3.24 3.22 3.22 3.2 3.2 0 0.5 1 1.5 2 2.5 3 3.5 Output Current (A) VOUT = 3.3 V 4 4.5 5 5.5 0 1 AUTO VOUT = 3.3 V Figure 38. Load and Line Regulation 6 LMS3 FPWM 40qC 25qC 105qC 1 Dropout Voltage (V) Output Current (mA) 5 1.2 1200 1000 800 600 400 0.8 0.6 0.4 0.2 200 0 0 0 5 10 15 20 25 Input Voltage (V) 30 35 0 40 1 2 LMS3 3 4 Output Current (A) 5 6 LMS3 VOUT = 3.3 V VOUT = 3.3 V Figure 41. Dropout for –3% Regulation Figure 40. Load Current for PFM-to-PWM Transition 450000 1.2 40qC 25qC 105qC 400000 Switching Frequency (Hz) 1 Dropout Voltage (V) 3 4 Output Current (A) Figure 39. Load and Line Regulation 1400 0.8 0.6 0.4 0.2 350000 300000 250000 200000 150000 8 VIN 12 VIN 18 VIN 24 VIN 100000 50000 0 0 1 2 3 4 Output Current (A) 5 6 LMS3 VOUT = 3.3 V Figure 42. Dropout for ≥ 330 kHz 36 2 LMS3 0 0.001 0.01 VOUT = 3.3 V 0.1 Output Current (A) 1 10 LMS3 AUTO Figure 43. Switching Frequency vs Load Current Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 9 8 Output Current (A) 7 6 5 4 3 2 1 LMS3655 0 0 5 10 VOUT = 3.3 V 15 20 25 30 Input Voltage (V) 35 40 45 LMS3 L = 10 µH AUTO COUT = 190 µF Figure 44. Output Current Level for Overcurrent Protection Trip FPWM COUT = 190 µF VOUT = 3.3 V IOUT = 0 A to 3.5 A Figure 46. Load Transient L = 10 µH, TR = TF = 1 µs VOUT = 3.3 V IOUT = 0 A to 3.5 A L = 10 µH, TR = TF = 1 µs Figure 45. Load Transient VOUT = 3.3 V IOUT = 10 mA Figure 47. Mode Change Transient AUTO to FPWM mode Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 37 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com 9.2.4 6-V Adjustable Output VIN 8 V ± 36 V PVIN 1 PVIN 2 PGND1 PGND2 AVIN RESET 10 µF 10 µF 0.1 µF 0.1 µF VCC 4.7 µF NC AGND LMS3655 BIAS 3Ÿ 0.1 µF FPWM FB 10.2 NŸ CBOOT EN 49.9 NŸ 22 pF 470 nF VOUT = 6 V SYNC SW L1 = 10 µH 1 X 67 µF 1 X 120 µF ESR = 25 PŸ Copyright © 2017, Texas Instruments Incorporated Figure 48. 6-V Output Power Supply 9.2.4.1 Design Requirements The application highlighted in this section is for a typical 6-V system. The input voltages are here for illustration purposes only. See Electrical Characteristics for minimum operating input voltage. Table 10. Example Requirements for 6-V Application DESIGN PARAMETER Input voltage range EXAMPLE VALUE 8-V to 18-V steady-state Output current 0 A to 5.5 A Switching Frequency at 0-A load > 250 kHz preferred Current Consumption at 0-A load Not critical Synchronization No 9.2.4.2 Detailed Design Procedure • BIAS is connected to the output. This example assumes that inductive shorts are a risk for this application so a 3-Ω resistor is added between BIAS and the output. A 0.1-µF capacitor is added close to the BIAS pin. • FB is connected to the output through a voltage divider in order to create a voltage of 1 V at the FB pin when the output is at 6 V. A 22-pF capacitance is added in parallel with the top feedback resistor in order to improve transient behavior. BIAS and FB are connected to the output through separate traces. This is important to reduce noise and achieve good performances. See Layout Guidelines for more details on the proper layout method. • SYNC is connected to ground directly as there is no need for this function in this application. • EN is toggled by an external device (like an MCU for example). A pulldown resistor is placed to ensure the part does not turn on if the external source is not driving the pin (Hi-Z condition). • FPWM is connected to VIN. This causes the device to operate in FPWM mode. To prevent frequency foldback behavior at low duty cycles, provide a 200mA load. In this mode, the device remains in CCM operation regardless of the output current and is ensured to be within the boundaries set by FSW. The drawback is that the efficiency is not optimized for light loads. See Device Functional Modes for more details. • A 4.7-µF capacitor is connected between VCC and GND close to the VCC pin. This ensure stable operation of the internal LDO. • RESET is not used in this example so the pin has been left floating. Other possible connections can be seen 38 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com • SNAS744B – JULY 2017 – REVISED MARCH 2018 in the previous typical applications and in RESET Flag Output. Power components (input capacitor, output capacitor, and inductor) selection can be found here in External Components Selection. 9.2.4.3 Application Curves The following characteristics apply only to the circuit of Figure 48. These parameters are not tested and represent typical performance only. Unless otherwise stated, the following conditions apply: VIN = 12 V, TA = 25°C. VOUT = 6 V FPWM IOUT = 0 A VOUT = 6 V IOUT = 0 A Figure 50. Start-Up Waveform (EN Tied to VIN) Figure 49. Start-Up Waveform FPWM COUT = 190 µF FPWM VOUT = 6 V IOUT = 0 A to 3.5 A L = 10 µH, TR = TF = 1 µs Figure 51. Load Transient Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 39 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com 9.3 Do's and Don't's • • • • • • • Don't: Exceed the Absolute Maximum Ratings. Don't: Exceed the Recommended Operating Conditions. Don't: Allow the EN, FPWM or SYNC input to float. Don't: Allow the output voltage to exceed the input voltage, nor go below ground. Don't: Use the thermal data given in the Thermal Information table to design your application. Do: Follow all of the guidelines and/or suggestions found in this data sheet before committing a design to production. TI Application Engineers are ready to help critique designs and PCB layouts to help ensure successful projects. Do: Refer to the helpful documents found in Related Documentation. 10 Power Supply Recommendations The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended Operating Conditions found in this data sheet. In addition, the input supply must be capable of delivering the required input current to the loaded regulator. The average input current can be estimated with Equation 6: VOUT ˜ IOUT VIN ˜ K IIN where • η is the efficiency (6) If the regulator is connected to the input supply through long wires or PCB traces, special care is required to achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR ceramic input capacitors, can form an under-damped resonant circuit. This circuit may cause overvoltage transients at the VIN pin, each time the input supply is cycled on and off. The parasitic resistance causes the voltage at the VIN pin to dip when the load on the regulator is switched on or exhibits a transient. If the regulator is operating close to the minimum input voltage, this dip may cause the device to shut down or reset. The best way to solve these kinds of issues is to reduce the distance from the input supply to the regulator or use an aluminum or tantalum input capacitor in parallel with the ceramics. The moderate ESR of these types of capacitors helps to damp the input resonant circuit and reduce any voltage overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help to hold the input voltage steady during large load transients. Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to instability, as well as some of the effects mentioned above, unless it is designed carefully. LP3913 Power Management IC for Flash Memory Based Portable Media Players (SNVA489) provides helpful suggestions when designing an input filter for any switching regulator. In some cases a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device has a snap-back V-I characteristic (thyristor type). The use of a device with this type of characteristic is not recommend. When the TVS fires, the clamping voltage drops to a very low value. If this holding voltage is less than the output voltage of the regulator, the output capacitors are discharged through the regulator back to the input. This uncontrolled current flow could damage the regulator. 11 Layout 11.1 Layout Guidelines The PCB layout of a DC-DC converter is critical for optimal performance of the application. For a buck converter the input loop formed by the input capacitors and power grounds are very critical. The input loop carries fast transient currents that cause larger transient voltages when reacting with a parasitic loop inductance. The IC uses two input loops in parallel IN1 and IN2 as shown in Figure 52 that cuts the parasitic input inductance in half. To get the minimum input loop area two small high frequency capacitors CIN1 and CIN2 are placed as close as possible. 40 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 Layout Guidelines (continued) To further reduce inductance, an input current return path should be placed underneath the loops IN1 and IN2. The closest metal plane is MID1 Layer2, and there is a solid copper plane placed right under the IN1 and IN2 loop the parasitic loop inductance is minimized. Connecting this MID1 Layer2 plane to GND provides a nice bridge connection between GND1 and GND2 as well. Minimizing the parasitic input loop inductance will minimize switch node ringing and EMI. The output current loop can be optimized as well by using two ceramic output caps COUT1 and COUT2, one on each side. They form two parallel ground return paths OUT1 from COUT1 back to the low-side FET PGND1 pins 5, 6, 7, 8, and a second symmetric ground return path OUT2 from COUT2 back to low-side FET PGND2 pins 10, 11, 12, and 13. Having two parallel ground return paths yield reduced ground bouncing and reduced sensitivity of surrounding circuits. Figure 52. Layout of the Power Components and Current Flow Providing adequate thermal paths to dissipate heat is critical for operation at full current. The recommended method for heat dissipation is to use large solid 2-oz copper planes well connected to the power pins VIN1, VIN2, GND1, and GND2 which transfer the heat out of the IC over the TOP Layer1 copper planes. It is important to leave the TOP Layer1 copper planes as unbroken as possible so that heat is not trapped near the IC. The heat flow can be further optimized by thermally connecting the TOP Layer1 plane to large BOTTOM Layer 4 2-oz copper planes with vias. MID2 Layer3 is then open for all other signal routing. A fully filled or solid BOTTOM Layer4 ground plane without any interruptions or ground splitting is beneficial for EMI as well. Most important for low EMI is to use the smallest possible switch node copper area. The switch node including the CBOOT cap has the largest dV/dt signal causing common-mode noise coupling. Using any kind of grounded shield around the switch node shortens and reduces this e-field. All these DC-DC converter descriptions can be transformed into layout guidelines: 1. Place two 0.047-µF, 50-V high frequency input capacitors CIN1 and CIN2 as close as possible to the VIN1, VIN2, PGND1, PGND2 pins to minimize switch node ringing. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 41 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com Layout Guidelines (continued) 2. Place bypass capacitors for VCC and BIAS close to their respective pins. Make sure AGND pin sees the CVCC and CBIAS capacitors first before a connection to PGND. 3. Place CBOOT capacitor with smallest parasitic loop. Shielding the CBOOT capacitor and switch node has the biggest impact to reduce common-mode noise. Placing a small RBOOT resistor (less than 3 Ω is recommended) in series to CBOOT slows down the dV/dt of the switch node and reduce EMI. 4. Place the feedback resistor divider as close as possible to the FB pin and to AGND pin of the device. Use a dedicated feedback trace, and route away from switch node and CBOOT capacitor to avoid any cross coupling into sensitive analog feedback. 5. Use a dedicated BIAS trace to avoid noise into feedback trace. 6. Use a 3-Ω to 5-Ω resistor between the output and BIAS if the load is far from the output of the converter or inductive shorts on the output are possible. 7. Use well connected large 2-oz. TOP and BOTTOM copper planes for all power pins VIN1/2 and PGND1/2. 8. Minimize switch node and CBOOT area for lowest EMI common mode noise. 9. Place input and output wires on the same side of the PCB using an EMI filter and away from the switch node for lowest EMI. The resources in Device and Documentation Support provide additional important guidelines. 11.2 Layout Example This example layout is the one used in the LMS3655 EVM. It shows the CIN and CIN_HF capacitors placed symmetrically on either side of the device. Figure 53. Recommended Layout for LMS3655 42 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 LMS3655 www.ti.com SNAS744B – JULY 2017 – REVISED MARCH 2018 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Documentation Support 12.2.1 Related Documentation For additional information, see the following: • Optimizing Transient Response of Internally Compensated DC-DC Converters With Feedforward Capacitor (SLVA289) • Output Ripple Voltage for Buck Switching Regulator (SLVA630) • AN-1149 Layout Guidelines for Switching Power Supplies (SNVA021) • AN-1229 Simple Switcher® PCB Layout Guidelines (SNVA054) • Constructing Your Power Supply- Layout Considerations (SLUP230) • AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419) • Semiconductor and IC Package Thermal Metrics (SPRA953) 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks HotRod, E2E are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 43 LMS3655 SNAS744B – JULY 2017 – REVISED MARCH 2018 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 44 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Product Folder Links: LMS3655 PACKAGE OPTION ADDENDUM www.ti.com 17-Jun-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LMS3655AMRNLR ACTIVE VQFN-HR RNL 22 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 LM3655A LMS3655AMRNLT ACTIVE VQFN-HR RNL 22 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 LM3655A LMS3655MMRNLR ACTIVE VQFN-HR RNL 22 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 LM3655M LMS3655MMRNLT ACTIVE VQFN-HR RNL 22 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 LM3655M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of