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LMV641
SNOSAW3D – SEPTEMBER 2007 – REVISED AUGUST 2016
LMV641 10-MHz, 12-V, Low-Power Amplifier
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
The LMV641 is a low-power, wide-bandwidth
operational amplifier with an extended power supply
voltage range of 2.7 V to 12 V.
1
Specified for 2.7-V, and ±5-V Performance
Low Power Supply Current: 138 µA
High Unity Gain Bandwidth: 10 MHz
Max Input Offset Voltage: 500 µV
CMRR: 120 dB
PSRR: 105 dB
Input Referred Voltage Noise: 14 nV/√Hz
1/f Corner Frequency: 4 Hz
Output Swing With 2-kΩ Load 40 mV from Rail
Total Harmonic Distortion: 0.002% at 1 kHz, 2 kΩ
Temperature Range −40°C to 125°C
2 Applications
•
•
•
Portable Equipment
Battery-Powered Systems
Sensors and Instrumentation
The device features 10 MHz of gain bandwidth
product with unity gain stability on a typical supply
current of 138 µA. Other key specifications are a
PSRR of 105 dB, CMRR of 120 dB, VOS of 500 µV,
input referred voltage noise of 14 nV/√Hz, and a THD
of 0.002%. This amplifier has a rail-to-rail output
stage and a common mode input voltage, which
includes the negative supply.
The LMV641 device operates over a temperature
range of −40°C to +125°C and is offered in the boardspace-saving 5-Pin SC70, SOT-23, and 8-Pin SOIC
packages.
Device Information(1)
PART NUMBER
PACKAGE
LMV641
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
SOT-23 (5)
2.90 mm × 1.60 mm
SC70 (5)
2.00 mm × 1.25 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
20
UNITS TESTED = 12,000
18
+
180
V = +5V
V = -5V
150
PHASE
GAIN (dB)
12
10
8
6
4
2
RL = 10 k: 120
120
TA = 25°C
CL = 20 pF
90
60
GAIN
0
100 200 300 400
OFFSET VOLTAGE (PV)
90
60
30
30
0
0
-30
-30
0
-400 -300 -200 -100
150
-
V = -6V
VCM = 0V
14
180
+
V = +6V
-
16
PERCENTAGE (%)
Open Loop Gain and Phase vs Frequency
-60
100
PHASE (°)
Offset Voltage Distribution
1k
10k
100k
1M
10M
-60
100M
FREQUENCY (Hz)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV641
SNOSAW3D – SEPTEMBER 2007 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
DC Electrical Characteristics: 2.7 V .........................
DC Electrical Characteristics: 10 V ...........................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Applications ................................................ 17
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (February 2013) to Revision D
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Moved Package thermal resistance (RθJA) rows from Recommended Operating Conditions to Thermal Information........... 4
Changes from Revision B (February 2013) to Revision C
•
2
Page
Changed layout of National Semiconductor Data Sheet to TI Format ................................................................................... 1
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SNOSAW3D – SEPTEMBER 2007 – REVISED AUGUST 2016
5 Pin Configuration and Functions
DBV and DCK Packages
5-Pin SOT-23 and SC70
Top View
D Package
8-Pin SOIC
Top View
N/C
VIN-
1
2
VIN+
3
V-
4
8
-
+
7
6
5
N/C
V+
VOUT
N/C
Pin Functions
PIN
NAME
SOT-23
SC70
SOIC
VIN+
3
3
3
VIN-
4
4
VOUT
1
1
V+
5
V–
2
(1)
TYPE (1)
DESCRIPTION
I
Noninverting Input
2
I
Inverting Input
6
O
Output
5
7
P
Positive supply input
2
4
P
Supply negative input
I = input; O = output; P = power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
Differential input VID
+
MIN
MAX
UNIT
±0.3
±0.3
V
13.2
V
(V− −0.3)
V+ +0.3
V
150
°C
150
°C
−
Supply voltage (VS = V - V )
Input and output pin voltage
Junction temperature
(3)
Storage temperature, Tstg
(1)
(2)
(3)
–65
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office / Distributors for availability and
specifications.
The maximum power dissipation is a function of TJ(MAX, RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/ RθJA. All numbers apply for packages soldered directly onto a PC board.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM),
(1)
±2000
Machine model (MM)
±200
UNIT
V
Human Body Model, applicable std. MIL-STD-883, Method 3015.7.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MAX
UNIT
(1)
MIN
–40
125
°C
Supply voltage (VS = V+ – V−)
2.7
12
V
Temperature
(1)
NOM
The maximum power dissipation is a function of TJ(MAX, RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/ RθJA. All numbers apply for packages soldered directly onto a PC board.
6.4 Thermal Information
LMV641
THERMAL METRIC (1)
DBV (SOT-23)
DCK (SC70)
D (SOIC)
5 PINS
5 PINS
8 PINS
UNIT
RθJA (2)
Junction-to-ambient thermal resistance
325
456
166
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
178.1
121.8
93.6
°C/W
RθJB
Junction-to-board thermal resistance
60.8
68.9
90.9
°C/W
ψJT
Junction-to-top characterization parameter
57.7
5.3
38.4
°C/W
ψJB
Junction-to-board characterization parameter
60.2
68.1
90.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The maximum power dissipation is a function of TJ(MAX, RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/ RθJA. All numbers apply for packages soldered directly onto a PC board.
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6.5 DC Electrical Characteristics: 2.7 V
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 2.7 V, V− = 0 V, VO = VCM = V+/2, and RL > 1 MΩ.
PARAMETER
VOS
Input offset voltage
TC VOS
Input offset average drift
IB
Input bias current
IOS
Input offset current
CMRR
PSRR
CMVR
AVOL
Common-mode rejection
ratio
Power supply rejection ratio
Input common-mode
voltage range
Large signal voltage gain
(1)
TA = 25°C
TYP
MAX
30
500
(2)
Temperature extremes
0.1
TA = 25°C
(3)
75
Temperature extremes
TA = 25°C
0 V ≤ VCM ≤ 1.7 V
(3)
89
Temperature extremes
84
(3)
2.7 V ≤ V+ ≤ 10 V, VCM = TA = 25°C
0.5
Temperature extremes
94.5
(3)
2.7 V ≤ V+ ≤ 12 V, VCM = TA = 25°C
0.5
Temperature extremes
94
(3)
CMRR ≥ 80 dB
TA = 25°C
CMRR ≥ 68 dB
Temperature extremes
nA
TA = 25°C
0.4 V ≤ VO ≤ 2.3 V, RL =
10 kΩ to V+/2
Temperature extremes
TA = 25°C
(3)
(3)
RL = 2 kΩ to V+/2, VIN =
100 mV
TA = 25°C
(3)
0
1.8
86
V
88
dB
98
82
42
58
68
22
35
40
38
48
mV from
rail
58
18
RL = 10 kΩ to V /2, VIN =
100 mV
dB
100
Temperature extremes
+
dB
105
Temperature extremes
(3)
= TA = 25°C
Temperature extremes
nA
114
1.8
78
0.3 V ≤ VO ≤ 2.4 V, RL =
10 kΩ to V+/2
5
0
82
Output swing low
95
92
0.4 V ≤ VO ≤ 2.3 V, RL = 2 kΩ to V+/2
RL = 10 kΩ to V /2, VIN
100 mV
µV/°C
92.5
0.3 V ≤ VO ≤ 2.4 V, RL = 2 kΩ to V+/2
+
µV
110
0.9
Output swing high
UNIT
(1)
750
RL = 2 kΩ to V+/2, VIN =
100 mV
VO
MIN
TEST CONDITIONS
30
35
Sourcing
22
Sinking
25
IOUT
Sourcing and sinking output VIN_DIFF = 100 mV to VO
current
= V+/2 (4)
IS
Supply current
SR
Slew rate
GBW
Gain bandwidth product
10
MHz
en
Input-referred voltage noise
f = 1 kHz
14
nV/√Hz
in
Input-referred current noise
f = 1 kHz
0.15
pA/√Hz
THD
Total harmonic distortion
f = 1 kHz, AV = 2, RL = 2 kΩ
(1)
(2)
(3)
(4)
TA = 25°C
(3)
138
Temperature extremes
AV = 1, VO = 1 VPP
mA
170
µA
220
Rising (10% to 90%)
2.3
Falling (90% to 10%)
1.6
V/µs
0.014%
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
Positive current corresponds to current flowing into the device.
The part is not short-circuit protected and is not recommended for operation with low resistive loads. Typical sourcing and sinking output
current curves are provided in Typical Characteristics and should be consulted before designing for heavy loads.
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6.6 DC Electrical Characteristics: 10 V
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 10 V, V− = 0 V,VO = VCM = V+/2, and RL > 1 MΩ.
PARAMETER
VOS
Input offset voltage
TC VOS
Input offset average drift
TA = 25°C
Input bias current
IOS
Input offset current
CMRR
Common-mode rejection
ratio
CMVR
AVOL
Power supply rejection
ratio
Input common-mode
voltage range
Large signal voltage gain
VO
(3)
IOUT
Sourcing and sinking
output current
IS
Supply current
SR
Slew rate
(1)
(2)
(3)
(4)
6
5
500
(1)
750
(3)
70
Temperature
extremes
0.7
94
0 V ≤ VCM ≤ 9 V
Temperature
extremes
90
(3)
94.5
Temperature
extremes
92.5
2.7 V ≤ V+ ≤ 12 V, VCM = 0.5
V
(3)
94
Temperature
extremes
92
TA = 25°C
TA = 25°C
5
105
dB
100
0
9.1
CMRR ≥ 76 dB
Temperature
extremes
0
9.1
(3)
90
Temperature
extremes
85
(3)
97
Temperature
extremes
92
TA = 25°C
TA = 25°C
(3)
37
(3)
65
55
65
Temperature
extremes
90
mV from
rail
110
TA = 25°C (3)
RL = 10 kΩ to V+/2, VIN = 100
Temperature
mV
extremes
32
42
52
Sourcing
26
Sinking
mA
112
(3)
158
Temperature extremes
AV = 1, VO = 2 V to 8 VPP
95
125
TA = 25°C
RL = 10 kΩ to V+/2, VIN = 100
Temperature
mV
extremes
TA = 25°C
dB
104
68
(3)
VIN_DIFF = 100 mV
to VO = V+/2 (4)
V
99
Temperature
extremes
TA = 25°C
nA
dB
(3)
0.3 V ≤ VO ≤ 9.7 V, RL = 10
kΩ to V+/2
0.4 V ≤ VO ≤ 9.6 V, RL = 10
kΩ to V+/2
nA
120
TA = 25°C
TA = 25°C
µV
90
CMRR ≥ 80 dB
0.3 V ≤ VO ≤ 9.7 V, RL = 2
kΩ to V+/2
0.4 V ≤ VO ≤ 9.6 V, RL = 2
kΩ to V+/2
UNIT
µV/°C
105
(3)
TA = 25°C
RL = 2 kΩ to V+/2, VIN = 100
mV
Output Swing Low
MAX
(2)
0.1
RL = 2 kΩ to V+/2, VIN = 100
mV
Output Swing High
TYP
Temperature extremes
2.7 V ≤ V+ ≤ 10 V, VCM = 0.5
V
PSRR
(1)
(3)
TA = 25°C
IB
MIN
TEST CONDITIONS
190
240
Rising (10% to 90%)
2.6
Falling (90% to 10%)
1.6
µA
V/µs
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
Positive current corresponds to current flowing into the device.
The part is not short-circuit protected and is not recommended for operation with low resistive loads. Typical sourcing and sinking output
current curves are provided in Typical Characteristics and should be consulted before designing for heavy loads.
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DC Electrical Characteristics: 10 V (continued)
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 10 V, V− = 0 V,VO = VCM = V+/2, and RL > 1 MΩ.
PARAMETER
GBW
Gain bandwidth product
en
Input-referred voltage
noise
in
THD
TEST CONDITIONS
MIN
(1)
TYP
(2)
MAX
UNIT
(1)
10
MHz
f = 1 kHz
14
nV/√Hz
Input-referred current
noise
f = 1 kHz
0.15
pA/√Hz
Total harmonic distortion
f = 1 kHz, AV = 2, RL = 2 kΩ
0.002%
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6.7 Typical Characteristics
Unless otherwise specified, TA = 25°C, V+ = 10 V, V− = 0 V, VCM = VS/2.
220
40
125°C
20
180
OFFSET VOLTAGE (PV)
SUPPLY CURRENT (PA)
200
160
25°C
140
120
-40°C
100
80
-40°C
0
25°C
-20
-40
125°C
-60
-80
60
40
2
3
4
5
6
7
8
9
-100
10 11 12
2
3
4
5
6
8
9
10 11 12
SUPPLY VOLTAGE (V)
Figure 1. Supply Current vs Supply Voltage
Figure 2. Offset Voltage vs Supply Voltage
50
0
-40°C
-20
-30
-40
25°C
-50
-60
-70
125°C
-80
+
V = +2.7V
-90
-
V = 0V
30
-40°C
20
10
0
25°C
-10
-20
-30
-40
-
V = 0V
-100
-50
0
+
V = +5V
40
OFFSET VOLTAGE (PV)
OFFSET VOLTAGE (PV)
-10
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
125°C
0
0.5
1
1.5
Figure 3. Offset Voltage vs VCM
50
OFFSET VOLTAGE (PV)
OFFSET VOLTAGE (PV)
-40°C
20
10
25°C
-10
-20
-30
125°C
1
2
3
4
5
4
6
7
+
-
V = 0V
-40°C
30
20
10
0
25°C
-10
-20
-30
-40
-50
0
3.5
V = +12V
40
-
V = 0V
-40
3
Figure 4. Offset Voltage vs VCM
+
0
2.5
50
V = +10V
40
30
2
VCM (V)
VCM (V)
8
125°C
-50
9
0
1
2
3
4
5
6
7
8
9 10 11
VCM (V)
VCM (V)
Figure 6. Offset Voltage vs VCM
Figure 5. Offset Voltage vs VCM
8
7
SUPPLY VOLTAGE (V)
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Typical Characteristics (continued)
Unless otherwise specified, TA = 25°C, V+ = 10 V, V− = 0 V, VCM = VS/2.
20
UNITS TESTED = 12,000
18
UNITS TESTED = 12,000
V = -1.35V
PERCENTAGE (%)
TA = 25°C
12
10
8
6
VCM = 0V
14
10
8
6
4
2
2
0
TA = 25°C
12
4
0
-400 -300 -200 -100
-
V = -5V
16
VCM = 0V
14
+
V = +5V
18
-
16
PERCENTAGE (%)
20
+
V = +1.35V
0
-400 -300 -200 -100
100 200 300 400
OFFSET VOLTAGE (PV)
0
100 200 300 400
OFFSET VOLTAGE (PV)
Figure 7. Offset Voltage Distribution
Figure 8. Offset Voltage Distribution
130
160
+PSRR
+
V = 5V
140
V = +5V
110
V = 5V
-
V = -5V
RL = 1 k:
120
80
100
PSRR (dB)
CMRR (dB)
+
-
80
60
-PSRR
70 V+ = +5V
-
V = -5V
-PSRR
50
+
V = +1.35V
-
V = -1.35V
30
40
+PSRR
+
10
20
V = +1.35V
-
V = -1.35V
0
10
100
1k
10k
100k
1M
-10
10
10M
1k
100
Figure 9. CMRR vs Frequency
100
+
-
95
V = 0V
125°C
90
10M
+
V = +10V
-
V = 0V
90
85
125°C
85
80
IBIAS (nA)
IBIAS (nA)
1M
100k
Figure 10. PSRR vs Frequency
100
V = +2.7V
95
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
25°C
75
70
65
-40°C
80
70
65
60
60
55
55
50
0
0.2 0.4 0.6 0.8
1
25°C
75
-40°C
50
1.2 1.4 1.6 1.8
0
1
2
3
4
5
6
7
8
9
VCM (V)
VCM (V)
Figure 11. Input Bias Current vs VCM
Figure 12. Input Bias Current vs VCM
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Typical Characteristics (continued)
Unless otherwise specified, TA = 25°C, V+ = 10 V, V− = 0 V, VCM = VS/2.
180
180
180
180
150
150
150
150
120
120
CL = 100 pF
CL = 50 pF
30
30
0
0
+
V = +1.35V
-
-30 V = -1.35V
RL = 2 k:
-60
100
10k
1k
100k
CL = 100 pF
GAIN
CL = 50 pF
30
0
+
V = +5V
-
-30 V = -5V
RL = 2 k:
-60
100
10k
1k
-60
100M
60
30
0
-30
10M
1M
90
90
60
CL = 100 pF
CL = 50 pF
120
CL = 20 pF
FREQUENCY (Hz)
CL = 100 pF
100k
10M
1M
-60
100M
FREQUENCY (Hz)
Figure 13. Open-Loop Gain and Phase With Capacitive Load
Figure 14. Open-Loop Gain and Phase With Capacitive Load
180
180
180
180
150
150
150
150
120
120
90
90
PHASE
120
+
V = +5V
PHASE
-
V = -5V
60
60
GAIN
RL = 10 k:
30
0
30
0
+
V = +6V
-
GAIN (dB)
90
PHASE (°)
RL = 2 k:
GAIN (dB)
-30
CL = 50 pF
-30 V = -6V
CL = 20 pF
-60
100
10k
1k
60
60
GAIN
30
30
0
+
10M
1M
-30 RL = 2 k:
CL = 20 pF
-60
100
10k
1k
-30
RL = 2 k:
100k
90
0
RL = 10 k:
120
PHASE (°)
GAIN
60
GAIN (dB)
90
90
60
PHASE (°)
GAIN (dB)
CL = 20 pF
PHASE
PHASE (°)
PHASE
120
-60
100M
FREQUENCY (Hz)
V = +1.35V
-30
-
V = -1.35V
100k
10M
1M
-60
100M
FREQUENCY (Hz)
Figure 15. Open-Loop Gain and Phase With Resistive Load
Figure 16. Open-Loop Gain and Phase With Supply Voltage
1000
1000
+
V = +5V
NOISE VOLTAGE
10
1
10
0.1
1
0.10
1
10
100
1k
10k
0.01
10
100k
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Input Referred Noise Voltage vs Frequency
10
AV = +1
100
ZOUT (:)
VOLTAGE NOISE (nV/ Hz)
-
V = -5V
100
Figure 18. Close Loop Output Impedance vs Frequency
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Typical Characteristics (continued)
Unless otherwise specified, TA = 25°C, V+ = 10 V, V− = 0 V, VCM = VS/2.
0.1
0.1
+
V = +5V
-
V = -5V
VIN = 1 VPP
0.01 AV = +2
THD+N (%)
THD+N (%)
RL = 2 k:
0.01
RL = 10 k:
RL = 2 k:
+
0.001
V = +1.35V
RL = 10 k:
-
V = -1.35V
VIN = 1 VPP
AV = +2
0.001
10
100
10k
1k
0.0001
10
100k
100
FREQUENCY (Hz)
1k
10k
100k
FREQUENCY (Hz)
0.1
0.1
THD+N (%)
Figure 20. THD+N vs Frequency
1
THD+N (%)
Figure 19. THD+N vs Frequency
1
RL = 100 k:
RL = 2 k:
0.01 V+ = +1.35V
RL = 2 k:
0.01 V+ = +5V
-
-
V = -1.35V
V = -5V
VIN = 1 kHz SINE WAVE
VIN = 1 kHz SINE WAVE
AV = +2
0.001
0.001
0.01
0.1
1
RL = 10 k:
AV = +2
0.001
0.001
0.01
10
0.1
1
10
VOUT (V)
VOUT (V)
Figure 21. THD+N vs VOUT
Figure 22. THD+N vs VOUT
35
120
+
+
VOUT = V /2
VOUT = V /2
30
100
25°C
80
20
ISINK (mA)
ISOURCE (mA)
25
-40°C
15
40
125°C
10
25°C
20
5
0
-40°C
60
125°C
2
3
4
5
6
7
8
9
0
10 11 12
SUPPLY VOLTAGE (V)
2
3
4
5
6
7
8
9
10
SUPPLY VOLTAGE (V)
Figure 23. Sourcing Current vs Supply Voltage
Figure 24. Sinking Current vs Supply Voltage
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Typical Characteristics (continued)
Unless otherwise specified, TA = 25°C, V+ = 10 V, V− = 0 V, VCM = VS/2.
25
45
+
V = +1.35V
-
V = -1.35V
35
-40°C
30
-40°C
15
10
ISINK (mA)
ISOURCE (mA)
40
V = -1.35V
20
+
V = +1.35V
25°C
-
125°C
25
25°C
20
125°C
15
10
5
5
0
0
0
0.5
1
1.5
2
2.5
1.5
2
2.5
VOUT FROM RAIL (V)
Figure 25. Sourcing Current vs VOUT
35
1
0.5
0
VOUT FROM RAIL (V)
Figure 26. Sinking Current vs VOUT
1.5
+
V = +5V
-
30
V = -5V
1
25°C
0.5
-40°C
20
VOUT (mV)
ISOURCE (mA)
25
15
125°C
+
V = +5V
-
V = -5V
0
CL = 15 pF, AV = +1
VIN = 2 VPP, 20 kHz
-0.5
10
-1
5
0
0
1
2
3
4
5
6
7
8
9
-1.5
10
0
20
VOUT FROM RAIL (V)
+
80
100
Figure 28. Large-Signal Transient
30
CL = 125 pF, AV = +1
25 V = +5V
20 V = -5V
60
TIME (Ps)
Figure 27. Sourcing Current vs VOUT
30
40
+
CL = 15 pF, AV = +1
V = +5V
25
-
VIN = 20 mVPP, 20 kHz
VIN = 20 mVPP, 20 kHz
V = -5V
20
15
15
VOUT (mV)
VOUT (mV)
10
5
0
-5
-10
0
-10
-20
-15
-25
12
5
-5
-15
-30
10
0
20
40
-20
60
70
80
0
20
40
60
80
100
TIME (Ps)
TIME (Ps)
Figure 29. Small-Signal Transient Response
Figure 30. Small-Signal Transient Response
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Typical Characteristics (continued)
Unless otherwise specified, TA = 25°C, V+ = 10 V, V− = 0 V, VCM = VS/2.
100
100
RL = 2 k:
RL = 2 k:
90
125°C
VOUT FROM RAIL (mV)
VOUT FROM RAIL (mV)
90
80
70
25°C
60
50
-40°C
40
80
125°C
70
25°C
60
-40°C
50
40
30
30
2
3
4
5
6
7
8
9
10 11 12
2
3
4
5
6
7
8
9
10 11 12
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 31. Output Swing High vs Supply Voltage
Figure 32. Output Swing Low vs Supply voltage
50
50
RL = 10 k:
RL = 10 k:
45
125°C
VOUT FROM RAIL (mV)
VOUT FROM RAIL (mV)
45
25°C
40
35
30
-40°C
25
20
40
125°C
35
25°C
30
-40°C
25
20
15
15
2
3
4
5
6
7
8
9
10 11 12
2
3
4
5
6
7
8
9
10 11 12
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 33. Output Swing High vs Supply Voltage
Figure 34. Output Swing Low and Supply Voltage
3
RISING
SLEW RATE (V/Ps)
2.5
2
1.5
FALLING
1
0.5
RL = 1 M:
CL = 20 pF
0
2
3
4
5
6
7
8
9
10
SUPPLY VOLTAGE (V)
Figure 35. Slew Rate vs Supply Voltage
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7 Detailed Description
7.1 Overview
The LMV641 is a wide-bandwidth, low-power operational amplifier with an extended power supply voltage range
of 2.7 V to 12 V. The device is unity-gain stable with a 10 MHz of gain bandwidth product. Operating on a typical
supply current of 138 µA, it provides a PSRR of 105 dB, CMRR of 120 dB, VOS of 500 µV, input referred voltage
noise of 14 nV/√Hz, and a THD of 0.002%. This amplifier has a rail-to-rail output stage and a common mode
input voltage which includes the negative supply.
7.2 Functional Block Diagram
V
IN ±
+
±
OUT
IN
+
+
V
±
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7.3 Feature Description
7.3.1 Low-Voltage and Low-Power Operation
The LMV641 has performance guaranteed at supply voltages of 2.7 V and 10 V. It is ensured to be operational
at all supply voltages between 2.7 V and 12 V. The LMV641 draws a low supply current of 138 µA. The LMV641
provides the low-voltage and low-power amplification, which is essential for portable applications.
7.3.2 Wide Bandwidth
Despite drawing the very low supply current of 138 µA, the LMV641 manages to provide a wide unity gain
bandwidth of 10 MHz. This is easily one of the best bandwidth to power ratios ever achieved, and allows this op
amp to provide wideband amplification while using the minimum amount of power. This makes the LMV641 ideal
for low power signal processing applications such as portable media players and other accessories.
7.3.3 Low Input Referred Noise
The LMV641 provides a flatband input referred voltage noise density of 14 nV/Hz, which is significantly better
than the noise performance expected from a low-power op amp. This op amp also feature exceptionally low 1/f
noise, with a very low 1/f noise corner frequency of 4 Hz. Because of this the LMV641 is ideal for low-power
applications which require decent noise performance, such as PDAs and portable sensors.
7.3.4 Ground Sensing and Rail-to-Rail Output
The LMV641 has a rail-to-rail output stage, which provides the maximum possible output dynamic range. This is
especially important for applications requiring a large output swing. The input common mode range of this part
includes the negative supply rail which allows direct sensing at ground in a single supply operation.
7.3.5 Small Size
The small footprint of the packages for the LMV641 saves space on printed-circuit boards, and enables the
design of smaller and more compact electronic products. Long traces between the signal source and the op amp
make the signal path susceptible to noise. By using a physically smaller package, these op amps can be placed
closer to the signal source, reducing noise pickup and enhancing signal integrity.
14
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7.4 Device Functional Modes
7.4.1 Stability of Op Amp Circuits
GAIN
If the phase margin of the LMV641 is plotted with respect to the capacitive load (CL) at its output, and if CL is
increased beyond 100 pF then the phase margin reduces significantly. This is because the op amp is designed
to provide the maximum bandwidth possible for a low supply current. Stabilizing the LMV641 for higher
capacitive loads would have required either a drastic increase in supply current, or a large internal compensation
capacitance, which would have reduced the bandwidth. Hence, if this device is to be used for driving higher
capacitive loads, it will have to be externally compensated.
STABLE
ROC ± 20 dB/decade
UNSTABLE
ROC = 40 dB/decade
0
FREQUENCY (Hz)
Figure 36. Gain vs Frequency for an Op Amp
An op amp, ideally, has a dominant pole close to DC which causes its gain to decay at the rate of 20 dB/decade
with respect to frequency. If this rate of decay, also known as the rate of closure (ROC), remains the same until
the op amp's unity gain bandwidth, then the op amp is stable. If, however, a large capacitance is added to the
output of the op amp, it combines with the output impedance of the op amp to create another pole in its
frequency response before its unity gain frequency (Figure 36). This increases the ROC to 40 dB/decade and
causes instability.
In such a case, a number of techniques can be used to restore stability to the circuit. The idea behind all these
schemes is to modify the frequency response such that it can be restored to an ROC of 20 dB/decade, which
ensures stability.
7.4.1.1 In The Loop Compensation
Figure 37 illustrates a compensation technique, known as in the loop compensation, that employs an RC
feedback circuit within the feedback loop to stabilize a non-inverting amplifier configuration. A small series
resistance, RS, is used to isolate the amplifier output from the load capacitance, CL, and a small capacitance, CF,
is inserted across the feedback resistor to bypass CL at higher frequencies.
VIN
+
ROUT
RS
-
CL
RL
CF
RF
RIN
Figure 37. In the Loop Compensation
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Device Functional Modes (continued)
The values for RS and CF are decided by ensuring that the zero attributed to CF lies at the same frequency as the
pole attributed to CL. This ensures that the effect of the second pole on the transfer function is compensated for
by the presence of the zero, and that the ROC is maintained at 20 dB/ decade. For the circuit shown in Figure 37
the values of RS and CF are given by Equation 1. Values of RS and CF required for maintaining stability for
different values of CL, as well as the phase margins obtained, are shown in Table 1. RF and RIN are 10 kΩ, RL is
2 kΩ, while ROUT is 680Ω.
RS = ROUTRIN
RF
§ RF + 2RIN
CLROUT
CF = ¨¨
2
© RF
§
¨
¨
©
(1)
Table 1. Loop Compensation Stability
CL (nF)
RS (Ω)
CF (pF)
PHASE MARGIN (°)
0.5
680
10
17.4
1
680
20
12.4
1.5
680
30
10.1
The LMV641 is capable of driving heavy capacitive loads of up to 1 nF without oscillating, however it is
recommended to use compensation should the load exceed 1 nF. Using this methodology will reduce any
excessive ringing and help maintain the phase margin for stability. The values of the compensation network
tabulated above illustrate the phase margin degradation as a function of the capacitive load.
Although this methodology provides circuit stability for any load capacitance, it does so at the price of bandwidth.
The closed loop bandwidth of the circuit is now limited by RF and CF.
7.4.1.2 Compensation by External Resistor
In some applications it is essential to drive a capacitive load without sacrificing bandwidth. In such a case, in the
loop compensation is not viable. A simpler scheme for compensation is shown in Figure 38. A resistor, RISO, is
placed in series between the load capacitance and the output. This introduces a zero in the circuit transfer
function, which counteracts the effect of the pole formed by the load capacitance, and ensures stability. The
value of RISO to be used should be decided depending on the size of CL and the level of performance desired.
Values ranging from 5Ω to 50Ω are usually sufficient to ensure stability. A larger value of RISO will result in a
system with less ringing and overshoot, but will also limit the output swing and the short circuit current of the
circuit.
RSO
VOUT
VIN
CL
Figure 38. Compensation by Isolation Resistor
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMV641 is a low-power, low noise, wide-bandwidth operational amplifier with an extended power supply
voltage range of 2.7 V to 12 V. With 10 MHz of gain bandwidth, 14 nV/√Hz input referred noise, and supply
current of 138 μA, the LMV641 is well suited for portable applications that require precision while amplifying at
high gains.
8.2 Typical Applications
8.2.1 High-Gain, Low-Power Inverting Amplifiers
CF
CC1
R1
1 k:
R2
100 k:
+
VIN
-
RB1
V
CC2
+
+
+
-
VOUT
RB2
AV = -
R2
R1
= -100
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Figure 39. High-Gain Inverting Amplifier
8.2.1.1 Design Requirements
The wide unity-gain bandwidth allows these parts to provide large gain over a wide frequency range, while
driving loads as low as 2 kΩ with less than 0.003% distortion.
8.2.1.2 Detailed Design Procedure
Figure 39 is an inverting amplifier, with a 100-kΩ feedback resistor, R2, and a 1-kΩ input resistor, R1, and
provides a gain of −100. With the LMV641, these circuits can provide gain of −100 with a −3-dB bandwidth of
120 kHz, for a quiescent current as low as 116 µA. Coupling capacitors CC1 and CC2 can be added to isolate the
circuit from DC voltages, while RB1 and RB2 provide DC biasing. A feedback capacitor CF can also be added to
improve compensation.
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Typical Applications (continued)
Signal Amplitudee
8.2.1.3 Application Curve
Vout (1V/div)
Vin (10mV/div)
0
50
100
150
200
Time (us)
C001
Figure 40. High Gain Inverting Amplifier Results
8.2.2 Anisotropic Magnetoresistive Sensor
BRIDGE TEMPCO COMPENSATION NETWORK
RA
RB
STANDOFF DISTANCE
x
580:
1%
+
V
24.5 k:
1%
x
-
B
+
V
+
V
RTH
-
U1
LMV641
+
LMV641
+
x
x
FROM mAs TO 20A
G = 23.2
BW-3 dB = 431 kHz
568 k:
1%
I(AC or DC)
HONEYWELL
HMC1051Z
or EQUIVALENT
CONDUCTOR TO BE
CURRENT MEASURED
VOUT
TO ADC or
METER
CIRCUITRY
24.5 k:
1%
x
U2
0.1 PF
+
V
9V
ALKALINE
BATTERY
x
20 k:
5 k:
20 k:
OFFSET TRIM
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Figure 41. A Battery-Operated System for Contact-Less Current Sensing Using an Anisotropic
Magnetoresistive Sensor
8.2.2.1 Design Requirements
The low operating current of the LMV641 makes it a good choice for battery-operated applications. Figure 41
shows two LMV641s in a portable application with a magnetic field sensor. The LMV641s condition the output
from an anisotropic magnetoresistive (AMR) sensor. The sensor is arranged in the form of a Wheatstone bridge.
This type of sensor can be used to accurately measure the current (either DC or AC) flowing in a wire by
measuring the magnetic flux density, B, emanating from the wire.
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Typical Applications (continued)
8.2.2.2 Detailed Design Procedure
In this circuit, the use of a 9-V alkaline battery exploits the LMV641’s high voltage and low supply current for a
low-power, portable-current-sensing application. The sensor converts an incident magnetic field (through the
magnetic flux linkage) in the sensitive direction, to a balanced voltage output. The LMV641 can be used for
moderate to high current sensing applications (from a few milliamps and up to 20 A) using a nearby external
conductor providing the sensed magnetic field to the bridge. The circuit shows a Honeywell HMC1051Z used as
a current sensor. Note that the circuit must be calibrated based on the final displacement of the sensed
conductor relative to the measurement bridge. Typically, once the sensor has been oriented properly, with
respect to the conductor to be measured, the conductor can be placed about one centimeter away from the
bridge and have reasonable capability of measuring from tens of milliamperes to beyond 20 amperes.
In Figure 41, U1 is configured as a single differential input amplifier. Its input impedance is relatively low,
however, and requires that the source impedance of the sensor be considered in the gain calculations. Also, the
asymmetrical loading on the bridge will produce a small offset voltage that can be cancelled out with the offset
trim circuit shown in Figure 41.
Figure 42 shows a typical magnetoresistive Wheatstone bridge and the Thevenin equivalent of its resistive
elements. As we shall see, the Thevenin equivalent model of the sensor is useful in calculating the gain needed
in the differential amplifier.
VEXC
R + 'R
R - 'R
SIG -
SIG +
R + 'R
R - 'R
(a)
R/2
SIG +
+
R/2
SIG -
+
-
WITH 'R
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