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LMX2485, LMX2485E
SNAS236G – OCTOBER 2005 – REVISED JANUARY 2016
LMX2485x 3-GHz Delta-Sigma Low-Power Dual PLLatinum™ Frequency Synthesizer
1 Features
3 Description
•
The LMX2485 device is a low power, high
performance delta-sigma fractional-N PLL with an
auxiliary integer-N PLL. The device is fabricated
using Texas Instruments' advanced process.
1
•
•
•
•
Quadruple Modulus Prescaler for Lower Divides
– RF PLL: 8/9/12/13 or 16/17/20/21
– IF PLL: 8/9 or 16/17
Advanced Delta-Sigma Fractional Compensation
– 12-Bit or 22-Bit Selectable Fractional Modulus
– Up to 4th Order Programmable Delta-Sigma
Modulator
Features for Improved Lock Time
– Fastlock / Cycle Slip Reduction With Integrated
Time-Out Counter Which Requires Only a
Single-Word Write
Wide Operating Range
– LMX2485 RF PLL: 500 MHz to 3.0 GHz
– LMX2485E RF PLL: 50 MHz to 3.0 GHz
Useful Features
– Digital Lock Detect Output
– Hardware and Software Power-Down Control
– On-Chip Input Frequency Doubler.
– RF Phase Detector Frequency up to 50 MHz
– 2.5 to 3.6 V Operation With ICC = 5.0 mA
With delta-sigma architecture, fractional spurs at
lower offset frequencies are pushed to higher
frequencies outside the loop bandwidth. The ability to
push close in spur and phase noise energy to higher
frequencies is a direct function of the modulator
order. Unlike analog compensation, the digital
feedback technique used in the LMX2485 is highly
resistant to changes in temperature and variations in
wafer processing. The LMX2485 delta-sigma
modulator is programmable up to fourth order, which
allows the designer to select the optimum modulator
order to fit the phase noise, spur, and lock time
requirements of the system.
Serial data for programming the LMX2485 is
transferred through a three-line, high-speed (20-MHz)
MICROWIRE interface. The LMX2485 offers fine
frequency resolution, low spurs, fast programming
speed, and a single-word write to change the
frequency. This makes it ideal for direct digital
modulation applications, where the N-counter is
directly modulated with information. The LMX2485 is
available in a 24-lead 4.0 × 4.0 × 0.8 mm WQFN
package.
2 Applications
•
•
•
•
Cellular Phones and Base Stations
Direct Digital Modulation Applications
Satellite and Cable TV Tuners
WLAN Standards
Device Information(1)
PART NUMBER
RF PLL Frequency
IF PLL Frequency
LMX2485E
50 - 3000 MHz
75 - 800 MHz
LMX2485
500 - 3000 MHz
75 - 800 MHz
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
IF N Divider
B Counter
8/9
or
16/17
Prescaler
A Counter
FinIF
ENOSC
OSCin
VddIF1
VddIF2
Phase
Comp
Charge
Pump
CPoutIF
Ftest/LD
MUX
Ftest/LD
Charge
Pump
CPoutRF
IF
LD
IF R
Divider
OSCout
VddRF1
VddRF2
1X / 2X
RF R
Divider
VddRF3
VddRF4
VddRF5
FinRF
FinRF*
RF LD
RF N Divider
C Counter
8/9/12/13
or
B Counter
RF N Divider
16/17/20/21
Prescaler
A Counter
Phase
Comp
CE
CLK
DATA
LE
RF Fastlock
MICROWIRE
Interface
6'
Compensation
FLoutRF
GND
GND
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMX2485, LMX2485E
SNAS236G – OCTOBER 2005 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
7
Parameter Measurement Information ................ 13
8
Detailed Description ............................................ 18
7.1 Bench Test Set-Ups................................................ 13
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8.3
8.4
8.5
8.6
9
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Maps .........................................................
18
23
24
26
Application and Implementation ........................ 37
9.1 Application Information............................................ 37
9.2 Typical Application ................................................. 37
10 Power Supply Recommendations ..................... 39
11 Layout................................................................... 39
11.1 Layout Guidelines ................................................. 39
11.2 Layout Example .................................................... 39
12 Device and Documentation Support ................. 40
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
40
40
40
40
40
13 Mechanical, Packaging, and Orderable
Information ........................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (February 2013) to Revision G
•
Page
Added Pin Configuration and Functions section, Storage Conditions table, ESD Ratings table, Feature Description
section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations
section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section ................................................................................................................................................................ 1
Changes from Revision E (February 2013) to Revision F
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 36
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Product Folder Links: LMX2485 LMX2485E
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SNAS236G – OCTOBER 2005 – REVISED JANUARY 2016
5 Pin Configuration and Functions
VddRF4
FLoutRF
VddRF3
NC
OSCin
ENOSC
RTW Package
24-Pin WQFN
Top View
24
23
22
21
20
19
CPoutRF
1
18 OSCout
GND
2
17 VddIF2
VddRF1
3
16 CPoutIF
Pin 0
(Ground Substrate)
FinRF
4
FinRF*
5
14 VddIF1
LE
6
13 FinIF
8
9
10
11
12
CLK
VddRF2
CE
VddRF5
Ftest/LD
DATA
7
15 GND
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
0
GND
—
Ground substrate; this is on the bottom of the package and must be grounded.
1
CPoutRF
O
RF PLL charge pump output
2
GND
—
RF PLL analog ground
3
VddRF1
—
RF PLL analog power supply
4
FinRF
I
RF PLL high-frequency input pin
5
FinRF*
I
RF PLL complementary high-frequency input pin; shunt to ground with a 100-pF capacitor.
6
LE
I
MICROWIRE load enable; high-impedance CMOS input. Data stored in the shift registers is loaded
into the internal latches when LE goes HIGH.
7
DATA
I
MICROWIRE data; high-impedance binary serial data input.
8
CLK
I
MICROWIRE clock; high-impedance CMOS Clock input. Data for the various counters is clocked into
the 24-bit shift register on the rising edge.
9
VddRF2
—
10
CE
I
Chip Enable control pin; must be pulled high for normal operation.
11
VddRF5
I
Power supply for RF PLL circuitry
12
Ftest/LD
O
Test frequency output / lock detect
IF PLL high-frequency input pin
Power supply for RF PLL digital circuitry
13
FinIF
I
14
VddIF1
—
IF PLL analog power supply
15
GND
—
IF PLL digital ground
16
CPoutIF
O
IF PLL charge pump output
17
VddIF2
—
IF PLL power supply
18
OSCout
O
Buffered output of the OSCin signal
19
ENOSC
I
Oscillator enable; when this is set to high, the OSCout pin is enabled regardless of the state of other
pins or register bits.
20
OSCin
I
Input for TCXO signal
21
NC
I
This pin must be left open.
22
VddRF3
—
Power supply for RF PLL digital circuitry
23
FLoutRF
O
RF PLL fastlock output; also functions as programmable TRI-STATE CMOS output.
24
VddRF4
—
RF PLL analog power supply
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Product Folder Links: LMX2485 LMX2485E
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SNAS236G – OCTOBER 2005 – REVISED JANUARY 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
.
MIN
MAX
UNIT
VCC
Power supply voltage
–0.3
4.25
V
Vi
Voltage on any pin with GND = 0 V
–0.3
VCC + 0.3
V
TL
Lead temperature (Solder 4 sec.)
260
°C
Tstg
Storage temperature
150
°C
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test
conditions listed. The voltage at all the power supply pins of VddRF1, VddRF2, VddRF3, VddRF4, VddRF5, VddIF1 and VddIF2 must be
the same. VCC will be used to refer to the voltage at these pins and ICC will be used to refer to the sum of all currents through all these
power pins.
6.2 ESD Ratings
VALUE
Electrostatic discharge (1)
V(ESD)
(1)
Human-body model (HBM)
±2000
Charged-device model (CDM)
±750
Machine model (MM)
±200
UNIT
V
This is a high performance RF device is ESD-sensitive. Handling and assembly of this device should be done at an ESD free
workstation.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VCC
Power supply voltage (1)
2.5
3
3.6
V
TA
Operating temperature
–40
25
85
°C
(1)
UNIT
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate
conditions for which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications
and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. The voltage at
all the power supply pins of VddRF1, VddRF2, VddRF3, VddRF4, VddRF5, VddIF1 and VddIF2 must be the same. VCC will be used to
refer to the voltage at these pins and ICC will be used to refer to the sum of all currents through all these power pins.
6.4 Thermal Information
THERMAL METRIC
LMX2485,
LMX2485E
(1)
RTW (WQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
47.2
°C/W
43
°C/W
RθJB
ψJT
Junction-to-board thermal resistance
24
°C/W
Junction-to-top characterization parameter
0.8
°C/W
ψJB
Junction-to-board characterization parameter
24
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SNAS236G – OCTOBER 2005 – REVISED JANUARY 2016
6.5 Electrical Characteristics
(VCC = 3.0V; -40°C ≤ TA ≤ +85°C unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC PARAMETERS
ICCRF
Power supply current,
RF synthesizer
IF PLL OFF
RF PLL ON
Charge Pump TRI-STATE
3.3
mA
ICCIF
Power supply current,
IF synthesizer
IF PLL ON
RF PLL OFF
Charge Pump TRI-STATE
1.7
mA
ICCTOTAL
Power supply current, entire
synthesizer
IF PLL ON
RF PLL ON
Charge Pump TRI-STATE
5
mA
ICCPD
Powerdown current
CE = ENOSC = 0 V
CLK, DATA, LE = 0 V
1
10
µA
RF SYNTHESIZER PARAMETERS
LMX2485
fFinRF
Operating
frequency (1)
LMX2485E
Input sensitivity
fCOMP
Phase detector frequency (2)
ICPoutRFSINK
500
2000
RF_P = 16
500
3000
RF_P = 8
50
2000
RF_P = 16
500 - 3000 MHz
pFinRF
ICPoutRFSRCE
RF_P = 8
50 - 500 MHz (LMX2485E only)
RF charge pump source
current (3)
RF charge pump sink current (3)
50
3000
-15
0
-8
8
50
MHz
dBm
MHz
RF_CPG = 0
VCPoutRF = VCC/2
95
µA
RF_CPG = 1
VCPoutRF = VCC/2
190
µA
RF_CPG = 15
VCPoutRF = VCC/2
1520
µA
RF_CPG = 0
VCPoutRF = VCC/2
–95
µA
RF_CPG = 1
VCPoutRF = VCC/2
–190
µA
RF_CPG = 15
VCPoutRF = VCC/2
–1520
µA
ICPoutRFTRI
RF charge pump TRI-STATE
current magnitude
| ICPoutRF%MIS |
Magnitude of RF CP sink vs. CP VCPoutRF = VCC/2
source mismatch
TA = 25°C
| ICPoutRF%V |
Magnitude of RF CP current vs.
CP voltage
| ICPoutRF%T |
Magnitude of RF CP current vs.
temperature
0.5 ≤ VCPoutRF ≤ VCC -0.5
2
10
RF_CPG > 2
3%
10%
RF_CPG ≤ 2
3%
13%
0.5 ≤ VCPoutRF ≤ VCC -0.5
TA = 25°C
2%
8%
VCPoutRF = VCC/2
4%
nA
IF SYNTHESIZER PARAMETERS
fFinIF
Operating frequency
pFinIF
IF input sensitivity
fCOMP
Phase detector frequency
ICPoutIFSRCE
IF charge pump source current
VCPoutIF = VCC/2
3.5
mA
ICPoutIFSINK
IF charge pump sink current
VCPoutIF = VCC/2
–3.5
mA
ICPoutIFTRI
IF charge pump TRI-STATE
current magnitude
0.5 ≤ VCPoutIF ≤ VCC RF -0.5
(1)
(2)
(3)
75
800
MHz
–10
5
dBm
10
MHz
2
10
nA
A slew rate of at least 100 V/uS is recommended for frequencies less than 500 MHz for optimal performance.
For Phase Detector Frequencies greater than 20 MHz, Cycle Slip Reduction (CSR) may be required. Legal divide ratios are also
required.
Refer to table in RF_CPG—RF PLL Charge Pump Gain for complete listing of charge pump currents.
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Electrical Characteristics (continued)
(VCC = 3.0V; -40°C ≤ TA ≤ +85°C unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
| ICPoutIF%MIS |
Magnitude of IF CP sink vs CP
source mismatch
VCPoutIF = VCC/2
TA = 25°C
1%
8%
| ICPoutIF%V |
Magnitude of IF CP current vs
CP voltage
0.5 ≤ VCPoutIF ≤ VCC -0.5
TA = 25°C
4%
10%
| ICPoutIF%TEMP
Magnitude of IF CP current vs
temperature
VCPoutIF = VCC/2
4%
UNIT
OSCILLATOR PARAMETERS
fOSCin
Oscillator operating frequency
vOSCin
Oscillator input sensitivity
IOSCin
Oscillator input current
OSC2X = 0
5
110
MHz
OSC2X = 1
5
20
MHz
0.5
VCC
VP-P
–100
100
µA
SPURS
Spurs in band
See
(4)
–55
dBc
PHASE NOISE
LF1HzRF
LF1HzIF
RF synthesizer normalized
phase noise contribution (5)
RF_CPG = 0
–202
RF_CPG = 1
–202
RF_CPG = 3
–206
RF_CPG = 7
–208
RF_CPG = 15
–210
IF synthesizer normalized phase
noise contribution
dBc/Hz
–209
dBc/Hz
DIGITAL INTERFACE (DATA, CLK, LE, ENOSC, CE, Ftest/LD, FLoutRF)
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
High-level input current
VIH = VCC
IIL
Low-level input current
VIL = 0 V
VOH
High-level output voltage
IOH = –500 µA
VOL
Low-level output voltage
IOL = 500 µA
(4)
(5)
6
1.6
VCC
V
0.4
V
–1
1
µA
–1
1
µA
VCC - 0.4
V
0.4
V
To measure the in-band spur, the fractional word is chosen such that when reduced to lowest terms, the fractional numerator is one.
The spur offset frequency is chosen to be the comparison frequency divided by the reduced fractional denominator. The loop bandwidth
must be sufficiently wide to negate the impact of the loop filter. Measurement conditions are: Spur Offset Frequency = 10 kHz, Loop
Bandwidth = 100 kHz, Fraction = 1/2000, Comparison Frequency = 20 MHz, RF_CPG = 7, DITH = 0, and a 4th Order Modulator (FM =
0). These are relatively consistent over tuning range.
Normalized Phase Noise Contribution is defined as: LN(f) = L(f) – 20log(N) – 10log(fCOMP) where L(f) is defined as the single side band
phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth. The offset frequency, f, must be chosen sufficiently smaller than
the PLL loop bandwidth, yet large enough to avoid substantial phase noise contribution from the reference source. Measurement
conditions are: Offset Frequency = 11 kHz, Loop Bandwidth = 100 kHz for RF_CPG = 7, Fraction = 1/2000, Comparison Frequency =
20 MHz, FM = 0, DITH = 0.
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SNAS236G – OCTOBER 2005 – REVISED JANUARY 2016
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
MICROWIRE INTERFACE TIMING
tCS
Data to clock set-up time
See Figure 1
25
ns
tCH
Data to clock hold time
See Figure 1
8
ns
tCWH
Clock pulse width high
See Figure 1
25
ns
tCWL
Clock pulse width low
See Figure 1
25
ns
tES
Clock to load enable set-up time
See Figure 1
25
ns
tEW
Load enable pulse width
See Figure 1
25
ns
MSB
DATA
LSB
D19
D18
D17
D16
D15
D0
C3
C2
C1
C0
CLK
tCS
tCH
tCWH
tES
tCWL
LE
tEW
Figure 1. Microwire Input Timing Diagram
6.7 Typical Characteristics
Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in the Electrical
Characteristics section.
6.7.1 Sensitivity
20
20
10
10
TA = 25oC, and 85oC
VCC = 2.5V, 3.0V and 3.6V
0
0
pFinRF (dBm)
pFinRF (dBm)
TA = -40oC
-10
-20
VCC = 3.6V
-30
-10
-20
TA = 85oC
-30
TA = -40oC
VCC = 2.5V
VCC = 3.0V
-40
-40
-50
TA = 25oC
-50
0
1000
2000
3000
4000
0
1000
2000
3000
4000
fFinRF (MHz)
fFinRF (MHz)
TA = 25°C, RF_P = 16
Figure 2. RF PLL Fin Sensitivity
VCC = 3 V, RF_P = 16
Figure 3. RF PLL Fin Sensitivity
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Sensitivity (continued)
20
20
10
10
VCC = 3.0V
VCC = 3.6V
0
TA = -40oC, 25oC, and 85oC
0
pFinIF (dBm)
pFinIF (dBm)
VCC = 2.5V
-10
-20
-10
-20
VCC = 3.6V
TA = -40oC
VCC = 3.0V
-30
-30
TA = 85oC
o
-40
-40
TA = 25 C
VCC = 2.5V
-50
-50
400
200
0
800
600
0
1000
200
400
20
1000
20
10
10
VCC = 2.5V, 3.0V, and 3.6V
TA = -40oC, 25oC, and 85oC
0
0
INPUT POWER (dBm)
INPUT POWER (dBm)
800
VCC = 3 V, IF_P = 16
Figure 5. IF PLL Fin Sensitivity
TA = 25°C, IF_P = 16
Figure 4. IF PLL Fin Sensitivity
-10
VCC = 3.6V
-20
VCC = 3.0V
VCC = 2.5V
-30
-10
-20
TA = -40oC
TA = 85oC
-30
-40
-40
-50
0
10
30
60
120
90
TA = 25oC
-50
150
0
10
30
60
fOSCin (MHz)
90
120
150
fOSCin (MHz)
TA = 25°C, OSC_2X = 0
Figure 6. OSCin Sensitivity
VCC = 3 V, OSC_2X = 0
Figure 7. OSCin Sensitivity
20
20
10
10
VCC = 2.5V, 3.0V, and 3.6V
TA = -40oC, 25oC, and 85oC
0
INPUT POWER (dBm)
0
INPUT POWER (dBm)
600
fFinIF (MHz)
fFinIF (MHz)
VCC = 3.6V
-10
VCC = 3.0V
-20
VCC =2.5V
-10
TA = 85oC
-20
TA = -40oC
-30
-30
-40
-40
-50
-50
TA = 25oC
0
5
10
15
20
25
0
10
5
fOSCin (MHz)
TA = 25°C, OSC_2X = 1
Figure 8. OSCin Sensitivity
8
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15
20
25
fOSCin (MHz)
VCC = 3 V, OSC_2X = 1
Figure 9. OSCin Sensitivity
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SNAS236G – OCTOBER 2005 – REVISED JANUARY 2016
6.7.2 FinRF Input Impedance
Marker 1:
50 MHz
Marker 2:
1.0 GHz
Marker 3:
2.0 GHz
2
Marker 4:
3.0 GHz
1
3
Start 1.0 GHz
Stop 3.5 GHz
4
Figure 10. FinRF Input Impedance
Table 1. FinRF Input Impedance
FREQUENCY (MHz)
REAL (Ω)
IMAGINARY (Ω)
50
670
–276
100
531
–247
200
452
–209
300
408
–212
400
373
–222
500
337
–231
600
302
–237
700
270
–239
800
241
–236
900
215
–231
1000
192
–221
1100
172
–218
1200
154
–209
1300
139
–200
1400
127
–192
1500
114
–184
1600
104
–175
1700
96
–168
1800
88
–160
1900
80
–153
2000
74
–147
2200
64
–134
2400
56
–123
2600
50
–113
2800
45
–103
3000
39
–94
3200
37
–86
3400
33
–78
3600
30
–72
3800
28
–69
4000
26
–66
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6.7.3 FinIF Input Impedance
Marker 1:
75 MHz
Marker 2:
800 MHz
2
1
Start 50 MHz
Stop 1000 MHz
Figure 11. FinIF Input Impedance
Table 2. IF PLL Input Impedance
FinIF INPUT IMPEDANCE
10
FREQUENCY (MHZ)
REAL (Ω)
IMAGINARY (Ω)
50
583
–286
75
530
–256
100
499
–241
200
426
–209
300
384
–209
400
347
–219
500
310
–224
600
276
–228
700
244
–228
800
216
–223
900
192
–218
1000
173
–208
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6.7.4 OSCin Input Impedance
MAGNITUDE OF INPUT IMPEDANCE (:)
6000
5000
4000
3000
Powered
Down
2000
1000
Powered
Up
0
0
25
50
75
100
125
150
FREQUENCY (MHz)
Figure 12. OSCin Input Impedance
Table 3. OSCin Input Impedance
POWERED-UP
POWERED-DOWN
FREQUENCY
(MHz)
REAL
IMAGINARY
MAGNITUDE
REAL
IMAGINARY
MAGNITUDE
5
1730
-3779
4157
392
-8137
8146
10
846
-2236
2391
155
-4487
4490
20
466
-1196
1284
107
-2215
2217
30
351
-863
932
166
-1495
-1504
40
316
-672
742
182
-1144
1158
50
278
-566
631
155
-912
925
60
261
-481
547
153
-758
774
70
252
-425
494
154
-652
669
80
239
-388
456
147
-576
595
90
234
-358
428
145
-518
538
100
230
-337
407
140
-471
492
110
225
-321
392
138
-436
458
120
219
-309
379
133
-402
123
130
214
-295
364
133
-374
397
140
208
-285
353
132
-349
373
150
207
-279
348
133
-329
355
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6.7.5 Currents
6.0
0.5
TA = 85oC
5.0
0.4
TA = 25oC
o
TA = -40 C
ICC PD (PA)
ICC TOTAL (mA)
4.0
3.0
0.3
0.2
2.0
TA = 85oC
TA = -40oC
TA = 25oC
0.1
1.0
0
0
2.5
2.75
3.3
3.0
3.6
2.5
2.75
3.0
VCC (V)
3.6
3.3
VCC (V)
CE = High
CE = LOW
Figure 13. Power Supply Current
Figure 14. Power Supply Current
2000
5.0
1500
4.0
RF_CPG = 15
1000
3.0
2.0
RF_CPG = 8
ICPoutIF (mA)
ICPoutRF (PA)
500
0
-500
1.0
0
-1.0
RF_CPG = 0
-2.0
-1000
-3.0
RF_CPG = 1
-4.0
-1500
-5.0
0
0.5
1.0
1.5
2.0
3.0
2.5
-2000
0
0.5
1.0
1.5
2.0
2.5
VCPoutIF (V)
3.0
VCPoutRF (V)
VCC = 3 V
VCC = 3 V
Figure 16. IF PLL Charge Pump Current
Figure 15. RF PLL Charge Pump Current
10
10
8
8
6
6
TA = 85o C
4
o
TA = 85 C
ICPoutIF TRI (nA)
ICPoutRF TRI (nA)
4
2
0
TA = -40o C
-2
0
-2
TA = -40o C
TA = 25o C
-4
2
-4
TA = 25o C
-6
-6
-8
-8
-10
-10
0.5
0
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
2.0
2.5
3.0
VCC = 3 V
VCC = 3 V
Figure 17. Charge Pump Leakage RF PLL
12
1.5
VCPoutIF (V)
VCPoutRF (V)
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Figure 18. Charge Pump Leakage IF PLL
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7 Parameter Measurement Information
7.1 Bench Test Set-Ups
7.1.1 Charge Pump Current Measurement
DC
Blocking
Capacitor
10 MHz
SMA Cable
Frequency
Input Pin
SMA Cable
CPout
Pin
Signal Generator
Semiconductor
Parameter
Analyzer
Device
Under
Test
OSCin
Pin
Evaluation Board
Power Supply
Figure 19. Charge Pump Current Measurement
Figure 19 shows the test procedure for testing the RF and IF charge pumps. These tests include absolute current
level, mismatch, and leakage measurement. To measure the charge pump currents, a signal is applied to the
high frequency input pins. The reason for this is to guarantee that the phase detector gets enough transitions to
be able to change states. If no signal is applied, it is possible that the charge pump current reading will be low
due to the fact that the duty cycle is not 100%. The OSCin Pin is tied to the supply. The charge pump currents
can be measured by simply programming the phase detector to the necessary polarity. For instance, to measure
the RF charge pump, a 10 MHz signal is applied to the FinRF pin. The source current can be measured by
setting the RF PLL phase detector to a positive polarity, and the sink current can be measured by setting the
phase detector to a negative polarity. The IF PLL currents can be measured in a similar way. The magnitude of
the RF PLL charge pump current is controlled by the RF_CPG bit. Once the charge pump currents are known,
the mismatch can be calculated as well. To measure leakage, the charge pump is set to a TRI-STATE mode by
enabling the RF_CPT and IF_CPT bits. Table 4 shows a summary of the various charge pump tests.
Table 4. Programmable Settings for Charge Pump Current Tests
CURRENT TEST
RF_CPG
RF_CPP
RF_CPT
IF_CPP
IF_CPT
RF Source
0 to 15
0
0
X
X
RF Sink
0 to 15
1
0
X
X
RF TRI-STATE
X
X
1
X
X
IF Source
X
X
X
0
0
IF Sink
X
X
X
1
0
IF TRI-STATE
X
X
X
X
1
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7.1.2 Charge Pump Current Specification Definitions
Figure 20. Charge Pump Current Specification Definitions
I1 = Charge Pump Sink Current at VCPout = Vcc - ΔV
I2 = Charge Pump Sink Current at VCPout = Vcc/2
I3 = Charge Pump Sink Current at VCPout = ΔV
I4 = Charge Pump Source Current at VCPout = Vcc - ΔV
I5 = Charge Pump Source Current at VCPout = Vcc/2
I6 = Charge Pump Source Current at VCPout = ΔV
ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this part.
vCPout refers to either VCPoutRF or VCPoutIF
ICPout refers to either ICPoutRF or ICPoutIF
7.1.2.1 Charge Pump Output Current Magnitude Variation vs Charge Pump Output Voltage
Use Equation 1 to calculate the charge pump output current variation versus the charge pump output voltage.
(1)
7.1.2.2 Charge Pump Sink Current vs Charge Pump Output Source Current Mismatch
Use Equation 2 to calculate the charge pump sink current versus the source current mismatch.
(2)
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7.1.2.3 Charge Pump Output Current Magnitude Variation vs Temperature
Use Equation 3 to calculate the charge pump output current magnitude variation versus the temperature.
(3)
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7.1.3 Sensitivity Measurement Procedure
SMA Cable
Signal Generator
Frequency
Input Pin
Matching
Network
DC
Blocking
Capacitor
SMA Cable
Device
Under
Test
Ftest/LD
Pin
Frequency Counter
Evaluation Board
Power Supply
Figure 21. Setup for Sensitivity Measurement
Table 5. Sensitivity Set-Up Diagram
DC-BLOCKING
CAPACITOR
CORRESPONDING
COUNTER
OSCin
1000 pF
FinRF
100 pF// 1000 pF
FinIF
OSCin
FREQUENCY INPUT PIN
DEFAULT COUNTER
VALUE
MUX VALUE
RF_R / 2
50
14
RF_N / 2
502 + 2097150 / 4194301
15
100 pF
IF_N / 2
534
13
1000 pF
IF_R / 2
50
12
Sensitivity is defined as the power level limits beyond which the output of the counter being tested is off by 1 Hz
or more of its expected value. It is typically measured over frequency, voltage, and temperature. To test
sensitivity, the MUX[3:0] word is programmed to the appropriate value. The counter value is then programmed to
a fixed value and a frequency counter is set to monitor the frequency of this pin. The expected frequency at the
Ftest/LD pin should be the signal generator frequency divided by twice the corresponding counter value. The
factor of two comes in because the LMX2485 has a flip-flop which divides this frequency by two to make the duty
cycle 50% to make it easier to read with the frequency counter. The frequency counter input impedance should
be set to high impedance. To perform the measurement, the temperature, frequency, and voltage is set to a fixed
value and the power level of the signal is varied. If the power level at the part is assumed to be 4 dB less than
the signal generator power level. This accounts for 1 dB for cable losses and 3 dB for the pad. The power level
range where the frequency is correct at the Ftest/LD pin to within 1 Hz accuracy is recorded for the sensitivity
limits. The temperature, frequency, and voltage can be varied to produce a family of sensitivity curves. Because
this is an open-loop test, the charge pump is set to TRI-STATE and the unused side of the PLL (RF or IF) is
powered down when not being tested. For this part, there are actually four frequency input pins, although there is
only one frequency test pin (Ftest/LD). The conditions specific to each pin are shown in Table 5.
NOTE
For the RF N counter, a fourth order fractional modulator is used in 22-bit mode with a
fraction of 2097150 / 4194301 is used. The reason for this long fraction is to test the RF N
counter and supporting fractional circuitry as completely as possible.
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7.1.4 Input Impedance Measurement
Frequency
Input Pin
Network Analyzer
Device
Under
Test
Evaluation Board
Power Supply
Figure 22. Input Impedance Measurement
Figure 22 shows the test set-up used for measuring the input impedance for the LMX2485. The DC-blocking
capacitor used between the input SMA connector and the pin being measured must be changed to a 0-Ω
resistor. This procedure applies to the FinRF, FinIF, and OSCin pins. The basic test procedure is to calibrate the
network analyzer, ensure that the part is powered up, and then measure the input impedance. The network
analyzer can be calibrated by using either calibration standards or by soldering resistors directly to the evaluation
board. An open can be implemented by putting no resistor, a short can be implemented by soldering a 0-Ω
resistor as close as possible to the pin being measured, and a short can be implemented by soldering two 100-Ω
resistors in parallel as close as possible to the pin being measured. Calibration is done with the PLL removed
from the PCB. This requires the use of a clamp down fixture that may not always be generally available. If no
clamp down fixture is available, then this procedure can be done by calibrating up to the point where the DCblocking capacitor usually is, and then implementing port extensions with the network analyzer. The 0-Ω resistor
is added back for the actual measurement. Once the set-up is calibrated, it is necessary to ensure that the PLL is
powered up. This can be done by toggling the power down bits (RF_PD and IF_PD) and observing that the
current consumption indeed increases when the bit is disabled. Sometimes it may be necessary to apply a signal
to the OSCin pin to program the part. If this is necessary, disconnect the signal once it is established that the
part is powered up. It is useful to know the input impedance of the PLL for the purposes of debugging RF
problems and designing matching networks. Another use of knowing this parameter is make the trace width on
the PCB such that the input impedance of this trace matches the real part of the input impedance of the PLL
frequency of operation. In general, it is good practice to keep trace lengths short and make designs that are
relatively resistant to variations in the input impedance of the PLL.
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8 Detailed Description
8.1 Overview
The LMX2485 consists of integrated N counters, R counters, and charge pumps. The TCXO, VCO and loop filter
are supplied external to the chip.
8.2 Functional Block Diagram
IF N Divider
B Counter
8/9
or
16/17
Prescaler
A Counter
FinIF
ENOSC
OSCin
VddIF1
VddIF2
Phase
Comp
Charge
Pump
CPoutIF
Ftest/LD
MUX
Ftest/LD
Charge
Pump
CPoutRF
IF
LD
IF R
Divider
OSCout
VddRF1
VddRF2
RF R
Divider
1X / 2X
VddRF3
RF LD
VddRF4
VddRF5
RF N Divider
C Counter
8/9/12/13
or
B
Counter
RF
N
Divider
16/17/20/21
Prescaler
A Counter
FinRF
FinRF*
Phase
Comp
CE
CLK
DATA
LE
RF Fastlock
MICROWIRE
Interface
6'
Compensation
FLoutRF
GND
GND
GND
8.3 Feature Description
8.3.1 TCXO, Oscillator Buffer, and R Counter
The oscillator buffer must be driven single-ended by a signal source, such as a TCXO. The OSCout pin is
included to provide a buffered output of this input signal and is active when the OSC_OUT bit is set to one. The
ENOSC pin can be also pulled high to ensure that the OSCout pin is active, regardless of the status of the
registers in the LMX2485.
The R counter divides this TXCO frequency down to the comparison frequency.
8.3.2 Phase Detector
The maximum phase detector operating frequency for the IF PLL is straightforward, but it is a little more involved
for the RF PLL because it is fractional. The maximum phase detector frequency for the LMX2485 RF PLL is 50
MHz. However, this is not possible in all circumstances due to illegal divide ratios of the N counter. The crystal
reference frequency also limits the phase detector frequency, although the doubler helps with this limitation.
There are trade-offs in choosing the phase detector frequency. If this frequency is run higher, then phase noise
will be lower, but lock time may be increased due to cycle slipping and the capacitors in the loop filter may
become rather large.
8.3.3 Charge Pump
For the majority of the time, the charge pump output is high impedance, and the only current through this pin is
the Tri-State leakage. However, it does put out fast correction pulses that have a width that is proportional to the
phase error presented at the phase detector.
The charge pump converts the phase error presented at the phase detector into a correction current. The
magnitude of this current is theoretically constant, but the duty cycle is proportional to the phase error. For the IF
PLL, this current is not programmable, but for the RF PLL it is programmable in 16 steps. Also, the RF PLL
allows for a higher charge pump current to be used when the PLL is locking to reduce the lock time.
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Feature Description (continued)
8.3.4 Loop Filter
The loop filter design can be rather involved. In addition to the regular constraints and design parameters, deltasigma PLLs have the additional constraint that the order of the loop filter should be one greater than the order of
the delta sigma modulator. This rule of thumb comes from the requirement that the loop filter must roll off the
delta sigma noise at 20 dB/decade faster than it rises. However, because the noise can not have infinite power, it
must eventually roll off. If the loop bandwidth is narrow, this requirement may not be necessary. For the purposes
of discussion in this data sheet, the pole of the loop filter at 0 Hz is not counted. So a second order filter has 3
components, a 3rd order loop filter has 5 components, and the 4th order loop filter has 7 components. Although a
5th order loop filter is theoretically necessary for use with a 4th order modulator, typically a 4th order filter is used
in this case. The loop filter design, especially for higher orders can be rather involved, but there are many
simulation tools and references available, such as the one given at the end of the functional description block.
8.3.5 N Counters and High Frequency Input Pins
The N counter divides the VCO frequency down to the comparison frequency. Because prescalers are used,
there are limitations on how small the N value can be. The N counters are discussed in greater depth in the
programming section. Because the input pins to these counters (FinRF and FinIF) are high frequency, layout
considerations are important.
8.3.5.1 High Frequency Input Pins, FinRF and FinIF
TI recommends that the VCO output go through a resistive pad and then through a DC-blocking capacitor before
it gets to these high frequency input pins. If the trace length is sufficiently short (< 1/10th of a wavelength), then
the pad may not be necessary, but a series resistor of about 39 Ω is still recommended to isolate the PLL from
the VCO. The DC-blocking capacitor should be chosen at least to be 27 pF, depending on frequency. It may turn
out that the frequency is above the self-resonant frequency of the capacitor, but because the input impedance of
the PLL tends to be capacitive, it actually is a benefit to exceed the tune frequency. The pad and the DCblocking capacitor should be placed as close to the PLL as possible
8.3.5.2 Complementary High Frequency Pin, FinRF*
These inputs may be used to drive the PLL differentially, but it is very common to drive the PLL in a single ended
fashion. A shunt capacitor should be placed at the FinRF* pin. The value of this capacitor should be chosen such
that the impedance, including the ESR of the capacitor, is as close to an AC short as possible at the operating
frequency of the PLL. 100 pF is a typical value, depending on frequency.
8.3.6 Digital Lock Detect Operation
The RF PLL digital lock detect circuitry compares the difference between the phase of the inputs of the phase
detector to a RC generated delay of ε. To indicate a locked state (Lock = HIGH) the phase error must be less
than the ε RC delay for 5 consecutive reference cycles. Once in lock (Lock = HIGH), the RC delay is changed to
approximately δ. To indicate an out of lock state (Lock = LOW), the phase error must become greater δ. The
values of ε and δ are dependent on which PLL is used and are shown in Table 6:
Table 6. Digital Lock Detection Tolerances
PLL
ε
δ
RF
10 ns
20 ns
IF
15 ns
30 ns
When the PLL is in the power-down mode and the Ftest/LD pin is programmed for the lock detect function, it is
forced LOW. The accuracy of this circuit degrades at higher comparison frequencies. To compensate for this, the
DIV4 word should be set to one if the comparison frequency exceeds 20 MHz. The function of this word is to
divide the comparison frequency presented to the lock detect circuit by 4. If the MUX[3:0] word is set such as to
view lock detect for both PLLs, an unlocked (LOW) condition is shown whenever either one of the PLLs is
determined to be out of lock.
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START
LD = LOW
(Not Locked)
NO
Phase Error < H
YES
NO
Phase Error < H
YES
NO
Phase Error < H
YES
NO
Phase Error < H
YES
NO
Phase Error < H
YES
LD = HIGH
(Locked)
YES
NO
Phase Error > G
8.3.7 Cycle Slip Reduction and Fastlock
The LMX2485 offers both cycle slip reduction (CSR) and Fastlock with time-out counter support. This means that
it requires no additional programming overhead to use them. TI recommends that the charge pump current in the
steady-state be 8X or less to use cycle slip reduction, and 4X or less in steady-state to use Fastlock. The next
step is to decide between using Fastlock or CSR. This determination can be made based on the ratio of the
comparison frequency (fCOMP) to loop bandwidth (BW).
Table 7. Using Cycle Slip Reduction and Fastlock
COMPARISON FREQUENCY
(fCOMP)
fCOMP ≤ 1.25 MHz
Noticeable better than CSR
1.25 MHz < fCOMP ≤ 2 MHz
Marginally better than CSR
fCOMP > 2 MHz
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CYCLE SLIP REDUCTION
(CSR)
FASTLOCK
Likely to provide a benefit, provided that
fCOMP > 100 X BW
Same or worse than CSR
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8.3.7.1 Cycle Slip Reduction (CSR)
Cycle slip reduction works by reducing the comparison frequency during frequency acquisition while keeping the
same loop bandwidth, thereby reducing the ratio of the comparison frequency to the loop bandwidth. In cases
where the ratio of the comparison frequency exceeds about 100 times the loop bandwidth, cycle slipping can
occur and significantly degrade lock times. The greater this ratio, the greater the benefit of CSR. This is typically
the case of high comparison frequencies. In circumstances where there is not a problem with cycle slipping, CSR
provides no benefit. There is a glitch when CSR is disengaged, but because CSR should be disengaged long
before the PLL is actually in lock, this glitch is not an issue. A good rule of thumb for CSR disengagement is to
do this at the peak time of the transient response. Because this time is typically much sooner than Fastlock
should be disengaged, it does not make sense to use CSR and Fastlock in combination.
8.3.7.2 Fastlock
Fastlock works by increasing the loop bandwidth only during frequency acquisition. In circumstances where the
comparison frequency is less than or equal to 2 MHz, Fastlock may provide a benefit beyond what CSR can
offer. Because Fastlock also reduces the ratio of the comparison frequency to the loop bandwidth, it may provide
a significant benefit in cases where the comparison frequency is greater than 2 MHz. However, CSR can usually
provide an equal or larger benefit in these cases, and can be implemented without using an additional resistor.
The reason for this restriction on frequency is that Fastlock has a glitch when it is disengaged. As the time of
engagement for Fastlock decreases and becomes on the order of the fast lock time, this glitch grows and limits
the benefits of Fastlock. This effect becomes worse at higher comparison frequencies. There is always the option
of reducing the comparison frequency at the expense of phase noise to satisfy this constraint on comparison
frequency. Despite this glitch, there is still a net improvement in lock time using Fastlock in these circumstances.
When using Fastlock, TI also recommends that the steady-state charge pump state be 4X or less. Also, Fastlock
was originally intended only for second order filters, so when implementing it with higher order filters, the third
and fourth poles can not be too close in, or it will not be possible to keep the loop filter well optimized when the
higher charge pump current and Fastlock resistor are engaged.
8.3.7.3 Using Cycle Slip Reduction (CSR) to Avoid Cycle Slipping
Once it is decided that CSR is to be used, the cycle slip reduction factor needs to be chosen. The available
factors are 1/2, 1/4, and 1/16. To preserve the same loop characteristics, TI recommends that the following
constraint be satisfied:
8.3.7.3.1 (Fastlock Charge Pump Current) / (Steady-State Charge Pump Current) = CSR
To satisfy this constraint, the maximum charge pump current in steady-state is 8X for a CSR of 1/2, 4X for a
CSR of 1/4, and 1X for a CSR of 1/16. Because the PLL phase noise is better for higher charge pump currents, it
makes sense to choose CSR only as large as necessary to prevent cycle slipping. Choosing it larger than this
will not improve lock time, and will result in worse phase noise.
Consider an example where the desired loop bandwidth in steady-state is 100 kHz and the comparison
frequency is 20 MHz. This yields a ratio of 200. Cycle slipping may be present, but would not be too severe if it
was there. If a CSR factor of 1/2 is used, this would reduce the ratio to 100 during frequency acquisition, which is
probably sufficient. A charge pump current of 8X could be used in steady-state, and a factor of 16X could be
used during frequency acquisition. This yields a ratio of 1/2, which is equal to the CSR factor and this satisfies
the above constraint. In this circumstance, it could also be decided to just use 16X charge pump current all the
time, because it would probably have better phase noise, and the degradation in lock time would not be too
severe.
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8.3.7.4 Using Fastlock to Improve Lock Times
Figure 23. Loop Filter with Fastlock Resistor
Once it is decided that Fastlock is to be used, the loop bandwidth multiplier, K, is needed to determine the
theoretical impact of Fastlock on the loop bandwidth and the resistor value, R2p, that is switched in parallel
during Fastlock. This ratio is calculated as follows:
Table 8. K = (Fastlock Charge Pump Current) / (Steady-State Charge Pump Current)
K
LOOP BANDWIDTH
R2p VALUE
LOCK TIME
1
1.00 X
Open
100%
2
1.41 X
R2/0.41
71%
3
1.73 X
R2/0.73
58%
4
2.00 X
R2
50%
8
2.83 X
R2/1.83
35%
9
3.00 X
R2/2
33%
16
4.00 X
R2/3
25%
Table 8 shows how to calculate the Fastlock resistor and theoretical lock time improvement, once the ratio , K, is
known. This all assumes a second order filter (not counting the pole at 0 Hz). However, TI generally
recommends that the loop filter order be one greater than the order of the delta sigma modulator, which means
that a second order filter is never recommended. In this case, the value for R2p is typically about 80% of what it
would be for a second order filter. Because the Fastlock disengagement glitch gets larger and it is harder to keep
the loop filter optimized as the K value becomes larger, designing for the largest possible value for K usually, but
not always yields the best improvement in lock time. To get a more accurate estimate requires more simulation
tools, or trial and error.
8.3.7.5 Capacitor Dielectric Considerations for Lock Time
The LMX2485 has a high fractional modulus and high charge pump gain for the lowest possible phase noise.
One consideration is that the reduced N value and higher charge pump may cause the capacitors in the loop
filter to become larger in value. For larger capacitor values, it is common to have a trade-off between capacitor
dielectric quality and physical size. Using film capacitors or NPO/COG capacitors yields the best possible lock
times, where as using X7R or Z5R capacitors can increase lock time by 0 – 500%. However, it is a general
tendency that designs that use a higher compare frequency tend to be less sensitive to the effects of capacitor
dielectrics. Although the use of lesser quality dielectric capacitors may be unavoidable in many circumstances,
allowing a larger footprint for the loop filter capacitors, using a lower charge pump current, and reducing the
fractional modulus are all ways to reduce capacitor values. Capacitor dielectrics have very little impact on phase
noise and spurs.
8.3.8 Fractional Spur and Phase Noise Controls
Control of the fractional spurs is more of an art than an exact science. The first differentiation that needs to be
made is between primary fractional and sub-fractional spurs. The primary fractional spurs are those that occur at
increments of the channel spacing only. The sub-fractional spurs are those that occur at a smaller resolution than
the channel spacing, usually one-half or one-fourth. There are trade-offs between fractional spurs, sub-fractional
spurs, and phase noise. The rules of thumb presented in this section are just that. There will be exceptions. The
bits that impact the fractional spurs are FM and DITH, and these bits should be set in this order.
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The first step to do is choose FM, for the delta sigma modulator order. TI recommends to start with FM = 3 for a
third order modulator and use strong dithering. In general, there is a trade-off between primary and sub-fractional
spurs. Choosing the highest order modulator (FM = 0 for 4th order) typically provides the best primary fractional
spurs, but the worst sub-fractional spurs. Choosing the lowest modulator order (FM = 2 for 2nd order), typically
gives the worst primary fractional spurs, but the best sub-fractional spurs. Choosing FM = 3, for a 3rd order
modulator is a compromise.
The second step is to choose DITH, for dithering. Dithering has a very small impact on primary fractional spurs,
but a much larger impact on sub-fractional spurs. The only problem is that it can add a few dB of phase noise, or
even more if the loop bandwidth is very wide. Disabling dithering (DITH = 0), provides the best phase noise, but
the sub-fractional spurs are worst (except when the fractional numerator is 0, and in this case, they are the best).
Choosing strong dithering (DITH = 2) significantly reduces sub-fractional spurs, if not eliminating them
completely, but adds the most phase noise. Weak dithering (DITH = 1) is a compromise.
The third step is to tinker with the fractional word. Although 1/10 and 400/4000 are mathematically the same,
expressing fractions with much larger fractional numerators often improve the fractional spurs. Increasing the
fractional denominator only improves spurs to a point. A good practical limit could be to keep the fractional
denominator as large as possible, but not to exceed 4095, so it is not necessary to use the extended fractional
numerator or denominator.
This steps can be done in different orders and it might take a few iterations to find the optimum performance.
Special considerations should be taken for lower frequencies that are less than 100 MHz. In addition squaring up
the wave, it is often helpful to use lowest terms fractions instead of highest terms fractions. Also, dithering may
turn out to not be so useful. All the things are to introduce a methodical way of thinking about optimizing spurs,
not an exact method. There will be exceptions to all these rules.
NOTE
For more information concerning delta-sigma PLLs, loop filter design, cycle slip reduction,
Fastlock, and many other topics, visit www.ti.com. Here there is the EasyPLL simulation
tool and an online reference called PLL Performance, Simulation, and Design.
8.4 Device Functional Modes
8.4.1 Power Pins, Power-Down, and Power-Up Modes
TI recommends that all of the power pins be filtered with a series 18-Ω resistor and then placing two capacitors
shunt to ground, thus creating a low pass filter. Although it makes sense to use large capacitor values in theory,
the ESR (Equivalent Series Resistance) is greater for larger capacitors. For optimal filtering minimize the sum of
the ESR and theoretical impedance of the capacitor. Therefore TI recommends to provide two capacitors of very
different sizes for the best filtering. 1 µF and 100 pF are typical values. The small capacitor should be placed as
close as possible to the pin.
The power down state of the LMX2485 is controlled by many factors. The one factor that overrides all other
factors is the CE pin. If this pin is low, the part will be powered down. Asserting a high logic level on this pin is
necessary to power up the chip, however, there are other bits in the programming registers that can override this
and put the PLL back in a power-down state. Provided that the voltage on the CE pin is high, programming the
RF_PD and IF_PD bits to zero ensures that the part will be powered up. Programming either one of these bits to
one will power down the appropriate section of the synthesizer, provided that the ATPU bit does not override this.
Table 9. Power-Up and Down States
CE PIN
RF_PD
ATPU Bit Enabled + N Counter Write
PLL STATE
Low
X
X
Powered Down
(Asynchronous)
High
X
Yes
Powered Up
High
0
No
Powered Up
No
Powered Down
(Asynchronous)
High
1
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8.5 Programming
8.5.1 General Programming Information
The 24-bit data registers are loaded through a MICROWIRE Interface. These data registers are used to program
the R counter, the N counter, and the internal mode control latches. The data format of a typical 24-bit data
register is shown in Table 10. The control bits CTL [3:0] decode the register address. On the rising edge of LE,
data stored in the shift register is loaded into one of the appropriate latches (selected by address bits). Data is
shifted in MSB first.
NOTE
It is best to program the N counter last, because doing so initializes the digital lock
detector and Fastlock circuitry. Initialize means it resets the counters, but it does NOT
program values into these registers. The exception is when 22-bit is not being used. In this
case, it is not necessary to program the R7 register.
Table 10. Register Structure
MSB
LSB
DATA [21:0]
CTL [3:0]
23
4 3
2
1
0
8.5.1.1 Register Location Truth Table
The control bits CTL [3:0] decode the internal register address. Table 11 shows how the control bits are mapped
to the target control register.
Table 11. Programmable Registers
C3
C2
C1
C0
DATA LOCATION
x
x
x
0
R0
0
0
1
1
R1
0
1
0
1
R2
0
1
1
1
R3
1
0
0
1
R4
1
0
1
1
R5
1
1
0
1
R6
1
1
1
1
R7
8.5.1.2 Control Register Content Map
Because the LMX2485 registers are complicated, they are organized into two groups, basic and advanced. The
first four registers are basic registers that contain critical information necessary for the PLL to achieve lock. The
last 5 registers are for features that optimize spur, phase noise, and lock time performance. The next page
shows these registers.
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8.5.1.3 Quick Start Register Map
Although TI highly recommends that the user eventually take advantage of all the modes of the LMX2485, the
quick start register map is shown in order for the user to get the part up and running quickly using only those bits
critical for basic functionality. The following default conditions for this programming state are a third order deltasigma modulator in 12-bit mode with no dithering and no Fastlock.
Table 12. Quick Start Register Map
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
DATA[19:0] (Except for the RF_N Register, which is [22:0])
R0
RF_N[10:0]
R1
RF_PD
R2
IF_PD
RF_P
0001
R4
0
1
0
0
1
0
C1
C0
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
0
RF_FD[11:0]
RF_CPG[3:0]
0
2
C2
RF_FN[11:0]
RF_R[5:0]
IF_N[18:0]
R3
3
C3
0
0
IF_R[11:0]
0
1
1
0
0
0
1
1
1
0
0
0
0
8.5.1.4 Complete Register Map
The complete register map shows all the functionality of all registers, including the last five.
Table 13. Complete Register Map
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
DATA[19:0] (Except for the RF_N Register, which is [22:0])
R0
RF_N[10:0]
R1
RF_PD
R2
IF_PD
R3
R4
RF_P
0
1
R5
R6
R7
RF_CPG[3:0]
0
0
0
IF_R[11:0]
DITH
[1:0]
FM
[1:0]
0
OSC
_2X
OSC
_OUT
IF_
CPP
RF_FD[21:12]
CSR[1:0]
0
0
0
0
RF_
CPP
IF_P
MUX [3:0]
RF_FN[21:12]
RF_CPF[3:0]
0
RF_TOC[13:0]
0
1
0
C1
C0
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
0
RF_FD[11:0]
IF_N[18:0]
ATPU
2
C2
RF_FN[11:0]
RF_R[5:0]
ACCESS[3:0]
3
C3
0
0
0
0
DIV4
0
1
0
0
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1
IF_
RST
RF_
RST
IF_
CPT
RF_
CPT
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8.6 Register Maps
8.6.1 R0 Register
NOTE
This register has only one control bit, so the N counter value to be changed with a single
write statement to the PLL.
Table 14. R0 Register
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA[22:0]
R0
C0
RF_N[10:0]
RF_FN[11:0]
0
8.6.1.1 RF_FN[11:0]—Fractional Numerator for RF PLL
Refer to Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], Access[1] } for a more detailed
description of this control word.
8.6.1.2 RF_N[10:0]—RF N Counter Value
The RF N counter contains an 8/9/12/13 and a 16/17/20/21 prescaler. The N counter value can be calculated as
follows:
N = RF_P·RF_C + 4·RF_B + RF_A
RF_C ≥Max{RF_A, RF_B} , for N-2FM-1 ... N+2FM is a necessary condition. This rule is slightly modified in the
case where the RF_B counter has an unused bit, where this extra bit is used by the delta-sigma modulator for
the purposes of modulation. Consult the tables below for valid operating ranges for each prescaler.
Table 15. Operation With the 8/9/12/13 Prescaler (RF_P=0)
RF_N [10:0]
RF_N
RF_C [6:0]
1023
N values greater than 1023 are prohibited.
Table 16. Operation With the 16/17/20/21 Prescaler (RF_P=1)
RF_N [10:0]
RF_N
RF_C [6:0]
N values less than 49 are prohibited.
49-50
Possible only with a second order delta-sigma engine.
51-54
26
RF_B [1:0]
2045
N values greater than 2045 are prohibited.
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8.6.2 R1 Register
Table 17. R1 Register
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
DATA[19:0]
R1
RF_PD
RF_P
RF_R[5:0]
3
2
1
0
C3
C2
C1
C0
0
0
1
1
RF_FD[11:0]
8.6.2.1 RF_FD[11:0]—RF PLL Fractional Denominator
The function of these bits are described in Fractional Denominator Determination { RF_FD[21:12], RF_FD[11:0],
Access[1]}.
8.6.2.2 RF_R [5:0]—RF R Divider Value
The RF R Counter value is determined by this control word.
NOTE
This counter does allow values down to one.
Table 18. RF_R [5:0]—RF R Divider Value
R VALUE
RF_R[5:0]
1
0
0
0
0
0
...
.
.
.
.
.
1
.
63
1
1
1
1
1
1
8.6.2.3 RF_P—RF Prescaler Bit
The prescaler used is determined by this bit.
Table 19. RF_P—RF Prescaler Bit
RF_P
PRESCALER
MAXIMUM FREQUENCY
0
8/9/12/13
2000 MHz
1
16/17/20/21
3000 MHz
8.6.2.4 RF_PD—RF Power-Down Control Bit
When this bit is set to 0, the RF PLL operates normally. When it is set to one, the RF PLL is powered down and
the RF Charge pump is set to a TRI-STATE mode. The CE pin and ATPU bit also control power down functions,
and will override the RF_PD bit. The order of precedence is as follows. First, if the CE pin is LOW, then the PLL
will be powered down. Provided this is not the case, the PLL will be powered up if the ATPU bit says to do so,
regardless of the state of the RF_PD bit. After the CE pin and the ATPU bit are considered, then the RF_PD bit
then takes control of the power-down function for the RF PLL.
8.6.3 R2 Register
Table 20. R2 Register
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
DATA[19:0]
R2
IF_PD
IF_N[18:0]
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8
7
6
5
4
3
2
1
0
C3
C2
C1
C0
0
1
0
1
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8.6.3.1 IF_N[18:0]—IF N Divider Value
Table 21. IF_N Counter Programming With the 8/9 Prescaler (IF_P=0)
IF_N[18:0]
N VALUE
IF_B
IF_A
≤23
N values less than or equal to 23 are prohibited because IF_B ≥ 3 is required.
24-55
Legal divide ratios in this range are:
24-27, 32-36, 40-45, 48-54
56
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
57
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
...
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
262143
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
Table 22. Operation With the 16/17 Prescaler (IF_P=1)
N VALUE
IF_B
IF_A
≤47
N values less than or equal to 47 are prohibited because IF_B ≥ 3 is required.
48-239
Legal divide ratios in this range are:
48-51, 64-68, 80-85, 96-102, 112-119, 128-136, 144-153, 160-170, 176-187, 192-204, 208-221, 224-238
240
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
241
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
...
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
524287
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8.6.3.2 IF_PD—IF Power Down Bit
When this bit is set to 0, the IF PLL operates normally. When it is set to 1, the IF PLL powers down and the
output of the IF PLL charge pump is set to a TRI-STATE mode. If the ATPU bit is set and register R0 is written
to, the IF_PD will be reset to 0 and the IF PLL will be powered up. If the CE pin is held low, the IF PLL will be
powered down, overriding the IF_PD bit.
8.6.4 R3 Register
Table 23. R3 Register
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
DATA[19:0]
R3
ACCESS[3:0]
RF_CPG[3:0]
IF_R[11:0]
3
2
1
0
C3
C2
C1
C0
0
1
1
1
8.6.4.1 IF_R[11:0]—IF R Divider Value
For the IF R divider, the R value is determined by the IF_R[11:0] bits in the R3 register. The minimum value for
IF_R is 3.
Table 24. IF_R[11:0]—IF R Divider Value
R VALUE
28
IF_R[11:0]
3
0
0
0
0
0
0
0
0
0
0
1
1
...
.
.
.
.
.
.
.
.
.
.
.
.
4095
1
1
1
1
1
1
1
1
1
1
1
1
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8.6.4.2 RF_CPG—RF PLL Charge Pump Gain
This is used to control the magnitude of the RF PLL charge pump in steady-state operation.
Table 25. RF_CPG—RF PLL Charge Pump Gain
TYPICAL RF CHARGE PUMP CURRENT
AT 3 V (µA)
RF_CPG
CHARGE PUMP STATE
0
1X
95
1
2X
190
2
3X
285
3
4X
380
4
5X
475
5
6X
570
6
7X
665
7
8X
760
8
9X
855
9
10X
950
10
11X
1045
11
12X
1140
12
13X
1235
13
14X
1330
14
15X
1425
15
16X
1520
8.6.4.3 ACCESS—Register Access Word
It is mandatory that the first 5 registers R0-R4 be programmed. The programming of registers R5-R7 is optional.
The ACCESS[3:0] bits determine which additional registers must be programmed. Any one of these registers can
be individually programmed. According to Table 26, when the state of a register is in default mode, all the bits in
that register are forced to a default state and it is not necessary to program this register. When the register is
programmable, it needs to be programmed through the MICROWIRE. Using this register access technique, the
programming required is reduced up to 37%.
Table 26. ACCESS—Register Access Word
ACCESS BIT
REGISTER LOCATION
REGISTER CONTROLLED
ACCESS[0]
R3[20]
Must be set to 1
ACCESS[1]
R3[21]
R5
ACCESS[2]
R3[22]
R6
ACCESS[3]
R3[23]
R7
The default conditions the registers is shown in Table 27:
Table 27. R4 – R7 Registers
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
Data[19:0]
R4
3
2
1
0
C3
C2
C1
C0
R4 Must be programmed manually.
R5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
R6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
R7
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
1
1
1
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This corresponds to the following bit settings.
Table 28. R4 – R7 Register Descriptions
REGISTER
BIT LOCATION
BIT NAME
BIT DESCRIPTION
BIT VALUE
BIT STATE
R4[23]
ATPU
Autopowerup
0
Disabled
R4[17:16]
DITH
Dithering
2
Strong
R4[15:14]
FM
Modulation Order
3
3rd Order
R4[12]
OSC_2X
Oscillator Doubler
0
Disabled
R4[11]
OSC_OUT
OSCout Pin Enable
0
Disabled
R4[10]
IF_CPP
IF Charge Pump
Polarity
1
Positive
R4[9]
RF_CPP
RF Charge Pump
Polarity
1
Positive
R4
R4[8]
IF_P
IF PLL Prescaler
1
16/17
R4[7:4]
MUX
Ftest/LD Output
0
Disabled
R5[23:14]
RF_FD[21:12]
Extended Fractional
Denominator
0
Disabled
R5[13:4]
RF_FN[21:12]
Extended Fractional
Numerator
0
Disabled
R6[23:22]
CSR
Cycle Slip Reduction
0
Disabled
R6[21:18]
RF_CPF
Fastlock Charge
Pump Current
0
Disabled
R6[17:4]
RF_TOC
RF Time-out Counter
0
Disabled
R7[13]
DIV4
Lock Detect
Adjustment
0
Disabled (Fcomp ≤
20 MHz)
R7[7]
IF_RST
IF PLL Counter Reset
0
Disabled
RF_RST
RF PLL Counter
Reset
0
Disabled
R5
R6
R7
R7[6]
R7[5]
IF_CPT
IF PLL Tri-State
0
Disabled
R7[4]
RF_CPT
RF PLL Tri-State
0
Disabled
8.6.5 R4 Register
This register controls the conditions for the RF PLL in Fastlock.
Table 29. R4 Register
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
DATA[19:0]
R4
30
ATPU
0
1
0
0
0
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DITH [1:0]
FM [1:0]
0
OSC_
2X
OSC_
OUT
IF_
CPP
RF_
CPP
IF_P
MUX [3:0]
4
3
2
1
0
C3
C2
C1
C0
1
0
0
1
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8.6.5.1 MUX[3:0] Frequency Out and Lock Detect MUX
These bits determine the output state of the Ftest/LD pin.
Table 30. MUX[3:0] Frequency Out and Lock Detect MUX
MUX[3:0]
0
OUTPUT TYPE
0
0
0
OUTPUT DESCRIPTION
High Impedance
Disabled
0
0
0
1
Push-Pull
General-purpose output,
Logical “High” State
0
0
1
0
Push-Pull
General-purpose output,
Logical “Low” State
0
0
1
1
Push-Pull
RF and IF Digital Lock
Detect
0
1
0
0
Push-Pull
RF Digital Lock Detect
0
1
0
1
Push-Pull
IF Digital Lock Detect
0
1
1
0
Open-Drain
RF and IF Analog Lock
Detect
0
1
1
1
Open-Drain
RF Analog Lock Detect
1
0
0
0
Open-Drain
IF Analog Lock Detect
1
0
0
1
Push-Pull
RF and IF Analog Lock
Detect
1
0
1
0
Push-Pull
RF Analog Lock Detect
1
0
1
1
Push-Pull
IF Analog Lock Detect
1
1
0
0
Push-Pull
IF R Divider divided by 2
1
1
0
1
Push-Pull
IF N Divider divided by 2
1
1
1
0
Push-Pull
RF R Divider divided by 2
1
1
1
1
Push-Pull
RF N Divider divided by 2
8.6.5.2 IF_P—IF Prescaler
When this bit is set to 0, the 8/9 prescaler is used. Otherwise the 16/17 prescaler is used.
Table 31. IF_P—IF Prescaler
IF_P
IF Prescaler
MAXIMUM FREQUENCY
0
8/9
800 MHz
1
16/17
800 MHz
8.6.5.3 RF_CPP—RF PLL Charge Pump Polarity
Table 32. RF_CPP—RF PLL Charge Pump Polarity
RF_CPP
RF CHARGE PUMP POLARITY
0
Negative
1
Positive (Default)
8.6.5.4 IF_CPP—IF PLL Charge Pump Polarity
For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit for a
negative phase detector polarity.
Table 33. IF_CPP—IF PLL Charge Pump Polarity
IF_CPP
IF CHARGE PUMP POLARITY
0
Negative
1
Positive
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8.6.5.5 OSC_OUT Oscillator Output Buffer Enable
Table 34. OSC_OUT Oscillator Output Buffer Enable
OSC_OUT
OSCout PIN
0
Disabled (High Impedance)
1
Buffered output of OSCin pin
8.6.5.6 OSC2X—Oscillator Doubler Enable
When this bit is set to 0, the oscillator doubler is disabled and the TCXO frequency presented to the IF R and RF
R counters is equal to that of the input frequency of the OSCin pin. When this bit is set to 1, the TCXO frequency
presented to the RF R counter is doubled. Phase noise added by the doubler is negligible.
Table 35. OSC2X—Oscillator Doubler Enable
FREQUENCY PRESENTED TO RF R
COUNTER
OSC2X
0
fOSCin
1
2 x fOSCin
FREQUENCY PRESENTED TO IF R
COUNTER
fOSCin
8.6.5.7 FM[1:0]—Fractional Mode
Determines the order of the delta-sigma modulator. Higher order delta-sigma modulators reduce the spur levels
closer to the carrier by pushing this noise to higher frequency offsets from the carrier. In general, the order of the
loop filter should be at least one greater than the order of the delta-sigma modulator to allow for sufficient roll-off.
Table 36. FM[1:0]—Fractional Mode
FM
FUNCTION
0
Fractional PLL mode with a 4th order delta-sigma modulator
1
Disable the delta-sigma modulator. Recommended for test use only.
2
Fractional PLL mode with a 2nd order delta-sigma modulator
3
Fractional PLL mode with a 3rd order delta-sigma modulator
8.6.5.8 DITH[1:0]—Dithering Control
Dithering is a technique used to spread out the spur energy. Enabling dithering can reduce the main fractional
spurs, but can also give rise to a family of smaller spurs. Whether dithering helps or hurts is application specific.
Enabling the dithering may also increase the phase noise. In most cases where the fractional numerator is zero,
dithering usually degrades performance.
Dithering tends to be most beneficial in applications where there is insufficient filtering of the spurs. This often
occurs when the loop bandwidth is very wide or a higher order delta-sigma modulator is used. Dithering tends
not to impact the main fractional spurs much, but has a much larger impact on the sub-fractional spurs. If it is
decided that dithering will be used, best results will be obtained when the fractional denominator is at least 1000.
Table 37. DITH[1:0]—Dithering Control
DITH
32
DITHERING MODE USED
0
Disabled
1
Weak Dithering
2
Strong Dithering
3
Reserved
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8.6.5.9 ATPU—PLL Automatic Power Up
When this bit is set to 1, both the RF and IF PLL when the R0 register is written to. When the R0 register is
written to, the PD_RF and PD_IF bits are changed to 0 in the PLL registers. The exception to this case is when
the CE pin is low. In this case, the ATPU function is disabled.
8.6.6 R5 Register
Table 38. R5 Register
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
DATA[19:0]
R5
RF_FD[21:12]
3
2
1
0
C3
C2
C1
C0
1
0
1
1
RF_FN[21:12]
8.6.6.1 Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], Access[1] }
In the case that the ACCESS[1] bit is 0, then the part operates in 12-bit fractional mode, and the RF_FN2[21:12]
bits become do not care bits. When the ACCESS[1] bit is set to 1, the part operates in 22-bit mode and the
fractional numerator is expanded from 12 to 22-bits.
Table 39. Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], Access[1] }
FRACTIONAL
RF_FN[21:12]
NUMERATOR
(THESE BITS ONLY APPLY IN 22-BIT MODE)
RF_FN[11:0]
0
In 12-bit mode, these are do not care.
In 22-bit mode, for N D
LMX2485SQ/NOPB
ACTIVE
WQFN
RTW
24
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
X2485>D
LMX2485SQX/NOPB
ACTIVE
WQFN
RTW
24
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
X2485>D
(1)
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LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
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(2)
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(3)
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(4)
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(5)
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Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
MECHANICAL DATA
RTW0024A
SQA24A (Rev B)
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