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LMZ22005
SNVS686J – MARCH 2011 – REVISED AUGUST 2015
LMZ22005 5-A SIMPLE SWITCHER® Power Module With 20-V Maximum Input Voltage
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
Integrated Shielded Inductor
Simple PCB Layout
Frequency Synchronization Input (650 kHz to
950 kHz)
Flexible Start-up Sequencing Using External
Soft-Start, Tracking and Precision Enable
Protection Against Inrush Currents and Faults
Such as Input UVLO and Output Short Circuit
Junction Temperature Range –40°C to 125°C
Single Exposed Pad for Easy Mounting and
Manufacturing
Fast Transient Response for Powering FPGAs
and ASICs
Fully Enabled for WEBENCH® Power Designer
Pin Compatible With
LMZ23605/LMZ23603/LMZ22003
Electrical Specifications
– 30-W Maximum Total Output Power
– Up to 5-A Output Current
– Input Voltage Range 6 V to 20 V
– Output Voltage Range 0.8 V to 6 V
– Efficiency up to 92%
Performance Benefits
– High Efficiency Reduces System Heat
Generation
– Tested to EN55022 Class B(1)
– Low Component Count, Only 5 External
Components
– Low Output Voltage Ripple
– Uses PCB as Heat Sink, No Airflow Required
(1)
•
Point-of-load Conversions from 12V Input Rail
Time-Critical Projects
Space Constrained/High Thermal Requirement
Applications
Negative Output Voltage Applications
(see AN-2027 SNVA425)
3 Description
The LMZ22005 SIMPLE SWITCHER® power module
is an easy-to-use step-down DC-DC solution capable
of driving up to 5-A load. The LMZ22005 is available
in an innovative package that enhances thermal
performance and allows for hand or machine
soldering.
The LMZ22005 can accept an input voltage rail
between 6 V and 20 V and can deliver an adjustable
and highly accurate output voltage as low as 0.8 V.
The LMZ22005 only requires two external resistors
and three external capacitors to complete the power
solution. The LMZ22005 is a reliable and robust
design with the following protection features: thermal
shutdown, input undervoltage lockout, output
overvoltage protection, short circuit protection, output
current limit, and the device allows start-up into a
prebiased
output.
The
sync
input
allows
synchronization over the 650- to 950-kHz switching
frequency range.
Device Information(1)(2)
PART NUMBER
PACKAGE
LMZ22005
NDW (7)
BODY SIZE (NOM)
10.16 mm × 9.85 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Peak reflow temperature equals 245°C. See SNAA214 for
more details.
EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007.
See AN-2125 SNVA473 and layout for information on device
under test. Vin = 12 V, Vo = 3.3 V, Io = 5 A
Simplified Application Schematic
Efficiency 5-V Output at 25°C Ambient
100
90
VOUT @ 5A
RFBT
Enable
CIN
See Table
CSS
22 PF
0.47 PF
RFBB
See Table
Co
220 PF
EFFICIENCY (%)
VOUT
SS/TRK
FB
PGND
EN
AGND
VIN
VIN
SYNC
LMZ22005
80
70
60
50
9 VIn
12 Vin
20 Vin
40
0
1
2
3
4
OUTPUT CURRENT (A)
5
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMZ22005
SNVS686J – MARCH 2011 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
14
16
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 17
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 23
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Examples...................................................
Power Dissipation and Thermal Considerations ...
Power Module SMT Guidelines ............................
23
23
25
26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (October 2013) to Revision J
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Revision H (March 2013) to Revision I
Page
•
Changed 10 mils................................................................................................................................................................... 23
•
Changed 10 mils................................................................................................................................................................... 25
•
Added Power Module SMT Guidelines................................................................................................................................. 26
2
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SNVS686J – MARCH 2011 – REVISED AUGUST 2015
5 Pin Configuration and Functions
NDW Package
7-Pin
Top View
PGND/EP
Connect to AGND
VOUT
SS/TRK
FB
AGND
EN
SYNC
VIN
7
6
5
4
3
2
1
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
AGND
4
Ground
Analog Ground — Reference point for all stated voltages. Must be externally connected to
EP/PGND.
EN
3
Analog
Enable — Input to the precision enable comparator. Rising threshold is 1.279 V typical. Once
the module is enabled, a 20-µA source current is internally activated to accommodate
programmable hysteresis.
FB
5
Analog
Feedback — Internally connected to the regulation, overvoltage, and short circuit comparators.
The regulation reference point is 0.796 V at this input pin. Connect the feedback resistor divider
between the output and AGND to set the output voltage.
PGND
—
Ground
Exposed Pad / Power Ground Electrical path for the power circuits within the module. — NOT
Internally connected to AGND / pin 4. Used to dissipate heat from the package during
operation. Must be electrically connected to pin 4 external to the package.
SS/TRK
6
Analog
Soft-Start/Track — To extend the 1.6-ms internal soft-start connect an external soft -start
capacitor. For tracking connect to an external resistive divider connected to a higher priority
supply rail. See Design Steps.
SYNC
2
Analog
Sync Input — Apply a CMOS logic level square wave whose frequency is between 650 kHz and
950 kHz to synchronize the PWM operating frequency to an external frequency source. When
not using synchronization connect to ground. The module free running PWM frequency is 812
kHz (typical)
VIN
1
Power
Supply input — Nominal operating range is 6 V to 20 V. A small amount of internal capacitance
is contained within the package assembly. Additional external input capacitance is required
between this pin and exposed pad (PGND).
VOUT
7
Power
Output Voltage — Output from the internal inductor. Connect the output capacitor between this
pin and exposed pad.
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SNVS686J – MARCH 2011 – REVISED AUGUST 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(2) (3)
MIN
MAX
UNIT
VIN to PGND
–0.3
24
V
EN, SYNC to AGND
–0.3
5.5
V
SS/TRK, FB to AGND
–0.3
2.5
V
AGND to PGND
–0.3
0.3
V
Junction temperature
150
°C
Peak reflow case temperature (30 sec)
245
°C
150
°C
Storage temperature, Tstg
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
For soldering specifications, refer to the following document: SNOA549
6.2 ESD Ratings
Electrostatic
discharge
V(ESD)
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
EN, SYNC
Operation junction temperature
MIN
MAX
6
20
UNIT
V
0
5
V
–40
125
°C
6.4 Thermal Information
LMZ22005
THERMAL METRIC (1)
NDW
UNIT
7 PINS
Junction-to-ambient thermal
resistance (2)
RθJA
RθJC(top)
(1)
(2)
4
Junction-to-case (top) thermal
resistance
4-layer Evaluation Printed-Circuit-Board,
60 vias, No air flow
19.3
2-layer JEDEC Printed-Circuit-Board,
No air flow
21.5
No air flow
1.9
°C/W
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Theta JA measured on a 3.5-in × 3.5-in 4-layer board, with 3-oz. copper on outer layers and 2-oz. copper on inner layers, sixty thermal
vias, no air flow, and 1-W power dissipation. Refer to application note layout diagrams.
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SNVS686J – MARCH 2011 – REVISED AUGUST 2015
6.5 Electrical Characteristics
Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply: VIN = 12 V, VOUT = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
MAX (1)
UNIT
SYSTEM PARAMETERS
ENABLE CONTROL
VEN
EN threshold trip point
VEN-HYS
EN input hysteresis current
VEN rising, TJ = 25°C
VEN rising, TJ = –40°C to +125°C
1.279
1.1
VEN > 1.279 V
1.458
21
V
µA
SOFT-START
ISS
SS source current
tSS
Internal soft-start interval
VSS = 0 V, TJ = 25°C
VSS = 0 V, TJ = –40°C to +125°C
50
40
60
1.6
µA
ms
CURRENT LIMIT
ICL
Current limit threshold
DC average, TJ = –40°C to +125°C
5.4
Sync input connected to ground.
711
A
INTERNAL SWITCHING OSCILLATOR
fosc
Free-running oscillator
frequency
fsync
Synchronization range
VIL-sync
Synchronization logic zero
amplitude
Relative to AGND, TJ = –40°C to +125°C
VIH-sync
Synchronization logic one
amplitude
Relative to AGND, TJ = –40°C to +125°C
Sync dc
Synchronization duty cycle
range
Dmax
Maximum Duty Factor
812
650
914
kHz
950
kHz
0.4
V
1.5
15%
V
50%
85%
83%
REGULATION AND OVERVOLTAGE COMPARATOR
VSS >+ 0.8 V, IO = 3 A, TJ = 25°C
VFB
In-regulation feedback voltage
VFB-OV
Feedback overvoltage
protection threshold
IFB
Feedback input bias current
IQ
Non-switching input current
ISD
Shutdown quiescent current
VSS >+ 0.8 V, IO = 3 A,
TJ = –40°C to +125°C
0.796
0.776
0.816
V
0.86
V
5
nA
VFB = 0.86 V
2.6
mA
VEN = 0 V
70
μA
THERMAL CHARACTERISTICS
TSD
Thermal shutdown
Rising
165
°C
TSD-HYST
Thermal shutdown hysteresis
Falling
15
°C
9
mVPP
PERFORMANCE PARAMETERS (3)
ΔVO
Output voltage ripple
Cout = 220 µF with 7 mΩ ESR + 100 µF
X7R + 2 x 0.047 µF BW at 20 MHz
ΔVO/ΔVIN
Line regulation
VIN = 12 V to 20 V, IO= 0.001 A
ΔVO/ΔIOUT
Load regulation
VIN = 12 V, IO= 0.001 A to 3 A
η
Peak efficiency
VIN = 12 V, VO = 3.3 V, IO = 1 A
86%
η
Full load efficiency
VIN = 12 V VO = 3.3 V, IO = 3 A
81.5%
(1)
(2)
(3)
±0.02%
1
mV/A
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely parametric norm.
Refer to BOM in Table 1.
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6.6 Typical Characteristics
100
6
90
5
DISSIPATION (W)
EFFICIENCY (%)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF
Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting is slightly higher output ripple – See Design Steps section.
80
70
60
50
0
1
2
3
4
OUTPUT CURRENT (A)
0
0
6
90
5
80
70
60
0
1
2
3
4
OUTPUT CURRENT (A)
3
2
0
0
90
5
DISSIPATION (W)
6
80
70
60
1
2
3
4
OUTPUT CURRENT (A)
5
20 Vin
12 Vin
9 Vin
6 Vin
4
3
2
1
9 Vin
12 Vin
20 Vin
0
1
2
3
4
OUTPUT CURRENT (A)
Figure 4. Dissipation 5-V Output at 25°C Ambient
100
40
20 Vin
12 Vin
9 Vin
4
5
Figure 3. Efficiency 5-V Output at 25°C Ambient
50
5
1
9 VIn
12 Vin
20 Vin
40
1
2
3
4
OUTPUT CURRENT (A)
Figure 2. Dissipation 6-V Output at 25°C Ambient
DISSIPATION (W)
EFFICIENCY (%)
2
100
50
EFFICIENCY (%)
3
5
Figure 1. Efficiency 6-V Output at 25°C Ambient
0
5
Figure 5. Efficiency 3.3-V Output at 25°C Ambient
6
4
1
10 Vin
12 Vin
20 Vin
40
20 Vin
12 Vin
10 Vin
0
1
2
3
4
OUTPUT CURRENT (A)
5
Figure 6. Dissipation 3.3-V Output at 25°C Ambient
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Typical Characteristics (continued)
90
6
80
5
DISSIPATION (W)
EFFICIENCY (%)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF
Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting is slightly higher output ripple – See Design Steps section.
70
60
50
6 Vin
9 Vin
12 Vin
20 Vin
40
30
0
1
2
3
4
OUTPUT CURRENT (A)
2
0
5
0
6
80
5
70
60
50
6 Vin
9 Vin
12 Vin
20 Vin
0
1
2
3
4
OUTPUT CURRENT (A)
3
2
0
5
0
5
DISSIPATION (W)
75
65
55
45
1
2
3
4
OUTPUT CURRENT (A)
5
Figure 10. Dissipation 1.8-V Output at 25°C Ambient
6
6 Vin
9 Vin
12 Vin
20 Vin
20 Vin
12 Vin
9 Vin
6 Vin
4
3
2
1
0
25
1
2
3
4
OUTPUT CURRENT (A)
20 Vin
12 Vin
9 Vin
6 Vin
4
85
0
5
1
Figure 9. Efficiency 1.8-V Output at 25°C Ambient
35
1
2
3
4
OUTPUT CURRENT (A)
Figure 8. Dissipation 2.5-V Output at 25°C Ambient
DISSIPATION (W)
EFFICIENCY (%)
3
90
30
EFFICIENCY (%)
4
1
Figure 7. Efficiency 2.5-V Output at 25°C Ambient
40
20 Vin
12 Vin
9 Vin
6 Vin
5
Figure 11. Efficiency 1.5-V Output at 25°C Ambient
0
1
2
3
4
OUTPUT CURRENT (A)
5
Figure 12. Dissipation 1.5-V Output at 25°C Ambient
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Typical Characteristics (continued)
80
6
70
5
DISSIPATION (W)
EFFICIENCY (%)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF
Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting is slightly higher output ripple – See Design Steps section.
60
50
40
6 Vin
9 Vin
12 Vin
20 Vin
30
20
0
0
0
6
70
5
60
50
40
6 Vin
9 Vin
12 Vin
20 Vin
0
1
2
3
4
OUTPUT CURRENT (A)
3
2
0
5
0
5
DISSIPATION (W)
60
50
40
30
6 Vin
9 Vin
12 Vin
20 Vin*
1
2
3
4
OUTPUT CURRENT (A)
1
2
3
4
OUTPUT CURRENT (A)
5
Figure 16. Dissipation 1-V Output at 25°C Ambient
6
0
20 Vin
12 Vin
9 VIn
6 Vin
4
70
10
5
1
Figure 15. Efficiency 1-V Output at 25°C Ambient
20
1
2
3
4
OUTPUT CURRENT (A)
Figure 14. Dissipation 1.2-V Output at 25°C Ambient
DISSIPATION (W)
EFFICIENCY (W)
2
80
20
EFFICIENCY (%)
3
5
Figure 13. Efficiency 1.2-V Output at 25°C Ambient
20 Vin*
12 Vin
9 Vin
6 Vin
4
3
2
1
0
5
Figure 17. Efficiency 0.8-V Output at 25°C Ambient
8
4
1
1
2
3
4
OUTPUT CURRENT (A)
30
20 Vin
12 Vin
9 Vin
6 Vin
0
1
2
3
4
OUTPUT CURRENT (A)
5
Figure 18. Dissipation 0.8-V Output at 25°C Ambient
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Typical Characteristics (continued)
100
6
90
5
DISSIPATION (W)
EFFICIENCY (%)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF
Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting is slightly higher output ripple – See Design Steps section.
80
70
60
50
0
1
2
3
4
OUTPUT CURRENT (A)
2
0
0
100
6
90
5
80
70
60
50
0
1
2
3
4
OUTPUT CURRENT (A)
3
2
0
0
80
5
DISSIPATION (W)
6
70
60
50
1
2
3
4
OUTPUT CURRENT (A)
5
20 Vin
12 Vin
9 Vin
4
3
2
1
9 Vin
12 Vin
20 Vin
0
1
2
3
4
OUTPUT CURRENT (A)
Figure 22. Dissipation 5-V Output at 85°C Ambient
90
30
20 Vin
12 Vin
9 Vin
4
5
Figure 21. Efficiency 5-V Output at 85°C Ambient
40
5
1
9 Vin
12 Vin
20 Vin
40
1
2
3
4
OUTPUT CURRENT (A)
Figure 20. Dissipation 6-V Output at 85°C Ambient
DISSIPATION (W)
EFFICIENCY (%)
3
5
Figure 19. Efficiency 6-V Output at 85°C Ambient
EFFICIENCY (%)
4
1
10 Vin
12 Vin
20 Vin
40
20 Vin
12 Vin
10 Vin
0
5
Figure 23. Efficiency 3.3-V Output at 85°C Ambient
0
1
2
3
4
OUTPUT CURRENT (A)
5
Figure 24. Dissipation 3.3-V Output at 85°C Ambient
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Typical Characteristics (continued)
90
6
80
5
DISSIPATION (W)
EFFICIENCY (%)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF
Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting is slightly higher output ripple – See Design Steps section.
70
60
50
6 Vin
9 Vin
12 Vin
20 Vin
40
30
0
1
2
3
4
OUTPUT CURRENT (A)
0
5
0
80
5
70
60
50
6 Vin
9 Vin
12 Vin
20 Vin
1
2
3
4
OUTPUT CURRENT (A)
3
2
0
5
0
5
DISSIPATION (W)
70
60
50
40
6 Vin
9 Vin
12 Vin
20 Vin
1
2
3
4
OUTPUT CURRENT (A)
1
2
3
4
OUTPUT CURRENT (A)
5
Figure 28. Dissipation 1.8-V Output at 85°C Ambient
6
0
20 Vin
12 Vin
9 Vin
6 Vin
4
80
20
5
1
Figure 27. Efficiency 1.8-V Output at 85°C Ambient
30
1
2
3
4
OUTPUT CURRENT (A)
Figure 26. Dissipation 2.5-V Output at 85°C Ambient
DISSIPATION (W)
EFFICIENCY (%)
2
6
0
EFFICIENCY (%)
3
90
30
20 Vin
12 Vin
9 Vin
6 Vin
4
3
2
1
0
5
Figure 29. Efficiency 1.5-V Output at 85°C Ambient
10
4
1
Figure 25. Efficiency 2.5-V Output at 85°C Ambient
40
20 Vin
12 Vin
9 Vin
6 Vin
0
1
2
3
4
OUTPUT CURRENT (A)
5
Figure 30. Dissipation 1.5-V Output at 85°C Ambient
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Typical Characteristics (continued)
80
6
70
5
DISSIPATION (W)
EFFICIENCY (%)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF
Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting is slightly higher output ripple – See Design Steps section.
60
50
40
6 Vin
9 Vin
12 Vin
20 Vin
30
20
0
2
5
0
75
6
65
5
55
45
35
6 Vin
9 Vin
12 Vin
20 Vin
0
20 Vin
12 Vin
9 Vin
6 Vin
4
3
2
0
1
2
3
4
OUTPUT CURRENT (A)
5
0
6
DISSIPATION (W)
40
6 Vin
9 Vin
12 Vin
20 Vin*
0
1
2
3
4
OUTPUT CURRENT (A)
5
20 Vin*
12 Vin
9 Vin
6 Vin
5
60
50
1
2
3
4
OUTPUT CURRENT (A)
Figure 34. Dissipation 1-V Output at 85°C Ambient
70
20
5
1
Figure 33. Efficiency 1-V Output at 85°C Ambient
30
1
2
3
4
OUTPUT CURRENT (A)
Figure 32. Dissipation 1.2-V Output at 85°C Ambient
DISSIPATION (W)
EFFICIENCY (%)
3
0
1
2
3
4
OUTPUT CURRENT (A)
15
EFFICIENCY (%)
4
1
Figure 31. Efficiency 1.2-V Output at 85°C Ambient
25
20 Vin
12 Vin
9 Vin
6 Vin
4
3
2
1
0
5
Figure 35. Efficiency 0.8-V at 85°C Ambient
0
1
2
3
4
OUTPUT CURRENT (A)
5
Figure 36. Dissipation 0.8-V Output at 85°C Ambient
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF
Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting is slightly higher output ripple – See Design Steps section.
6
MAXIMUM OUTPUT CURRENT (A)
MAXIMUM OUTPUT CURRENT (A)
6
5
4
3
2
1
JA=12°C/W
0
4
3
2
1
JA = 12 °C/W
0
30 40 50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
VIN = 12 V, VOUT = 5 V
30 40 50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
VIN= 12 V, VOUT = 3.3 V
Figure 37. Thermal Derating
NORMALLIZED OUTPUT VOLTAGE (V/V)
5
Figure 38. Thermal Derating
1.002
1.001
1.000
0.999
9 Vin
12 Vin
20 Vin
0.998
0
1
2
3
4
OUTPUT CURRENT (A)
5
10 mV/Div
500 ns/Div
12 VIN 3.3 VO at 5 A, BW = 20 MHz
VOUT = 3.3 V
Figure 40. Output Ripple
Figure 39. Normalized — Line and Load Regulation
2A/Div
10 mV/Div
500 ns/Div
12 VIN 3.3 VO at 5 A BW = 250 MHz
Figure 41. Output Ripple
12
100 mV/Div
500 µs/Div
12 VIN 3.3 VO 0.5- to 5-A Step
Figure 42. Transient Response From Evaluation Board
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 12 V; CIN = 2 x 10 μF + 1-μF X7R Ceramic; CO = 220-μF
Specialty Polymer + 10-µF Ceramic; TA = 25°C for waveforms. Efficiency and dissipation plots marked with * have cycle
skipping at light loads resulting is slightly higher output ripple – See Design Steps section.
9
8
CURRENT (A)
7
Output Current
6
5
4
3
2
Input Current
1
0
5
10
15
INPUT VOLTAGE (V)
20
Figure 43. Short Circuit Current vs Input Voltage
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7 Detailed Description
7.1 Overview
The architecture used is an internally compensated emulated peak current mode control, based on a monolithic
synchronous SIMPLE SWITCHER core capable of supporting high load currents. The output voltage is
maintained through feedback compared with an internal 0.8-V reference. For emulated peak current-mode, the
valley current is sampled on the down-slope of the inductor current. This is used as the DC value of current to
start the next cycle.
The primary application for emulated peak current-mode is high input voltage to low output voltage operating at a
narrow duty cycle. By sampling the inductor current at the end of the switching cycle and adding an external
ramp, the minimum ON-time can be significantly reduced, without the need for blanking or filtering which is
normally required for peak current-mode control.
7.2 Functional Block Diagram
Linear
Regulator
2M
VIN
1
3
3
CIN
EN
CBST
CINint
1
SYNC
CSS
2
800 kHz
PWM
SS/TRK
3.3 uH VOUT
VREF
3
RFBT
CO
FB
1
2
Comp
RFBB
AGND
Regulator IC
EP/
PGND
Internal Passives
7.3 Feature Description
7.3.1 Synchronization Input
The PWM switching frequency can be synchronized to an external frequency source. If this feature is not used,
connect this input either directly to ground, or connect to ground through a resistor of 1.5 kΩ or less. The allowed
synchronization frequency range is 650 kHz to 950 kHz. The typical input threshold is 1.4-V transition level.
Ideally the input clock must overdrive the threshold by a factor of 2, so direct drive from 3.3-V logic through a 1.5kΩ Thevenin source resistance is recommended.
NOTE
Applying a sustained logic 1 corresponds to zero Hz PWM frequency and will cause the
module to stop switching.
7.3.2 Output Overvoltage Protection
If the voltage at FB is greater than the 0.86-V internal reference the output of the error amplifier is pulled toward
ground causing VO to fall.
14
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Feature Description (continued)
7.3.3 Current Limit
The LMZ22005 is protected by both low-side (LS) and high-side (HS) current limit circuitry. The LS current limit
detection is carried out during the OFF-time by monitoring the current through the LS synchronous MOSFET.
Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows
through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 5.4 A (typical) the
current limit comparator disables the start of the next switching period. Switching cycles are prohibited until
current drops below the limit.
NOTE
DC current limit is dependent on duty cycle as illustrated in the graph in the Typical
Characteristics section.
The HS current limit monitors the current of top side MOSFET. Once HS current limit is detected (7 A typical) ,
the HS MOSFET is shutoff immediately, until the next cycle. Exceeding HS current limit causes VO to fall. Typical
behavior of exceeding LS current limit is that fSW drops to 1/2 of the operating frequency.
7.3.4 Thermal Protection
The junction temperature of the LMZ22005 must not be allowed to exceed its maximum ratings. Thermal
protection is implemented by an internal thermal shutdown circuit which activates at 165°C (typical) causing the
device to enter a low power standby state. In this state the main MOSFET remains off causing VO to fall, and
additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for
accidental device overheating. When the junction temperature falls back below 150°C (typical hysteresis = 15°C)
the SS pin is released, VO rises smoothly, and normal operation resumes.
Applications requiring maximum output current especially those at high input voltage may require additional
derating at elevated temperatures.
7.3.5 Prebiased Start-Up
The LMZ22005 will properly start up into a prebiased output. This start-up situation is common in multiple rail
logic applications where current paths may exist between different power rails during the start-up sequence.
Figure 44 shows proper behavior in this mode. Trace one is Enable going high. Trace two is 1.5-V prebias rising
to 3.3 V. Rise time determined by CSS, trace three.
Figure 44. Prebiased Start-Up
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7.4 Device Functional Modes
7.4.1 Discontinuous And Continuous Conduction Modes
At light load the regulator will operate in discontinuous conduction mode (DCM). With load currents above the
critical conduction point, it will operate in continuous conduction mode (CCM). In CCM, current flows through the
inductor through the entire switching cycle and never falls to zero during the OFF-time. When operating in DCM,
inductor current is maintained to an average value equaling IOUT. Inductor current exhibits normal behavior for
the emulated current mode control method used. Output voltage ripple typically increases during this mode of
operation.
Figure 45 is a comparison pair of waveforms of the showing both CCM (upper) and DCM operating modes.
VIN = 12 V, VO = 3.3 V, IO = 3 A / 0.3 A 2 μs/div
Figure 45. CCM and DCM Operating Modes
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMZ22005 is a step-down DC-to-DC power module. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 5 A. The following design procedure can be used to select
components for the LMZ22005. Alternately, the WEBENCH software may be used to generate complete designs.
When generating a design, the WEBENCH software uses iterative design procedure and accesses
comprehensive databases of components. Please go to www.ti.com for more details.
8.2 Typical Application
U1
7V to 20V
PGND/EP
VIN
Enable
VOUT
SS
3.3VO @ 5A
7
AGND
EN
FB
6
5
4
3
1
CIN6 OPT
150 PF
2
VIN
+
SYNC
LMZ22005TZ
RENT
42.2k
SYNC
D1 OPT
5.1V
RENB
12.7k
RENH OPT
100:
CIN2,3
10 PF
CIN1,5
0.047 PF
RSNOPT
1.50 k:
RFBT
3.32k
CSS
0.47 PF
RFBB
1.07k
RFRA OPT
23.7:
CO1,6
0.047 PF
CO2
100 PF
OPT
+
CO5
220 PF
Figure 46. Typical Application Schematic
8.2.1 Design Requirements
For this example the following application parameters exist:
• VIN Range = Up to 20 V
• VOUT = 0.8 V to 6 V
• IOUT = 5 A
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Typical Application (continued)
8.2.2 Detailed Design Procedure
8.2.2.1 Design Steps
The LMZ22005 is fully supported by WEBENCH which offers: component selection, electrical and thermal
simulations. Additionally there is are evaluation and demonstration boards that may be used a starting point for
design. The following list of steps can be used to quickly design the LMZ22005 application.
1.
2.
3.
4.
5.
6.
Select minimum operating VIN with enable divider resistors
Program VO with resistor divider selection
Select CO
Select CIN
Determine module power dissipation
Layout PCB for required thermal performance
8.2.2.2 Enable Divider, RENT, RENB and RENH Selection
Internal to the module is a 2-MΩ pullup resistor connected from VIN to Enable. For applications not requiring
precision undervoltage lockout (UVLO), the Enable input may be left open circuit and the internal resistor will
always enable the module. In such case, the internal UVLO occurs typically at 4.3 V (VIN rising).
In applications with separate supervisory circuits Enable can be directly interfaced to a logic source. In the case
of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than
the LMZ22005 output rail.
Enable provides a precise 1.279-V threshold to allow direct logic drive or connection to a voltage divider from a
higher enable voltage such as VIN. Additionally there is 21 μA (typical) of switched offset current allowing
programmable hysteresis. See Figure 47.
The function of the enable divider is to allow the designer to choose an input voltage below which the circuit will
be disabled. This implements the feature of programmable UVLO. The two resistors must be chosen based on
the following ratio:
RENT / RENB = (VIN UVLO / 1.279 V) – 1
(1)
The LMZ22005 typical application shows 12.7 kΩ for RENB and 42.2 kΩ for RENT resulting in a rising UVLO of
5.46 V.
NOTE
A midpoint 5.1-V Zener clamp is present to allow setting UVLO to cover an extended
range of operation. The Zener clamp is not required if the target application prohibits the
maximum Enable input voltage from being exceeded.
Additional enable voltage hysteresis can be added with the inclusion of RENH. It may be possible to select values
for RENT and RENB such that RENH is a value of zero allowing it to be omitted from the design.
Rising threshold can be calculated as follows:
VEN(rising) = 1.279 ( 1 + RENT|| 2 meg/ RENB)
(2)
Whereas falling threshold level can be calculated using:
VEN(falling) = VEN(rising) – 21 µA ( RENT|| 2 meg || RENTB + RENH )
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Typical Application (continued)
P/O LMZ22005
INT-VCC (5V)
VIN
21 uA
RENT
42.2k
RENH
2.0M
ENABLE
RUN
100Ö
RENB
12.7k
5.1V
1.279V
Figure 47. Enable Input Detail
8.2.2.3 Output Voltage Selection
Output voltage is determined by a divider of two resistors connected between VO and ground. The midpoint of
the divider is connected to the FB input.
The regulated output voltage determined by the external divider resistors RFBT and RFBB is:
VO = 0.8 V × (1 + RFBT / RFBB)
(4)
Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:
RFBT / RFBB = (VO / 0.796 V) – 1
(5)
These resistors must generally be chosen from values in the range of 1.0 kΩ to 10.0 kΩ.
For VO = 0.8 V the FB pin can be connected to the output directly and RFBB can be omitted.
Table 1 lists the values for RFBT , and RFBB.
Table 1. Typical Application Bill of Materials
REF DES
DESCRIPTION
CASE SIZE
MANUFACTURER
U1
SIMPLE SWITCHER
PFM-7
Texas Instruments
MANUFACTURER P/N
LMZ22005TZ
Cin1,5
0.047 µF, 50 V, X7R
1206
Yageo America
CC1206KRX7R9BB473
Cin2,3
10 µF, 50 V, X7R
1210
Taiyo Yuden
UMK325BJ106MM-T
Cin6 (OPT)
CAP, AL, 150 µF, 50 V
Radial G
Panasonic
EEE-FK1H151P
CO1,6
0.047 µF, 50 V, X7R
1206
Yageo America
CC1206KRX7R9BB473
CO2 (OPT)
100 µF, 6.3 V, X7R
1210
TDK
C3225X5R0J107M
CO5
220 μF, 6.3 V, SP-Cap
(7343)
Panasonic
EEF-UE0J221LR
RFBT
3.32 kΩ
0805
Panasonic
ERJ-6ENF3321V
RFBB
1.07 kΩ
0805
Panasonic
ERJ-6ENF1071V
RSN (OPT)
1.50 kΩ
0805
Vishay Dale
CRCW08051K50FKEA
RENT
42.2 kΩ
0805
Panasonic
ERJ-6ENF4222V
RENB
12.7 kΩ
0805
Panasonic
ERJ-6ENF1272V
RFRA(OPT)
23.7Ω
0805
Vishay Dale
CRCW080523R7FKEA
RENH
100 Ω
0805
Vishay Dale
CRCW0805100RFKEA
CFF
180 pF, ±10%, C0G, 50 V
0805
TDK
08055A181JAT2A
CSS
047 μF, ±10%, X7R, 16 V
0805
AVX
0805YC474KAT2A
D1(OPT)
5.1 V, 0.5 W
SOD-123
Diodes Inc.
MMSZ5231BS-7-F
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8.2.2.4 Soft-start Capacitor Selection
Programmable soft-start permits the regulator to slowly ramp to its steady-state operating point after being
enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time.
Upon turnon, after all UVLO conditions have been passed, an internal 2-ms circuit slowly ramps the SS/TRK
input to implement internal soft-start. If 1.6 ms is an adequate turnon time then the CSS capacitor can be left
unpopulated. Longer soft-start periods are achieved by adding an external capacitor to this input.
Soft-start duration is given by the formula:
tSS = VREF × CSS / Iss = 0.796 V × CSS / 50 µA
(6)
This equation can be rearranged as follows:
CSS = tSS × 50 μA / 0.796 V
(7)
Using a 0.22-μF capacitor results in 3.5-ms typical soft-start duration; and 0.47 μF results in 7.5-ms typical. 0.47
μF is a recommended initial value.
Once the soft-start input exceeds 0.796 V the output of the power stage will be in regulation and the 50-μA
current is deactivated. The following conditions will reset the soft-start capacitor by discharging the SS input to
ground with an internal current sink.
•
•
•
The Enable input being pulled low
Thermal shutdown condition
Internal VCC UVLO (Approx 4.3V input to VIN)
8.2.2.5 Tracking Supply Divider Option
The tracking function allows the module to be connected as a slave supply to a primary voltage rail (often the
3.3-V system rail) where the slave module output voltage is lower than that of the master. Proper configuration
allows the slave rail to power up coincident with the master rail such that the voltage difference between the rails
during ramp-up is small (that is,
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