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LP3470A
SNVSBF5C – JULY 2019 – REVISED MAY 2020
LP3470A Ultra Low Power Voltage Supervisor With Programmable Delay and 1% Reset
Threshold
1 Features
3 Description
•
•
•
•
The LP3470A device is a micropower voltage
supervisory circuit designed to monitor voltages
within 1% of reset threshold overtemperature and is
pin-to-pin compatible with existing TI device LP3470.
The LP3470A device provides accurate, nano-power
voltage monitoring with programmable delay.
1
•
•
•
•
Pin-to-pin compatible with LP3470
5-Pin SOT-23 package
Open-drain RESET output
Programmable reset time-out period using an
external capacitor
Immune to short VCC transients
±1% Reset threshold accuracy (typical)
Ultra-low quiescent current (0.3 µA typical)
RESET valid down to VCC = 0.95 V
2 Applications
•
•
•
•
•
•
•
Critical µP and µC power monitoring
Intelligent instruments
Computers
Portable and battery-powered equipment
Building automation: building security system,
video surveillance
Factory automation: field transmitters, position
and proximity sensors
Motor drives
The LP3470A asserts a reset signal whenever the
VCC supply voltage falls below a reset threshold. The
reset time-out period is adjustable using an external
capacitor. Reset remains asserted for an interval
(programmed by an external capacitor) after VCC has
risen above the threshold voltage plus hysteresis.
For information on available reset threshold voltage
options, see Mechanical, Packaging, and Orderable
Information.
Device Information(1)
PART NUMBER
PACKAGE
LP3470A
BODY SIZE (NOM)
SOT-23 (5)
1.60 mm × 2.90 mm
(1) For all available packages, see the Package Option
Addendum at the end of the data sheet.
Basic Operating Circuit
Typical Supply Current for LP3470A
0.6
25°C
-40°C
125°C
0.55
IN
LDO OUT
0.5
0.45
VCC
SRT
RESET
LP3470A
GND
0.4
Microcontroller
RESET
ICC (µA)
VCC VCC1
0.35
0.3
0.25
0.2
0.15
0.1
0.05
1
2
3
4
5
6
VCC (V)
7
8
9
10
Iq_v
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP3470A
SNVSBF5C – JULY 2019 – REVISED MAY 2020
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics .............................................
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 11
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2019) to Revision C
•
Page
Changed Figure 12 caption to 0.01 µF................................................................................................................................. 13
Changes from Revision A (October 2019) to Revision B
Page
•
Changed Ultra-low quiescent current 0.35 to 0.3 to align with the Electrical Characteristics table ....................................... 1
•
Changed the typical value of ICC in the Electrical Characteristics table from 300 to 0.3 to match with the units of µA......... 6
Changes from Original (July 2019) to Revision A
•
2
Page
Initial Public Release ............................................................................................................................................................. 1
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5 Device Comparison Table
PART NUMBER
VIT- (typ) (VCC RAMPING DOWN)
VIT+ (typ) (VCC RAMPING UP)
LP3470A263
2.63 V
2.73 V
LP3470A275
2.75 V
2.85 V
LP3470A293
2.93 V
3.03 V
LP3470A308
3.08 V
3.28 V
LP3470A365
3.65 V
3.85 V
LP3470A400
4.0 V
4.2 V
LP3470A438
4.38 V
4.58 V
LP3470A463
4.63 V
4.83 V
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6 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
SOT-23 (5)
DBV (5)
Top View
SRT
1
GND
2
VCC1
3
5
RESET
4
VCC
Not to scale
Pin Functions
PIN
NO.
1
NAME
I/O
DESCRIPTION
Set reset time-out. Connect a capacitor between this pin and ground to select the reset time-out period (tD).
tD = 619 × C1 (CSRT in µF and tD in ms). If no capacitor is connected, leave this pin floating.
SRT
I
2
GND
—
3
VCC1
I
Can be connected to VCC or left floating. DO NOT CONNECT TO GND.
4
VCC
I
Supply voltage, and reset threshold monitor input.
5
RESET
O
Open-drain, active-low reset output. Connect to an external pullup resistor. RESET changes from high to low
whenever the monitored voltage (VCC) drops below the reset threshold voltage (VIT-). Once VCC exceeds
the reset threshold (VIT-) + hysteresis (VHYS), RESET remains low for the reset time-out period (tD) and then
deasserts to logic high.
4
Ground pin.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted (1)
Voltage
Current
(2)
MAX
–0.3
12
RESET
–0.3
12
SRT
–0.3
5.5
RESET
Temperature (2)
(1)
MIN
VCC
±70
Operating junction temperature, TJ
–40
150
Storage, Tstg
–65
150
UNIT
V
mA
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
± 2000
Charged device model (CDM), per JEDEC specification
JESD22-C101 (2)
± 750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
Input supply voltage
VRESET, VRESET
IRESET, IRESET
TJ
Junction temperature (free air temperature)
NOM
MAX
UNIT
0.95
10
V
RESET pin voltage
0
10
V
RESET pin current
0
±5
mA
–40
125
°C
7.4 Thermal Information
LP3470A
THERMAL METRIC
(1)
DBV (SOT23-5)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
187.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
109.2
°C/W
RθJB
Junction-to-board thermal resistance
92.8
°C/W
ψJT
Junction-to-top characterization parameter
35.4
°C/W
ψJB
Junction-to-board characterization parameter
92.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
At 0.95 V ≤ VCC ≤ 10 V, SRT = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VCC, output reset load (CLOAD) = 10 pF and
over the operating free-air temperature range – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
VIT-
Negative-going input threshold accuracy
-40°C to 125°C
–1.5
1
1.5
%
VHYS
Hysteresis on VIT- pin
VIT- = 3.08 V to 4.63 V
175
200
225
mV
VHYS
Hysteresis on VIT- pin
VIT- = 2.64 V to 2.93 V
75
100
125
mV
ICC
Supply current into VCC pin
VCC = 0.95 V < VCC < 10 V
VCC > VIT+ (1)
TA = -40°C to 125°C
0.3
1
µA
RSRT
SRT pin internal resistance
500
350
Power on Reset Voltage (3)
Low level output voltage
VOL
Ilkg(OD)
(1)
(2)
(3)
(2)
10
UNIT
Input supply voltage
VPOR
0.95
MAX
VCC
650
kΩ
VOL(max) = 0.2 V
IOUT (Sink) = 5.6 uA
950
mV
1.5 V < VCC < 5 V
VCC < VITIOUT(Sink) = 2 mA
200
mV
90
nA
RESET pin in High Impedance,
VCC = VRESET = 5.5 V
VIT+ < VCC
Open-Drain output leakage current
V
VIT+ = VHYS + VITThis parameter is guranteed by design and characterization
VPOR is the minimum VDD voltage level for a controlled output state. VDD slew rate ≤ 100mV/µs
7.6 Timing Requirements
At 0.95 V ≤ VCC ≤ 10 V, SRT = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VCC, output reset load (CLOAD) = 10 pF and
over the operating free-air temperature range – 40°C to 125°C, VCC slew rate < 100mV / us, unless otherwise noted. Typical
values are at TJ = 25°C.
PARAMETER
tP_HL
tD
6
VCC = VIT+ to (VIT-) - 10%
(1)
MIN
TYP
MAX
15
30
µs
50
µs
SRT pin = open
VCC = (VIT- -1V) to (VIT+ + 1V)
Reset time delay
tGI_VIT(1)
(2)
(3)
(4)
TEST CONDITIONS
Propagation detect delay for VCC falling
below VIT-
SRT pin = 10 nF (2) (3)
6.2
ms
SRT pin = 1 µF (2) (3)
619
ms
10
µs
5% VIT- overdrive (3) (4)
Glitch immunity VIT-
UNIT
tP_HL measured from threhold trip point (VIT-) to VOL
Ideal capacitor
Parameter is guranteed by design.
Overdrive % = [(VCC/ VIT-) - 1] × 100%
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7.7 Typical Characteristics
Typical characteristics show the typical performance of the LP3470A device. Test conditions are at TA = TJ = 25°C (unless
otherwise noted).
10
0.6
25°C
-40°C
125°C
0.55
0.5
8
0.45
7
VRESET (V)
ICC (µA)
0.4
0.35
0.3
0.25
6
5
4
0.2
3
0.15
2
0.1
1
0.05
1
2
3
4
5
6
VCC (V)
7
8
9
0
10
0
1
2
3
4
Iq_v
Figure 1. Supply Current vs Supply Voltage
25°C
-40°C
125°C
45
5
6
VCC (V)
7
8
9
10
VCC_
Figure 2. Output Voltage vs Supply Voltage for LP3470A293
0.34
50
0.32
0.3
VIT- Accuracy (%)
40
VOL (mV)
25°C
-40°C
125°C
9
35
30
25
0.28
0.26
0.24
0.22
0.2
0.18
20
0.16
15
1.4
1.6
1.8
2
2.2
VCC (V)
2.4
2.6
0.14
-40
2.8
VOL_
0.6
0.55
0.5
RSRT (kohm)
VIT+ Accuracy (%)
0.45
0.4
0.3
0.25
0.2
0.15
0.1
0.05
0
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
479
478.5
478
477.5
477
476.5
476
475.5
475
474.5
474
473.5
473
472.5
-40
-20
VITp
Figure 5. Positive-going Input Threshold VIT+ Accuracy vs
Temperature
0
20
40
60
80
Temperature (°C)
100
120
140
VIT-
Figure 4. Negative-going Input Threshold VIT- Accuracy vs
Temperature
Figure 3. Low Level Output Voltage vs Supply Voltage
0.35
-20
0
20
40
60
80
Temperature (°C)
100
120
140
RSRT
Figure 6. SRT Pin Internal Resistance Overtemperature
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Typical Characteristics (continued)
Typical characteristics show the typical performance of the LP3470A device. Test conditions are at TA = TJ = 25°C (unless
otherwise noted).
5
25°C
-40°C
125°C
500
25°C
-40°C
125°C
4.5
tD with Large Capacitor (s)
tD with Small Capacitor (ms)
600
400
300
200
100
4
3.5
3
2.5
2
1.5
1
0
0.01
0.5
0.02 0.03
0.050.07 0.1
0.2 0.3
Capacitor Value (µF)
0.5 0.7
1
Figure 7. Reset Time Delay vs Small Capacitor Values
8
1
2
Dela
3
4
5
Capacitor Value (µF)
6
7
8 9 10
Dela
Figure 8. Reset Time Delay vs Large Capacitor Values
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8 Detailed Description
8.1 Overview
The LP3470A micropower voltage supervisory circuit provides a simple solution to monitor the power supplies in
microprocessor and digital systems and provides a reset controlled by the factory-programmed reset threshold
on the VCC supply voltage pin. When the voltage declines below the reset threshold, the reset signal is asserted
and remains asserted for an interval programmed by an external capacitor after VCC has risen above the
threshold voltage. The reset threshold options are 2.63 V, 2.75 V, 2.93 V, 3.08 V, 3.65 V, 4 V, 4.38 V, 4.63 V.
8.2 Functional Block Diagram
VCC1
+
VCC
Reference
±
RESET
LOGIC
TIMER
RESET
GND
RSRT
SRT
GND
8.3 Feature Description
8.3.1 RESET Time-Out Period
The reset time delay can be set to a minimum value of 50 µs by leaving the SRT pin floating, or a maximum
value of approximately 6.2 seconds by connecting 10 µF delay capacitor. The reset time delay (tD) can be
programmed by connecting a capacitor no larger than 10 µF between SRT pin and GND.
The relationship between external capacitor (CSRT) in Farads at SRT pin and the time delay (tD) in seconds is
given by Equation 1.
tD = -ln (0.29) x RSRT x CSRT + tD (no cap)
(1)
Equation 1 is simplified to Equation 2 by plugging RSRT and tD(no
cap)
given in Electrical Characteristics section:
tD = 618937 x CSRT + 50 µs
(2)
Equation 3 solves for external capacitor value (CSRT) in units of Farads where tD is in units of seconds
CSRT = (tD- 50 µs) ÷ 618937
(3)
The reset delay varies according to three variables: the external capacitor variance (CSRT), SRT pin internal
resistance (RSRT) provided in the Electrical Characteristics table, and a constant. The minimum and maximum
variance due to the constant is shown in Equation 5 and Equation 6.
tD (minimum) = -ln (0.36) x RSRT (min) x CSRT (min) + tD (no cap, min)
tD (maximum) = -ln (0.26) x RSRT (max) x CSRT (max) + tD (no cap, max)
(4)
(5)
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Feature Description (continued)
The recommended maximum delay capacitor for the LP3470A is limited to 10 µF as this ensures there is enough
time for the capacitor to fully discharge when the reset condition occurs. When a voltage fault occurs, the
previously charged up capacitor discharges, and if the monitored voltage returns from the fault condition before
the delay capacitor discharges completely, the delay capacitor will begin charging from a voltage above zero and
the reset delay will be shorter than expected. Larger delay capacitors can be used so long as the capacitor has
enough time to fully discharge during the duration of the voltage fault.
8.3.2 RESET Output
In applications like microprocessor (µP) systems, errors might occur in system operation during power up, power
down, or brownout conditions. It is imperative to monitor the power supply voltage to prevent these errors from
occurring.
The LP3470A asserts a reset signal whenever the VCC supply voltage is below a threshold (VIT-) voltage.
RESET is ensured to be a logic low for VCC > 0.95 V. Once VCC exceeds the reset threshold plus a hysteresis
voltage, the reset is kept asserted for a time period (tD) programmed by an external capacitor (CSRT); after this
interval RESET goes to logic high. If a brownout condition occurs (monitored voltage falls below the reset
threshold), RESET goes low. When VCC returns above the reset threshold plus a hysteresis voltage, RESET
remains low for a time period tD before going to logic high. Figure 9 shows this behavior.
VIT+
VIT-
VHYS
VCC
VCC(0v)
VCCmin
tD
tP_HL
tD
VOH
RESET
VOL
Figure 9. RESET Output Timing Diagram
8.3.3 Pull-up Resistor Selection
The RESET output structure of the LP3470A is an open-drain N-channel MOSFET switch. A pull-up resistor
(Rpull-up) must be connected to VCC to keep the output logic high when RESET is not asserted.
Connect the pull-up resistor to the desired pull-up voltage source and RESET can be pulled up to any voltage up
to 10 V independent of the VCC voltage. To ensure proper voltage levels, give some consideration when
choosing the pull-up resistor values. Rpull-up must be large enough to limit the current through the output within
the recommended operating conditions. The pull-up resistor value determines the actual VOL, the output
capacitive loading, and the output leakage current (ILKG(OD)). A typical pull-up resistor value of 20 kΩ is sufficient
in most applications.
8.3.4 VCC Transient Immunity
The LP3470A is immune to quick voltage transients or excursions on VCC. Sensitivity to transients depends on
both pulse duration and overdrive. Overdrive is defined by how much VCC deviates from the specified threshold.
Threshold overdrive is calculated as a percent of the threshold in question, as shown in Equation 6. A 0.1-µF
bypass capacitor mounted close to VCC provides additional transient immunity.
Overdrive = | (VCC / VIT- – 1) × 100% |
10
(6)
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Feature Description (continued)
VCC
VIT+
VIT-
VHYS
Overdrive
Pulse
Duration
Figure 10. Overdrive vs Pulse Duration
8.4 Device Functional Modes
8.4.1 RESET Output Low
When the VCC supply voltage is below the reset threshold (VIT-), the RESET pin will output logic low. RESET is
ensured to be a logic low for VCC > 0.95 V.
8.4.2 RESET Output High
When the VCC supply voltage exceeds the reset threshold (VIT-) plus the hysteresis voltage (VHYS), the RESET
remains asserted for a time period (tD) programmed by an external capacitor (CSRT); after this interval RESET
goes to logic high.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LP3470A is a micropower CMOS voltage supervisor that is ideal for use in battery-powered microprocessor
and other digital systems. It is small in size and provides voltage monitoring and supervisory functions with nanoIq and programmable delay, making it a good solution in a variety of applications. The LP3470A is available in
six standard reset threshold voltage options, and the reset time-out period is adjustable using an external
capacitor providing maximum flexibility in any application. This device can ensure system reliability and ensures
that a connected microprocessor will operate only when a minimum voltage supply is satisfied.
9.2 Typical Application
The LP3470A can be used as a simple supervisor circuit to monitor the input supply to a microprocessor as
shown in Figure 11.
IN
LDO OUT
VCC
VCC VCC1
SRT
RESET
LP3470A
Microcontroller
RESET
GND
Figure 11. Power-On Reset Circuit
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input supply voltage
0.95 to 10 V
Reset threshold voltage
2.63 V, 2.75 V, 2.93 V, 3.08 V, 3.65 V, 4 V, 4.38 V, 4.63 V
External pullup resistor
0.68 to 68 kΩ
External reset time-out period capacitor
CSRT = 1 nF
Reset time-out period
619 µs
9.2.2 Detailed Design Procedure
The minimum application circuit requires the LP3470A Power-On Reset Circuit IC and a pullup resistor
connecting the reset pin to VCC. The reset delay can be programmed with an additional capacitor connected
from the SRT pin to GND. See RESET Time-Out Period and Pull-up Resistor Selection for information on
choosing specific values for components.
12
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9.2.3 Application Curves
Two capacitor values for CSRT (0.01 µF and 1 µF) are used as examples to show the programmability of the
output time delay as shown in Figure 12 and Figure 13.
VDD
VDD
Reset Delay (tD) = 5.8 ms
Reset Delay (tD)= 654 ms
RESET
RESET
Figure 12. Reset Delay Time with 0.01-µF Capacitor at SRT
Figure 13. Reset Delay Time with 1-µF Capacitor at SRT
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10 Power Supply Recommendations
The input of the LP3470A is designed to handle up to the supply voltage absolute maximum rating of 12 V. If the
input supply is susceptible to any large transients above the maximum rating, then take extra precautions. An
input capacitor is optional but not required to help avoid false reset output triggers due to noise.
11 Layout
11.1 Layout Guidelines
•
•
•
•
Good analog design practice recommends placing a minimum of 0.1-µF ceramic capacitor as near as
possible to the VCC pin.
Place components as close as possible to the IC
Keep traces short between the IC and the CSRT capacitor to ensure the timing delay is as accurate as
possible.
For VCC slew rate > 100 mV/µs, increase input capacitance and pull-up resistor value
11.2 Layout Example
Figure 14 shows a layout example.
Figure 14. LP3470A Layout Example
14
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: LP3470A
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LP3470A263DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D263
LP3470A275DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D275
LP3470A293DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D293
LP3470A308DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D308
LP3470A365DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D365
LP3470A400DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D400
LP3470A438DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D438
LP3470A463DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D463
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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