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LP3910
SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015
LP3910 Power Management IC for Hard-Drive-Based Portable Media Players
1 Features
2 Applications
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Two Low-Dropout Regulators With Programmable
Output Voltages:
– LDO1 for General Purpose Applications
– LDO2 for Low-Noise Analog Applications
Green and Red LED-Charger Status Drivers
4-Channel 8-Bit Dual Slope
Analog-to-Digital (ADC) Converter
2 High-Efficiency DVS Buck Converters
Wide Load Range Buck-Boost DC-DC Converter
400-kHz I2C-Compatible Interface
Linear Constant-Current and Constant-Voltage
Charger for Single-Cell Lithium-Ion Batteries
USB and Adapter Charging
System Power Supply Management
Voltage and Thermal Supervisory Circuits
Continuous Battery Voltage Monitoring
Interrupt Request Output With 8 Sources
50-mΩ Battery Path Resistance
100-mA to 1000-mA Full-Rate Charge Current
Using Wall Adapter
Selectable 0.05C and 0.1C End-of-Charge (EOC)
Current
USB Current Limits of 100, 500, and 800 mA
USB Pre-Qualification Current of 50 mA
Selectable 4.1-V, 4.2-V or 4.38-V BatteryTermination Voltages
0.35% Battery-Termination Accuracy
±1 LSB INL/DNL on 8-Bit ADC
Hard Drive-Based Media Players
Portable Gaming Players
Portable Navigation Devices
3 Description
The LP3910 is a programmable system power
management unit optimized for HDD-based portable
media players. The device incorporates two lowdropout LDO voltage regulators, two integrated buck
DC-DC converters with dynamic voltage scaling
(DVS), one wide load-range buck-boost DC-DC
converter with programmable output voltage, a 4channel, 8-bit ADC, and a dual-source lithium-ion or
lithium-polymer battery charger.
The LP3910 also incorporates some advanced
battery management functions such as battery
temperature measurement, reverse current blocking
for USB, LED-charger status indication, thermally
regulated internal power FETs, battery-voltage
monitoring, overcurrent protection, and a 10-hour
safety timer. The device is programmable through a
400-kHz I2C-compatible interface.
The LP3910 is available in a thermally-enhanced
6-mm × 6-mm × 0.8-mm 48-pin WQFN package.
Device Information(1)
PART NUMBER
LP3910
PACKAGE
WQFN (48)
BODY SIZE (NOM)
6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
LP3910
USB Controller
Apps Processor
Buck1
Buck2
Memory
LDO1
Touch
LDO2
Audio
Buck-Boost
HDD
Battery
Battery Monitor
Linear Charger
ACDC Wall Adapter
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP3910
SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Tables...................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
Electrical Characteristics: I2C Interface ................... 8
Electrical Characteristics: Li-Ion Battery Charger .... 9
Detection and Timing .............................................. 10
Output Electrical Characteristics: CHG, STAT........ 10
Output Electrical Characteristics: NRST, IRQB,
ONSTAT................................................................... 10
7.11 Input Electrical Characteristics: USBSUSP,
USBISEL .................................................................. 11
7.12 Input Electrical Characteristics: POWERACK,
ONOFF, LDO2EN, BUCK1EN ................................. 11
7.13 Electrical Characteristics: LDO1 Low Dropout Linear
Regulators................................................................ 11
7.14 Electrical Characteristics: LDO2 Low Dropout Linear
Regulator.................................................................. 12
7.15 Electrical Characteristics: Buck1 Converter ......... 12
7.16 Electrical Characteristics: Buck2 Converter.......... 13
7.17 Electrical Characteristics: Buck-Boost .................. 13
7.18
7.19
7.20
7.21
8
14
14
15
16
Detailed Description ............................................ 24
8.1
8.2
8.3
8.4
8.5
8.6
9
Electrical Characteristics: ADC .............................
I2C Timing Requirements......................................
USB Timing Requirements ...................................
Typical Characteristics .........................................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
24
26
27
43
50
53
Application and Implementation ........................ 61
9.1 Application Information............................................ 61
9.2 Typical Application .................................................. 61
10 Power Supply Recommendations ..................... 68
11 Layout................................................................... 68
11.1 Layout Guidelines ................................................ 68
11.2 Layout Example ................................................... 69
11.3 Thermal Performance of the WQFN Package ...... 70
12 Device and Documentation Support ................. 71
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
71
71
71
71
71
71
13 Mechanical, Packaging, and Orderable
Information ........................................................... 71
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (March 2013) to Revision M
•
Added Device Information and Pin Configuration and Functions sections, ESD Ratings and Thermal Information
tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply
Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable
Information sections................................................................................................................................................................ 1
Changes from Revision K (February 2012) to Revision L
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 68
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SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015
5 Device Comparison Tables
Table 1. Device Default Voltage Options
LDO1
LDO2
BUCK1
BUCK2
BUCK-BOOST
ICHRG
LP3910SQ-AA
ORDER NUMBER
2V
3.3 V
1.2 V
3.3 V
3.3 V
100 mA
LP3910SQX-AA
2V
3.3 V
1.2 V
3.3 V
3.3 V
100 mA
LP3910SQ-AK
2.5 V
3V
1.6 V
1.8 V
3.3 V
100 mA
LP3910SQX-AK
2.5 V
3V
1.6 V
1.8 V
3.3 V
100 mA
LP3910SQ-AM
3.3 V
3.3 V
1.5 V
1.8 V
3.3 V
100 mA
LP3910SQX-AM
3.3 V
3.3 V
1.5 V
1.8 V
3.3 V
100 mA
LP3910SQ-AN
1.2 V
2.5 V
1V
1.8 V
3.3 V
1000 mA
LP3910SQX-AN
1.2 V
2.5 V
1V
1.8 V
3.3 V
1000 mA
Table 2. Device Option Parameters for AP Option
SYMBOL
DESCRIPTION
VALUE
LDO1
Default LDO1
2.8 V
LDO2
Default LDO2
1.5 V
Buck1
Default Buck1
1.45 V
Default Buck2
1.8 V
Buck2
Buck-Boost
Default Buck-Boost
3.3 V
Default charge current
100 mA
T1
Turnon delay for LDO1 and LDO2
6 ms
T2
Turnon delay for Buck1
3 ms
T3
Turnon delay for Buck2
1 ms
T4
Turnon delay for Buck-Boost
0 ms
T5
Turnon delay for NRST
10 ms
T1
Turnoff delay for LDO1 and LDO2
10 ms
T2
Turnoff delay for Buck1
10 ms
T3
Turnoff delay for Buck2
10 ms
T4
Turnoff delay for Buck-Boost
10 ms
T5
Turnoff delay for NRST
3 ms
battery low threshold
2.5 V
Full-rate threshold
2.55 V
Default LED current
2V
ICHRG
VBATTLOW
VFULLRATE
ILED
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LP3910
SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015
www.ti.com
The following options are programmed for the LP3910. The system designer that needs specific options is
advised to contact the local Texas Instruments sales office.
Table 3. Factory Programmable Options
FACTORY PROGRAMMABLE OPTIONS
DEFAULT VALUE (AA)
LDO1 output voltage after power up
2V
LDO2 output voltage after power up
3.3 V
BUCK1 output voltage after power up
1.2 V
BUCK2 output voltage after power up
3.3 V
BUCK-BOOST power voltage after power up
3.3 V
Battery low threshold
2.9 V
Delay for LDO1 and LDO2
5 ms
Delay for BUCK1
15 ms
Delay for BUCK2
20 ms
Delay for BUCK-BOOST
25 ms
Delay for NRST
60 ms
Default full-rate charge current
100 mA
EOC default
0.1C
VTERM default
4.2 V
ONOFF edge/level
Level
ONOFF polarity
Positive
BUCK1 enable polarity
Positive
LDO2 enable polarity
Positive
Ignore ten-hour timer
No
LED default current
10 mA
Buck-boost 500-mA output current
No
Thermistor 10 k/100 k
100 k
The I2C Chip ID address is offered as a metal mask option. The current value equals 60 hex.
4
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SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015
6 Pin Configuration and Functions
NJV Package
48-Pin WQFN
Top View
36
35
34
33
32
31
30
29
28
27
26
25
37
24
38
23
39
22
40
21
41
20
42
19
43
18
44
17
45
16
46
15
47
14
48
13
1
2
3
4
5
6
7
8
9
10
11
12
Pin Functions
PIN
NO.
NAME
I/O
TYPE (1)
DESCRIPTION
1
TS
I
A
Battery temperature sense pin. This pin is normally connected to the thermistor pin of
the battery cell.
2
VBATT1
O
A
Positive battery terminal. This pin must be externally shorted to VBATT2 and VBATT3
3
AGND
—
G
Analog ground
4
VREFH
O
A
Connection to bypass capacitor for internal high reference
5
LDO2EN
I
D
Digital input to enable/disable LDO2
6
VLDO2
O
A
LDO2 output
7
VIN1
I
PWR
8
VLDO1
O
A
Power input to LDO1 and LDO2. VIN1 pin must be externally shorted to the VDD pins.
LDO1 output
9
POWERACK
I
D
Digital power acknowledgement input (see Power-On, Power-Off Sequencing)
10
ISENSE
I
A
A 4.64-kΩ resistor must be connected between this pin and GND. A fraction of the
charge current flows through this resistor to enable the ADC to measure the charge
current.
11
ADC2
I
A
Channel 2 input to ADC
12
ADC1
I
A
Channel 1 input to ADC
Open drain active low interrupt request
Open drain active low reset during standby
13
IRQB
O
Open
Drain
14
NRST
O
Open
Drain
15
CHG
O
D
This output indicates that a valid charger supply source (USB adapter) has been
detected, and the device is charging. (Red LED)
16
STAT
O
D
Battery Status output indicator - off during constant current (CC), 50% duty cycle during
constant voltage (CV), 100% duty cycle with a fully charged Li-ion battery (Green LED)
17
BUCK1EN
I
D
Digital input to enable/disable BUCK1
18
VFB1
I
A
Buck1 Feedback input terminal
19
BCKGND1
—
G
Buck1 Ground
20
VBUCK1
O
A
Buck1 Output
(1)
A: Analog; D: Digital: G: Ground; PWR: Power
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SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015
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Pin Functions (continued)
PIN
NO.
NAME
I/O
TYPE (1)
DESCRIPTION
21
VIN2
I
PWR
Power input to Buck1. VIN2 pin must be externally shorted to the VDD pins.
22
VIN3
I
PWR
Power input to Buck2. VIN3 pin must be externally shorted to the VDD pins.
23
VBUCK2
O
A
Buck2 Output
24
BCKGND2
—
G
Buck2 Ground
25
VFB2
I
A
Buck2 Feedback input terminal
26
ONOFF
I
D
Power ONOFF pin configured either as level (High or Low) triggered or edge (High or
Low) triggered.
27
I2C_SCL
I
D
I2C-compatible interface clock terminal
28
VDDIO
I
D
Supply to input / output stages of digital I/O
29
I2C_SDA
I/O
D
I2C-compatible interface data terminal
30
ONSTAT
O
Open
Drain
31
VBBFB
I
A
Buck-Boost Feedback input terminal
32
VBBOUT
O
A
Buck-Boost Output voltage
33
VBBL2
I
A
Buck-Boost inductor
34
BBGND1
—
G
Buck-Boost high current ground
35
VBBL1
I
A
Buck-Boost inductor
36
VIN4
I
PWR
37
USBSUSP
I
D
This pin must be pulled high during USB suspend mode.
38
USBISEL
I
D
Pulling this pin low limits the USB charge current to 100 mA. Pulling this pin high limits
the USB charge current to 500 mA.
39
BBGND2
—
G
BUCK-BOOST Core Ground
40
DGND
—
G
Digital ground
41
VDD3
I
PWR
Power input to supply application. This pin must be externally shorted to VDD1 and
VDD2.
42
VDD2
I
PWR
Power input to supply application This pin must be externally shorted to VDD1 and
VDD3.
43
VBATT3
O
A
Positive battery terminal. This pin must be externally shorted to V\BATT1 and VBATT2.
44
VBATT2
O
A
Positive battery terminal. This pin must be externally shorted to VBATT1 and VBATT3.
45
USBPWR
I
PWR
USB power input pin
46
VDD1
I
PWR
Power input to supply application This pin is shorted to VDD2 and VDD3.
47
CHG_DET
I
A
Wall adapter power input pin
48
IREF
I
A
A 121-kΩ resistor must be connected between this pin and AGND. The resistor value
determines the reference current for the internal bias generator.
6
Open Drain output that reflects the debounced state of ONOFF pin.
Power input to Buck-Boost. VIN4 pin must be externally shorted to the VDD pins.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
MAX
UNIT
Supply voltage
CHG_DET
–0.3
6.5
V
Battery voltage
VBATT1, 2, 3
–0.3
5
V
USBPWR, VIN1,VIN2,VIN3,VIN4, VDD1,VDD2,VDD3
–0.3
6.2
V
All other pins
–0.3
VDD + 0.3
V
2.6
W
–45
150
ºC
Voltage
Power dissipation (TA = 70°C)
(4)
Storage temperature, Tstg
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to the potential at the GND pin.
In applications where high power dissipation or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP − (RθJA × PD-MAX).
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160°C (typical) and
disengages at TJ = 140°C (typical).
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Machine model
V
±200
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
NOM
MAX
UNIT
CHG_DET
4.5
6
V
USBPWR
4.35
6
V
VBATT1, 2, 3
0
4.5
V
VIN1, VIN2, VIN3, VIN4, VDD1, VDD2, VDD3
2.5
6
V
VDDIO
2.5
VDD
V
Junction temperature, TJ
–40
125
°C
Ambient temperature, TA
–40
85
°C
Power dissipation, TJ-MAX and TA-MAX
(1)
(2)
(3)
1.6
W
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
Minimum and maximum limits are specified by design, test, or statistical analysis. Nominal numbers are not ensured, but do represent
the most likely norm.
Nominal values and limits are for TJ = 25°C.
7.4 Thermal Information
LP3910
THERMAL METRIC
(1)
NJV (WQFN)
UNIT
48 PINS
RθJA
(1)
Junction-to-ambient thermal resistance
25
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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SNVS481M – NOVEMBER 2006 – REVISED DECEMBER 2015
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7.5 Electrical Characteristics
Unless otherwise noted, VDD = 5 V, VBATT = 3.6 V, and limits apply for TJ = 25°C. (1) (2) (3) (4)
PARAMETER
TEST CONDITIONS
MIN
IQ_BATT
Battery standby supply
current
All circuits off except for POR and battery
monitor. No adapter or USB power
connected.
IQ_BATT
Battery standby supply
current
All circuits off except for POR and battery
monitor. No adapter or USB power
connected.
TJ = 0°C to 125°C
VPOR
Power-on reset threshold
VDD falling edge
TSD
TYP
MAX
UNIT
6
20
µA
20
µA
1.9
V
Thermal shutdown
threshold
160
°C
TSDH
Thermal shutdown
hysteresis
20
°C
TTH-ALERT
Thermal interrupt threshold
VDDIO
IO supply
FCLK
Internal system clock
frequency
(1)
(2)
(3)
(4)
115
2.5
°C
VDD
2
V
MHz
All voltages are with respect to the potential at the GND pin.
Minimum and maximum limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the
most likely norm.
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
This specification is ensured by design. Not tested during production.
7.6 Electrical Characteristics: I2C Interface
Unless otherwise noted, VDDIO = 3.6 V, and minimum and maximum limits apply for TJ = 0°C to 125°C. (1) (2) (3) (4)
PARAMETER
TEST CONDITIONS
2
MIN
2
VIL
Low level input voltage
I C_SDA & I C_SCL
VIH
High level input voltage
I2C_SDA & I2C_SCL
0.7 × VDDIO
VOL
Low level output voltage
I2C_SDA & I2C_SCL
0
VHYS
(1)
(2)
(3)
(4)
8
Schmitt trigger input hysterisis
2
2
I C_SDA & I C_SCL
TYP
MAX
0.3 × VDDIO
0.1 × VDDIO
UNIT
V
V
0.2 × VDDIO
V
V
All voltages are with respect to the potential at the GND pin.
Minimum and maximum limits are specified by design, test, or statistical analysis.
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
This specification is ensured by design.
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7.7 Electrical Characteristics: Li-Ion Battery Charger
Unless otherwise noted, VDD = 5 V, VBATT = 3.6 V, CBATT = 4.7 µF, CCHG_DET = 10 µF, RIREF = 121 kΩ. Typical limits apply for
TJ = 25°C; minimum and maximum limits apply for TJ = 0°C to 125°C, unless otherwise specified. (1) (2) (3) (4)
PARAMETER
TEST CONDITIONS
VUSB
Minimum external USB
supply voltage
VUSB_HYST
USBPWR detect
hysteresis
CHG_DET
TJ = 25°C
Minimum external adapter
Adapter current limit = 1 A
supply voltage range
VFWD Schottky = 350 mV
VCHG_HYST
CHG_DET input
hysteresis
IUSB_SUSP
Quiescent current in USB
suspend mode
VTERM_TOL
Battery charge termination
voltage tolerance
(selected in CHCTL
Register (01)H Charger
Control Register)
ICHG_WA
Full-rate charging current
from wall adapter input
(see Full-Rate Charging
Mode)
ICHG_USB
Full-rate charging current
from usbpwr input (see
Full-Rate Charging Mode)
USB ILIMIT
IPREQUAL
VFULL_RATE
VTH_H
USB charge-current limit
Pre-qualification current
Full-rate qualification
threshold
Lower TS comparator limit
ITSENSE
Battery temperature sense
current
TREG
Regulated charger
junction temperature
(3)
(4)
MIN
TYP
MAX
UNIT
4.15
4.25
4.35
V
110
4.4
4.5
mV
4.6
150
USB suspend mode, VUSB = 5 V
USBSUSP = USBPWR
USBISEL = 0 V
V
mV
30
60
µA
TJ = 25°C
IPROG = 500 mA, ICHG = 50 mA
–0.35%
−0.5%
−0.5%
4.2
4.1
4.38
0.35%
0.5%
0.5%
V
TJ = 0°C to 125°C
IPROG = 500 mA, ICHG = 50 mA
–1%
–1.5%
–1.5%
4.2
4.1
4.38
1%
1.5%
1.5%
V
CHG_DET = 5.25 V
VBATT = 3.6 V, IPROG = 500 mA
450
500
550
mA
USB = 5 V, VBATT = 3.6 V
IPROG = 500 mA, USB_ISEL = 800 mA
450
500
550
mA
USB = 5 V, VBATT = 3.6 V
IPROG = 500 mA, USB_ISEL = 500 mA
405
450
495
mA
USB_ISEL = 100 mA
90
95
100
USB_ISEL = 500 mA
450
475
500
USB_ISEL = 800 mA
720
760
800
VBATT = 2.5 V, wall-adapter charge
current
Percentage of programmed full-rate
current
8%
10%
12%
VBATT = 2.5 V, USB charge current
40
50
60
VBATT rising, transition from prequalification to full-rate charging
(standard)
2.75
2.85
2.95
VBATT rising, transition from prequalification to full-rate charging (AP
version only)
2.45
2.55
Upper TS comparator limit
VTH_L
(1)
(2)
TJ = 25°C
USB current limit = 500 mA
mA
mA
V
2.65
2.82
2.87
2.93
45°C CHSPV Reg D3 = 0
0.315
0.33
0.345
50°C CHSPV Reg D3 = 1
0.255
0.27
0.285
7.75
8
8.25
µA
105
115
125
°C
TJ = 25°C
V
V
All voltages are with respect to the potential at the GND pin.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
Minimum and maximum limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the
most likely norm.
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
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7.8 Detection and Timing
Typical limits apply for TJ = 25°C; minimum and maximum limits apply for TJ = 0°C to 125°C, unless otherwise specified.
PARAMETER
IEOC
End-of-charge current
VRESTART
Battery restart charging
voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IPROG = 500 mA
10% EOC setting
40
50
60
mA
IPROG = 500 mA
5% EOC setting
20
25
30
mA
VTERM = 4.1 V
3.82
3.9
3.94
VTERM = 4.2 V
3.94
4
4.06
VTERM = 4.38 V
4.14
4.2
4.26
V
7.9 Output Electrical Characteristics: CHG, STAT
Unless otherwise noted, VDD = 5 V, VBATT = 3.6 V. CBATT = 4.7 µF, CCHG_DET = 10 µF. Typical limits apply for TJ = 25°C;
minimum and maximum limits apply for TJ = 0°C to 125°C, unless otherwise specified. (1) (2) (3) (4)
PARAMETER
ILED
Output high level
ILED
Output high level
ILEAKAGE
Leakage current
LEDFREQ
Blinking frequency
(1)
(2)
(3)
(4)
TEST CONDITIONS
VLED = 2 V
CHSPV Register (02)h bit 5 = 1
(standard)
VLED = 2 V
CHSPV Register (02)h bit 5 = 1 (AP
version only)
VLED = 2 V
CHSPV Register (02)h bit 5 = 0
(standard)
VLED = 2 V
CHSPV Register (02)h bit 5 = 0 (AP
version only)
MIN
TYP
MAX
4
5
6
UNIT
mA
0.75
1
1.25
8
10
12
1.6
2
2.4
mA
VLED = 1.5 V, LED off
0.8
0.1
5
µA
1
1.2
Hz
All voltages are with respect to the potential at the GND pin.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
Minimum and maximum limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the
most likely norm.
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
7.10 Output Electrical Characteristics: NRST, IRQB, ONSTAT
Unless otherwise noted, VDD = 5 V, VBATT = 3.6 V, CBATT = 4.7 µF, CCHG_DET = 10 µF. Minimum and maximum limits apply over
the entire junction temperature range for operation, TJ = 0°C to 125°C. (1) (2) (3) (4)
PARAMETER
TEST CONDITIONS
VOL
Output low level
IOL = 4 mA
ILEAKAGE
Leakage current
VDD = 2.5 V, output logic high
(1)
(2)
(3)
(4)
10
MIN
–1
TYP
MAX
UNIT
0.4
V
1
µA
All voltages are with respect to the potential at the GND pin.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
Minimum and maximum limits are specified by design, test, or statistical analysis.
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
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7.11 Input Electrical Characteristics: USBSUSP, USBISEL
Unless otherwise noted, VUSB = 5 V, VBATT = 3.6 V, CBATT = 4.7 µF, CCHG_DET = 10 µF. Minimum and maximum limits apply
over the entire junction temperature range for operation, TJ = 0°C to 125°C. (1) (2) (3) (4) (5)
PARAMETER
VIL
Input low level
VIH
Input high level
ILEAKAGE
Input leakage
(1)
(2)
(3)
(4)
(5)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.3 × VUSB
V
1
µA
0.7 × VUSB
V
−1
LDO2EN, BUCK1EN, and USBSUSP have weak internal pulldowns while pins POWERACK, ONOFF do not have weak pulldowns.
All voltages are with respect to the potential at the GND pin.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
Minimum and maximum limits are specified by design, test, or statistical analysis.
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
7.12 Input Electrical Characteristics: POWERACK, ONOFF, LDO2EN, BUCK1EN
Unless otherwise noted, VDD = 5 V, VBATT = 3.6 V, CBATT = 4.7 µF, CCHG_IN = 10 µF. Minimum and maximum limits apply over
the entire junction temperature range for operation, TJ = 0°C to 125°C. (1) (2) (3) (4) (5)
PARAMETER
TEST CONDITIONS
MIN
VIL
Input low level
VIH
Input high level
1.4
ILEAKAGE
Input leakage
–1
(1)
(2)
(3)
(4)
(5)
TYP
MAX
UNIT
0.4
V
V
1
µA
LDO2EN, BUCK1EN, and USBSUSP have weak internal pulldowns, while pins POWERACK, ONOFF do not have this.
All voltages are with respect to the potential at the GND pin.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
Minimum and maximum limits are specified by design, test, or statistical analysis.
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
7.13 Electrical Characteristics: LDO1 Low Dropout Linear Regulators
Unless otherwise noted, VIN1 = 3.6 V, IMAX = 150 mA, VOUT = default value, CVDD = 10 µF, CLDO1 = 1 µF, ESR = 5 mΩ – 500
mΩ, CVREFH = 100 nF. Typical limits apply for TJ = 25°C; minimum and maximum limits apply for TJ = 0°C to 125°C, unless
otherwise specified.
PARAMETER
VIN1
Operational voltage
VOUT Range
Output voltage
programming range
VOUT Accuracy Output voltage accuracy
TEST CONDITIONS
TJ = 25°C
1.2 V to 3.3 V in 100-mV steps
1 mA ≤ IOUT ≤ IMAX over full line and
load regulation.
VOUT = default value
MIN
TYP
UNIT
6
V
1.2
3.3
V
–3%
3%
Line regulation
VIN = (VOUT + 500 mV) to 5.5 V
Load current = IMAX
Load regulation
VIN = 3.6 V,
Load current = 1 mA to IMAX
ISC
Short-circuit current limit
VOUT = 0 V
VIN – VOUT
Dropout voltage
Load current = IMAX
60
PSRR
Power supply ripple
rejection
F = 10 kHz, load current = IMAX
30
RSHUNT
LDO output impedance
LDO disabled, VOUT = default value
ΔVOUT
MAX
2.5
600
3
mV
10
mV
750
mA
150
mV
dB
200
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7.14 Electrical Characteristics: LDO2 Low Dropout Linear Regulator
Unless otherwise noted VIN1 = 3.6V, IMAX = 150 mA, VOUT = default value, CVDD = 10 µF, CLDO2 = 1 µF, ESR = 5 mΩ to 500
mΩ, CVREFH = 100 nF. Typical limits apply for TJ = 25°C; minimum and maximum limits apply for TJ = 0°C to 125°C, unless
otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
VIN2
Operational voltage
VOUT range
Output voltage programming
range
TA = 25°C
1.3 V to 3.3 V in 100-mV steps
VOUT accuracy
Output voltage accuracy
(default VOUT)
1 mA ≤ IOUT ≤ IMAX over full line
and load regulation
Line regulation
VIN = (VOUT + 500 mV) to 5.5 V,
Load current = IMAX
Load regulation
VIN = 3.6 V,
Load current = 1 mA to IMAX
ISC
Short-circuit current limit
VOUT = 0 V
VIN – VOUT
Dropout voltage
Load current = IMAX
60
F = 1 kHz, load current = IMAX
50
F = 10 kHz, load current = IMAX
35
50
ΔVOUT
PSRR
Power supply ripple rejection
eN
Analog supply output noise
voltage
10 Hz < F < 100 kHz
RSHUNT
LDO output impedance
LDO disabled, VOUT = default
value
MAX
UNIT
2.5
6
V
1.3
3.3
V
–3%
3%
600
3
mV
10
mV
750
mA
150
mV
dB
µVRMS
200
Ω
7.15 Electrical Characteristics: Buck1 Converter
Unless otherwise noted, VIN2 = 3.6 V, VOUT = default value, CVIN2 = 10 µF, CSW1 = 10 µF, LSW1 = 2.2 µH. Typical limits apply
for TJ = 25°C; minimum and maximum limits apply for TJ = 0°C to 125°C, unless otherwise specified. Modulation mode is
PWM mode with automatic switch to PFM at light loads.
PARAMETER
TEST CONDITIONS
VIN2
Input voltage
VOUT range
Output voltage programming
range
TJ = 25°C
0.8 V to 2 V in 50-mV Steps
Static output voltage tolerance
IOUT = 200 mA including line and
load regulation
Line regulation
IOUT = 10 mA
VIN2 = 2.5 V − VDD
Load regulation
100 mA < IOUT < 300 mA
ΔVOUT
IOUT
IPFM
MIN
0.8
2
V
–3%
3%
0.2
850
Quiescent current
FOSC
Internal oscillator frequency
η
Peak efficiency
TON
Turnon time
(1)
This specification is ensured by design.
12
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%/V
0.002
Peak output current limit
%/mA
mA
1000
1150
75
IOUT = 0 mA
30
BUCK1 disabled
PWM mode
UNIT
V
600
IQ
MAX
6
Continuous output current
Maximum ILOAD, PFM mode
TYP
2.7
mA
mA
90
1
2
µA
MHz
90%
To 95% level (1)
1
ms
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7.16 Electrical Characteristics: Buck2 Converter
Unless otherwise noted, VIN3 = 3.6 V, VOUT = default value, CVIN3 = 10 µF, CSW1 = 10 µF, LSW2 = 2.2 µH. Typical limits apply
for TJ = 25°C; minimum and maximum limits apply for TJ = 0°C to 125°C, unless otherwise specified. Modulation mode is
PWM mode with automatic switch to PFM at light loads.
PARAMETER
TEST CONDITIONS
VIN3
Input voltage
VOUT Range
Output voltage programming
range
1.8 V – 3.3 V in 100-mV steps
Static output voltage tolerance
IOUT = 200 mA including line and
load regulation
Line regulation
IOUT = 10 mA
VIN3 = 2.5 V − VDD
Load regulation
100 mA < IOUT < 300 mA
ΔVOUT
IOUT
IPFM
0.8
2
V
–3%
3%
0.2
850
Internal oscillator frequency
Peak efficiency
TON
Turnon time
%/V
0.002
Maximum ILOAD, PFM mode
η
UNIT
V
Peak output current limit
FOSC
MAX
6
600
Quiescent current
TYP
2.7
Continuous output current
IQ
(1)
MIN
%/mA
mA
1000
1150
mA
75
IOUT = 0 mA
mA
30
90
Buck2 disabled
µA
1
PWM mode
2
MHz
90%
To 95% level (1)
1
ms
This specification is ensured by design..
7.17 Electrical Characteristics: Buck-Boost
Unless otherwise noted, VIN4 = 3.6 V, CVIN4 = 10 µF, CBB = 22 µF, LBB = 2.2 µH. Typical limits apply for TJ = 25°C; minimum
and maximum limits apply for TJ = 0°C to 125°C, unless otherwise specified. Modulation mode is PWM mode with automatic
switch to PFM at light loads.
PARAMETER
TEST CONDITIONS
V
2.7
5.7
V
1.8
3.3
V
–4%
4%
Output voltage programming
range
TJ = 25°C
1.80 V to 3.30 V in 50-mV steps
Static output voltage tolerance
IOUT = 0 mA to 1000 mA including
line and load regulation
Line regulation
IOUT = 10 mA
Load regulation
100 mA < IOUT < 1000 mA
Continuous output current
IPFM
Quiescent current
FOSC
Internal oscillator frequency
η
Peak efficiency
TON
Turnon time
(1)
0.2
%/V
0.0016
%/mA
1000
VOUT = 3.3 V
1-A load at VIN = 2.7 V
Maximum ILOAD, PFM mode
IQ
UNIT
IOUTMAX = 800 mA
VOUT Range
Peak inductor current limit
MAX
5.7
Input voltage
IOUT
TYP
2.9
VIN4
ΔVOUT
MIN
IOUTMAX = 1000 mA
mA
1800
2400
mA
75
IOUT = 0 mA PFM no switching
Buck-Boost disabled
PWM mode
mA
80
µA
1
2
MHz
93%
To 95% level (1)
1
ms
This specification is ensured by design.
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7.18 Electrical Characteristics: ADC
All limits apply for TJ = 25°C unless otherwise specified.
PARAMETER
TEST CONDITIONS
TYP
MAX
UNIT
V
1.22
1.225
1.23
TJ = 0°C to 125°C
1.2
1.225
1.23
VREF = 1.225 (1)
–1
1
LSB
DNL
Core ADC differential non-linearity VREF = 1.225 (1)
–0.5
0.5
LSB
VGP_IN
General purpose ADC input
voltage range
VREF
2 × VREF
V
VREF
Reference voltage
INL
Core ADC integral non-linearity
TJ = 25°C
MIN
V
Battery maximum voltage scalar
output
VBATT = 3.5 V
2.435
2.45
2.465
V
Battery minimum voltage scalar
output
VBATT = 2.6 V
1.217
1.225
1.232
V
Battery maximum voltage scalar
output
VBATT = 4.4 V
2.435
2.45
2.465
V
Battery minimum voltage scalar
output
VREF = 2.6 V
1.217
1.225
1.232
V
ISENSE maximum voltage scalar
output
VISENSE = 0.6463 V
ICHG = 0.605 A,
RSENSE = 4.64 kΩ
2.373
2.45
2.519
V
ISENSE minimum voltage scalar
output
VISENSE = 0 V
ICHG = 0 A,
RSENSE = 4.64 kΩ
1.186
1.225
1.260
V
ISENSE maximum voltage scalar
output
VISENSE = 1.175 V
ICHG = 1.1 A,
RSENSE = 4.64 kΩ
2.373
2.45
2.519
V
ISENSE minimum voltage scalar
output
VISENSE = 0 V
ICHG = 0 A,
RSENSE = 4.64 kΩ
1.186
1.225
1.26
V
ADC1 and
ADC2MIN
ADC1 and ADC2 minimum
voltage scalar output
VREFH = 1.225 V
1.218
1.225
1.23
V
ADC1 and
ADC2MAX
ADC1 and ADC2 maximum
voltage scalar output
VREFH = 1.225 V
2.436
2.45
2.46
V
tCONV
Conversion time (1)
tWARM
Warm-up time
VBATT,
RANGE 0
VBATT,
RANGE 1
VISENSE ,
RANGE 0
VISENSE,
RANGE 1
(1)
5
2
ms
ms
This specification is ensured by design.
7.19 I2C Timing Requirements
Unless otherwise noted, VDDIO = 3.6 V and minimum and maximum limits apply for TJ = 0°C to 125°C. (1)
MIN
NOM
MAX
UNIT
400
kHz
FCLK
Clock frequency
tBF
Bus-free time between START and STOP
1.3
µs
tHOLD
Hold time repeated START condition
0.6
µs
tCLK-LP
CLK low period
1.3
µs
tCLK-HP
CLK high period
0.6
µs
tSU
Set-up time repeated START condition
0.6
µs
tDATA-HOLD
Data hold time
0
µs
tDATA-SU
Data set-up time
100
ns
tSU
Set-up time for STOP condition
0.6
µs
tTRANS
Maximum pulse width of spikes that must be suppressed by the input filter
of both data and CLK signals
TJ = 25°C
50
µs
(1)
14
These specifications are ensured by design.
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7.20 USB Timing Requirements
Nominal limits apply for TJ = 25°C; minimum and maximum limits apply for TJ = 0°C to 125°C, unless otherwise specified.
MIN
NOM
MAX
UNIT
TCHG_IN
Deglitch adapter insertion
28
32
36
ms
TUSB
Deglitch USB power insertion
28
32
36
ms
TPQ_FULL
Deglitch time for pre-qualification to full-rate charge transition
8
10
12
ms
TFULL_PQ
Deglitch time for full-rate to pre-qualification transition
8
10
12
ms
TBATTLOWF
Deglitch time for VBATT falling below VBATTLOW threshold
4
5
6
ms
TBATTLOWR
Deglitch time for VBATT rising above VBATTLOW threshold
4
5
6
ms
TBATTEMP
Deglitch time for recovery from battery temperature fault
8
10
12
ms
TONOFF_F
Deglitching on falling edge of ONOFF pin
28
32
36
ms
TONOFF_R
Deglitching on rising edge of ONOFF pin
28
32
36
ms
TRESTART
Deglitching on falling VBATT crossing VRESTART
8
10
12
ms
TCCCV
Deglitching of CC→CV charging transition
8
10
12
ms
TCVEOC
Deglitching of CV→EOC (End of Charge)
8
10
12
ms
TPOWERACK
Deglitching of POWERACK pin
4
5
6
ms
TTSHD
Deglitching of thermal shutdown
TTOPOFF
Topoff timer
T10HR
10-hour safety timer
T1HR
1-hour prequalification safety timer
2
ms
17
21
25
min
9
10
11
hours
0.9
1
1.1
hour
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7.21 Typical Characteristics
TA = 25°C unless otherwise noted
7.21.1 Battery-Charger Characteristics
4.25
TS PIN SOURCE CURRENT (éA)
4.24
4.23
VTERM (V)
4.22
4.21
4.20
4.19
4.18
4.17
-7.50
-7.70
-7.90
-8.10
-8.30
-8.50
4.16
-20
4.15
-50
0
50
100
JUNCTION TEMPERATURE (°C)
10
150
40
70
100
130
TEMPERATURE (°C)
Figure 2. TS Pin Current vs Temperature
Figure 1. VTERM 4.2 V vs Temperature
520
25°C
0°C
125°C
-7.70
125°C
25°C
ICHG (mA)
TS PIN SOURCE CURRENT (éA)
540
-7.50
-7.90
-8.10
-20°C
500
480
-8.30
460
-8.50
4.0
4.5
5.0
5.5
440
2.75
6.0
3.00
3.25
CHG_DET PIN VOLTAGE (V)
3.50
3.75
4.00
4.25
VBATT (V)
CHG_DET = 5 V
Figure 3. TS Pin Current vs CHG_DET
CC
Figure 4. CHG vs VBATT
55.0
56.0
25°C
53.0
ICHG (mA)
ICHG (mA)
54.0
51.0
125°C
0°C
49.0
25°C
0°C
52.0
50.0
125°C
47.0
48.0
45.0
1.0
1.5
2.0
2.5
3.0
4.0
VBATT(V)
Prequal IPROG = 500 mA
CHG_DET = 5 V
5.0
USBPWR (V)
5.5
6.0
VBATT = 2.5 V Prequal
Figure 5. IU vs VBATT
16
4.5
Figure 6. ICHG vs USBPWR
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Battery-Charger Characteristics (continued)
540
540
520
520
ICHG (mA)
ICHG (mA)
0°C
500
25°C
480
125°C
500
480
460
460
440
0
440
4.0
4.5
5.0
5.5
25
50
75
100
125
150
6.0
JUNCTION TEMPERATURE (°C)
CHG_DET (V)
VBATT = 3.75 V, CC
VBATT = 3.5 V, CC
CHG_DET = 5 V
Figure 8. ICHG vs Temperature
Figure 7. ICHG vs CHG_DET
600
CHARGE CURRENT (mA)
55.0
ICHG (mA)
53.0
51.0
49.0
47.0
45.0
500
400
300
Active Thermal Regulation
200
100
0
25
50
75
100
125
0
80
150
JUNCTION TEMPERATURE (°C)
90
100
110
120
130
JUNCTION TEMPERATURE (°C)
VBATT = 3.75 V, Prequal
CHG_DET = 5 V
Figure 10. Thermal Regulation of Charge Current
Figure 9. ICHG vs Temperature
520
USB ILIMIT (mA)
500
480
460
440
420
0
25
50
75
100
125
150
JUNCTION TEMPERATURE (°C)
Ch1 = Charge Current (mA)
Ch3 = CHG_DET (V)
Figure 11. USB ILIMIT vs Temperature
Ch4 = USBPWR (V)
Figure 12. Wall Adapter Insertion With USBPWR Present
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1.0
1.0
0.5
0.5
VOUT VARIANCE (%)
VOUT VARIANCE (%)
7.21.2 LDO Characteristics
0.0
-0.5
-1.0
0.0
-0.5
-1.0
-1.5
-1.5
-2.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
-2.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
VIN = 4.3 V
VOUT = 3.3 V
TEMPERATURE (°C)
Load = 100 mA
Figure 13. Output Voltage Change vs Temperature (LDO1)
VIN = 3.6 V
VOUT = 3.3 V
Load = 0 to 100 mA
VIN = 4.3 V
VOUT = 3.3 V
Load = 150 mA
VIN = 3.6 V
VOUT = 1.8 V
Load = 0 to 100 mA
Figure 16. Load Transient (LDO2)
VIN = 3 to 4.2 V
VOUT = 1.8 V
Load = 150 mA
Figure 18. Line Transient (LDO2)
Figure 17. Line Transient (LDO1)
18
Load = 100 mA
Figure 14. Output Voltage Change vs Temperature (LDO2)
Figure 15. Load Transient (LDO1)
VIN = 3.6 to 4.5 V
VOUT = 1.8 V
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7.21.3 Buck Characteristics
3.35
2.05
IOUT = 20 mA
3.33
2.04
IOUT = 600 mA
IOUT = 300 mA
3.31
2.03 IOUT = 20 mA
VOUT (V)
VOUT (V)
IOUT = 600 mA
3.29
2.02
2.01
IOUT = 300 mA
3.27
2.00
3.0
3.25
4.0
4.3
4.6
4.9
5.2
5.5
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
VOUT = 2 V
VOUT = 3.3 V
Figure 20. Output Voltage vs Supply Voltage
Figure 19. Output Voltage vs Supply Voltage
0.825
1.25
0.820
1.24
IOUT = 600 mA
IOUT = 300 mA
0.815
VOUT (V)
VOUT (V)
1.23
IOUT = 20 mA
1.22
0.810
IOUT = 600 mA
1.21
0.805
IOUT = 300 mA
IOUT = 20 mA
1.20
3.0
3.5
4.0
4.5
5.0
0.800
5.5
3.0
4.0
4.5
5.0
5.5
VOUT = 0.8 V
VOUT = 1.2 V
Figure 22. Output Voltage vs Supply Voltage
Figure 21. Output Voltage vs Supply Voltage
100
90
Vin = 3.2 V
80
Vin = 3.2 V
90
Vin = 4 V
Vin = 4 V
80
70
EFFICIENCY (%)
Vin = 5 V
EFFICIENCY (%)
3.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
60
50
40
30
20
Vin = 5 V
70
60
50
40
30
20
10
10
0
0.1
1.0
10
100
0
1000
0.1
OUTPUT CURRENT (mA)
VOUT = 1.2 V
L = 2.2 µH
Forced PWM Mode
Figure 23. Buck1 Efficiency vs Output Current
VOUT = 2 V
1.0
10
100
OUTPUT CURRENT (mA)
L = 2.2 µH
1000
Forced PWM Mode
Figure 24. Buck 1 Efficiency vs Output Current
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Buck Characteristics (continued)
95
85
Vin = 3.2 V
Vin = 3.2 V
80
75
70
65
60
55
75
70
65
50
60
45
55
50
0.1
VOUT = 1.2 V
1.0
10
100
OUTPUT CURRENT (mA)
L = 2.2 µH
VOUT = 1.2 V
0.1
1000
PFM-to-PWM Mode
Load = 200 to 400 mA
VOUT = 2 V
Load = 0 to 400 mA
L = 2.2 µH
VIN = 4.2 V
PFM-to-PWM Mode
100
1000
PFM-to-PWM Mode
VOUT = 1.2 V
Load = 50 to 150 mA
Figure 28. Buck1 Load Transient Response
VIN = 4.2 V
PFM-to_PWM Mode
Figure 29. Buck2 Load Transient Response
20
10
Figure 26. Buck1 Efficiency vs Output Current
Figure 27. Buck1 Load Transient Response
VOUT = 3.3 V
1.0
OUTPUT CURRENT (mA)
Figure 25. Buck1 Efficiency vs Output Current
VIN = 4.2 V
PWM Mode
Vin = 5 V
80
40
VIN = 4.2 V
PWM Mode
Vin = 4 V
85
Vin = 5 V
EFFICIENCY (%)
EFFICIENCY (%)
90
Vin = 4 V
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VOUT = 3.3 V
Load = 50 to 150 mA
Figure 30. Buck2 Load Transient Response
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Buck Characteristics (continued)
VIN = 3 to 3.6 V
VOUT = 1.2 V
Load = 250 mA
VIN = 3 to 3.6 V
Figure 31. Line Transient Response
VOUT = 1.8 V
Load = 30 mA
VOUT = 3.3 V
Load = 30 mA
Load = 250 mA
Figure 32. Line Transient Response
Figure 33. Start-up into PWM Mode
VOUT = 1.8 V
VOUT = 3.3 V
Load = 30 mA
Figure 34. Start-up into PWM Mode
VOUT = 3.3 V
Figure 35. Start-up Into PFM Mode
Load = 30 mA
Figure 36. Start-up Into PFM Mode
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7.21.4 Buck-Boost Characteristics
100
100
95
80
EFFICIENCY (%)
EFFICIENCY (%)
90
VOUT = 3.3 V
85
80
VOUT = 1.8 V
75
VBATT = 2.7 V
60
VBATT = 3.3 V
40
VBATT = 4.2 V
70
20
65
0
60
2.5
3.0
3.5
4.0
4.5
5.0
0.1
5.5
VIN (V)
Figure 38. Forced PWM Efficiency vs ILOAD
Figure 37. Efficiency vs VIN
100
100
VIN = 4.2 V
VIN = 2.7 V
90
EFFICIENCY (%)
90
EFFICIENCY (%)
1000
VOUT = 3.3 V
ILOAD= 100 mA
80
VIN = 2.7 V
VIN = 3.3 V
70
60
80
VIN = 3.6 V
70
VIN = 4.2 V
60
50
50
0.1
1
10
100
1000
0.1
OUTPUT CURRENT (mA)
1000
Figure 40. Automode Efficiency vs ILOAD
Figure 39. Automode Efficiency vs ILOAD
VIN = 4.2 V
1
10
100
OUTPUT CURRENT (mA)
VOUT = 1.8 V
VOUT = 3.3 V
VOUT = 3.3 V
ILOAD = 250 mA
Figure 41. Switch Pins in Buck Mode Operation
22
1
10
100
OUTPUT CURRENT (mA)
VIN = 3.6 V
VOUT = 3.3 V
ILOAD = 250 mA
Figure 42. Switch Pin on Edge of Buck Mode Operation
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Buck-Boost Characteristics (continued)
VIN = 3.35 V
VOUT = 3.3 V
ILOAD = 250 mA
Figure 43. Switch Pin on Edge of Boost Mode Operation
VIN = 4.2 V
VOUT = 3.3 V
ILOAD = 0 to 500 mA
Figure 45. Load Transient, Buck Response
VIN = 2.7 V
VOUT = 3.3 V
ILOAD = 0 to 500 mA
VIN = 3.2 V
VOUT = 3.3 V
ILOAD = 250 mA
Figure 44. Switch Pins in Boost Mode Operationa
VIN = 3.6 V
VOUT = 3.3 V
ILOAD = 0 to 500 mA
Figure 46. Load Transient, Edge of Buck Response
VIN = 3 V to 3.6 V
Figure 47. Load Transient, Boost Response
VOUT = 3.3 V
ILOAD = 500 mA
Figure 48. Line Transient, Boost Response
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8 Detailed Description
8.1 Overview
The LP3910 incorporates 2 low-dropout LDO voltage regulators, 2 integrated buck DC-DC converters with
dynamic voltage scaling (DVS), one wide load range buck-boost DC-DC converter with programmable output
voltage, a 4-channel 8-bit ADC and a dual source Li-ion or Li-polymer battery charger. The charger has the
capability to charge and maintain a single cell battery by seamlessly switching between regulated wall adapter
and USB power sources. The LP3910 also incorporates advanced battery management functions such as battery
temperature measurement, reverse current blocking for USB, LED charger status indication, thermally regulated
internal power FETs, battery-voltage monitoring, overcurrent protection, and a 10-hour safety timer.
The buck-boost DC-DC converter targets the power management of hard disk drives and maintains a typical
operating voltage of 3.3 V ±5% with a battery voltage below or above this output level. The buck- boost output
voltage can be selected to be as low as 1.8 V.
The 4-channel ADC measures the battery voltage and charge current, which can be used for fuel gauging. Two
undedicated channels can be used to measure other analog parameters such as discharge current, battery
temperature, keyboard resistor scanning and more. The various device parameters are programmable through a
400-kHz I2C-compatible interface.
8.1.1 Two Buck Converters
The LP3910 incorporates two high efficiency synchronous switching buck regulators, Buck1 and Buck2 that
deliver a constant voltage from a wall adapter or a single Li-ion battery to the portable system processors,
memory and I/O. Using a voltage mode architecture with synchronous rectification, both bucks have the ability to
deliver up to 600 mA. Buck1 can output voltages from 0.8 V to 2 V while Buck2 can output voltages from 1.8 V to
3.3 V. Additional features include soft-start, undervoltage lockout, current-overload protection, and thermaloverload protection.
8.1.2 Buck-Boost Converter
The synchronous buck-boost magnetic DC-DC converter supplies power to a hard drive that has a typical 3.3-V
operating voltage. This voltage is lower than the maximum battery (4.2 V typically for Li-polymer cells) and higher
than the minimum battery (typically 2.8 V). Therefore, in order to provide 3.3 V, regardless of the battery voltage,
the buck-boost converter either steps down the battery voltage or steps up the battery voltage. The buck-boost
automatically switches between PWM and PFM modes depending on the load and automatically switches
between buck and boost modes depending on the battery voltage. The buck-boost converter uses an input
voltage from 2.7 V to 5.7 V and generates an output voltage between 1.8 V and 3.3 V for up to 1-A loads.
8.1.3 LDO Regulators
LDO1 is a regulator that can respond to fast transients and is slated for digital loads and high bandwidth analog
loads. LDO2 is a linear regulator with a similar architecture but has a slower transient response time with a lower
noise performance to supply analog loads. Both regulators can supply up to 150-mA loads and have output
voltages that are register programmable through the I2C interface. The LDO1 output voltage is programmable
from 1.2 V to 3.3 V, and the LDO2 output voltage is programmable in steps of 100 mV from 1.3 V to 3.3 V.
8.1.4 Battery Charger
The LP3910 can safely charge and maintain a single-cell Li-ion or Li-polymer battery operating off a regulated 6V automotive adapter, an AC wall adapter, or USB power (VBUS). Input power source selection of USB/adapter
is seamless. If present, the charger uses the adapter power regardless of the presence of USB power. The
connection of either power source is detected by LP3910. The charger module is a linear charger with constant
current pre-qualification, constant current (CC) full-rate charging and constant voltage (CV) charging. CC and CV
regulation is performed using an internal power FET Q2 with reverse current blocking. The power FET Q1 acts
as a switch with programmable current limit for USB operation.
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Overview (continued)
8.1.5 ADC
The LP3910 is equipped with an 8-bit dual-slope integrating analog-to-digital converter (ADC). Dual-slope
converters provide effective filtering of > 500-kHz and < 125-kHz noise components on the input voltage and do
not require a sample-and-hold stage. The ADC core digitizes the input voltage ranging from VREF to 2 × VREF,
where VREF is the voltage measured on the VREFH pin.
8.1.6 Supply Specification
Table 4 lists the output characteristics of various regulators.
Table 4. Supply Specification
VOUT (V)
RANGE (V)
RESOLUTION (mV)
IMAX MAXIMUM
OUTPUT CURRENT
(mA)
various
1.2 to 3.3
100
150
analog
1.3 to 3.3
100
150
600
SUPPLY
LOAD
LDO1
LDO2
DEFAULT (V)
Factory-programmed
default
Buck1
CPU, DSP
0.8 to 2
50
Buck2
I/O, logic, memory
1.8 to 3.3
100
600
Buck-Boost
HD
1.8 to 3.3
50
1000
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8.2 Functional Block Diagram
ADC1
12
36
VIN4
ADC2
11
35
VBBL1
VDD2
42
33
VBBL2
VDD3
41
32
VBBOUT
VBATT3
43
31
VBBFB
VBATT2
44
34
BBGND1
ISENSE
10
39
BBGND2
CHG_DET
47
22
VIN3
USBPWR
45
23
VBUCK2
25
VFB2
24
BCK2GND
21
VIN2
20
VBUCK1
18
VFB1
17
BUCK1EN
19
BCK1GND
5
LDO2EN
ADC
BUCK
BOOST
BUCK2
VDD1
LINEAR
CHARGER
46
VBATT1
2
TS
1
VREFH
4
BATTERY
MONITOR
BUCK1
VREFHI
OSC
IREF
48
VDDIO
28
TSD
IREF
LDO2
USBSUSP
37
6
VLDO2
USBISEL
38
7
VIN1
CHG
15
8
VLDO1
STAT
16
30
ONSTAT
ONOFF
26
14
NRST
I2C_SCL
27
13
IRQB
9
POWERACK
LDO1
LOGIC
I2C
I2C_SDA
26
29
3
40
AGND
DGND
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8.3 Feature Description
8.3.1 Buck1, Buck2: Synchronous Step-Down Magnetic DC-DC Converters
The LP3910 incorporates two high-efficiency synchronous switching buck regulators, Buck1 and
deliver a constant voltage from a wall adapter or a single Li-ion battery to the portable system
memory and I/O. Using a voltage mode architecture with synchronous rectification, both bucks have
deliver up to 600 mA depending on the input voltage and output voltage (voltage headroom), and
chosen (maximum current capability).
Buck2, that
processors,
the ability to
the inductor
There are three modes of operation depending on the current required: PWM, PFM, and shutdown. PWM mode
handles current loads of approximately 70 mA or higher, delivering voltage precision of ±3% with 90% efficiency
or better. Lighter output current loads cause the device to automatically switch into PFM for reduced current
consumption (IQ = 15 µA typical) and a longer battery life. The Standby operating mode turns off the device,
offering the lowest current consumption. PWM or PFM mode is selected automatically or PWM mode can be
forced through the setting of the buck control register.
Both Buck1 and Buck2 can operate up to a 100% duty cycle (PMOS switch always on). Additional features
include soft-start, undervoltage lockout, current overload protection, and thermal overload protection.
8.3.1.1 Buck1, Buck2 Operation
Buck1 is recommended to be used as the processor core supply and has I2C selectable output voltages ranging
from 0.8 V to 2 V (typical). Buck2 is recommended for I/O power, Memory power and logic power. Its voltage
range can be programmed using the I2C interface from 1.8 V to 3.3 V (typical). The default output voltage for
each buck converter is factory programmable (see Application and Implementation).
The system designer can also determine the output voltage of either Buck1 or Buck2 through an external
feedback resistor ladder by clearing the output voltage selection field in the Buck1 or Buck2 control registers.
Lsw
VBUCK
Load
Csw
R1
Cff
VFB
R2
BCKGND
Figure 49. External Control Of Buck Output Voltage Through Feedback Resistor Ladder
8.3.1.2 Circuit Operation Description
A buck converter contains a control block, a switching PFET connected between input and output, a synchronous
rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path. During the first
portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow
from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a
ramp with a slope of VIN – VOUT / L.
by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET
switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor
draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor
current down with a slope of –VOUT / L.
The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage
across the load.
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Feature Description (continued)
8.3.1.3 PWM Operation
During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This
allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional
to the input voltage. To eliminate this dependence, feed-forward voltage inversely proportional to the input
voltage is introduced.
8.3.1.4 Internal Synchronous Rectification
While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
8.3.1.5 Current Limiting
A current limit feature allows the buck to protect itself and external components during overload conditions PWM
mode implements cycle-by-cycle current limiting using an internal comparator that trips at 1000 mA (typical).
8.3.1.6 PFM Operation
At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply
current to maintain high efficiency.
The device automatically transitions into PFM mode when either of two conditions occurs for a duration of 32 or
more clock cycles:
The inductor current becomes discontinuous or the peak PMOS switch current drops below the IMODE level:
(Typically IMODE < 66 mA +
VIN
160:
)
(1)
During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy
load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output
FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output
voltage. If the output voltage is below the high PFM comparator threshold, the PMOS power switch is turned on.
It remains on until the output voltage exceeds the high PFM threshold or the peak current exceeds the IPFM level
set for PFM mode. The typical peak current in PFM mode is:
IPFM = 66 mA +
VIN
80:
(2)
Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps
to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output
voltage is below the high PFM comparator threshold (see Figure 50), the PMOS switch is again turned on and
the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM
threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output
switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this
sleep mode is less than 30 µA, which allows the part to achieve high efficiencies under extremely light load
conditions. When the output drops below the low PFM threshold, the cycle repeats to restore the output voltage
to approximately 1.6% above the nominal PWM output voltage.
If the load current increases during PFM mode (see Figure 50) causing the output voltage to fall below the ‘low2’
PFM threshold, the device automatically transitions into fixed-frequency PWM mode.
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Feature Description (continued)
PFM Mode at Light Load
High PFM Threshold
approx. 1.016 x VOUT
Load
current
increases
PFET on
until
Ipfm limit
reached
NFET on
drains inductor
until
I inductor=0
Current load increases,
draws VOUT towards
Low2 PFM Threshold
Low PFM
Threshold,
turn on
PFET
High PFM
Voltage
Threshold reached,
go into
sleep mode
Low1 PFM Threshold
approx. 1.008 x VOUT
Low2 PFM
Threshold VOUT
Low2 PFM
Threshold,
switch back to
PWMmode
PWM Mode at
Moderate to Heavy
Loads
Figure 50. Operation in PFM Mode and Transfer to PWM Mode
8.3.2 Buck-Boost: Synchronous Buck-Boost Magnetic DC-DC Converter
The LP3910 is equipped with a synchronous buck-boost magnetic DC-DC converter to supply power to the hard
drive that has a typical 3.3-V operating voltage. This voltage is lower than the maximum battery (4.2 V typically
for Li-polymer cells) and higher than the minimum battery (typically 2.8 V). Therefore, in order to provide 3.3 V,
regardless of the battery voltage, the Buck-Boost converter either steps down the battery voltage or steps up the
battery voltage. The Buck-Boost automatically switches between PWM and PFM modes depending on the load
and automatically switches between buck and boost modes, depending on the battery voltage.
By setting bit D6 of the Buck-Boost control register, the Buck-Boost is forced to operate using PWM modulation
regardless of the load. By default this bit is cleared.
35
VBBL
1
Lbb
2.2 PH
BUCK/
BOOST
33
VBBL
32
2
VBBOUT
VBBFB
Cbb
LOAD
22 PF
31
Figure 51. Schematic Section for Buck-Boost Operation
8.3.3 Linear Low Dropout Regulators (LDOs)
LDO1 is a regulator that can respond to fast transients and is slated for digital loads and high bandwidth analog
loads. LDO2 is a linear regulator with a similar architecture but has a slower transient response time with a lower
noise performance to supply analog loads. The output voltages of both LDOs are register programmable through
the I2C interface. The default output voltages are factory programmed during final test.
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Feature Description (continued)
VIN
VLDO
+
-
LDO
Register
controlled
VREF
Vref
AGND
Figure 52. LDO Architecture Diagram
8.3.3.1 No-Load Stability
The LDOs remain stable and in regulation with no external load. This is an important consideration in some
circuits, for example, CMOS RAM keep-alive applications.
8.3.4 Li-Ion Linear Charger
8.3.4.1 Charger Architecture
The LP3910 can safely charge and maintain a single cell Li-ion or Li-polymer battery operating from a regulated
6-V car adapter, AC wall adapter, or USB power (VBUS). Input power source selection of USB/adapter is
seamless. If present, the charger uses the adapter power regardless of the presence of USB power. The
connection of either power source is detected by the LP3910 device.
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Feature Description (continued)
External or
USB Power
Iprog
+
+
CC
+
-
Batt
Thermal
regulation
Vref
+
-
+
Current
Control
CV
Iref
Li - Ion Cell
Ts
Vbatt Vref
+
+
-
Vrestart
Charger
State
Machine and
registers
Vfull
+
-
Ref 0.27V
Batt_temp
+
-
Ref 2.87V
I2C
CV: Constant Voltage regulation
CC: Constant Current regulation
Figure 53. Charger Architecture
The charger module is a linear charger with constant current pre-qualification, CC full-rate charging and CV
charging. CC and CV regulation is performed using an internal Power FET Q2 with reverse current blocking. The
termination voltage is controlled to within ±0.35% at room temperature.
The power FET Q1 acts as a switch with programmable current limit for USB operation.
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Feature Description (continued)
VDD
Adapter
CHG_DET
USBPWR
USB
Q1
Q2
+
VBATT
Li-Ion Cell
-
Figure 54. Switches for USB Charging Path
8.3.4.2 Charge Status Indication
Two LEDs connected to the LP3910 are used to indicate the status of the charging. The CHG pin is connected to
a red LED that is enabled when an external power source is connected and the battery is charging. The second
STAT pin is connected to a green LED. When the battery charging transitions from CC to CV mode, then the
green LED is blinking with a 50% duty cycle and a period of 1 second. When the battery is fully charged, then the
green LED is always on.
Both LEDs are off when there is no external power connected.
Table 5. Truth Table for the LED Status Indicators
CONDITION
RED LED
GREEN LED
No Charger or USB
OFF
OFF
Charger off
ON
OFF
OFF
Pre-Qualification
ON
Constant Current CC
ON
OFF
Constant Voltage CV
ON
50% duty cycle
EOC / Top-OFF charging
ON
ON
Charge cycle complete
ON
ON
ERROR (Battery Temperature, Thermal shutdown)
50% duty cycle
OFF
Safety Timer Expired
50% duty cycle
OFF
50% duty cycle indicates the LED is pulsed on and off for equal times at a frequency of 1 Hz.
The RED pin and GREEN pin are connected to a regulated driver to ensure that the brightness is independent
from the external power. The LEDs need to be connected between the CHG and STAT pins and GND.
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8.3.4.3 Thermal Charger Power FET Regulation
The internal power FET Q2 in the linear charger module is thermally regulated to the junction temperature of
115°C to ensure optimal charging of the battery. The charge current is limited by the charge current selected in
the charger control register but is also thermally limited to prevent the junction from overheating during high
charge currents at high ambient temperatures as the package power dissipation is limited.
Thermal regulation ensures maximum charge current and superior charge rate without exceeding the power
dissipation limits of LP3910 device.
8.3.4.4 Battery Charger Operating Modes
8.3.4.4.1 Pre-Qualification Mode
Lithium batteries cannot be subjected to a high current when the battery voltage is under a certain threshold,
otherwise the longevity of the battery would be compromised. Below this threshold of VFULLRATE, which typically
measures 2.85 V, the charger circuit supplies a pre-qualification charge current. If the wall adapter is charging
the battery, the charger circuit supplies a constant current of 10% of the programmed charge current. If the USB
is charging the battery, the charger circuit supplies a constant 50-mA charge current. When the battery voltage
reaches VFULL_RATE, the charger transitions from pre-qualification to full-rate charging. In pre-qualification mode,
the STAT2, STAT1, and STAT0 bits in the charger supervisory register are respectively low, low, high.
8.3.4.4.2 Full-Rate Charging Mode
The full-rate charge cycle is initiated following the successful completion of the pre-qualification mode. During
full-rate charging, the battery voltage steadily increases while charged with a CC. The three charger status bits
STAT2, STAT1, and STAT0 are respectively low, high, and low. The full-rate charge current is selected using the
charge control register, which defaults to 100 mA.
Charging Li-ion batteries at a rate of 1C is recommended (where C is the capacity of the battery). As an
example, it is recommended to charge a battery with a capacity of 800 mA at 800 mA, or 1C. Charging at a
higher rate may compromise the quality and lifetime of the battery.
8.3.4.4.3 Constant-Voltage (CV) Charging Mode
The battery voltage increases rapidly as a result of full-rate charging and once it reaches the programmable
termination voltage of either 4.1 V, 4.2 V or 4.38 V, the charger moves to constant-voltage charge mode. During
this mode, the charge current gradually decreases while the battery remains at the termination voltage. The
termination voltage can be selected to be either 4.1 V, 4.2 V or 4.38 V by programming bits D6 and D7 in the
Charger Control register to accommodate different battery chemistries. In CV charging mode, the Charge Control
Status bits STAT2, STAT1 and STAT0 are respectively logic 0, logic 1, and logic 1.
8.3.4.4.4 Top-Off Charging Mode
When the charge current reduces to the EOC threshold (programmable to 5% or 10% of programmed full rate
charge current), constant voltage charging continues for an additional 21 minute TOP-OFF time period. In TOPOFF charging mode, the Charge Control Status bits STAT2, STAT1 and STAT0 are respectively logic 1, logic 1
and logic 1. At the end of the TOP-OFF period, the charger transitions to Charge Cycle Complete.
8.3.4.4.5 Charge Cycle Complete
During charge cycle complete, the charger is automatically disabled, regardless of the state of the charge enable
bit. In charge cycle complete, the STAT2, STAT1 and STAT0 bits are respectively logic 1, logic 0, and logic 1.
When the battery voltage drops below the VRESTART threshold, charging resumes in full-rate charging mode.
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Battery voltage
Battery charge current
1.0C
Termination voltage
4.1V, 4.2V or 4.38V
Charging restart voltage
3.9V, 4.0V or 4.2V
2.85V
0.1 C PREQUAL CURRENT
0.05 C EOC CURRENT
Time
0V
Pre-qualification
RED LED
GREEN LED
Full Rate
Topoff
Constant Voltage Charging
ON
ON
OFF
Battery discharge
Full Rate
End-Of-Charge
(EOC)
ON
ON
ON
OFF
50% Duty cycle
CV
Figure 55. Charge Cycle Complete
8.3.4.5 Battery Temperature Monitoring (TS Pin)
The LP3910 is equipped with a battery thermistor terminal to continuously monitor the battery temperature by
measuring the voltage between the TS pin and GND. With the TS pin connected to the battery thermistor,
charging is allowed only if the battery temperature is within the acceptable temperature range set by a pair of
internal comparators inside the LP3910. The temperature window is 0°C to 45°C or 0°C to 50°C, depending on
the setting of D2 of the charger supervisory (CHSPV) register. There is 3°C of temperature hysteresis associated
with each temperature threshold. The default temperature range is 0°C to 50°C and can be changed to 0°C to
45°C by setting bit D3 in the CHSPV register. If the battery temperature is out of range, STAT2, STAT1, and
STAT0 bits in the CHSPV register are set to logic1, logic0, logic0, and charging is suspended.
The TS pin is only active during charging and draws no current from the battery when no external power source
is present.
If the TS pin is not used in the application, it must be connected to GND through a 100-kΩ pulldown resistor.
When the TS pin is left floating (battery removal), the charger is disabled as the TS voltage exceeds the lower
temperature limit.
Ts
ntc
Logic
charger
control
+
+
-
hiRef
loRef
Figure 56. Battery Temperature Monitor with TS Pin
8.3.4.6 Disabling Charger
Charging can be safely interrupted by clearing the Charge enable bit D1 in the Charge Control Register and can
subsequently resume upon setting this bit. When the charger is disabled, STAT2, STAT1, and STAT0 bits in the
CHSPV register are set to logic 0.
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8.3.4.7 Safety Timer
In order to prevent endless charging, which could degrade the battery quality and life time, the LP3910 contains
a safety timer that limits charging regardless whether the battery has reached its full capacity or not. In
prequalification the safety timer is 1 hour. In full rate or constant voltage charging the safety timer is a maximum
of 10 hours minus the time in prequalification.
When the timer times out of uninterrupted charging, an IRQ is generated to alert system processor. The status of
the timer can also be polled by reading the IRQ register if the system doesn’t support hardware interrupts.
The safety timer resets and starts counting from zero upon the following events:
1. Power ON (through connecting valid power to either USBPWR or CHGN_IN pins).
2. Interchanging USBPWR and CHG_IN sources.
3. The voltage of a charged battery drops below the restart value, and the charger is enabled.
4. Disabling and re-enabling of the charger by toggling bit D1 of the Charge Control Register.
5. Emerging from thermal shutdown.
6. Emerging from a battery temperature out-of-range, and the charger is enabled.
7. Emerging from USB suspend mode when charging with USB power.
8.3.4.8 Charging Maintenance
When a fully charged battery is being loaded by the system while the external power is present and while bit D1
in the charge control register is set to a 1 (charge enable) then the charging restarts when the battery voltage
drops below the charging restart threshold. The value of the threshold depends on the termination voltage
according to the following table:
Table 6. Charging Thresholds
VTERM
CHARGING RESTART VOLTAGE
4.1 V
3.9 V
4.2 V
4V
4.38 V
4.2 V
8.3.5 ADC
The LP3910 is equipped with an 8-bit dual-slope integrating an ADC. Dual-slope converters provide effective
filtering of > 500-kHz and < 125-kHz noise components on the input voltage, and does not require a sample and
hold stage. The ADC core digitizes the input voltage ranging from VREF to 2VREF, where VREF is the voltage
measured on the VREFH pin. After an initial 2-ms warm-up for the first activation of the ADC enable bit, the dualslope converter integrates the input signal during the first phase for approximately 2 ms, followed by a second
phase that integrates VREF for 0 ms to 2 ms depending on the level of the input signal. As a result the total
conversion time varies from 2 ms to 4 ms.
START
Enable
8 Bit ADC
VO
Vsignal
1&2
or
1&3
2
1
Integrator
+
-
3
Comparator
Vbias
+
-
Dready
Control
Logic
Overflow
Data
Figure 57. Simplified ADC Block Diagram
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The ADC multiplexes 4 different sources:
1. The battery voltage
2. The battery charge current
3. External source ADC1
4. External source ADC2
The voltage ranges for the first two sources are scaled to match the input voltage interval of the ADC: [VREFH,
2VREFH]. This is accomplished by using two internal scalars.
8.3.5.1 Battery Voltage Measurement
The battery voltage scalar transforms the battery voltage ranging from 2.6 V to 3.5 V to the reference voltage
interval: [VREFH, 2*VREFH]. A wider voltage range (2.6 V to 4.4 V) can be selected through I2C by setting the
voltage range bit D7 in register 0xA to 0’b1.
8.3.5.2 Battery Charge Current Measurement
The battery charge current is indirectly measured by measuring the voltage across the ISENSE resistor, RSENSE.
A fixed portion of the battery charge current is mirrored over the RSENSE as in Equation 3:
VISENSE = K × ICHARGE × RSENSE
(3)
where K is a ratio between the ISENSE current and the charge current.
The battery charge current scalar transforms the voltage across the external ISENSE resistor to the [VREFH, 2 ×
VREFH] input voltage interval of the ADC.
VDD
1:4343
ADC
ISENSE
Vbatt
Rsense
Charge
control Loop
Figure 58. Battery Charge Scalar
8.3.5.3 External General-Purpose Sources
Two additional ADC sources are available on the ADC1 and ADC2 pins of the LP3910. These two external ADC
sources are not internally scaled and have an input voltage range of [VREFH, 2 × VREFH]. The system designer can
use these two sources for general-purpose applications such as resistive keyboard matrix scanning, temperature
measurements, battery load current, battery ID resistor measurement, and others.
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VBATT
ISET
MUX_CONTROL
2
Current range 0 / 1
Icharge
Scaler
Vbatt
Scaler
ADC
MUX
To ADC
core
Voltage range 0 / 1
ADC1
ADC2
Figure 59. ADC Analog Front-End Block Diagram
The source selection and the access to the conversion results are established through the I2C linked control
registers: ADCC and ADCD.
The ADC is by default disabled to minimize current consumption and must be enabled by setting D2 in the ADCC
register. Writing a logic 1 to bit D3 in the ADC initiates a conversion. It is advised to select the correct ADC
source before a conversion is started. The ADC sets bit D4 in the ADCC register upon the completion of a
conversion, which is typically 4 ms after the start of the conversion. At the same time an interrupt request is
generated. (See IRQ Register (0d)H Interrupt Request Register).
To save power, disable the ADC by setting bit 2 of D2 to 0. To make repetitive starts, set bit D3 to 0 then to 1 for
register 0Ah to initiate start of conversion. The interrupt driven protocol between LP3910 and the system
processor is the most efficient way to acquire data from successive measurements as shown in Figure 60:
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Start
I2C
transfers
CPU sends start
conversion command
to ADC
start
cid
reg
data
start
Cid/R
stop
Select adc source
ADC executes
conversion request
Conversion done
pulls down IRQB
line
System CPU
services IRQ
CPU reads data
CPU
sends next
start conversion
command
?
start
cid
reg
start
cid
reg
data
reg
stop
stop
Y
N
End
Figure 60. Data Measurement and Acquisition Sequence
8.3.6 Interrupt Request Output
The LP3910 has the ability to interrupt the system processor through the open drain IRQB pin, which transitions
to an active logic low level upon the following 8 events:
• USB Power detected
• USB disconnected
• CHG_IN Power detected
• CHG_IN disconnected
• Battery low alarm
• Thermal alarm
• ADC conversion completed
• Charger safety timer time-out
The events form the interrupt sources that correspond to a certain bit location in the interrupt request (IRQ)
register. All interrupt sources can be masked by the interrupt mask register (IMR). Masking the interrupt prevents
the interrupt event from asserting the IRQB pin, yet the event is still captured in the IRQ register, which allows
the processor to poll the interrupt sources.
After an active low IRQB has been detected by the system processor, the latter services the interrupt and
accesses the IRQ register to determine which source was responsible for the interrupt request. Reading the IRQ
register automatically clears the register to enable the capture of the next interrupt events.
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As new interrupts can occur while the I2C read cycle is clearing the IRQ register, a buffer register called interrupt
pending register (IPR), not accessible through the I2C-compatible interface holds the next interrupts. Deasserting the IRQB output is immediately followed by a new transition of IRQB to logic low when an interrupt is
pending.
The Interrupts are not hardware prioritized. It is up to the firmware to determine the priority in case more than
one interrupt request is set.
IMR
Interrupt
sources
IRQ
IRQB
int0
CHG_IN power
detected
int1
CHG_IN power
removed
int2
USB Power
detected
int3
USB Power
removed
int4
Battery Low
int5
Thermal alarm
int6
ADC conversion completed
int7
Charger
safety timer
timeout
Interrupt
Pending
register
Figure 61. Interrupt Request Setting
8.3.6.1 Interrupts and Standby Mode
Interrupts are captured in standby mode and can be serviced when the system processor is enabled when the
LP3910 is in an active state.
8.3.6.2 Interrupt Sources
• CHG_IN Power Detected and CHG_IN Disconnect (INT0 and INT1): An interrupt (INT0) is generated when
CHG_IN power is connected to the LP3910. Another interrupt (INT1) is generated upon CHG_IN power
removal.
• USB Power Detected and USB Disconnect (INT2 and INT3): An interrupt (INT2) is generated when USB
power is connected to the LP3910. Another interrupt (INT3) is generated upon disconnecting the USB power.
• Battery Low (INT4): When the battery voltage drops below the battery low threshold IRQ, an interrupt is
generated. This allows the processor to perform some routine tasks prior to going to standby mode.
• Thermal Alarm (INT5): If the junction temperature of the LP3910 exceeds 115°C, an interrupt is generated.
• ADC Conversion Done (INT6): The ADC generates an interrupt request upon the completion of a data
conversion.
• Charger Timer Interrupt (INT7): A charger timeout occurs 10 hours after it started (see Li-Ion Linear Charger)
and subsequently requests an interrupt.
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8.3.7 Power-On-Reset
The LP3910 is equipped with an internal power-on-reset (POR ) circuit that resets the logic when VDD < VPOR.
This ensures that the logic is properly initialized when VDD rises above the minimum operating voltage of the
logic and the internal oscillator that clocks the sequential logic in the control section.
8.3.8 Thermal Shutdown and Thermal Alarm
An internal temperature sensor monitors the junction temperature of the LP3910. This sensor forcibly invokes
standby mode in the unusual case of the junction temperature of the silicon exceeding the normal operating level
due to excessive loads on all power regulators, the Li-ion charger, or due to an abnormally high ambient
temperature. The thermal shutdown threshold is 160°C.
The thermal shutdown is preceded by a thermal alarm that generates an interrupt request if unmasked. The
temperature threshold for triggering the alarm is 115°C.
8.3.9 NRST Pin
The NRST pin is an open-drain output and is active low during standby, power-off and charger standby modes.
The NRST timing is determined by a factory programmable counter.
8.3.10 Operation Without I2C Interface
Operation of the LP3910 without the I2C interface is possible if the system can operate with default values for the
DC-DC converters and the charge (see Table 3). The I2C-less system must use the POWERACK pin to power
cycle the LP3910.
8.3.11 I2C Master Power Concern
The processor that contains the I2C master must be powered by BUCK1 or LDO2 as these converters require no
I2C access to enable/disable them. If the I2C master were to be powered by a DC-DC converter that is
enable/disabled through a control register, then a corrupted application software execution could by accident
disable the power to the I2C master, which in this case has no means to recover. It is possible that the regulator
connected to VDDIO may accidentally disable, in which case the processor should recognize that communication
has been broken, then power down the system to allow for a clean restart.
8.3.12 System Operation When the Load Current Exceeds the USB or Adapter Current Limit
In the event that the system requires current that exceeds the current limit of either the USB or the adapter
source, then the battery can provide the extra power provided that it has been charged. It is clear that a long
sustained overload eventually discharges the battery such that its extra power is no longer be sufficient to
properly operate the system. This is the case when the system is for instance operated from a USB host with a
100-mA current limit.
8.3.13 Power Routing
The LP3910 power can originate from three different sources: Adapter power, USB power, or battery power. The
objective of the power routing is to be able to:
• Operate the portable system from external power regardless of the battery voltage.
• Operate the portable system from USBPWR when the battery exceeds the full-rate qualification threshold
voltage (VFULLRATE).
• Concurrently charging and operating the system when external power is present
• Seamless selection of Adapter or USB power as the primary external power source
Power Routing supports 4 modes:
1. A regulated external adapter power is present and concurrently supplies the system power and the battery
charger.
2. USB power is present and supplies the system and the battery.
3. USB power is present but the system demand exceeds the USB current limit, so that the battery provides the
additional power to operate the system.
4. The battery is the sole supply source to the system when no external power source is present
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The current flows in the different modes are realized through internal FETS and an external Schottky as shown in
Figure 62:
xxxxx
xxxxx
xxxxx
xxxxx
ADAPTER
VDD
USBPWR
Q1
Q2
VBATT
+
Li - Ion Cell
-
Figure 62. Charging and Sourcing Current Paths
The current provided by the external adapter power or USB power, when inserted, first supplies the system load;
the remainder is used for charging.
The different paths are configured through two internal power FETs, Q1 and Q2, and an external Schottky diode.
Q1 is a power FET that is only active during USB charging. Q2 functions either as a linear power FET during
charging or as a low RDSON switch when no external power is present, and the battery discharges to supply
power to the system.
Table 7. Power Routing Options
POWER ROUTE
Q1
Q2
Regulated adapter supply & battery
charging
OFF
Regulated
USB supply & battery charging
ON
Regulated
No external supply and battery
discharging
OFF
ON
The power routing function allocates power to the system through the VDD pin and to the battery. VDD1, VDD2,
VDD3, VIN1, VIN2, VIN3, and VIN4 must be connected together externally. VBATT1, VBATT2, and VBATT3
must be connected together externally.
8.3.14 Battery Monitor
The battery voltage is monitored and invokes the power-off mode when the battery low threshold is breached for
more than 5 ms (typical). The battery-low threshold DEFAULT is factory programmed. The battery low threshold
range is 2.5 V to 3.5 V with steps of 50 mV. The battery-low threshold in the table below refers to a decreasing
battery voltage. The threshold when the battery voltage is transitioning out of the VBATTLOW is 50 mV (typical)
higher than the values listed in the table below due to a built-in hysteresis of 50 mV (typical).
The battery low IRQ is triggered 200 mV above the battery low alarm threshold that powers down the device.
This gives the user time for a controlled shutdown.
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8.3.15 External Power and Battery Detection
When a wall adapter is detected, regardless of the battery voltage, the LP3910 moves to the active mode and
the power-up sequencer is started. Similar to the ONOFF pin, there is a 32-ms deglitch time to ensure a clean
wall adapter detection and the system processor must set the PACK bit (D4) in the PON register or the
POWERACK pin within 128 ms (maximum) of the start of the power-up sequencer.
When USB PWR is detected, and the battery is above the low-battery-alarm threshold, the LP3910 moves to the
active mode, and the power-up sequencer is started. As with the ONOFF pin, there is a 32-ms deglitch time to
ensure a clean USB detection, and the system processor must set the PACK bit (D4) in the PON register or the
POWERACK pin within 128 ms (maximum) of the start of the power-up sequencer. If the battery is below the
low-battery-alarm threshold, the system remains powered down until the USBPWR charges the battery up to the
low-battery-alarm threshold, at which point the power-up sequencer is started.
The four LSB bits of the PON register indicate which PON source moves the LP3910 device out of standby and
into active mode:
• Battery insert
• ONOFF push button
• CHG_IN detect (connection of power adapter)
• USB power (plug-in of powered USB cable)
These bits are cleared upon powering off.
Power Up Sequence
t0 t1
t2
t3
t5
t4
CHG_DET/USBPWR
External
Events
or
32 ms
deglitch
ONOFF
ONSTAT
(To Microprocessor)
32 ms
deglitch
VLDO1, VLDO2
(If LDO2ENB is logic 1 during NRST Low,
otherwise LDO2 are register or pin enabled)
T1
VBUCK1
T2
VBUCK2
T3
BUCK/BOOST
T4
NRST
xxxxxx
xxxxxx
T5
POWERACK
(From Microprocessor)
(Bit D4 in PON register or
POWERBACK pin)
128 ms
POWERACK deadline
5 ms
VREFH
Figure 63. Power-Up Sequence
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8.3.16 USB Suspend Mode
The LP3910 USB current consumption can be disabled during suspend mode through a dedicated pin
(USBSUSP). Applying a logic 1 to this pin disables the USB current path, and current is reduced to input leakage
current less than 30 µA on the USBPWR pin.
8.3.17 Setting the USB Current Limit
The USB current that is available from the USB on the VBUS wire is limited by default to 100 mA. More current
(up to 800 mA) can be negotiated through a session request protocol between host and peripheral. The USB
current limit must be signaled to the LP3910 by means of the USBISEL pin or the ILIMIT register as indicated
below:
• If the USB current limit is 100 mA then the USB controller of the peripheral system must set the USBISEL
logic 0 or by setting the ILIMIT register bits [D1, D0] to 2’b00.
• If the USB current limit is 500 mA, the USB controller must apply logic 1 to the USBISEL pin or change the
ILIMIT register accordingly. Under this condition, the LP3910 allows charging with a charge current that is
determined by the charge control register, not exceeding 500 mA.
The LP3910 prevents (through internal circuitry) the charge current from exceeding the USB current limit, even if
the current setting in the Charge Control Register exceeds 500 mA.
The controller can also select a USB current limit of 800 mA through I2C that exceeds current USB spec values.
8.3.18 Control Registers
The LP3910 contains 14 user-programmable registers that configure the functionality of the individual modules
inside the device. Registers are programmed through an I2C interface and have default values that are invoked
during an internal reset. Some of the default values can be tailored to the specific needs of the system designer.
8.4 Device Functional Modes
The LP3910 can be in 3 different operating modes as shown in Figure 64:
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Device Functional Modes (continued)
BATTERY INSERT VBATT> VBLA
POWER OFF
No Battery
BATTERY INSERT VBATT < VBLA
POWERACK PIN AND BIT = 0
NO WA / USB
STANDBY
WA AND USB REMOVED
ONOFF AND
VBATT > VBLA
WA INSERT
USB INSERT
AND VBATT > VBLA
(CHARGING IF NEEDED)
ACTIVE
VBATT < VBLA AND NO WA
ONOFF
POWERACK PIN OR BIT = 1
WA OR USB
POWERACK PIN AND BIT
FAILED TO GO HIGH DURING
POWERUP SEQUENCE
CHG
STANDBY
WA OR USB
Figure 64. Operating Mode State Diagram
8.4.1 State Machine Definitions
VBLA
Battery low alarm threshold
VBATT
Battery voltage
WA
Wall Adapter
USB
Universal Serial Bus Adapter
ONOFF
On off pin event
POWERACK Acknowledgment from the Host Processor
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Device Functional Modes (continued)
Vterm
Active
4.2V (Typ.)
VBLA
2.4-3.5V (factory
programmable)
Standby
Vuvlo
Battery safety switch on/off threshold
2.4V (Typ.)
2.1V
Vpor
PowerOff
0.9V
Figure 65. Voltage Threshold Levels
Table 8. Power State Table
POWER OFF
STANDBY
ACTIVE
CHARGER STANDBY
LDO1,2
Off
Off
On
Off
Buck1,2
Off
Off
On
Off
Buck-Boost
Off
Off
On
Off
Charger
Off
Off
On if Charger / USB
Present
On if Charger / USB
Present
ADC
Off
Off
On
Off
NRST
Low
Low
High
Low
I2C interface
Off
Off
On
On
Internal system oscillator
Off
Off
On
On
Battery monitor
Current consumption
Off
On
On
On
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