LP875701-Q1
SNVSA05A – DECEMBER 2019 – REVISED AUGUST 2021
LP875701-Q1 Four-Phase 3-MHz 1-V 10-A DC/DC Buck Converter With Integrated
Switches
1 Features
3 Description
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•
The LP875701-Q1 device is designed to meet
the power-management requirements of the latest
processors and platforms in various automotive power
applications. The device contains four step-down
DC/DC converter cores, which are configured as a
4-phase output in forced-PWM mode. The device is
controlled by an I2C-compatible serial interface and by
enable signals.
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to +125°C
Ambient Operating Temperature
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
Input Voltage: 2.8 V to 5.5 V
Output Voltage: 1.0 V
Four High-Efficiency Step-Down DC/DC Converter
Cores:
– Maximum Output Current: 10 A (2.5 A per
Phase)
Switching Frequency: 3 MHz
Spread-Spectrum Mode and Phase Interleaving
Configurable General Purpose I/O (GPIOs)
I2C-Compatible Interface That Supports Standard
(100 kHz), Fast (400 kHz), Fast+ (1 MHz), and
High-Speed (3.4 MHz) Modes
Interrupt Function With Programmable Masking
Programmable Power-Good Signal (PGOOD)
Output Short-Circuit and Overload Protection
Overtemperature Warning and Protection
Overvoltage Protection (OVP) and Undervoltage
Lockout (UVLO)
2 Applications
•
•
•
•
Automotive Infotainment
Cluster
Radar
Camera Power Applications
The LP875701-Q1 supports remote differentialvoltage sensing for multiphase outputs to compensate
IR drop between the regulator output and the point-ofload (POL) which improves the accuracy of the output
voltage. The switching clock can be forced to PWM
mode and also synchronized to an external clock to
minimize the disturbances.
The LP875701-Q1 device supports load-current
measurement without the addition of external currentsense resistors. The LP875701-Q1 device also
supports programmable start-up and shutdown delays
and sequences synchronized to enable signals. The
sequences can also include GPIO signals to control
external regulators, load switches, and processor
reset. During start-up , the device controls the output
slew rate to minimize output-voltage overshoot and
in-rush current.
Device Information(1)
PART NUMBER
LP875701-Q1
(1)
VIN_B0
VIN_B1
VIN_B2
VIN_B3
VANA
SW_B1
VOUT
SW_B2
SW_B3
NRST
SDA
SCL
nINT
FB_B0
FB_B1
CLKIN
EN1 (GPIO1)
EN2 (GPIO2)
EN3 (GPIO3)
BODY SIZE (NOM)
4.50 mm × 4.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
100
SW_B0
90
LOAD
Efficiency (%)
VIN
PACKAGE
VQFN-HR (26)
PGOOD
FB_B2
FB_B3
80
70
60
50
GNDs
40
0.01
Copyright © 2017, Texas Instruments Incorporated
Simplified Schematic
VIN = 3.3 V
VIN = 5.0 V
0.1
1
Current (A)
10
D140
Efficiency vs Output Current
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP875701-Q1
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SNVSA05A – DECEMBER 2019 – REVISED AUGUST 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 I2C Serial Bus Timing Requirements........................ 10
6.7 Typical Characteristics.............................................. 12
7 Detailed Description......................................................13
7.1 Overview................................................................... 13
7.2 Functional Block Diagram......................................... 14
7.3 Feature Descriptions.................................................14
7.4 Device Functional Modes..........................................30
7.5 Programming............................................................ 31
7.6 Register Maps...........................................................34
8 Application and Implementation.................................. 56
8.1 Application Information............................................. 56
8.2 Typical Application.................................................... 56
9 Power Supply Recommendations................................61
10 Layout...........................................................................62
10.1 Layout Guidelines................................................... 62
10.2 Layout Example...................................................... 63
11 Device and Documentation Support..........................64
11.1 Receiving Notification of Documentation Updates.. 64
11.2 Support Resources................................................. 64
11.3 Trademarks............................................................. 64
11.4 Electrostatic Discharge Caution.............................. 64
11.5 Glossary.................................................................. 64
12 Mechanical, Packaging, and Orderable
Information.................................................................... 64
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (December 2019) to Revision A (August 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
2
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5 Pin Configuration and Functions
CLKIN
4
AGND
VIN_B3
3
22
SW_B3
EN3
23
PGND_B23
2
24
SW_B2
FB_B2
25
VIN_B2
1
26
FB_B3
21
NRST
20
nINT
19
VANA
18
AGND
SDA
PGOOD
16
7
EN1
EN2
15
8
FB_B0
FB_B1
14
VIN_B1
6
SW_B1
17
PGND_B01
AGND
SW_B0
SCL
VIN_B0
5
9
10
11
12
13
Figure 5-1. RNF Package 26-Pin VQFN-HR With Thermal Pad Top View
Table 5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
1
FB_B2
A
2
EN3
D/I/O
3
CLKIN
D/I
External clock input. Connect this pin to ground if the external clock is not used.
4, 17,
Thermal Pad
AGND
G
Ground
5
SCL
D/I
Serial interface clock input for I2C access. Connect this pin to a pullup resistor.
6
SDA
D/I/O
Serial interface data input and output for I2C access. Connect this pin to a pullup resistor.
7
EN1
D/I/O
Programmable enable signal for the buck regulators (can be also configured to select between
two buck output voltage levels). This pin functions alternatively as GPIO1.
8
FB_B0
A
Output voltage feedback (positive) for the BUCK0 converter.
9
VIN_B0
P
Input for the BUCK0 converter. The separate power pins, VIN_Bx, are not connected together
internally. The VIN_Bx pins must be connected together in the application and be locally
bypassed.
10
SW_B0
A
BUCK0 switch node
11
PGND_B01
G
Power ground for the BUCK0 and BUCK1 converters
12
SW_B1
A
BUCK1 switch node
13
VIN_B1
P
Input for the BUCK1 converter. The separate power pins, VIN_Bx, are not connected together
internally. The VIN_Bx pins must be connected together in the application and be locally
bypassed.
Output voltage feedback (positive) for the BUCK2 converter.
Programmable enable signal for the buck regulators (can be also configured to select between
two buck output-voltage levels). This pin functions alternatively as GPIO3.
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Table 5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
FB_B1
A
Output voltage feedback (positive) for the BUCK1 converter. This pin functions alternatively as the
output ground feedback (negative) for the BUCK0 converter.
15
EN2
D/I/O
Programmable enable signal for the buck regulators (can be also configured to select between
two buck output voltage levels). This pin functions alternatively as GPIO2.
16
PGOOD
D/O
Power-good indication signal
18
VANA
P
19
nINT
D/O
Open-drain interrupt output. This pin is active low.
20
NRST
D/I
Reset signal for the device
21
FB_B3
A
Output voltage feedback (positive) for the BUCK3 converter. This pin functions alternatively as the
output ground feedback (negative) for the BUCK2 converter.
22
VIN_B3
P
Input for the BUCK3 converter. The separate power pins, VIN_Bx, are not connected together
internally. The VIN_Bx pins must be connected together in the application and be locally
bypassed.
23
SW_B3
A
BUCK3 switch node
24
PGND_B23
G
Power ground for the BUCK2 and BUCK3 converters
25
SW_B2
A
BUCK2 switch node
26
VIN_B2
P
Input for the BUCK2 converter. The separate power pins, VIN_Bx, are not connected together
internally. The VIN_Bx pins must be connected together in the application and be locally
bypassed.
NO.
NAME
14
(1)
4
Supply voltage for the analog and digital blocks. This pin must be connected to the same node as
VIN_Bx.
A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
UNIT
Voltage on power connections
VIN_Bx, VANA
–0.3
6
V
Voltage on buck switch nodes
SW_Bx
–0.3
(VIN_Bx + 0.3 V)
with 6 V
maximum
V
Voltage on buck voltage sense nodes
FB_Bx
–0.3
(VANA + 0.3 V)
with 6 V
maximum
V
Voltage on NRST input
NRST
–0.3
6
V
SDA, SCL, nINT, CLKIN
–0.3
6
V
–0.3
(VANA + 0.3 V)
with 6 V
maximum
V
260
°C
Voltage on logic pins (input or output pins)
EN1 (GPIO1), EN2 (GPIO2), EN3
(GPIO3), PGOOD
Maximum lead temperature (soldering, 10 sec.)
Junction temperature, TJ-MAX
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values are with respect to network ground.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC
V(ESD)
(1)
Electrostatic
discharge
Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
UNIT
±2000
All pins
±500
Corner pins (1, 8, 14, and 21)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
2.8
5.5
V
INPUT VOLTAGE
Voltage on power connections
VIN_Bx, VANA
Voltage on NRST
NRST
1.65
VANA with
5.5 V maximum
V
Voltage on logic pins (input or output pins)
nINT, CLKIN
1.65
5.5
V
Voltage on logic pins (input or output pins)
ENx, PGOOD
0
VANA with
5.5 V maximum
V
Voltage on I2C interface, standard (100 kHz), fast (400
SCL, SDA
khz), fast+ (1 MHz), and high-speed (3.4 MHz) modes
1.65
1.95
V
Voltage on I2C interface, standard (100 kHz), fast (400
SCL, SDA
kHz), and fast+ (1 MHz) modes
3.1
VANA with
3.6 V maximum
V
Junction temperature, TJ
–40
140
°C
Ambient temperature, TA
–40
125
°C
TEMPERATURE
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6.4 Thermal Information
LP875701-Q1
THERMAL
METRIC(1)
UNIT
RNF (VQFN-HR)
26 PINS
RθJA
Junction-to-ambient thermal resistance
34.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
16.5
°C/W
RθJB
Junction-to-board thermal resistance
4.7
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
4.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
–40°C ≤ TJ ≤ +140°C, CPOL = 122 µF/phase, specified VVANA, VVIN_Bx , VNRST, VVOUT_Bx, and IOUT range, unless otherwise
noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1.0 V, unless otherwise noted.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.9
10
µF
10
22
µF
122
µF
EXTERNAL COMPONENTS
CIN
Input filtering capacitance
COUT
Output filtering capacitance
per phase, local
Connected from VIN_Bx to PGND_Bx
CPOL
Point-of-load (POL)
capacitance per phase
COUT-TOTAL
Total output capacitance(2)
4-phase output
(local and POL)
ESRC
ESR of the input and
output capacitor
L
Inductor value and
tolerance of the inductor
DCRL
Inductor DCR
400
1 MHz ≤ f ≤ 10 MHz
2
1500
µF
10
mΩ
0.33
–30%
µH
30%
20
mΩ
BUCK REGULATOR
VVIN_Bx
Input voltage range
IOUT
Output current(3)The
4-phase output, VIN ≥ 3 V
maximum output current
from device is 10A
regardless of device phase 4-phase output, 2.8 V ≤ VIN < 3 V
configurations.
2.8
Input and output voltage
difference
Minimum voltage between
VIN_x and VOUT to
fulfill the electrical
characteristics
VIN= 3.3 V +/- 5% , 5 V +/- 5%, forced
PWM mode, forced 4-phase operation, fSW=
3 MHz +/- 10% (either through internal or
external clock), in case external clock is
used: spread-spectrum disabled
Ripple voltage
4-phase output, forced PWM mode, ESRC <
2 mΩ, L = 0.33 µH
DCLNR
DC line regulation
IOUT = IOUT(max)
DCLDR
DC load regulation in PWM
0 A ≤ IOUT ≤ IOUT(max)
mode
6
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V
10
7.2
0.5
DC output voltage and
accuracy, includes voltage
reference, DC load and
line regulations, process,
and temperature
VVOUT_DC
5.5
0.985
A
V
1
3
1.015
V
mVp-p
0.1
%/V
0.01
%/A
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6.5 Electrical Characteristics (continued)
–40°C ≤ TJ ≤ +140°C, CPOL = 122 µF/phase, specified VVANA, VVIN_Bx , VNRST, VVOUT_Bx, and IOUT range, unless otherwise
noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1.0 V, unless otherwise noted.(1)
PARAMETER
TRLDSR
TRLNSR
ILIM FWD
ILIM NEG
RDS(ON) HS
FET
RDS(ON) LS
FET
fSW
Transient load step
response in PWM mode
Transient line response
TEST CONDITIONS
MIN
TYP
VIN = 5 V +/- 5%, fSW= 3 MHz +/10% (either through internal or external
clock), in case external clock is used:
spread-spectrum disabled, forced 4-phase
operation, forced PWM mode
1.5 A ≤ IOUT ≤ 7.5 A, tr = tf = 1 µs, COUT
= 22 µF/phase, L = 0.33 µH, CPOL = 122 µF/
phase
±12
VIN = 3.3 V +/- 5%, fSW= 3 MHz +/10% (either through internal or external
clock), in case external clock is used:
spread-spectrum disabled, forced 4-phase
operation, forced PWM mode
1.5 A ≤ IOUT ≤ 7.5 A, tr = tf = 1 µs, COUT
= 22 µF/phase, L = 0.33 µH, CPOL = 122 µF/
phase
±15
VVIN_Bx stepping 3.15 V ↔ 3.4 V, tr = tf = 10
µs, IOUT = IOUT(max)
±2
VVIN_Bx ≥ 3 V
Forward current limit for each phase set to
3.5A (ILIMx[2:0]=4h)
Forward current limit for
each phase (peak for each
2.8 V ≤ VVIN_Bx < 3 V
switching cycle)
Forward current limit for each phase set to
3.5A (ILIMx[2:0]=4h)
Negative current limit per
phase (peak for each
switching cycle)
MAX UNIT
mV
3.3
3.8
mV
4.2
A
2.8
3.8
4.2
1.6
2
2.4
A
On-resistance, high-side
FET
Each phase, between VIN_Bx and SW_Bx
pins, I = 1 A
29
65
mΩ
On-resistance, low-side
FET
Each phase, between SW_Bx and
PGND_Bx pins, I = 1 A
17
35
mΩ
Switching frequency, PWM
mode
2.7
Current balancing for
multiphase outputs
Current mismatch between phases, IOUT > 1
A/phase
Start-Up time (soft start)
From ENx to VOUT = 0.35 V (slew-rate
control begins), COUT_TOTAL = 144 µF/phase
3
3.3 MHz
10%
200
µs
Output voltage slew-rate(4)
3.23
3.8
4.4 mV/µs
Output pulldown resistance Regulator disabled
160
230
300
Overvoltage monitoring (compared to DC
output-voltage level, VVOUT_DC)
39
50
64
Undervoltage monitoring (compared to DC
output-voltage level, VVOUT_DC)
–53
–40
–29
Deglitch time during regulator enable
PGOOD_SET_DELAY = 0h
4
7
10
µs
Deglitch time during regulator enable
PGOOD_SET_DELAY = 1h
10
11
13
ms
4
7
10
µs
–20
–14
–8
8
14
20
Output voltage monitoring
for PGOOD pin
Deglitch time during operation and after
voltage change
Power-good threshold for
interrupt BUCKx_PG_INT,
difference from final
voltage
Rising ramp voltage, enable or voltage
change
Falling ramp voltage, voltage change
Ω
mV
mV
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6.5 Electrical Characteristics (continued)
–40°C ≤ TJ ≤ +140°C, CPOL = 122 µF/phase, specified VVANA, VVIN_Bx , VNRST, VVOUT_Bx, and IOUT range, unless otherwise
noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1.0 V, unless otherwise noted.(1)
PARAMETER
Power-good threshold
for status bit
BUCKx_PG_STAT
TEST CONDITIONS
During operation, status signal is forced to
0h during voltage change
MIN
TYP
–20
–14
MAX UNIT
–8
mV
EXTERNAL CLOCK AND PLL
Nominal frequency of the
external input clock
1
Nominal frequency step
size of the external input
clock
24 MHz
1
Required accuracy from
nominal frequency of the
external input clock
–30%
MHz
10%
Delay time for missing
external clock detection
1.8
µs
Delay and debounce time
for external clock detection
20
µs
Clock change delay
(internal to external)
delay from valid clock
detection to use of external
clock
600
µs
Cycle-to-cycle PLL output
clock jitter
300
ps, pp
PROTECTION FUNCTIONS
Thermal warning
Temperature rising, TDIE_WARN_LEVEL =
0h
115
125
135
Temperature rising, TDIE_WARN_LEVEL =
1h
127
137
147
°C
Thermal warning
hysteresis
Thermal shutdown
20
Temperature rising
140
Thermal shutdown
hysteresis
VANAOVP
VANA overvoltage
VANA undervoltage
lockout
160
20
°C
°C
Voltage rising
5.6
5.8
6.1
Voltage falling
5.45
5.73
5.96
VANA overvoltage
hysteresis
VANAUVLO
150
°C
40
V
mV
Voltage rising
2.51
2.63
2.75
Voltage falling
2.5
2.6
2.7
V
LOAD CURRENT MEASUREMENT
Current measurement
range
Output current for maximum code
Resolution
LSB
Measurement accuracy
IOUT > 1 A
Measurement time
PWM mode
20.47
20
A
mA
VANAUVLO
From any state except
SHUTDOWN
READ
OTP
REGISTER
RESET
I2C RESET
STANDBY
REGULATOR
ENABLED
REGULATORS
DISABLED
ACTIVE
Figure 7-11. Device Operation Modes
7.5 Programming
7.5.1 I2C-Compatible Interface
The I2C-compatible synchronous serial interface provides access to the programmable functions and registers
on the device. This protocol uses a two-wire interface for bidirectional communications between the devices
connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Each
device on the bus is assigned a unique address and acts as either a master or a slave depending on whether
it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed
somewhere on the line and stays HIGH even when the bus is idle. Note: CLK pin is not used for serial bus data
transfer. The LP875701-Q1 supports standard mode (100 kHz), fast mode (400 kHz), fast mode+ (1 MHz), and
high-speed mode (3.4 MHz).
7.5.1.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the
state of the data line can only be changed when clock signal is LOW.
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SCL
SDA
data
change
allowed
data
change
allowed
data
valid
data
valid
data
change
allowed
Figure 7-12. Data Validity Diagram
7.5.1.2 Start and Stop Conditions
The LP875701-Q1 is controlled through the an I2C-compatible interface. START and STOP conditions classify
the beginning and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW
while SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The
I2C master always generates the START and STOP conditions.
SDA
SCL
S
P
START
Condition
STOP
Condition
Figure 7-13. Start and Stop Sequences
The I2C bus is considered busy after a START condition and free after a STOP condition. During data
transmission the I2C master can generate repeated START conditions. A START and a repeated START
condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock
signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 7-14 shows the
SDA and SCL signal timing for the I2C-compatible bus.
tBUF
SDA
tHD;STA
trCL
tfDA
tLOW
tfCL
trDA
tSP
SCL
tHD;STA
tSU;STA
tSU;STO
tHIGH
S
tHD;DAT
START
tSU;DAT
RS
P
S
REPEATED
START
STOP
START
Figure 7-14. I2C-Compatible Timing
32
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7.5.1.3 Transferring Data
Each byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP875701-Q1
pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP875701-Q1 generates an
acknowledge after each byte has been received.
There is one exception to the acknowledge after each byte rule. When the master is the receiver, it must indicate
to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the
slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the
SDA line is not pulled down.
Note
I2C
If the NRST signal is low during
communication the LP875701-Q1 device does not drive SDA line.
The ACK signal and data transfer to the master is disabled at that time.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by
an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE and a 1
indicates a READ. The second byte selects the register to which the data will be written. The third byte contains
data to write to the selected register.
ACK from slave
ACK from slave
START
MSB Chip Address LSB
ACK from slave
W ACK MSB Register Address LSB ACK
MSB
Data LSB
ACK STOP
W ACK
address 0x40 data
ACK STOP
SCL
SDA
START
id = 0x60
address = 0x40
ACK
Figure 7-15. Write Cycle (w = write; SDA = 0), id = Device Address = 0x60 for LP875701-Q1
ACK from slave
START
MSB Chip Address LSB
W
id = 0x60
W
ACK from slave
MSB Register Address LSB
REPEATED START
ACK from slave Data from slave NACK from master
RS
MSB Chip Address LSB
R
RS
id = 0x60
R
MSB
Data
LSB
STOP
SCL
SDA
START
ACK
address = 0x3F
ACK
ACK
address 0x3F data
NACK
STOP
When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.
Figure 7-16. Read Cycle ( r = read; SDA = 1), id = Device Address = 0x60 for LP875701-Q1
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7.5.1.4 I2C-Compatible Chip Address
Note
The device address for the LP875701-Q1 is defined in the Technical Reference Manual (TRM).
After the START condition, the I2C master sends the 7-bit address followed by an eighth bit, read or write (R/W).
R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address
selects the register address to which the data will be written. The third byte contains the data for the selected
register.
MSB
1
Bit 7
LSB
1
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
R/W
Bit 0
I2C Slave Address (chip address)
A.
Here device address is 1100000Bin = 60Hex.
Figure 7-17. Example Device Address
7.5.1.5 Auto-Increment Feature
The auto-increment feature allows writing several consecutive registers within one transmission. Each time an
8-bit word is sent to the device, the internal address index counter is incremented by one and the next register is
written. Table 7-8 below shows writing sequence to two consecutive registers. Note that auto increment feature
does not work for read.
Table 7-8. Auto-Increment Example
MASTER
ACTION
START
DEVICE
ADDRESS =
0x60
LP875701-Q1
REGISTER
ADDRESS
WRITE
ACK
DATA
ACK
DATA
ACK
STOP
ACK
7.6 Register Maps
7.6.1 Register Descriptions
The LP875701-Q1 is controlled by a set of registers through the I2C-compatible interface. The device registers,
their addresses, and their abbreviations are listed in Table 7-9. A more detailed description is given in Section
7.6.1.2 through Section 7.6.1.30.
Note
This register map describes the default values for bits which are not read from OTP memory. The
orderable code and the default register bit values are defined in part number specific Technical
Reference Manual.
34
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Table 7-9. Summary of LP875701-Q1 Control Registers
Address
Register
Access
D7
0x00
DEV_REV
R
0x01
OTP_REV
R
0x02
BUCK0_CTRL1
R/W
D6
D5
DEVICE_ID[1:0]
D4
D3
D2
ALL_LAYER[1:0]
Reserved - Do not
D0
METAL_LAYER[3:0]
OTP_ID[7:0]
EN_BUCK0
EN_PIN_CTRL0
BUCK0_EN_PINSELECT[1:0]
Reserved - do not
use
0x03
D1
RW
Reserved - Do not use
RW
Reserved - Do not use
RW
Reserved - Do not use
RW
Reserved - Do not use
RW
Reserved - Do not use
RW
Reserved - Do not use
RW
Reserved - Do not use
RW
Reserved - Do not use
RW
Reserved - Do not use
RW
Reserved - Do not use
RW
Reserved - Do not use
RW
Reserved - Do not use
RW
Reserved - Do not use
EN_RDIS0
Reserved - Do not Reserved - Do not
use
use
use
0x04
Reserved - Do not
use
0x05
Reserved - Do not
use
0x06
Reserved - Do not
use
0x07
Reserved - Do not
use
0x08
Reserved - Do not
use
0x09
Reserved - Do not
use
0x0A
Reserved - Do not
use
0x0B
Reserved - Do not
use
0x0C
Reserved - Do not
use
0x0D
Reserved - Do not
use
0x0E
Reserved - Do not
use
0x0F
Reserved - Do not
use
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Table 7-9. Summary of LP875701-Q1 Control Registers (continued)
Address
0x10
Register
Access
Reserved - Do not
D7
D6
D5
D4
D3
D2
RW
Reserved - Do not use
RW
Reserved - Do not use
D1
D0
use
0x11
Reserved - Do not
use
0x12
BUCK0_DELAY
R/W
BUCK0_SHUTDOWN_DELAY[3:0]
BUCK0_STARTUP_DELAY[3:0]
0x13
Reserved - Do not
RW
Reserved - Do not use
RW
Reserved - Do not use
RW
Reserved - Do not use
use
0x14
Reserved - Do not
use
0x15
Reserved - Do not
use
0x16
GPIO2_DELAY
R/W
GPIO2_SHUTDOWN_DELAY[3:0]
GPIO2_STARTUP_DELAY[3:0]
0x17
GPIO3_DELAY
R/W
GPIO3_SHUTDOWN_DELAY[3:0]
GPIO3_STARTUP_DELAY[3:0]
0x18
RESET
R/W
0x19
CONFIG
R/W
Reserved
DOUBLE_DELAY
CLKIN_PD
Reserved
EN3_PD
SW_RESET
TDIE_WARN_LE
EN2_PD
EN1_PD
Reserved
TDIE_WARN
INT_OVP
I_LOAD_READY
VEL
0x1A
INT_TOP1
R/W
Reserved
INT_BUCK23
INT_BUCK01
NO_SYNC_CLK
TDIE_SD
0x1B
INT_TOP2
R/W
0x1C
INT_BUCK_0_1
R/W
Reserved
BUCK1_PG_INT
BUCK1_SC_INT
BUCK1_ILIM_INT
Reserved
BUCK0_PG_INT
BUCK0_SC_INT
BUCK0_ILIM_INT
0x1D
INT_BUCK_2_3
R/W
Reserved
BUCK3_PG_INT
BUCK3_SC_INT
BUCK3_ILIM_INT
Reserved
BUCK2_PG_INT
BUCK2_SC_INT
BUCK2_ILIM_INT
0x1E
TOP_STAT
R
SYNC_CLK_STA
TDIE_SD_STAT
TDIE_WARN_ST
OVP_STAT
Reserved
Reserved
BUCK0_ILIM_ST
Reserved
Reserved
RESET_REG
T
0x1F
BUCK_0_1_STAT
R
BUCK1_STAT
BUCK1_PG_STA
Reserved
T
0x20
BUCK_2_3_STAT
R
BUCK3_STAT
TOP_MASK1
R/W
Reserved
BUCK3_PG_STA
Reserved
BUCK3_ILIM_ST
Reserved
SYNC_CLK_MAS
TOP_MASK2
R/W
Reserved
BUCK0_PG_STA
T
BUCK2_STAT
AT
K
0x22
BUCK0_STAT
AT
T
0x21
BUCK1_ILIM_ST
AT
AT
BUCK2_PG_STA
Reserved
T
Reserved
BUCK2_ILIM_ST
AT
TDIE_WARN_MA
SK
Reserved
I_LOAD_READY_
MASK
RESET_REG_MA
SK
36
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Table 7-9. Summary of LP875701-Q1 Control Registers (continued)
Address
0x23
Register
BUCK_0_1_MAS
Access
D7
R/W
D6
Reserved
D5
BUCK1_PG_MAS
K
0x24
BUCK_2_3_MAS
SEL_I_LOAD
Reserved
D3
BUCK1_ILIM_MA
K
R/W
Reserved
BUCK3_PG_MAS
K
0x25
D4
D2
Reserved
D1
BUCK0_PG_MAS
SK
Reserved
BUCK3_ILIM_MA
K
Reserved
BUCK0_ILIM_MA
K
Reserved
SK
BUCK2_PG_MAS
SK
R/W
D0
Reserved
BUCK2_ILIM_MA
K
SK
Reserved
LOAD_CURRENT_BUCK_SELECT[1
:0]
0x26
I_LOAD_2
R
0x27
I_LOAD_1
R
0x28
PGOOD_CTRL1
R/W
0x29
PGOOD_CTRL2
R/W
Reserved
BUCK_LOAD_CURRENT[9:8]
BUCK_LOAD_CURRENT[7:0]
PG3_SEL[1:0]
HALF_DELAY
PG2_SEL[1:0]
EN_PG0_NINT
PG1_SEL[1:0]
PGOOD_SET_DE EN_PGFLT_STAT
Reserved
PGOOD_WINDO
LAY
0x2A
PGOOD_FLT
R
0x2B
PLL_CTRL
R/W
0x2C
PIN_FUNCTION
R/W
PGOOD_OD
PGOOD_POL
PG1_FLT
PG0_FLT
GPIO3_SEL
GPIO2_SEL
GPIO1_SEL
GPIO3_DIR
GPIO2_DIR
GPIO1_DIR
W
PG3_FLT
PLL_MODE[1:0]
PG0_SEL[1:0]
Reserved
PG2_FLT
EXT_CLK_FREQ[4:0]
EN_SPREAD_SP EN_PIN_CTRL_G EN_PIN_SELECT EN_PIN_CTRL_G EN_PIN_SELECT
EC
PIO3
_GPIO3
PIO2
_GPIO2
Reserved
GPIO3_OD
GPIO2_OD
GPIO1_OD
Reserved
0x2D
GPIO_CONFIG
R/W
0x2E
GPIO_IN
R
Reserved
GPIO3_IN
GPIO2_IN
GPIO1_IN
0x2F
GPIO_OUT
R/W
Reserved
GPIO3_OUT
GPIO2_OUT
GPIO1_OUT
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Complex bit access types are encoded to fit into small table cells. Table 7-10 shows the codes that are used for access types in this section.
Table 7-10. Access Type Codes
Access Type
Code
Description
R
R
Read
RC
R
Read
R-0
R
Read
W
W
Write
W1C
W
1C
Write
1 to clear
Read Type
Write Type
Reset or Default Value
38
-n
Value after reset or the default value
X
Value is set by OTP memory
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7.6.1.1 DEV_REV
Address: 0x00
D7
D6
D5
DEVICE_ID[1:0]
D4
D3
D2
ALL_LAYER[1:0]
D1
D0
METAL_LAYER[3:0]
Bits
Field
Type
Default
7:6
DEVICE_ID[1:0]
R
X
Device specific ID code.
Description
5:4
ALL_LAYER[1:0]
R
1h
Shows the all layer version of the device:
0h = First all layer version (ES1.0 silicon)
1h = Second all layer version (ES2.x silicon)
2h = Third all layer version
3h = Fourth all layer version
3:0
METAL_LAYER
[3:0]
R
2h
Shows the metal layer version of the device:
0h = All layer version
1h = First metal layer spin
Fh = 15th metal layer spin
7.6.1.2 OTP_REV
Address: 0x01
D7
D6
D5
D4
D3
D2
D1
D0
OTP_ID[7:0]
Bits
Field
Type
Default
7:0
OTP_ID[7:0]
R
X
Description
Identification code of the OTP EPROM version
7.6.1.3 BUCK0_CTRL1
Address: 0x02
D7
D6
D5
EN_BUCK0
EN_PIN_CTRL
0
D4
BUCK0_EN_PIN_SELECT[1:0]
D3
D2
D1
D0
Reserved
EN_RDIS0
Reserved
Reserved
Bits
Field
Type
Default
7
EN_BUCK0
R/W
X
This bit enables the BUCK0 regulator
0h = BUCK0 regulator is disabled
1h = BUCK0 regulator is enabled
Description
6
EN_PIN_CTRL0
R/W
X
This bit enables the EN1, EN2, EN3 pin control for the BUCK0 regulator
0h = Only the EN_BUCK0 bit controls the BUCK0 regulator
1h = EN_BUCK0 bit AND ENx pin control the BUCK0 regulator
5:4
BUCK0_EN_PIN_S
ELECT[1:0]
R/W
X
This bit enables the EN1, EN2, EN3 pin control for the BUCK0 regulator
0h = EN_BUCK0 bit AND EN1 pin control BUCK0
1h = EN_BUCK0 bit AND EN2 pin control BUCK0
2h = EN_BUCK0 bit AND EN3 pin control BUCK0
3h = Reserved
3
Reserved
R/W
0h
Reserved, do not use
2
EN_RDIS0
R/W
1h
This bit enables the output of the discharge resistor when the BUCK0 regulator is
disabled
0h = Discharge resistor disabled
1h = Discharge resistor enabled
1
Reserved
R/W
X
Reserved, do not use
0
Reserved
R/W
X
Reserved, do not use
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7.6.1.4 BUCK0_DELAY
Address: 0x12
D7
D6
D5
D4
D3
BUCK0_SHUTDOWN_DELAY[3:0]
D2
D1
D0
BUCK0_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
7:4
BUCK0_SHUTDOW
N_DELAY[3:0]
R/W
X
Shutdown delay of the BUCK0 regulator from the falling edge of the ENx signal (the
DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is
set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up
and Shutdown Delays table.
0h = 0 ms
1h = 1 ms
Fh = 15 ms
Description
3:0
BUCK0_STARTUP_
DELAY[3:0]
R/W
X
Start-Up delay the of the BUCK0 regulator from the rising edge of the ENx signal (the
DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is
set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up
and Shutdown Delays table.
0h = 0 ms
1h = 1 ms
Fh = 15 ms
7.6.1.5 GPIO2_DELAY
Address: 0x16
D7
D6
D5
D4
D3
GPIO2_SHUTDOWN_DELAY[3:0]
D2
D1
D0
GPIO2_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
7:4
GPIO2_SHUTDOW
N_DELAY[3:0]
R/W
X
Delay for the GPIO2 falling edge from the falling edge of the ENx signal (the
DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is
set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up
and Shutdown Delays table.
0h = 0 ms
1h = 1 ms
Fh = 15 ms
3:0
GPIO2_STARTUP_
DELAY[3:0]
R/W
X
Delay for the GPIO2 rising edge from the rising edge of the ENx signal (the
DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is
set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up
and Shutdown Delays table.
0h = 0 ms
1h = 1 ms
Fh = 15 ms
40
Description
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7.6.1.6 GPIO3_DELAY
Address: 0x17
D7
D6
D5
D4
D3
GPIO3_SHUTDOWN_DELAY[3:0]
D2
D1
D0
GPIO3_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
7:4
GPIO3_SHUTDOW
N_DELAY[3:0]
R/W
X
Delay for the GPIO3 falling edge from the falling edge of the ENx signal (the
DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is
set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up
and Shutdown Delays table.
0h = 0 ms
1h = 1 ms
Fh = 15 ms
Description
3:0
GPIO3_STARTUP_
DELAY[3:0]
R/W
X
Delay for GPIO3 rising edge from rising edge of ENx signal (the DOUBLE_DELAY
bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the
PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown
Delays table.
0h = 0 ms
1h = 1 ms
. Fh = 15 ms
7.6.1.7 RESET
Address: 0x18
D7
D6
D5
D4
D3
D2
Reserved
Bits
Field
Type
Default
7:1
Reserved
R/W
0h
0
SW_RESET
R/W
0h
D1
D0
SW_RESET
Description
Software commanded reset. When this bit is written to 1h, the registers are reset to
the default values, OTP memory is read, and the I2C interface is reset.
The bit is automatically cleared.
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7.6.1.8 CONFIG
Address: 0x19
D7
D6
D5
D4
D3
D2
D1
D0
DOUBLE_DEL
AY
CLKIN_PD
Reserved
EN3_PD
TDIE_WARN_
LEVEL
EN2_PD
EN1_PD
Reserved
Bits
Field
Type
Default
7
DOUBLE_DELAY
R/W
X
Start-Up and shutdown delays from the ENx signals
0h = 0 ms to 15 ms with 1-ms steps
1h = 0 ms to 30 ms with 2-ms steps
6
CLKIN_PD
R/W
X
This bit selects the pulldown resistor on the CLKIN input pin.
0h = Pulldown resistor is disabled
1h = Pulldown resistor is enabled
5
Reserved
R/W
0h
4
EN3_PD
R/W
X
This bit selects the pulldown resistor on the EN3 (GPIO3) input pin.
0h = Pulldown resistor is disabled
1h = Pulldown resistor is enabled
3
TDIE_WARN_LEVE
L
R/W
X
Thermal warning threshold level
0h = 125°C
1h = 137°C
2
EN2_PD
R/W
X
This bit selects the pulldown resistor on the EN2 (GPIO2) input pin.
0h = Pulldown resistor is disabled
1h = Pulldown resistor is enabled
1
EN1_PD
R/W
X
This bit selects the pulldown resistor on the EN1 (GPIO1) input pin.
0h = Pulldown resistor is disabled
1h = Pulldown resistor is enabled
0
Reserved
R/W
0h
42
Description
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7.6.1.9 INT_TOP1
Address: 0x1A
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
INT_BUCK23
INT_BUCK01
NO_SYNC_CL
K
TDIE_SD
TDIE_WARN
INT_OVP
I_LOAD_READ
Y
Bits
Field
Type
Default
Description
7
Reserved
R/W
0h
6
INT_BUCK23
R
0h
Interrupt indicating that the output of the BUCK3 regulator,BUCK2 regulator, or both
regulators has a pending interrupt. The reason for the interrupt is indicated in the
INT_BUCK_2_3 register.
This bit is cleared automatically when the INT_BUCK_2_3 register is cleared to 0x00.
5
INT_BUCK01
R
0h
Interrupt indicating that the output of the BUCK1 regulator, BUCK0 regulator, or both
regulators has a pending interrupt. The reason for the interrupt is indicated in the
INT_BUCK_0_1 register.
This bit is cleared automatically when the INT_BUCK_0_1 register is cleared to 0x00.
4
NO_SYNC_CLK
R/W1C
0h
Latched status bit indicating that the external clock is not valid.
Write this bit to 1h to clear the interrupt.
3
TDIE_SD
R/W1C
0h
Latched status bit indicating that the die junction temperature is greater than the
thermal shutdown level. The regulators are disabled if previously enabled. The
regulators cannot be enabled if this bit is active. The actual status of the thermal
warning condition is indicated by the TDIE_SD_STAT bit in the TOP_STAT register.
Write this bit to 1h to clear the interrupt.
2
TDIE_WARN
R/W1C
0h
Latched status bit indicating that the die junction temperature is greater than the
thermal warning level. The actual status of the thermal warning condition is indicated
by the TDIE_WARN_STAT bit in the TOP_STAT register.
Write this bit to 1h to clear the interrupt.
1
INT_OVP
R/W1C
0h
Latched status bit indicating that the input voltage is greater than the overvoltagedetection level. The actual status of the overvoltage condition is indicated by the
OVP_STAT bit in the OP_STAT register.
Write this bit to 1h to clear the interrupt.
0
I_LOAD_READY
R/W1C
0h
Latched status bit indicating that the load-current measurement result is available in
the I_LOAD_1 and I_LOAD_2 registers.
Write this bit to 1h to clear the interrupt.
7.6.1.10 INT_TOP2
Address: 0x1B
D7
D6
D5
D4
D3
D2
Reserved
Bits
Field
Type
Default
7:1
Reserved
R/W
0h
0
RESET_REG
R/W1C
0h
D1
D0
RESET_REG
Description
Latched status bit indicating that either start-up (NRST rising edge) is done, VANA
supply voltage is less than the undervoltage threshold level, or the host has
requested a reset (the SW_RESET bit in the RESET register). The regulators are
disabled, the registers are reset to default values, and the normal start-up procedure
is done.
Write this bit to 1h to clear the interrupt.
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7.6.1.11 INT_BUCK_0_1
Address: 0x1C
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK1_PG
_INT
BUCK1_SC
_INT
BUCK1_ILIM
_INT
Reserved
BUCK0_PG
_INT
BUCK0_SC
_INT
BUCK0_ILIM
_INT
Bits
44
Field
Type
Default
Description
7
Reserved
R/W
0h
6
BUCK1_PG_INT
R/W1C
0h
Latched status bit indicating that the BUCK1 output voltage reached the power-goodthreshold level.
Write this bit to 1h to clear.
5
BUCK1_SC_INT
R/W1C
0h
Latched status bit indicating that the BUCK1 output voltage has fallen to less than the
0.35-V level during operation or the BUCK1 output did not reach the 0.35-V level in 1
ms from enable.
Write this bit to 1h to clear.
4
BUCK1_ILIM_INT
R/W1C
0h
Latched status bit indicating that output current limit is active.
Write this bit to 1h to clear.
3
Reserved
R/W
0h
2
BUCK0_PG_INT
R/W1C
0h
Latched status bit indicating that the BUCK0 output voltage reached power-goodthreshold level.
Write this bit to 1h to clear.
1
BUCK0_SC_INT
R/W1C
0h
Latched status bit indicating that the BUCK0 output voltage has fallen to less than the
0.35-V level during operation or the BUCK0 output did not reach the 0.35-V level in 1
ms from enable.
Write this bit to 1h to clear.
0
BUCK0_ILIM_INT
R/W1C
0h
Latched status bit indicating that output current limit is active.
Write this bit to 1h to clear.
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7.6.1.12 INT_BUCK_2_3
Address: 0x1D
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK3_PG
_INT
BUCK3_SC
_INT
BUCK3_ILIM
_INT
Reserved
BUCK2_PG
_INT
BUCK2_SC
_INT
BUCK2_ILIM
_INT
Bits
Field
Type
Default
Description
7
Reserved
R/W
0h
6
BUCK3_PG_INT
R/W1C
0h
Latched status bit indicating that the BUCK3 output voltage reached the power-goodthreshold level.
Write this bit to 1h to clear.
5
BUCK3_SC_INT
R/W1C
0h
Latched status bit indicating that the BUCK3 output voltage has fallen to less than the
0.35-V level during operation or the BUCK3 output did not reach the 0.35-V level in 1
ms from enable.
Write this bit to 1h to clear.
4
BUCK3_ILIM_INT
R/W1C
0h
Latched status bit indicating that the output current limit is active.
Write this bit to 1h to clear.
3
Reserved
R/W
0h
2
BUCK2_PG_INT
R/W1C
0h
Latched status bit indicating that the BUCK2 output voltage reached the power-goodthreshold level.
Write this bit to 1h to clear.
1
BUCK2_SC_INT
R/W1C
0h
Latched status bit indicating that the BUCK2 output voltage has fallen to less than the
0.35-V level during operation or the BUCK2 output did not reach the 0.35-V level in 1
ms from enable.
Write this bit to 1h to clear.
0
BUCK2_ILIM_INT
R/W1C
0h
Latched status bit indicating that the output current limit is active.
Write this bit to 1h to clear.
7.6.1.13 TOP_STAT
Address: 0x1E
D7
D6
D5
Reserved
Bits
D4
D3
D2
D1
D0
SYNC_CLK
_STAT
TDIE_SD
_STAT
TDIE_WARN
_STAT
OVP_STAT
Reserved
Field
Type
Default
Description
7:5
Reserved
R
0h
4
SYNC_CLK_STAT
R
0h
Status bit indicating the status of the external clock (CLKIN).
0h = External clock frequency is valid
1h = External clock frequency is not valid
3
TDIE_SD_STAT
R
0h
Status bit indicating the status of the thermal shutdown condition.
0h = Die temperature is less than the thermal shutdown level
1h = Die temperature is greater than the thermal shutdown level
2
TDIE_WARN_STAT
R
0h
Status bit indicating the status of thermal warning condition.
0h = Die temperature is less than the thermal warning level
1h = Die temperature is greater than the thermal warning level
1
OVP_STAT
R
0h
Status bit indicating the status of input overvoltage monitoring.
0h = Input voltage is less than the overvoltage threshold level
1h = Input voltage is greater than the overvoltage threshold level
0
Reserved
R
0h
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7.6.1.14 BUCK_0_1_STAT
Address: 0x1F
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_STAT
BUCK1_PG
_STAT
Reserved
BUCK1_ILIM
_STAT
BUCK0_STAT
BUCK0_PG
_STAT
Reserved
BUCK0_ILIM
_STAT
Bits
Field
Type
Default
7
BUCK1_STAT
R
0
Status bit indicating the enable or disable status of the BUCK1 regulator.
0h = BUCK1 regulator is disabled
1h = BUCK1 regulator is enabled
6
BUCK1_PG_STAT
R
0
Status bit indicating the validity of the BUCK1 output voltage (raw status).
0h = BUCK1 output is less than the power-good-threshold level
1h = BUCK1 output is greater than the power-good-threshold level
5
Reserved
R
0
4
BUCK1_ILIM_STAT
R
0
Status bit indicating the BUCK1 current limit status (raw status).
0h = BUCK1 output current is less than the current limit level
1h = BUCK1 output current limit is active
3
BUCK0_STAT
R
0
Status bit indicating the enable or disable status of the BUCK0 regulator.
0h = BUCK0 regulator is disabled
1h = BUCK0 regulator is enabled
2
BUCK0_PG_STAT
R
0
Status bit indicating the validity of the BUCK0 output voltage (raw status).
0h = BUCK0 output is less than the power-good-threshold level
1h = BUCK0 output is greater than the power-good-threshold level
1
Reserved
R
0
0
BUCK0_ILIM_STAT
R
0
46
Description
Status bit indicating the BUCK0 current limit status (raw status).
0h = BUCK0 output current is less than the current limit level
1h = BUCK0 output current limit is active
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7.6.1.15 BUCK_2_3_STAT
Address: 0x20
D7
D6
D5
D4
D3
D2
D1
D0
BUCK3_STAT
BUCK3_PG
_STAT
Reserved
BUCK3_ILIM
_STAT
BUCK2_STAT
BUCK2_PG
_STAT
Reserved
BUCK2_ILIM
_STAT
Bits
Field
Type
Default
Description
7
BUCK3_STAT
R
0
Status bit indicating the enable or disable status of the BUCK3 regulator.
0h = BUCK3 regulator is disabled
1h = BUCK3 regulator is enabled
6
BUCK3_PG_STAT
R
0
Status bit indicating the validity of the BUCK3 output voltage (raw status).
0h = BUCK3 output is less than the power-good-threshold level
1h = BUCK3 output is greater than the power-good-threshold level
5
Reserved
R
0
4
BUCK3_ILIM_STAT
R
0
Status bit indicating the BUCK3 current limit status (raw status).
0h = BUCK3 output current is less than the current limit level
1h = BUCK3 output current limit is active
3
BUCK2_STAT
R
0
Status bit indicating the enable or disable status of the BUCK2 regulator.
0h = BUCK2 regulator is disabled
1h = BUCK2 regulator is enabled
2
BUCK2_PG_STAT
R
0
Status bit indicating the validity of the BUCK2 output voltage (raw status)
0h = BUCK2 output is less than the power-good-threshold level
1h = BUCK2 output is greater than the power-good-threshold level
1
Reserved
R
0
0
BUCK2_ILIM_STAT
R
0
Status bit indicating the BUCK2 current limit status (raw status).
0h = BUCK2 output current is less than the current limit level
1h = BUCK2 output current limit is active
7.6.1.16 TOP_MASK1
Address: 0x21
D7
D6
Reserved
D5
Reserved
Bits
Field
Type
Default
7
Reserved
R/W
1h
6:5
Reserved
R/W
0h
4
SYNC_CLK_MASK
R/W
X
3
Reserved
R/W
0h
2
TDIE_WARN_MAS
K
R/W
X
1
Reserved
R/W
0
0
I_LOAD_READY_M
ASK
R/W
X
D4
D3
D2
D1
D0
SYNC_CLK
_MASK
Reserved
TDIE_WARN
_MASK
Reserved
I_LOAD_
READY_MASK
Description
Masking for the external clock detection interrupt (the NO_SYNC_CLK bit in the
INT_TOP1 register)
0h = Interrupt generated
1h = Interrupt not generated
Masking for the thermal warning interrupt (the TDIE_WARN bit in the INT_TOP1
register)
This bit does not affect TDIE_WARN_STAT status bit in the TOP_STAT register.
0h = Interrupt generated
1h = Interrupt not generated
Masking for the load-current measurement-ready interrupt (the I_LOAD_READY bit in
the INT_TOP register).
0h = Interrupt generated
1h = Interrupt not generated
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7.6.1.17 TOP_MASK2
Address: 0x22
D7
D6
D5
D4
D3
D2
D1
Reserved
Bits
Field
Type
Default
7:1
Reserved
R/W
0h
0
RESET_REG_MAS
K
R/W
X
D0
RESET_REG
_MASK
Description
Masking for the register reset interrupt (the RESET_REG bit in the INT_TOP2
register)
0h = Interrupt generated
1h = Interrupt not generated
7.6.1.18 BUCK_0_1_MASK
Address: 0x23
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK1_PG
_MASK
Reserved
BUCK1_ILIM
_MASK
Reserved
BUCK0_PG
_MASK
Reserved
BUCK0_ILIM
_MASK
Bits
Field
Type
Default
7
Reserved
R/W
0h
6
BUCK1_PG_MASK
R/W
X
48
5
Reserved
R
0h
4
BUCK1_ILIM_MAS
K
R/W
X
3
Reserved
R/W
0h
2
BUCK0_PG_MASK
R/W
X
1
Reserved
R
0h
0
BUCK0_ILIM_MAS
K
R/W
X
Description
Masking for the BUCK1 power-good interrupt (the BUCK1_PG_INT bit in the
INT_BUCK_0_1 register)
This bit does not affect BUCK1_PG_STAT status bit in BUCK_0_1_STAT register.
0h = Interrupt generated
1h = Interrupt not generated
Masking for the BUCK1 current-limit-detection interrupt (the BUCK1_ILIM_INT bit in
the INT_BUCK_0_1 register)
This bit does not affect the BUCK1_ILIM_STAT status bit in the BUCK_0_1_STAT
register.
0h = Interrupt generated
1h = Interrupt not generated
Masking for the BUCK0 power-good interrupt (the BUCK0_PG_INT bit in the
INT_BUCK_0_1 register)
This bit does not affect the BUCK0_PG_STAT status bit in the BUCK_0_1_STAT
register.
0h = Interrupt generated
1h = Interrupt not generated
Masking for the BUCK0 current-limit-detection interrupt (the BUCK0_ILIM_INT bit in
the INT_BUCK_0_1 register)
This bit does not affect the BUCK0_ILIM_STAT status bit in the BUCK_0_1_STAT
register.
0h = Interrupt generated
1h = Interrupt not generated
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7.6.1.19 BUCK_2_3_MASK
Address: 0x24
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK3_PG
_MASK
Reserved
BUCK3_ILIM
_MASK
Reserved
BUCK2_PG
_MASK
Reserved
BUCK2_ILIM
_MASK
Bits
Field
Type
Default
7
Reserved
R/W
0h
6
BUCK3_PG_MASK
R/W
X
5
Reserved
R
0h
4
BUCK3_ILIM_MAS
K
R/W
X
3
Reserved
R/W
0h
2
BUCK2_PG_MASK
R/W
X
1
Reserved
R
0h
0
BUCK2_ILIM_MAS
K
R/W
X
Description
Masking for the BUCK3 power-good interrupt (the BUCK3_PG_INT bit in the
INT_BUCK_2_3 register)
This bit does not affect the BUCK3_PG_STAT status bit in the BUCK_2_3_STAT
register.
0h = Interrupt generated
1h = Interrupt not generated
Masking for the BUCK3 current-limit-detection interrupt (the BUCK3_ILIM_INT bit in
the INT_BUCK_2_3 register)
This bit does not affect the BUCK3_ILIM_STAT status bit in the BUCK_2_3_STAT
register.
0h = Interrupt generated
1h = Interrupt not generated
Masking for the BUCK2 power-good interrupt (the BUCK2_PG_INT bit in the
INT_BUCK_2_3 register)
This bit does not affect the BUCK2_PG_STAT status bit in the BUCK_2_3_STAT
register.
0h = Interrupt generated
1h = Interrupt not generated
Masking for the BUCK2 current limit-detection interrupt (the BUCK2_ILIM_INT bit in
the INT_BUCK_2_3 register)
This bit does not affect the BUCK2_ILIM_STAT status bit in the BUCK_2_3_STAT
register.
0h = Interrupt generated
1h = Interrupt not generated
7.6.1.20 SEL_I_LOAD
Address: 0x25
D7
D6
D5
D4
D3
D2
Reserved
Bits
Field
Type
Default
7:2
Reserved
R/W
0h
1:0
LOAD_CURRENT_
BUCK_SELECT[1:0
]
R/W
0h
D1
D0
LOAD_CURRENT_BUCK
_SELECT[1:0]
Description
This bit starts the current measurement on the selected regulator.
One measurement is started when the register is written.
If the selected buck is a master, the measurement result is the sum of the current of
both the master and slave bucks.
If the selected buck is a slave, the measurement result is the current of the selected
slave bucks.
0h = BUCK0
1h = BUCK1
2h = BUCK2
3h = BUCK3
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7.6.1.21 I_LOAD_2
Address: 0x26
D7
D6
D5
D4
D3
D2
D1
Reserved
Bits
Field
Type
Default
7:2
Reserved
R
0h
1:0
BUCK_LOAD_CUR
RENT[9:8]
R
0h
D0
BUCK_LOAD_CURRENT[9:8]
Description
This register describes the three MSB bits of the average load current on the selected
regulator with a resolution of 20 mA per LSB and maximum code corresponding to a
20.47-A current.
7.6.1.22 I_LOAD_1
Address: 0x27
D7
D6
D5
D4
D3
D2
D1
D0
BUCK_LOAD_CURRENT[7:0]
Bits
Field
Type
Default
Description
7:0
BUCK_LOAD_CUR
RENT[7:0]
R
0x00
This register describes the eight LSB bits of the average load current on the selected
regulator with a resolution of 20 mA per LSB and maximum code corresponding to a
20.47-A current.
7.6.1.23 PGOOD_CTRL1
Address: 0x28
D7
D6
D5
PG3_SEL[1:0]
D4
PG2_SEL[1:0]
D3
D2
D1
PG1_SEL[1:0]
PG0_SEL[1:0]
Bits
Field
Type
Default
7:6
PG3_SEL[1:0]
R/W
X
PGOOD signal source control from the BUCK3 regulator
0h = Masked
1h = Power-good-threshold voltage
2h = Reserved, do not use
3h = Power-good-threshold voltage AND current limit
5:4
PG2_SEL[1:0]
R/W
X
PGOOD signal source control from the BUCK2 regulator
0h = Masked
1h = Power-good-threshold voltage
2h = Reserved, do not use
3h = Power-good threshold voltage AND current limit
3:2
PG1_SEL[1:0]
R/W
X
PGOOD signal source control from the BUCK1 regulator
0h = Masked
1h = Power-good-threshold voltage
2h = Reserved, do not use
3h = Power-good-threshold voltage AND current limit
1:0
PG0_SEL[1:0]
R/W
X
PGOOD signal source control from the BUCK0 regulator
0h = Masked
1h = Power-good-threshold voltage
2h = Reserved, do not use
3h = Power-good-threshold voltage AND current limit
50
D0
Description
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7.6.1.24 PGOOD_CTRL2
Address: 0x29
D7
D6
D5
D4
D3
D2
D1
D0
HALF_DELAY
EN_PG0
_NINT
PGOOD_SET
_DELAY
EN_PGFLT
_STAT
Reserved
PGOOD_
WINDOW
PGOOD_OD
PGOOD_POL
Bits
Field
Type
Default
Description
7
HALF_DELAY
R/W
X
This bit elects the time step for the start-up and shutdown delays.
0h = Start-Up and shutdown delays have 0.5-ms or 1-ms time steps, based on the
DOUBLE_DELAY bit in the CONFIG register.
1h = Start-Up and shutdown delays have 0.32-ms or 0.64-ms time steps, based on
the DOUBLE_DELAY bit in the CONFIG register.
6
EN_PG0_NINT
R/W
X
This bit combines theBUCK0 PGOOD signal with the nINT signal
0h = BUCK0 PGOOD signal not included with the nINT signal
1h = BUCK0 PGOOD signal included with the nINT signal. If the nINT OR the BUCK0
PGOOD signal is low then the nINT signal is low.
5
PGOOD_SET_DEL
AY
R/W
X
Debounce time of the output voltage monitoring for the PGOOD signal (only when the
PGOOD signal goes valid)
0h = 4-10 µs
1h = 11 ms
4
EN_PGFLT_STAT
R/W
X
Operation mode for PGOOD signal
0h = Indicates live status of monitored voltage outputs
1h = Indicates status of the PGOOD_FLT register, inactive if at least one of the
PGx_FLT bit is inactive
3
Reserved
R/W
0h
2
PGOOD_WINDOW
R/W
X
Voltage monitoring method for the PGOOD signal
0h = Only undervoltage monitoring
1h = Overvoltage and undervoltage monitoring
1
PGOOD_OD
R/W
X
PGOOD signal type
0h = Push-pull output (VANA level)
1h = Open-drain output
0
PGOOD_POL
R/W
X
PGOOD signal polarity
0h = PGOOD signal high when monitored outputs are valid
1h = PGOOD signal low when monitored outputs are valid
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7.6.1.25 PGOOD_FLT
Address: 0x2A
D7
D6
D5
D4
Reserved
D3
D2
D1
D0
PG3_FLT
PG2_FLT
PG1_FLT
PG0_FLT
Bits
Field
Type
Default
7:4
Reserved
R/W
0x0
Description
3
PG3_FLT
R
0
Source for the PGOOD inactive signal
0h = BUCK3 has not set the PGOOD signal inactive.
1h = BUCK3 has set the PGOOD signal inactive. This bit can be cleared by reading
this register when the BUCK3 output is valid.
2
PG2_FLT
R
0
Source for the PGOOD inactive signal
0h = BUCK2 has not set the PGOOD signal inactive.
1h = BUCK2 has set the PGOOD signal inactive. This bit can be cleared by reading
this register when the BUCK2 output is valid.
1
PG1_FLT
R
0
Source for the PGOOD inactive signal
0h = BUCK1 has not set the PGOOD signal inactive.
1h = BUCK1 has set the PGOOD signal inactive. This bit can be cleared by reading
this register when the BUCK1 output is valid.
0
PG0_FLT
R
0
Source for the PGOOD inactive signal
0h = BUCK0 has not set the PGOOD signal inactive.
1h = BUCK0 has set the PGOOD signal inactive. This bit can be cleared by reading
this register when the BUCK0 output is valid.
7.6.1.26 PLL_CTRL
Address: 0x2B
D7
D6
D5
PLL_MODE[1:0]
D4
Reserved
Bits
Field
Type
Default
7:6
PLL_MODE[1:0]
R/W
X
5
Reserved
R/W
0
4:0
EXT_CLK_FREQ[4:
0]
R/W
X
52
D3
D2
D1
D0
EXT_CLK_FREQ[4:0]
Description
This bit selects the external clock and PLL operation.
0h = Forced to internal RC oscillator (PLL is disabled).
1h = PLL is enabled in the STANDBY and ACTIVE states. Automatic external clock
use when available, interrupt generated if external clock appears or disappears.
2h = PLL is enabled only in the ACTIVE state. Automatic external clock use when
available, interrupt generated if external clock appears or disappears.
3h = Reserved
Frequency of the external clock (CLKIN). For the input clock frequency tolerance see
the Electrical Characteristics table. Settings 18h through 1Fh are reserved and must
not be used.
0x00h = 1 MHz
0x01h = 2 MHz
2h = 3 MHz
16h = 23 MHz
17h = 24 MHz .
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7.6.1.27 PIN_FUNCTION
Address: 0x2C
D7
D6
D5
D4
D3
D2
D1
D0
EN_SPREAD_
SPEC
EN_PIN_CTRL
_GPIO3
EN_PIN_SELE
CT_GPIO3
EN_PIN_CTRL
_GPIO2
EN_PIN_SELE
CT_GPIO2
GPIO3_SEL
GPIO2_SEL
GPIO1_SEL
Bits
Field
Type
Default
Description
7
EN_SPREAD_SPE
C
R/W
X
This bit enables the spread-spectrum feature.
0h = Disabled
1h = Enabled
6
EN_PIN_CTRL_GPI
O3
R/W
X
This bit enables EN1 and EN2 pin control for GPIO3 (the GPIO3_SEL bit is set to 1h
AND the GPIO3_DIR bit is set to 1h).
0h = Only GPIO3_OUT bit controls GPIO3
1h = GPIO3_OUT bit AND ENx pin control GPIO3
5
EN_PIN_SELECT_
GPIO3
R/W
X
This bit enables EN1 and EN2 pin control for GPIO3.
0h = GPIO3_SEL bit AND EN1 pin control GPIO3
1h = GPIO3_SEL bit AND EN2 pin control GPIO3
4
EN_PIN_CTRL_GPI
O2
R/W
X
This bit enables EN1 and EN3 pin control for GPIO2 (the GPIO2_SEL bit is set to 1h
AND the GPIO2_DIR bit is set to 1h).
0h = Only GPIO2_OUT bit controls GPIO2
1h = GPIO2_OUT bit AND ENx pin control GPIO2
3
EN_PIN_SELECT_
GPIO2
R/W
X
This bit enables EN1 and EN3 pin control for GPIO2
0h = GPIO2_SEL bit AND EN1 pin control GPIO2
1h = GPIO2_SEL bit AND EN3 pin control GPIO2
2
GPIO3_SEL
R/W
X
This bit selects the EN3 pin function
0h = EN3
1h = GPIO3
1
GPIO2_SEL
R/W
X
This bit selects the EN2 pin function
0h = EN2
1h = GPIO2
0
GPIO1_SEL
R/W
X
This bit selects the EN1 pin function
0h = EN1
1h = GPIO1
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7.6.1.28 GPIO_CONFIG
Address: 0x2D
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
GPIO3_OD
GPIO2_OD
GPIO1_OD
Reserved
GPIO3_DIR
GPIO2_DIR
GPIO1_DIR
D2
D1
D0
GPIO3_IN
GPIO2_IN
GPIO1_IN
Bits
Field
Type
Default
7
Reserved
R
0h
Description
6
GPIO3_OD
R/W
X
GPIO3 signal type when configured as an output
0h = Push-pull output (VANA level)
1h = Open-drain output
5
GPIO2_OD
R/W
X
GPIO2 signal type when configured as an output
0h = Push-pull output (VANA level)
1h = Open-drain output
4
GPIO1_OD
R/W
X
GPIO1 signal type when configured as an output
0h = Push-pull output (VANA level)
1h = Open-drain output
3
Reserved
R
0h
2
GPIO3_DIR
R/W
X
GPIO3 signal direction
0h = Input
1h = Output
1
GPIO2_DIR
R/W
X
GPIO2 signal direction
0h = Input
1h = Output
0
GPIO1_DIR
R/W
X
GPIO1 signal direction
0h = Input
1h = Output
7.6.1.29 GPIO_IN
Address: 0x2E
D7
D6
D5
D4
D3
Reserved
Bits
Field
Type
Default
7:3
Reserved
R
0h
2
GPIO3_IN
R
0h
State of the GPIO3 signal
0h = Logic-low level
1h = Logic high level
1
GPIO2_IN
R
0h
State of the GPIO2 signal
0h = Logic-low level
1h = Logic-high level
0
GPIO1_IN
R
0h
State of the GPIO1 signal
0h = Logic-low level
1h = Logic-high level
54
Description
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7.6.1.30 GPIO_OUT
Address: 0x2F
D7
D6
D5
D4
D3
Reserved
D2
D1
D0
GPIO3_OUT
GPIO2_OUT
GPIO1_OUT
Bits
Field
Type
Default
7:3
Reserved
R/W
0h
Description
2
GPIO3_OUT
R/W
X
Control for theGPIO3 signal when configured as the GPIO output
0h = Logic-low level
1h = Logic-high level
1
GPIO2_OUT
R/W
X
Control for the GPIO2 signal when configured as the GPIO output
0h = Logic-low level
1h = Logic-high level
0
GPIO1_OUT
R/W
0h
Control for theGPIO1 signal when configured as the GPIO output
0h = Logic-low level
1h = Logic-high level
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The LP875701-Q1 is a multiphase step-down converter with four switcher cores, which is configured as a single
output 4-phase regulator.
8.2 Typical Application
R0
VIN
VIN_B0
CIN0 CIN1 CIN2 CIN3
SW_B0
C0
L0
VIN_B1
R1
VIN_B2
SW_B1
VIN_B3
C1
L1
VOUT0
VANA
CVANA
NRST
SDA
SCL
nINT
CLKIN
PGOOD
EN1 (GPIO1)
EN2 (GPIO2)
EN3 (GPIO3)
LOAD
R2
SW_B2
L2
C2
COUT0 COUT1 COUT2 COUT3
CPOL0
R3
SW_B3
FB_B0
FB_B1
FB_B2
FB_B3
C3
L3
GNDs
Copyright © 2017, Texas Instruments Incorporated
Figure 8-1. 4-Phase Configuration
8.2.1 Design Requirements
8.2.1.1 Inductor Selection
The inductors are L0, L1, L2, and L3 are shown in Section 8.2. The inductance and DCR of the inductor affects
the control loop of the buck regulator. TI recommends using inductors similar to those listed in Table 8-1. Pay
attention to the saturation current and temperature rise current of the inductor. Check that the saturation current
is higher than the peak current limit and the temperature rise current is higher than the maximum expected rms
output current. The minimum effective inductance to make sure performance is good is 0.22 μH at maximum
peak output current over the operating temperature range. DC resistance of the inductor must be less than
0.05 Ω for good efficiency at high-current condition. The inductor AC loss (resistance) also affects conversion
efficiency. Higher Q factor at switching frequency usually gives better efficiency at light load to middle load.
Shielded inductors are preferred as they radiate less noise.
56
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Table 8-1. Recommended Inductors
MANUFACTURER
Murata
(1)
PART NUMBER
VALUE
DFE252012PD-R33M 0.33 µH (20%)
DIMENSIONS
L × W × H (mm)
RATED DC CURRENT,
ISAT maximum (typical) / ITEMP
maximum (typical) (A)
DCR typical /
maximum
(mΩ)
2.5 × 2 × 1.2
6.0 (–) / 4.6 (–)(1)
- / 23
Operating temperature range is up to 125°C including self temperature rise.
8.2.1.2 Input Capacitor Selection
The input capacitors CIN0, CIN1, CIN2, and CIN3 are shown in Section 8.2. A ceramic input bypass capacitor of
10 μF is required for each phase of the regulator. Place the input capacitor as close as possible to the VIN_Bx
pin and PGND_Bx pin of the device. A larger value or higher voltage rating improves the input voltage filtering.
Use X7R type of capacitors, not Y5V or F. DC bias characteristics capacitors must be considered. The minimum
effective input capacitance to make sure performance is good is 1.9 μF for each buck input at the maximum
input voltage including tolerances and ambient temperature range. This value assumes that at least 22 μF of
additional capacitance is common for all the power input pins on the system power rail. See Table 8-2.
The input filter capacitor supplies current to the high-side FET switch in the first half of each cycle and decreases
voltage ripple imposed on the input power source. A ceramic capacitor's low ESR provides the best noise
filtering of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with
sufficient ripple current rating. In addition ferrite can be used in front of the input capacitor to decrease the EMI.
Table 8-2. Recommended Input Capacitors (X7R Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
Murata
GCM21BR71A106KE22
10 µF (10%)
0805
DIMENSIONS L × W × H VOLTAGE RATING
(mm)
(V)
2 × 1.25 × 1.25
10 V
8.2.1.3 Output Capacitor Selection
The output capacitors COUT0, COUT1, COUT2, and COUT3 are shown in Section 8.2. A ceramic local output
capacitor of 22 μF is required per phase. Use ceramic capacitors, X7R or X7T types; do not use Y5V or F. DC
bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out
current flow from the inductor to the load, helps keep a steady output voltage during transient load changes and
decreases output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently
low ESR and ESL to do these functions. The minimum effective output capacitance to make sure performance is
good is 10 μF for each phase including the DC voltage roll-off, tolerances, aging and temperature effects.
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to
its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for
selection process is at the switching frequency of the part. See Table 8-3.
POL capacitor (CPOL0) needs to be used to maintain output voltage stability and improve load transient
performance and to decrease the ripple voltage. Note that the output capacitor may be the limiting factor in
the output voltage ramp and the maximum total output capacitance listed in electrical characteristics must not
be exceeded. At shutdown the output voltage is discharged to 0.6 V level using forced-PWM operation. This can
increase the input voltage if the load current is small and the output capacitor is large. Below 0.6 V level the
output capacitor is discharged by the internal discharge resistor and with large capacitor more time is required to
settle VOUT down as a consequence of the increased time constant.
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Table 8-3. Recommended Output Capacitors (X7R or X7T Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
Murata
GCM31CR71A226KE02
22 µF (10%)
1206
DIMENSIONS L × W × H VOLTAGE RATING
(mm)
(V)
3.2 × 1.6 × 1.6
10
8.2.1.4 Snubber Components
If the input voltage for the regulators is above 4 V, snubber components are needed at the switching nodes to
decrease voltage spiking in the switching node and to improve EMI. The snubber capacitors C0, C1, C2, and
C3 and the snubber resistors R0, R1, R2, and R3 are shown in Figure 8-1. The recommended components are
shown in Table 8-4 and these component values give good performance on LP875701-Q1 EVM. The optimal
resistance and capacitance values finally depend on the PCB layout.
Table 8-4. Recommended Snubber Components
DIMENSIONS L × W x H VOLTAGE / POWER
(mm)
RATING
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
Vishay-Dale
CRCW04023R90JNED
3.9 Ω (5%)
0402
1 × 0.5 × 0.4
62 mW
Murata
GCM1555C1H391JA16
390 pF (5%)
0402
1 × 0.5 × 0.5
50 V
8.2.1.5 Supply Filtering Components
The VANA input is used to supply analog and digital circuits in the device. See Table 8-5 for recommended
components for VANA input supply filtering.
Table 8-5. Recommended Supply Filtering Components
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L × W × H
(mm)
VOLTAGE RATING
(V)
Murata
GCM155R71C104KA55
100 nF (10%)
0402
1.0 × 0.5 × 0.5
16
Murata
GCM188R71C104KA37
100 nF (10%)
0603
1.6 × 0.8 × 0.8
16
8.2.2 Detailed Design Procedure
The performance of the LP875701-Q1 device depends greatly on the care taken in designing the printed circuit
board (PCB). The use of low-inductance and low serial-resistance ceramic capacitors is strongly recommended,
while correct grounding is crucial. Attention must be given to decoupling the power supplies. Decoupling
capacitors must be connected close to the device and between the power and ground pins to support high
peak currents being drawn from system power rail during turnon of the switching MOSFETs. Keep input and
output traces as short as possible, because trace inductance, resistance, and capacitance can easily become
the performance limiting items. The separate power pins VIN_Bx are not connected together internally. Connect
the VIN_Bx power connections together outside the package using power plane construction.
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100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
8.2.3 Application Curves
70
60
50
70
60
50
VIN = 3.3 V
40
0.01
0.1
1
VIN = 5.0 V
Current (A)
0.1
1
10
Current (A)
D142
VOUT = 1.0 Volt
D144
VOUT = 1.0 Volt
Figure 8-2. Efficiency in Forced-PWM-Four-Phase
mode
Figure 8-3. Efficiency in Forced-PWM-Four-Phase
Mode
1.02
1.02
1.016
1.016
1.012
1.012
1.008
1.008
Voltage (V)
Voltage (V)
40
0.01
10
1.004
1
0.996
0.992
1.004
1
0.996
0.992
0.988
0.988
VIN = 3.3 V
VIN = 5.0 V
0.984
0.98
0
2
4
6
Current (A)
8
VIN = 3.3 V
VIN = 5.0 V
0.984
10
0.98
-40
-20
0
D146
VOUT = 1.0 Volt
Figure 8-4. Output Voltage vs Load Current in
Forced-PWM-Four-Phase Mode
20
40
60
Temperature (qC)
80
100
120
D148
VOUT = 1.0 Volt ILOAD = 1 A / phase
(4 A total)
Figure 8-5. Output Voltage vs Temperature
V(EN1)(1V/div)
V(EN1)(1V/div)
VOUT(200mV/div)
VOUT(200mV/div)
ILOAD(1A/div)
V(SW_B0)(2V/div)
V(SW_B0)(2V/div)
Time (100 µs/div)
VOUT = 1.0 Volt
Slew-Rate =3.8
mV / µs
Time (100 µs/div)
ILOAD = 0 A
Figure 8-6. Start-Up With EN1, Forced-PWM-FourPhase Mode
VOUT = 1.0 Volt
Slew-Rate =3.8
mV / µs
RLOAD = 0.25 Ω
Figure 8-7. Start-Up With EN1, Forced-PWM-FourPhase Mode
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V(EN1)(1V/div)
VOUT(200mV/div)
VOUT(1mV/div)
ILOAD(1A/div)
V(SW_B0)(2V/div)
V(SW_B0)(2V/div)
Time (100 µs/div)
VOUT = 1.0 Volt
Slew-Rate =3.8
mV / µs
Time (200 ns/div)
RLOAD = 0.25 Ω
Figure 8-8. Shutdown With EN1, Forced-PWMFour-Phase Mode
VOUT = 1.0 Volt, VIN
= 3.3 V
ILOAD= 200 mA
Internal Clock,
Spread-Spectrum
Enabled
Figure 8-9. Output Voltage Ripple, Forced-PWMFour-Phase Mode
ILOAD (2A/div)
VOUT(1mV/div)
VOUT (10mV/div)
V(SW_B0)(2V/div)
Time (40 µs/div)
Time (200 ns/div)
VOUT = 1.0 Volt, VIN
= 5.0 V
ILOAD= 200 mA
Internal Clock,
Spread-Spectrum
Enabled
Figure 8-10. Output Voltage Ripple, Forced-PWMFour-Phase Mode
VOUT = 1.0 Volt, VIN
= 3.3 V
IOUT= 1.5 A → 7.5
A → 1.5 A
Figure 8-11. Transient Load Step Response,
Forced-PWM-Four-Phase Mode, TA=+25oC
ILOAD (2A/div)
ILOAD (2A/div)
VOUT (10mV/div)
VOUT (10mV/div)
Time (40 µs/div)
VOUT = 1.0 Volt, VIN
= 3.3 V
IOUT= 1.5 A → 7.5
A → 1.5 A
Time (40 µs/div)
tR = tF = 1 µs
Figure 8-12. Transient Load Step Response,
Forced-PWM-Four-Phase Mode, TA=-40oC
60
tR = tF = 1 µs
VOUT = 1.0 Volt, VIN
= 3.3 V
IOUT= 1.5 A → 7.5
A → 1.5 A
tR = tF = 1 µs
Figure 8-13. Transient Load Step Response,
Forced-PWM-Four-Phase Mode, TA=+125oC
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ILOAD (2A/div)
ILOAD (2A/div)
VOUT (10mV/div)
VOUT (10mV/div)
Time (40 µs/div)
Time (40 µs/div)
VOUT = 1.0 Volt, VIN
= 5.0 V
IOUT= 1.5 A → 7.5
A → 1.5 A
VOUT = 1.0 Volt, VIN
= 5.0 V
tR = tF = 1 µs
IOUT= 1.5 A → 7.5
A → 1.5 A
tR = tF = 1 µs
Figure 8-15. Transient Load Step Response,
Forced-PWM-Four-Phase Mode, TA=-40oC
Figure 8-14. Transient Load Step Response,
Forced-PWM-Four-Phase Mode, TA=+25oC
ILOAD (2A/div)
VOUT (10mV/div)
Time (40 µs/div)
VOUT = 1.0 Volt, VIN = 5.0 V
IOUT= 1.5 A → 7.5 A → 1.5 A
tR = tF = 1 µs
Figure 8-16. Transient Load Step Response, Forced-PWM-Four-Phase Mode, TA=+125oC
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.8 V and 5.5 V. This input supply
must be well regulated and can withstand maximum input current and keep a stable voltage without voltage
drop even at load transition condition. The resistance of the input supply rail must be low enough that the input
current transient does not cause too high drop in the LP875701-Q1 supply voltage that can cause false UVLO
fault triggering. If the input supply is located more than a few inches from the LP875701-Q1 additional bulk
capacitance may be required in addition to the ceramic bypass capacitors.
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10 Layout
10.1 Layout Guidelines
The high frequency and large switching currents of the LP875701-Q1 make the choice of layout important. Good
power supply results only occur when care is given to correct design and layout. Layout affects noise pickup
and generation and can cause a good design to perform with less-than-expected results. With a range of output
currents from milliamps to 10 A and over, good power supply layout is much more difficult than most general
PCB design. Use the following steps as a reference to make sure the device is stable and keeps correct voltage
and current regulation across its intended operating voltage and current range.
•
•
•
•
•
•
Place CIN as close as possible to the VIN_Bx pin and the PGND_Bxx pin. Route the VIN trace wide and
thick to avoid IR drops. The trace between the positive node of the input capacitor and the VIN_Bx pin(s) of
LP875701-Q1 , as well as the trace between the negative node of the input capacitor and power PGND_Bxx
pin(s), must be kept as short as possible. The input capacitance provides a low-impedance voltage source
for the switching converter. The inductance of the connection is the most important parameter of a local
decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for correct
device operation. The parasitic inductance can be decreased by using a ground plane as close as possible to
top layer by using thin dielectric layer between top layer and ground plane.
The output filter, consisting of COUT and L, converts the switching signal at SW_Bx to the noiseless output
voltage. It must be placed as close as possible to the device keeping the switch node small, for best EMI
behavior. Route the traces between the LP875701-Q1 output capacitors and the load direct and wide to avoid
losses due to the IR drop.
Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a
quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling
capacitor as close as possible to the VANA pin.
If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the LP875701Q1 device to the respective sense pins on the processor. The sense lines are susceptible to noise. They
must be kept away from noisy signals such as PGND_Bxx, VIN_Bx, and SW_Bx, as well as high bandwidth
signals such as the I2C. Avoid both capacitive and inductive coupling by keeping the sense lines short, direct,
and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or
ground plane if possible. Running the signal as a differential pair is recommended for multiphase outputs. If
series resistors are used for load current measurement, place them after connection of the voltage feedback.
Connect feedback pin FB_B0 to supply terminal of the point-of-load, and feedback pin FB_B1 to the GND of
the point-of-load.
PGND_Bxx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers,
which are cannot withstand interference from noisy PGND_Bxx, VIN_Bx and SW_Bx.
If the input voltage is above 4 V, place snubber components (capacitor and resistor) between SW_Bx and
ground on all four phases. The components can be also placed to the other side of the board if there are area
limitations and the routing traces can be kept short.
Due to the small package of this converter and the overall small solution size, the thermal performance of
the PCB layout is important. Many system-dependent parameters such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component. Correct PCB layout, focusing on thermal performance, results in lower
die temperatures. Wide and thick power traces can sink dissipated heat. This can be improved further on
multi-layer PCB designs with vias to different planes. This results in decreased junction-to-ambient (RθJA) and
junction-to-board (RθJB) thermal resistances and thereby decreases the device junction temperature, TJ. TI
strongly recommends doing a careful system-level 2D or full 3D dynamic thermal analysis at the beginning
product design process, by using a thermal modeling analysis software.
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10.2 Layout Example
Below example is an illustrative example only. For an exact PCB layout example, please refer to the EVM
Manual
Via to GND plane
Via to VIN plane
Bottom side component
VOUT1
VOUT0
L0
L1
COUT0
COUT1
GND
CIN0
CIN1
VIN
VIN
13 12 11 10 9
GND
CVANA
VIN
14 FB_B1
15 EN2
16 PGOOD
17 AGND
SCL 5
AGND 4
19 nINT
CLKIN 3
21 FB_B3
R3
C0
SDA 6
18 VANA GND
20 NRST
C3
R0
FB_B0 8
EN1 7
AGND 27
VIN_B3
SW_B3
PGND_B23
SW_B2
VIN_B2
C1
VIN_B1
SW_B1
PGND_B01
SW_B0
VIN_B0
R1
EN3 2
FB_B2 1
GND
C2
R2
22 23 24 25 26
VIN
VIN
CIN2
CIN3
GND
COUT3
VOUT3
A.
L3
COUT2
L2
VOUT2
The output voltage rails are shorted together based on the configuration as shown in Section 8.2.
Figure 10-1. Board Layout
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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4-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LP875701ARNFRQ1
ACTIVE
VQFN-HR
RNF
26
3000
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
-40 to 125
LP8757
01A-Q1
LP875701ARNFTQ1
ACTIVE
VQFN-HR
RNF
26
250
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
-40 to 125
LP8757
01A-Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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