LP8758A2EAYFFR

LP8758-EA SNVSC24LP8758-EA – APRIL 2021 SNVSC24 – APRIL 2021 www.ti.com LP8758-EA Four 4-A Output Synchronous Step-Down DCDC Converters 1 Features 3 Description • The LP8758-EA device is designed to meet power management requirements for low-power processors in mobile phones, network cards, and similar applications. The device contains four step-down DCDC converter cores, providing four output voltage rails. The device is controlled by an I2C-compatible serial interface. • • • • • • • • • Fully integrated quad buck, up to 4-A programmable maximum output current per buck – Auto PWM-PFM and forced-PWM operations – Programmable output voltage slew rate from 30 mV/µs to 0.5 mV/µs – Input voltage range: 2.5 V to 5.5 V – VOUT range: 0.5 V to 3.36 V with DVS Programmable start-up and shutdown sequencing with enable signal I2C-compatible interface that supports standard (100 kHz), fast (400 kHz), fast+ (1 MHz), and high-speed (3.4 MHz) modes Interrupt function with programmable masking Load current measurement Output short-circuit and overload protection Spread-spectrum mode for EMI reduction The four buck cores operate 90° out of phase thereby reducing input ripple current Overtemperature warning and protection Undervoltage Lockout (UVLO) 2 Applications • • • • Optical modules Drone systems Smart phones, eBooks, and tablets Solid state drives The automatic PWM-PFM (AUTO mode) operation maximizes efficiency over a wide output-current range. The LP8758-EA supports programmable start-up and shutdown sequencing synchronized to hardware Enable input signal. The protection features include short-circuit protection, current limits, input supply UVLO, and temperature warning and shutdown functions. Several error flags are provided for status information of the device. In addition, the LP8758-EA device supports load current measurement without the addition of external current sense resistors. During start-up and voltage change, the device controls the output slew rate to minimize output voltage overshoot and the inrush current. Device Information(1) PART NUMBER LP8758-EA (1) VIN_B2 VIN_B3 800 mV 800 mV VOUT3 800 mV 100 SW_B0 FB_B0 SW_B1 95 VOUT1 FB_B1 VANA NRST SDA SCL nINT EN1 EN2 VOUT1 VOUT2 VOUT0 SW_B2 FB_B2 SW_B3 FB_B3 GNDs VOUT2 Efficiency (%) VIN_B0 VIN_B1 800 mV For all available packages, see the orderable addendum at the end of the data sheet. LP8758 VIN DEFAULT OUTPUT VOLTAGE VOUT0 90 85 80 VIN = 3.3 V 2.5 V 1.8 V 75 VOUT3 70 0.001 0.01 0.1 Output Current (A) 1 5 D038 VOUT settings = 1.8 V and 2.5 V Efficiency vs Output Current Simplified Schematic An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2021 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: LP8758-EA 1 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 5 6.1 Absolute Maximum Ratings........................................ 5 6.2 ESD Ratings............................................................... 5 6.3 Recommended Operating Conditions.........................5 6.4 Thermal Information....................................................6 6.5 Electrical Characteristics.............................................6 6.6 I2C Serial Bus Timing Requirements.......................... 8 6.7 Switching Characteristics..........................................10 6.8 Typical Characteristics.............................................. 11 7 Detailed Description......................................................12 7.1 Overview................................................................... 12 7.2 Functional Block Diagram......................................... 13 7.3 Feature Description...................................................13 7.4 Device Functional Modes..........................................22 7.5 Programming............................................................ 23 7.6 Register Maps...........................................................26 8 Application and Implementation.................................. 46 8.1 Application Information............................................. 46 8.2 Typical Application.................................................... 46 9 Power Supply Recommendations................................53 10 Layout...........................................................................54 10.1 Layout Guidelines................................................... 54 10.2 Layout Example...................................................... 55 11 Device and Documentation Support..........................56 11.1 Device Support........................................................56 11.2 Documentation Support.......................................... 56 11.3 Receiving Notification of Documentation Updates.. 56 11.4 Support Resources................................................. 56 11.5 Trademarks............................................................. 56 11.6 Electrostatic Discharge Caution.............................. 56 11.7 Glossary.................................................................. 56 12 Mechanical, Packaging, and Orderable Information.................................................................... 57 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 2 DATE REVISION NOTES April 2021 * Initial Release Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 5 Pin Configuration and Functions VIN _B2 SW _B2 PGND _B23 SW _B3 VIN _B3 G G VIN _B3 SW _B3 PGND _B23 SW _B2 VIN _B2 VIN _B2 SW _B2 PGND _B23 SW _B3 VIN _B3 F F VIN _B3 SW _B3 PGND _B23 SW _B2 VIN _B2 SCL FB _B2 PGND _B23 FB _B3 VANA E E VANA FB _B3 PGND _B23 FB _B2 SCL SDA NRST EN2 nINT AGN D D D AGN D nINT EN2 NRST SDA EN1 FB _B0 PGND _B01 FB _B1 SGND C C SGND FB _B1 PGND _B01 FB _B0 EN1 VIN _B0 SW _B0 PGND _B01 SW _B1 VIN _B1 B B VIN _B1 SW _B1 PGND _B01 SW _B0 VIN _B0 VIN _B0 SW _B0 PGND _B01 SW _B1 VIN _B1 A A VIN _B1 SW _B1 PGND _B01 SW _B0 VIN _B0 5 4 3 2 1 Figure 5-1. YFF Package 35-Pin DSBGA Top View 1 2 3 4 5 Figure 5-2. YFF Package 35-Pin DSBGA Bottom View Table 5-1. Pin Functions PIN NO. NAME A1, B1 VIN_B1 TYPE DESCRIPTION P Input for Buck1. The separate power pins VIN_Bx are not connected together internally – VIN_Bx pins must be connected together in the application and be locally bypassed. Buck1 switch node. A2, B2 SW_B1 A A3, B3, C3 PGND_B01 G Power Ground for Buck0 and Buck1. A4, B4 SW_B0 A Buck0 switch node. A5, B5 VIN_B0 P Input for Buck0. The separate power pins VIN_Bx are not connected together internally – VIN_Bx pins must be connected together in the application and be locally bypassed. C1 SGND G Substrate Ground. C2 FB_B1 A Output voltage feedback for Buck1. C4 FB_B0 A Output voltage feedback for Buck0. C5 EN1 D/I Programmable Enable signal for Buck converter core or cores. Can be also configured to switch between two output voltage levels. D1 AGND G Ground. D2 nINT D/O Open-drain interrupt output. Active LOW. D3 EN2 D/I Programmable Enable signal for Buck converter one or more cores. Can be also configured to switch between two output voltage levels. D4 NRST D/I Reset signal for the device. Can be also used to enable the regulator. D5 SDA D/I/O Serial interface data input and output for system access. Connect a pullup resistor. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 3 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 Table 5-1. Pin Functions (continued) PIN NO. NAME TYPE DESCRIPTION E1 VANA P Supply voltage for Analog and Digital blocks. E2 FB_B3 A Output voltage feedback for Buck3. E4 FB_B2 A Output voltage feedback for Buck2. E5 SCL D/I F1, G1 VIN_B3 P Input for Buck3. The separate power pins VIN_Bx are not connected together internally – VIN_Bx pins must be connected together in the application and be locally bypassed. Serial interface clock input for system access. Connect a pullup resistor. F2, G2 SW_B3 A Buck3 switch node. E3, F3, G3 PGND_B23 G Power Ground for Buck2 and Buck3. F4, G4 SW_B2 A Buck2 switch node. F5, G5 VIN_B2 P Input for Buck2. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed. A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin 4 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 6 Specifications 6.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted).(1) (2) MIN MAX UNIT –0.3 6 V V INPUT VOLTAGE VIN_Bx, VANA Voltage on power connections SW_Bx Voltage on buck switch nodes –0.3 (VIN_Bx + 0.3 V) with 6 V maximum FB_Bx Voltage on buck voltage sense nodes –0.3 (VANA + 0.3 V) with 6 V maximum V NRST Voltage on NRST input –0.3 3.6 V ENx, SDA, SCL, nINT Voltage on logic pins (input or output pins) –0.3 3.6 CURRENT VIN_Bx, SW_Bx, PGND_Bx Current on power pins (average current over 100k hour lifetime, TJ = 125°C) 0.62 A/pin TEMPERATURE TJ-MAX Junction temperature −40 Maximum lead temperature (soldering, 10 seconds)(3) Tstg (1) (2) (3) Storage temperature –65 150 °C 260 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 6.3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground. For detailed soldering specifications and information, please refer to DSBGA Wafer Level Chip Scale Package. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted). MIN MAX UNIT 2.5 5.5 V 0 VANA with 3.6 V maximum V 0 VANA with 3.6 V maximum V Voltage on I2C interface, standard (100 kHz), fast (400 khz), fast+ (1 MHz), and high-speed (3.4 MHz) modes 0 1.95 V Voltage on I2C interface, standard (100 kHz), fast (400 kHz), and fast+ (1 MHz) modes 0 VANA with 3.6 V maximum V INPUT VOLTAGE VIN_Bx, VANA NRST ENx, nINT SCL, SDA Voltage on power connections Voltage on NRST Voltage on logic pins (input or output pins) TEMPERATURE TJ Junction temperature –40 125 °C TA Ambient temperature –40 85 °C Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 5 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 6.4 Thermal Information LP8758 THERMAL METRIC(1) UNIT YFF (DSBGA) 35 PINS RθJA Junction-to-ambient thermal resistance 56.1 °C/W RθJCtop Junction-to-case (top) thermal resistance 0.2 °C/W RθJB Junction-to-board thermal resistance 8.5 °C/W ψJT Junction-to-top characterization parameter 0.9 °C/W ψJB Junction-to-board characterization parameter 8.4 °C/W RθJCbot Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics Limits apply over the junction temperature range –40°C ≤ TJ ≤ +125°C, specified V(VANA), VIN , V(NRST), VOUT and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, ƒSW = 3 MHz, V(VANA) = VIN = 3.7 V and VOUT = 1 V, unless otherwise noted.(1) (2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.9 10 µF 10 22 µF EXTERNAL COMPONENTS CIN Input filtering capacitance Connected from VIN_Bx to PGND_Bx COUT Output filtering capacitance, Capacitance per output voltage rail local COUT-TOTAL Output capacitance, total (local and remote) Total output capacitance ESRC Input and output capacitor ESR [1-10] MHz L Inductor Inductance of the inductor DCRL Inductor DCR TDK, VLS252010HBX-R47M 2 50 µF 10 mΩ 0.47 –30% µH 30% 29 mΩ BUCK REGULATORS VIN VOUT IOUT Input voltage range Output voltage Output current Dropout voltage Voltage between VIN_Bx and ground terminals. VANA must be connected to the same supply as VIN_Bx. 2.5 Programmable voltage range 0.5 Step size, 0.5 V ≤ VOUT < 0.73 V 5.5 V 1 3.36 V 10 Step size, 0.73 V ≤ VOUT < 1.4 V 5 Step size, 1.4 V ≤ VOUT ≤ 3.36 V 20 mV Output current, VIN ≤ 3 V ILIM FWD programmed to 5 A per phase. 3(3) Output current, VIN > 3 V, VOUT ≤ 2 V ILIM FWD programmed to 5 A per phase. 4(3) Output current, VIN > 3 V, VOUT > 2 V ILIM FWD programmed to 5 A per phase. 3.5(3) VIN – VOUT DC output voltage accuracy, Force PWM mode includes voltage reference, DC load and line PFM mode, the average output voltage regulations, process and level is increased by a maximum of 20 mV. temperature 6 3.7 Submit Document Feedback 0.7 A V min (–2%, –20 mV) max (2%, 20 mV) min (–2%, –20 mV) max ( 2%, 20 mV) + 20 mV Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 6.5 Electrical Characteristics (continued) Limits apply over the junction temperature range –40°C ≤ TJ ≤ +125°C, specified V(VANA), VIN , V(NRST), VOUT and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, ƒSW = 3 MHz, V(VANA) = VIN = 3.7 V and VOUT = 1 V, unless otherwise noted.(1) (2) PARAMETER Ripple TEST CONDITIONS MIN TYP PWM mode, L = 0.47 µH 10 PFM mode, L = 0.47 µH 20 MAX UNIT mVp-p DCLNR DC line regulation IOUT = 1 A ±0.05 DCLDR DC load regulation in PWM mode IOUT from 0 to IOUT(max) 0.3% TLDSR Transient load step response IOUT = 0 A to 2 A, TR = TF = 400 ns, PWM mode, COUT = 44 µF, L = 0.47 µH ±55 mV TLNSR Transient line response VIN stepping 3.3 V ↔ 3.8 V, TR = TF = 10 µs, IOUT = IOUT(max) ±15 mV ILIM FWD Forward current limit (peak for every switching cycle), per phase Programmable range 2.5 Step size %/V 5 0.5 A Accuracy, 3 V ≤ VIN ≤ 5.5 V, ILIM FWD = 5 A -5% 7.5% 20% Accuracy, 2.5 V ≤ VIN ≤ 3 V, ILIM FWD = 5 A -20% 7.5% 20% 1.6 2 2.4 A ILIM NEG Negative current limit RDS(ON) HS On-resistance, high-side FET Between VIN_Bx and SW_Bx pins (I = 1 A) 40 90 mΩ On-resistance, low-side FET Between SW_Bx and PGND_Bx pins (I = 1 A) 33 50 mΩ Overshoot during start-up Slew-rate = 10 mV/µs FET RDS(ON) LS FET < 50 mV IPFM-PWM PFM-to-PWM switch current threshold(4) 600 mA IPWM-PFM PWM-to-PFM switch current threshold(4) 240 mA Output pulldown resistance Regulator disabled 150 250 350 Powergood threshold for interrupt BUCKx_INT(BUCKx_SC_I NT), difference from final voltage Rising ramp voltage, enable or voltage change –23 –17 –10 10 17 23 –23 –17 –10 Ω mV Falling ramp, voltage change Powergood threshold for status signal During operation, status signal is forced to BUCKx_STAT(BUCKx_PG_ 0 during voltage change. STAT) mV PROTECTION FEATURES Thermal warning Temperature rising, CONFIG(TDIE_WARN_LEVEL) = 0 125 Temperature rising, CONFIG(TDIE_WARN_LEVEL) = 1 105 Hysteresis Thermal shutdown VANAUVLO VANA undervoltage lockout °C 15 Temperature rising 150 Hysteresis °C 15 Voltage falling Hysteresis 2.3 2.4 50 2.5 V mV LOAD CURRENT MEASUREMENT Current measurement range Maximum code Resolution LSB Measurement accuracy IOUT ≥ 1 A 20.46 20 A mA < 10% Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 7 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 6.5 Electrical Characteristics (continued) Limits apply over the junction temperature range –40°C ≤ TJ ≤ +125°C, specified V(VANA), VIN , V(NRST), VOUT and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, ƒSW = 3 MHz, V(VANA) = VIN = 3.7 V and VOUT = 1 V, unless otherwise noted.(1) (2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT CONSUMPTION Shutdown current consumption V(NRST) = 0 V 1 µA Standby current consumption, converter cores disabled V(NRST) = 1.8 V 6 µA Active current consumption during PFM operation, one converter core enabled V(NRST) = 1.8 V, IOUT = 0 mA, not switching 55 µA Active current consumption during PWM operation, per converter core V(NRST) = 1.8 V, IOUT = 0 mA, L = 0.47 µH 14.5 mA DIGITAL INPUT SIGNALS NRST, ENx, SCL, SDA VIL Input low level 0.4 V VIH Input high level 1.2 VHYS Hysteresis of Schmitt trigger inputs (SCL, SDA) 10 80 160 mV V ENx pulldown resistance ENx_PD = 1 350 500 720 kΩ NRST pulldown resistance Always present 800 1200 1700 kΩ 0.4 V DIGITAL OUTPUT SIGNALS nINT, SDA VOL Output low level ISOURCE = 2 mA, RP External pullup resistor for nINT To VIO supply 10 kΩ ALL DIGITAL INPUTS ILEAK (1) (2) (3) (4) Input current All logic inputs over pin voltage range −1 1 µA All voltage values are with respect to network ground. Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified, but do represent the most likely norm. The maximum output current can be limited by the forward current limit, ILIM FWD. The maximum output current is available with 5-A forward current limit setting. The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependant on the output voltage, input voltage and the magnitude of inductor's ripple current. 6.6 I2C Serial Bus Timing Requirements See table notes.(1) (2) MIN ƒSCL Serial clock frequency MAX UNIT Standard mode 100 kHz Fast mode 400 kHz Fast mode + High-speed mode, Cb = 100 pF High-speed mode, Cb = 400 pF tLOW 8 SCL low time Standard mode 4.7 Fast mode 1.3 Fast mode + 0.5 High-speed mode, Cb = 100 pF 160 High-speed mode, Cb = 400 pF 320 Submit Document Feedback 1 MHz 3.4 MHz 1.7 MHz µs ns Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 6.6 I2C Serial Bus Timing Requirements (continued) See table notes.(1) (2) MIN Standard mode Fast mode tHIGH tSU;DAT tHD;DAT SCL high time Data setup time Data hold time Fast mode + Setup time for a start or a repeated start condition 60 120 Standard mode 250 Fast mode 100 Fast mode + 50 High-speed mode 10 tBUF Hold time for a start or a repeated start condition Bus free time between a stop and start condition Setup time for a stop condition tfDA Rise time of SDA signal Fall time of SDA signal 3.45 0 0.9 Fast mode + 0 High-speed mode, Cb = 100 pF 0 70 High-speed mode, Cb = 400 pF 0 150 High-speed mode 160 µs ns µs 0.6 0.26 High-speed mode 160 Standard mode 4.7 Fast mode 1.3 Fast mode + 0.5 Fast mode ns µs 4 0.6 Fast mode + 0.26 High-speed mode 160 µs ns 1000 Fast mode 300 Fast mode + 120 High-speed mode, Cb = 100 pF 80 High-speed mode, Cb = 400 pF 160 Standard mode 250 Fast mode 250 Fast mode + 120 Standard mode ns 4 Fast mode + High-speed mode, Cb = 400 pF Rise time of SCL signal 0.6 0.26 Fast mode µs 4.7 Fast mode + High-speed mode, Cb = 100 pF trCL ns 0 Standard mode trDA ns Fast mode Standard mode tSU;STO µs Standard mode Standard mode tHD;STA 0.6 High-speed mode, Cb = 400 pF Fast mode UNIT 0.26 High-speed mode, Cb = 100 pF Standard mode tSU;STA MAX 4 ns ns 80 160 1000 Fast mode 300 Fast mode + 120 High-speed Mode, Cb = 100 pF 40 High-speed Mode, Cb = 400 pF 80 ns Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 9 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 6.6 I2C Serial Bus Timing Requirements (continued) See table notes.(1) (2) MIN MAX Standard mode trCL1 tfCL Rise time of SCL signal after a repeated start condition and after an acknowledge bit Fall time of a SCL signal Fast mode 300 Fast mode + 120 High-speed mode, Cb = 100 pF 80 High-speed mode, Cb = 400 pF 160 Standard mode 300 Fast mode 300 Fast mode + 120 High-speed mode, Cb = 100 pF 40 High-speed mode, Cb = 400 pF 80 Cb Capacitive load for each bus line (SCL and SDA) tSP Pulse width of spike suppressed Fast mode, fast mode + in SCL and SDA lines (spikes that are less than the indicated High-speed mode width are suppressed) (1) (2) UNIT 1000 400 ns ns pF 50 10 ns See Figure 6-1 for timing diagram. Cb refers to the capacitance of one bus line. Cb is expressed in pF units. 6.7 Switching Characteristics Limits apply over the junction temperature range –40°C ≤ TJ ≤ +125°C, specified V(VANA), VIN , V(NRST), VOUT and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, ƒSW = 3 MHz, V(VANA) = VIN = 3.7 V and VOUT = 1 V, unless otherwise noted.(1) PARAMETER ƒSW Switching frequency, PWM mode Start-up time (soft start) Output voltage slew-rate(2) Load current measurement time (1) (2) 10 TEST CONDITIONS MIN TYP MAX VOUT ≥ 0.6 V 2.7 3 3.3 VOUT < 0.6 V 1.8 2 2.2 From ENx to VOUT = 0.225 V (slew-rate control begins), COUT-TOTAL = 44 µF, no load 140 SLEW_RATEx[2:0] = 000, VOUT ≥ 0.5 V –15% 30 15% –15% 15 15% SLEW_RATEx[2:0] = 010, VOUT ≥ 0.5 V –15% 10 15% SLEW_RATEx[2:0] = 011, VOUT ≥ 0.5 V –15% 7.5 15% SLEW_RATEx[2:0] = 100, VOUT ≥ 0.5 V –15% 3.8 15% SLEW_RATEx[2:0] = 101, VOUT ≥ 0.5 V –15% 1.9 15% SLEW_RATEx[2:0] = 110, VOUT ≥ 0.5 V –15% 0.94 15% SLEW_RATEx[2:0] = 111, VOUT ≥ 0.5 V –15% 0.4 0.4 15% PWM mode MHz µs SLEW_RATEx[2:0] = 001, VOUT ≥ 0.5 V PFM mode (automatically changing to PWM mode for the measurement) UNIT mV/µs 50 µs 4 Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified, but do represent the most likely normal. Specified by design without testing. The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance, and load current. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 tBUF SDA tHD;STA trCL tfDA tLOW trDA tSP tfCL SCL tHD;STA tSU;STA tSU;STO tHIGH tHD;DAT S tSU;DAT START RS P S REPEATED START STOP START Figure 6-1. I2C Timing 6.8 Typical Characteristics 2 8 1.8 7.6 1.6 7.2 1.4 6.8 Input Current (PA) Input Current (PA) Unless otherwise specified: TA = 25°C, VIN = 3.7 V, ƒSW = 3 MHz, L = 470 nH. 1.2 1 0.8 0.6 6.4 6 5.6 5.2 0.4 4.8 0.2 4.4 0 2.5 3 3.5 4 4.5 Input Voltage (V) 5 4 2.5 5.5 3 3.5 D011 V(NRST) = 1.8 V V(NRST) = 0 V Figure 6-2. Shutdown Current Consumption vs Input Voltage 4 4.5 Input Voltage (V) 5 5.5 D010 All converter cores disabled Figure 6-3. Standby Current Consumption vs Input Voltage 18 60 59 58 Input Current (mA) Input Current (PA) 17 57 56 55 54 53 16 15 52 51 50 2.5 V(NRST) = 1.8 V 3 3.5 4 4.5 Input Voltage (V) Load = 0 mA 5 5.5 14 2.5 D012 VOUT setting = 1000 mV Figure 6-4. PFM Mode Current Consumption vs Input Voltage —One Output Enabled V(NRST) = 1.8 V 3 3.5 4 4.5 Input Voltage (V) Load = 0 mA 5 5.5 D039 VOUT setting = 1000 mV Figure 6-5. PWM Mode Current Consumption vs Input Voltage — One Output Enable Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 11 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7 Detailed Description 7.1 Overview The LP8758-xx devices are a family of configurable step-down DC-DC converters with four converter cores. The LP8758-xx devices are ideally suited for systems powered from 2.5-V to 5.5-V supply voltage. In LP8758-EA the cores are configured for a four single-phase configuration. The LP8758-EA is well suited for space-constrained applications where high efficiency is required at low output voltages. Typical applications include network interface cards, modem cards, smart phones and mobile devices, solid-state drives (SSDs), systems-on-a-chip (SoCs), ASICs, and low power processors. There are two modes of operation for the converter cores, depending on the output current required: pulsewidth modulation (PWM) and pulse-frequency modulation (PFM). The cores operate in PWM mode at high load currents of approximately 600 mA or higher. Lighter output current loads cause the converter cores to automatically switch into PFM mode for reduced current consumption and a longer battery life when forced PWM mode is disabled. Additional features include soft-start, undervoltage lockout, overload protection, thermal warning, and thermal shutdown. 7.1.1 Buck Information The LP8758-EA has four integrated high-efficiency buck converter cores. The cores are designed for flexibility; most of the functions are programmable, thus giving a possibility to optimize the regulator operation for each application. 7.1.1.1 Operating Modes • • • OFF: Output is isolated from the input voltage rail in this mode. Output has an optional pulldown resistor. PWM: Converter operates in buck configuration with fixed switching frequency. PFM: Converter switches only when output voltage decreases below programmed threshold. Inductor current is discontinuous. 7.1.1.2 Programmability The following parameters can be programmed through registers: • • • • • Output voltage Forced PWM operation Switch current limit Output voltage slew rate Enable and disable delays 7.1.1.3 Features • • • • • • • • • • 12 Dynamic voltage scaling (DVS) support with programmable slew-rate Automatic mode control based on the loading Synchronous rectification Current mode loop with PI compensator Optional spread spectrum technique to reduce EMI Soft start Power-good flag with maskable interrupt Phase control for optimized EMI: The four cores operate 90° out of phase thereby reducing input ripple current Average output current sensing (for PFM entry and load current measurement) Voltage sensing from point of the load Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.2 Functional Block Diagram VANA BUCK0 ILIM Detection nINT Power-Good Detection Interrupts Overload and SC Detection EN1 ILOAD ADC Enable, Roof/Floor, Slew-Rate Control EN2 BUCK1 ILIM Detection Power-Good Detection SDA I 2C SCL Overload and SC Detection ILOAD ADC Registers OTP EPROM BUCK2 ILIM Detection Power-Good Detection UVLO Digital Logic Overload and SC Detection Oscillator NRST ILOAD ADC BUCK3 ILIM Detection SW Reset Reference and Bias Thermal Monitor Power-Good Detection Overload and SC Detection ILOAD ADC 7.3 Feature Description 7.3.1 Overview A block diagram of a single core is shown in Figure 7-1. Interleaving switching action of the converters is illustrated in Figure 7-2. The LP8758-EA regulator switches each core 90° apart, reducing input ripple current. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 13 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 High-Side FET Current Sense FB Positive Current Limit Ramp Generator ± Error Amp + + Voltage Setting Slew Rate Control VDAC Loop Comparator Programmable Parameters Control Block SW Gate Control VOUT Negative Current Limit Power good ± VIN Low-Side FET Current Sense Master Interface Slave Interface Zero Cross detect GND IADC Figure 7-1. Detailed Block Diagram Showing One Core IL0 IL1 IL2 IL3 0 90 180 270 360 450 540 630 720 540 630 720 PWM0 PWM1 PWM2 PWM3 SWITCHING CYCLE 360º 0 90 180 270 360 450 Phase (Degrees) Figure 7-2. PWM Timings and Inductor Current Waveforms 1 1 14 Graph is not in scale and is for illustrative purposes only. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.3.1.1 Transition Between PWM and PFM Modes The LP8758-EA converter cores operate in PWM mode at load current of about 600 mA or higher. At lighter load current levels the cores automatically switches into PFM mode for reduced current consumption when Forced PWM mode is disabled (AUTO mode operation). By combining the PFM and the PWM modes a high efficiency is achieved over a wide output-load current range. 7.3.1.2 Buck Converter Load Current Measurement Buck load current can be monitored via I2C registers. The monitored buck converter core is selected with the SEL_I_LOAD.LOAD_CURRENT_BUCK_SELECT[1:0] register bits. A write to this selection register starts a current measurement sequence. The measurement sequence is typically 50 µs long. The LP8758-EA device can be configured to give out an interrupt INT_TOP.I_LOAD_READY after the load current measurement sequence is finished. Load current measurement interrupt can be masked with TOP_MASK.I_LOAD_READY_MASK bit. The measurement result can be read from registers I_LOAD_1 and I_LOAD_2. Register I_LOAD_1 bits BUCK_LOAD_CURRENT[7:0] give out the LSB bits and register I_LOAD_2 bits BUCK_LOAD_CURRENT[9:8] the MSB bits. The measurement result BUCK_LOAD_CURRENT[9:0] LSB is 20 mA, and maximum value of the measurement is 20.46 A. 7.3.1.3 Spread-Spectrum Mode Radiated Energy Power Spectrum is Spread and Lowered Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add EMI-filters and shields to the boards. The register-selectable spread-spectrum mode of the device minimizes the need for output filters, ferrite beads, or chokes. In spread-spectrum mode, the switching frequency varies randomly by ±5% about the center frequency, reducing the EMI emissions radiated by the converter and associated passive components and PCB traces (see Figure 7-3). This feature is enabled with the CONFIG.EN_SPREAD_SPEC bit, and it affects all the buck converter cores. Frequency Where a fixed frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread spectrum architecture of the v spreads that energy over a large bandwidth. Figure 7-3. Spread-Spectrum Modulation 7.3.2 Power-Up The power-up sequence for the LP8758-EA is as follows: • • • • VANA (and VIN_Bx) reach minimum recommended levels (V(VANA) > VANAUVLO). NRST is set to high level. This initiates power-on-reset (POR), OTP reading and enables the system I/O interface. The I2C host must allow at least 1.2 ms before writing or reading data to the LP8758-EA. The device enters STANDBY mode. The host can change the default register setting by I2C if needed. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 15 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 • One or more of the converter cores can be enabled or disabled by one or more of the ENx pins and by the I2C interface. 7.3.3 Regulator Control 7.3.3.1 Enabling and Disabling The buck converter cores can be enabled when the device is in STANDBY or ACTIVE state. There are two ways to enable and disable the buck converter cores: • Using BUCKx_CTRL1.EN_BUCKx register bit (when BUCKx_CTRL1.EN_PIN_CTRLx register bit is 0). • Using EN1/2 control pins (BUCKx_CTRL1.EN_BUCKx register bit is 1 and BUCKx_CTRL1.EN_PIN_CTRLx register bit is 1). If the EN1/2 control pins are used for enable and disable, the delay from the control signal rising edge to start-up is set by BUCKx_DELAY.BUCKx_STARTUP_DELAY[3:0] bits and the delay from control signal falling edge to shutdown is set by BUCKx_DELAY.BUCKx_SHUTDOWN_DELAY[3:0] bits. The delays are valid only for EN1/2 signal and not for control with BUCKx_CTRL1.EN_BUCKx bit. The delay time implemented by EN1/2 has overall ±10% timing accuracy. The control of the converter cores (with 0 ms delays) is shown in Table 7-1. Table 7-1. Regulator Control CONTROL METHOD ROW EN_BUCKx BUCKx_CTRL1 EN_PIN_CTRLx BUCKx_CTRL1 EN_PIN_SELECTx BUCKx_CTRL1 EN_ROOF_FLOORx EN1 PIN EN2 PIN BUCKx OUTPUT VOLTAGE Enable or disable control with EN_BUCKx bit 1 0 Don't Care Don't Care Don't Care Don't Care Don't Care Disabled 2 1 0 Don't Care Don't Care Don't Care Don't Care BUCKx_VOUT.BUCKx_VSET[7:0] Enable or disable control with EN1 pin 3 1 1 0 0 Low Don't Care Disabled 4 1 1 0 0 High Don't Care BUCKx_VOUT.BUCKx_VSET[7:0] Enable or disable control with EN2 pin 5 1 1 1 0 Don't Care Low Disabled 6 1 1 1 0 Don't Care High BUCKx_VOUT.BUCKx_VSET[7:0] Roof or floor control with EN1 pin 7 1 1 0 1 Low Don't Care BUCKx_FLOOR_VOUT.BUCKx_FL OOR_VSET[7:0] 8 1 1 0 1 High Don't Care BUCKx_VOUT.BUCKx_VSET[7:0] Roof or floor control with EN2 pin 9 1 1 1 1 Don't Care Low BUCKx_FLOOR_VOUT.BUCKx_FL OOR_VSET[7:0] 10 1 1 1 1 Don't Care High BUCKx_VOUT.BUCKx_VSET[7:0] The following buck configuration bit settings allows the device to enable or disable the corresponding buck using the ENx pin: • BUCKx_CTRL1.EN_BUCKx = 1 • BUCKx_CTRL1.EN_PIN_CTRLx = 1 • BUCKx_CTRL1.EN_ROOF_FLOORx = 0 • BUCKx_VOUT.BUCKx_VSET[7:0] = Required voltage when the ENx pin is high • The enable pin for control is selected with BUCKx_CTRL1.EN_PIN_SELECTx When the ENx pin is low, Table 7-1 row 3 (or 5) is valid, and the converter core is disabled. By setting ENx pin high, Table 7-1 row 4 (or 6) is valid, and the converter core is enabled with required voltage. If a converter core is enabled all the time, and the ENx pin controls selection between the two voltage levels, then the following configuration is used: • BUCKx_CTRL1.EN_BUCKx = 1 • BUCKx_CTRL1.EN_PIN_CTRLx = 1 • BUCKx_CTRL1.EN_ROOF_FLOORx = 1 • BUCKx_VOUT.BUCKx_VSET[7:0] = Required voltage when the ENx pin is high • The enable pin for control is selected with BUCKx_CTRL1.EN_PIN_SELECTx When the ENx pin is low, Table 7-1 row 7 (or 9) is valid, and the core is enabled with a voltage defined by BUCKx_FLOOR_VOUT.BUCKx_FLOOR_VSET[7:0] bits. Setting the ENx pin high, Table 7-1 row 8 (or 10) is valid, and the core is enabled with a voltage defined by BUCKx_VOUT.BUCKx_VSET[7:0] bits. 16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 If the core is controlled by I2C writings, the BUCKx_CTRL1.EN_PIN_CTRLx bit is set to 0. The enable or disable is controlled by the BUCKx_CTRL1.EN_BUCKx bit, and when the regulator is enabled, the output voltage is defined by the BUCKx_VOUT.BUCKx_VSET[7:0] bits. The Table 7-1 rows 1 and 2 are valid for I2C controlled operation (ENx pins are ignored). The buck converter core is enabled by the ENx pin or by I2C writing as shown in Figure 7-4. The soft-start circuit limits the in-rush current during start-up. Output voltage increase rate is around 5 mV/μsec during soft-start. When the output voltage rises to approximately 0.3 V, the output voltage becomes slew-rate controlled. If there is a short circuit at the output, and the output voltage does not increase above a 0.35-V level in 1 ms, the converter core is disabled, and interrupt is set. When the output voltage reaches the powergood threshold level the INT_BUCK_x.BUCKx_PG_INT interrupt flag is set. The powergood interrupt flag can be masked using BUCK_x_MASK.BUCKx_PG_MASK bit. The ENx input pins have integrated pull-down resistors. The pull-down resistors are enabled by default and host can disable those with CONFIG.ENx_PD bits. Voltage decrease because of load No new Power-good interrupt Voltage BUCKx_VSET[7:0] Power good Ramp SLEW_RATEx[2:0] bit in BUCKx_CTRL2 register 0.6 V 0.35 V Resistive pulldown (if enabled) Soft start Time Enable BUCKx_STAT bit 0 (BUCK_x_STAT register) 1 0 BUCKx_PG_STAT bit 0 (BUCK_x_STAT register) 1 BUCKx_PG_INT bit 0 (INT_BUCK_x register) 1 0 1 0 0 nINT Power-good interrupt Host clears interrupt Figure 7-4. Converter Core Enable and Disable 7.3.3.2 Changing Output Voltage The converter core's output voltage can be changed by the ENx pin (voltage levels defined by the BUCKx_VOUT and BUCKx_FLOOR_VOUT registers) or by writing to the BUCKx_VOUT and BUCKx_FLOOR_VOUT registers. The voltage change is always slew-rate controlled, and the slew-rate is defined by the BUCKx_CTRL2.SLEW_RATEx[2:0] bits. During voltage change the Forced PWM mode is used automatically. When the programmed output voltage is achieved, the mode becomes the one defined by load current, and the BUCKx_CTRL1.BUCKx_FPWM bit. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 17 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 Voltage BUCKx_VSET Power-good Ramp SLEW_RATEx[2:0] bit in BUCKx_CTRL2 register BUCKx_FLOOR_VSET Power-good Time ENx BUCKx_STAT bit 1 (BUCKx_STAT register) BUCKx_PG_STAT bit 1 (BUCKx_STAT register) 0 BUCKx_PG_INT bit 0 (INT_BUCKx register) 1 1 0 0 1 1 nINT Power-good interrupt Host clears interrupt Power-good interrupt Host clears interrupt Figure 7-5. Output Voltage Change 7.3.4 Device Reset Scenarios There are three reset methods implemented on the LP8758-EA: • • • Software reset with RESET.SW_RESET register bit; Reset from low logic level of NRST signal; and Undervoltage lockout (UVLO) reset from VANA supply. A SW-reset occurs when RESET.SW_RESET bit is written 1. The bit is automatically cleared after writing. This event disables all the buck converter cores immediately, resets all the register bits to the default values and OTP bits are loaded (see Figure 7-7). I2C interface is not reset during software reset. If VANA supply voltage falls below UVLO threshold level or NRST signal is set low, then all the converter cores are disabled immediately, and all the register bits are reset to the default values. When the VANA supply voltage is above UVLO threshold level and NRST signal rises above threshold level an internal power-on reset (POR) occurs. OTP bits are loaded to the registers, and a start-up is initiated according to the register settings. 7.3.5 Diagnosis and Protection Features The LP8758-EA is capable of providing three levels of protection features: • Warnings for diagnosis which sets interrupt; • Protection events which are disabling one or more converter cores; and • Faults which are causing the device to shutdown. When the device detects one or more warning or protection conditions, the LP8758-EA sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all the pending interrupts are cleared. When a fault is detected, it is indicated by a INT_TOP.RESET_REG interrupt flag after next start-up. 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 Table 7-2. Summary of Interrupt Signals EVENT Current limit triggered (20 µs debounce) RESULT No effect Short circuit (VOUT < 0.35 V at 1 ms after enable) or overload Converter core (VOUT decreasing disable below 0.35 V during operation, 1 ms debounce) Thermal Warning No effect Thermal Shutdown All converter cores disabled INTERRUPT REGISTER AND BIT INTERRUPT MASK STATUS BIT RECOVERY / INTERRUPT CLEAR INT_TOP.INT_BUCKx = 1 INT_BUCKx.BUCKx_ILIM_I NT = 1 Write 1 to INT_BUCKx.BUCKx_ILIM BUCKx_MASK.BUCKx_ILI BUCKx_STAT.BUCKx_ILI _INT bit M_MASK M_STAT Interrupt is not cleared if current limit is active INT_TOP.INT_BUCKx = 1 INT_BUCK_0_1.BUCKx_SC _INT = 1 or INT_BUCK_2_3.BUCKx_SC _INT = 1 Write 1 to INT_BUCK_0_1.BUCKx_ SC_INT or to INT_BUCK_2_3.BUCKx_ SC_INTbit INT_TOP.TDIE_WARN = 1 INT_TOP.TDIE_SD = 1 N/A N/A Write 1 to INT_TOP.TDIE_WARN bit TOP_MASK.TDIE_WARN_ TOP_STAT.TDIE_WARN Interrupt is not cleared MASK _STAT if temperature is above thermal warning level N/A Write 1 to INT_TOP.TDIE_SD bit TOP_STAT.TDIE_SD_ST Interrupt is not cleared AT if temperature is above thermal shutdown level Powergood, output voltage reaches the programmed value No effect INT_TOP.INT_BUCKx = 1 Write 1 to INT_BUCK_0_1.BUCKx_PG BUCK_0_1_MASK.BUCKx BUCK_0_1_STAT.BUCKx INT_BUCK_0_1.BUCKx_ _INT = 1 _PG_MASK _PG_STAT PG_INT bit or BUCK_2_3_MASK.BUCKx BUCK_2_3_STAT.BUCKx or to INT_BUCK_2_3.BUCKx_PG _PG_MASK _PG_STAT INT_BUCK_2_3.BUCKx_ _INT = 1 PG_INT bit Load current measurement ready No effect INT_TOP.I_LOAD_READY = TOP_MASK.I_LOAD_REA 1 DY_MASK N/A Write 1 to INT_TOP.I_LOAD_READ Y bit Start-up (NRST rising edge) Device ready for operation, registers reset to default values INT_TOP.RESET_REG = 1 TOP_MASK.RESET_REG_ MASK N/A Write 1 to INT_TOP.RESET_REG bit Glitch on supply voltage and UVLO triggered (VANA falling and rising) Immediate shutdown followed by powerup, registers reset to default values INT_TOP.RESET_REG = 1 TOP_MASK.RESET_REG_ MASK N/A Write 1 to INT_TOP.RESET_REG bit Software requested reset Immediate shutdown followed by powerup, registers reset to default values INT_TOP.RESET_REG = 1 TOP_MASK.RESET_REG_ MASK N/A Write 1 to INT_TOP.RESET_REG bit 7.3.5.1 Warnings for Diagnosis (Interrupt) 7.3.5.1.1 Output Current Limit The converter cores have programmable output peak current limits. The limits are individually programmed for all buck converter cores with BUCKx_CTRL2.ILIMx[2:0] bits. If the load current is increased so that the current limit is triggered, the regulator continues to regulate to the limit current level (current peak regulation). The voltage may decrease if the load current is higher than limit current. If the current regulation continues for 20 µs, the LP8758-EA device sets the INT_BUCKx.BUCKx_ILIM_INT bit and pulls the nINT pin low. The host processor can read BUCKx_STAT.BUCKx_ILIM_STAT bits to see if the converter cores is still in peak current regulation mode. For example, if the load on Buck0 output is so high that the output voltage VOUT decreases below a 350-mV level, the LP8758-EA device disables the converter core Buck0 and sets the INT_BUCK_0_1.BUCK0_SC_INT bit. In addition the BUCK_0_1_STAT.BUCK0_STAT bit is set to 0. The interrupt is cleared when the host processor writes 1 to INT_BUCK_0_1.BUCK0_SC_INT bit. The overload situation is shown in Figure 7-6. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 19 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 New startup if enable is valid Regulator disabled by digital Voltage VOUTx 350 mV Resistive pulldown 1 ms Time Current ILIMx Time 25 ms BUCKx_ILIM_INT bit (INT_BUCKx register) 0 BUCKx_SC_INT bit (INT_BUCKx register) 0 1 0 BUCKx_STAT bit (BUCKx_STAT register) 1 0 1 1 0 nINT Host clearing the interrupt by writing to flags Figure 7-6. Overload Situation 7.3.5.1.2 Thermal Warning The LP8758-EA device includes protection features against overtemperature by setting an interrupt for host processor. The threshold level of the thermal warning is selected with CONFIG.TDIE_WARN_LEVEL bit. If the LP8758-EA device temperature increases above the thermal warning level, the device sets INT_TOP.TDIE_WARN bit and pulls nINT pin low. The status of the thermal warning can be read from TOP_STAT.TDIE_WARN_STAT bit, and the interrupt is cleared by writing 1 to INT_TOP.TDIE_WARN bit. 7.3.5.2 Protection (Regulator Disable) If the regulator is disabled because of protection or fault (short-circuit protection, overload protection, thermal shutdown, or undervoltage lockout), the output power FETs are set to high-impedance mode, and the output pulldown resistor is enabled (if enabled with the BUCKx_CTRL1.EN_RDISx bits). The turnoff time of the output voltage is defined by the output capacitance, load current, and the resistance of the integrated pulldown resistor. 7.3.5.2.1 Short-Circuit and Overload Protection A short-circuit protection feature allows the LP8758-EA to protect itself and external components against short circuit at the output or against overload during start-up. The fault threshold is 350 mV, and the protection is triggered and the converter core is disabled if the output voltage is still below the threshold level 1 ms after the converter core was enabled. In a similar way the overload situation is protected during normal operation. If a feedback-pin voltage falls below 0.35 V, and remains below the threshold level for 1 ms, the respective converter core is disabled. For example, if the Buck core 0 output is overloaded, then the INT_BUCK_0_1.BUCK0_SC_INT and the INT_TOP.INT_BUCK0 bits are set to 1, the BUCK_0_1_STAT.BUCK0_STAT bit is set to 0, and the nINT signal is pulled low. The host processor clears the interrupt by writing 1 to the INT_BUCK_0_1.BUCK0_SC_INT bit. 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 The regulator makes a new start-up attempt (upon clearing the interrupt) if the enable register bits, ENx control signal, or both are valid. 7.3.5.2.2 Thermal Shutdown The LP8758-EA has an over-temperature protection function that operates to protect itself from short-term misuse and overload conditions. When the junction temperature exceeds around 150°C, the cores are disabled, the INT_TOP.TDIE_SD bit is set to 1, the nINT signal is pulled low, and the device enters STANDBY. The nINT is cleared by writing 1 to the INT_TOP.TDIE_SD bit. If the temperature is above the thermal shutdown level, then the interrupt is not cleared. The host can read the status of the thermal shutdown from the TOP_STAT.TDIE_SD_STAT bit. Converter cores cannot be enabled as long as the junction temperature is above the thermal shutdown level or the thermal shutdown interrupt is pending. 7.3.5.3 Fault (Power Down) 7.3.5.3.1 Undervoltage Lockout When the input voltage falls below VANAUVLO at the VANA pin, the converter cores are disabled immediately, and the output capacitors are discharged using the pulldown resistors and the LP8758-EA device enters SHUTDOWN. When VANA voltage is above the UVLO threshold level and NRST signal is high, the device powers up to STANDBY state. If the reset interrupt is unmasked by default (TOP_MASK.RESET_REG_MASK = 0) the INT_TOP.RESET_REG interrupt indicates that the device has been in SHUTDOWN. The host processor must clear the interrupt by writing 1 to the INT_TOP.RESET_REG bit. If the host processor reads the INT_TOP.RESET_REG flag after detecting an nINT low signal, it knows that the input supply voltage has been below UVLO level (or the host has requested reset), and the registers are reset to default values. 7.3.6 Digital Signal Filtering The digital signals have debounce filtering. The signal or supply is sampled with a clock signal and a counter. This results as an accuracy of one clock period for the debounce window. Table 7-3. Digital Signal Filtering EVENT SIGNAL / SUPPLY Enable, disable, or voltage select for BUCKx VANA undervoltage lockout Thermal warning Thermal shutdown Current limit RISING EDGE LENGTH FALLING EDGE LENGTH ENx 3 µs(1) 3 µs(1) VANA Immediate Immediate TDIE_WARN 20 µs 20 µs TDIE_SD 20 µs 20 µs VOUTx_ILIM 20 µs 20 µs Overload FB_B0, FB_B1, FB_B2, FB_F3 1 ms 1 ms Power-good FB_B0, FB_B1, FB_B2, FB_F3 20 µs 20 µs (1) No glitch filtering, only synchronization. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 21 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.4 Device Functional Modes 7.4.1 Modes of Operation SHUTDOWN: The V(NRST) voltage is below threshold level. All switch, reference, control and bias circuitry of the LP8758-EA device are turned off. WAIT-ON: The V(NRST) voltage is above threshold level. The reference and bias circuitry are enabled. The converter cores of the LP8758-EA device are turned off. READ OTP: The main supply voltage V(VANA) is above VANAUVLO level and V(NRST) voltage is above threshold level. The converter cores are disabled and the reference and bias circuitry of the LP8758-EA are enabled. The OTP bits are loaded to registers. STANDBY: The main supply voltage V(VANA) is above VANAUVLO level and V(NRST) voltage is above threshold level. The converter cores are disabled and the reference, control and bias circuitry of the LP8758-EA are enabled. All registers can be read or written by the host processor through the system serial interface. The converter cores can be enabled if needed. ACTIVE: The main supply voltage V(VANA) is above VANAUVLO level and V(NRST) voltage is above threshold level. At least one converter core is enabled. All registers can be read or written by the host processor through the system serial interface. The operating modes and transitions between the modes are shown in Figure 7-7. SHUTDOWN NRST high NRST low From any state except SHUTDOWN V(VANA) > VANAUVLO WAIT-ON READ OTP V(VANA) < VANAUVLO From any state except SHUTDOWN REGISTER RESET I2C RESET STANDBY REGULATOR ENABLED REGULATORS DISABLED ACTIVE Figure 7-7. Device Operation Modes 22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.5 Programming 7.5.1 I2C-Compatible Interface The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the devices connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). Every device on the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed somewhere on the line and remain HIGH even when the bus is idle. The LP8758-EA supports standard mode (100 kHz), fast mode (400 kHz), fast mode plus (1 MHz), and high-speed mode (3.4 MHz). 7.5.1.1 Data Validity The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state of the data line can only be changed when clock signal is LOW. SCL SDA data change allowed data valid data change allowed data valid data change allowed Figure 7-8. Data Validity Diagram 7.5.1.2 Start and Stop Conditions The LP8758-EA is controlled through an I2C-compatible interface. START and STOP conditions classify the beginning and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I2C master always generates the START and STOP conditions. SDA SCL S P START Condition STOP Condition Figure 7-9. Start and Stop Sequences The I2C bus is considered busy after a START condition and free after a STOP condition. During data transmission the I2C master can generate repeated START conditions. A START and a repeated START condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 7-10 shows the SDA and SCL signal timing for the I2C-Compatible Bus. See the Section 6.6 for timing values. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 23 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 tBUF SDA tHD;STA trCL tfDA tLOW trDA tSP tfCL SCL tHD;STA tSU;STA tSU;STO tHIGH tHD;DAT S tSU;DAT START RS P S REPEATED START STOP START Figure 7-10. I2C-Compatible Timing 7.5.1.3 Transferring Data Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP8758-EA pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP8758-EA generates an acknowledge after each byte has been received. There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. Note If the NRST signal is low during I2C communication the LP8758-EA device does not drive SDA line. The ACK signal and data transfer to the master is disabled at that time. After the START condition, the bus master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1 indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register. ACK from slave ACK from slave START MSB Chip Address LSB ACK from slave W ACK MSB Register Address LSB ACK MSB Data LSB ACK STOP W ACK address 0x40 data ACK STOP SCL SDA START id = 0x60 address = 0x40 ACK Figure 7-11. Write Cycle (w = write; SDA = 0), id = Device Address = 60Hex for LP8758-EA 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 ACK from slave START MSB Chip Address LSB W id = 0x60 W ACK from slave MSB Register Address LSB REPEATED START ACK from slave Data from slave NACK from master RS MSB Chip Address LSB R RS id = 0x60 R MSB Data LSB STOP SCL SDA START address = 0x3F ACK ACK address 0x3F data ACK NACK STOP When READ function is to be accomplished, a WRITE function must precede the READ function as shown above. Figure 7-12. Read Cycle ( r = read; SDA = 1), id = Device Address = 60Hex for LP8758-EA 7.5.1.4 I2C-Compatible Chip Address The device address for the LP8758-EA is 0x60. After the START condition, the I2C master sends the 7-bit address followed by an eighth bit, read or write (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address selects the register address to which the data will be written. The third byte contains the data for the selected register. MSB 1 Bit 7 LSB 1 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 R/W Bit 0 2 I C Slave Address (chip address) Here device address is 110 0000Bin = . Figure 7-13. Device Address 7.5.1.5 Auto Increment Feature The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-bit word is sent to the LP8758-EA, the internal address index counter is incremented by one and the next register is written. Table 7-4 below shows writing sequence to two consecutive registers. Note: the autoincrement feature does not work for read. Table 7-4. Auto-Increment Example Master Action Start Device Address = 60H Write LP8758EA Action Register Address ACK Data ACK Data ACK Stop ACK Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 25 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.6 Register Maps 7.6.1 Register Descriptions The LP8758-EA is controlled by a set of registers through the serial interface port. The device registers, their addresses and their abbreviations are listed in Table 7-5. A more detailed description is given in sections Section 7.6.1.1 to Section 7.6.1.35. The asterisk (*) marking indicates register bits which are updated from OTP memory during READ OTP state. Table 7-5. Summary of LP8758-EA Control Registers Addr 26 Register Read / Write D7 D6 D5 D4 D3 D2 D1 D0 0x01 OTP_REV R OTP_ID[7:0] 0x02 BUCK0_ CTRL1 R/W 0x03 BUCK0_ CTRL2 R/W 0x04 BUCK1_ CTRL1 R/W 0x05 BUCK1_ CTRL2 R/W 0x06 BUCK2_ CTRL1 R/W 0x07 BUCK2_ CTRL2 R/W 0x08 BUCK3_ CTRL1 R/W 0x09 BUCK3_ CTRL2 R/W 0x0A BUCK0_ VOUT R/W BUCK0_VSET[7:0] 0x0B BUCK0_ FLOOR_ VOUT R/W BUCK0_FLOOR_VSET[7:0] 0x0C BUCK1_ VOUT R/W BUCK1_VSET[7:0] 0x0D BUCK1_ FLOOR_ VOUT R/W BUCK1_FLOOR_VSET[7:0] 0x0E BUCK2_ VOUT R/W BUCK2_VSET[7:0] 0x0F BUCK2_ FLOOR_ VOUT R/W BUCK2_FLOOR_VSET[7:0] 0x10 BUCK3_ VOUT R/W BUCK3_VSET[7:0] 0x11 BUCK3_ FLOOR_ VOUT R/W BUCK3_FLOOR_VSET[7:0] 0x12 BUCK0_ DELAY R/W BUCK0_SHUTDOWN_DELAY[3:0] BUCK0_STARTUP_DELAY[3:0] 0x13 BUCK1_ DELAY R/W BUCK1_SHUTDOWN_DELAY[3:0] BUCK1_STARTUP_DELAY[3:0] 0x14 BUCK2_ DELAY R/W BUCK2_SHUTDOWN_DELAY[3:0] BUCK2_STARTUP_DELAY[3:0] 0x15 BUCK3_ DELAY R/W BUCK3_SHUTDOWN_DELAY[3:0] BUCK3_STARTUP_DELAY[3:0] 0x16 RESET R/W 0x17 CONFIG R/W 0x18 INT_TOP R/W EN_BUCK0 EN_PIN_ CTRL0 EN_PIN_ SELECT0 Reserved EN_BUCK1 EN_PIN_ CTRL1 EN_PIN_ SELECT1 Reserved EN_ROOF _FLOOR1 EN_PIN_ CTRL2 EN_PIN_ SELECT2 EN_ROOF _FLOOR2 EN_RDIS1 Reserved EN_PIN_ SELECT3 Reserved EN_ROOF _FLOOR3 EN_RDIS2 Reserved BUCK1_ FPWM BUCK2_ FPWM EN_RDIS3 Reserved BUCK3_ FPWM INT_ BUCK2 INT_ BUCK1 INT_ BUCK0 Submit Document Feedback Reserved Reserved SLEW_RATE3[2:0] Reserved INT_ BUCK3 Reserved SLEW_RATE2[2:0] ILIM3[2:0] Reserved Reserved SLEW_RATE1[2:0] ILIM2[2:0] EN_PIN_ CTRL3 BUCK0_ FPWM SLEW_RATE0[2:0] ILIM1[2:0] Reserved EN_BUCK3 EN_RDIS0 ILIM0[2:0] Reserved EN_BUCK2 EN_ROOF _FLOOR0 SW_ RESET TDIE _WARN _LEVEL EN2_PD EN1_PD EN_ SPREAD _SPEC TDIE_SD TDIE_ WARN RESET_ REG I_LOAD_ READY Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 Table 7-5. Summary of LP8758-EA Control Registers (continued) Addr Register Read / Write D7 D6 D5 D4 D3 D2 D1 D0 0x19 INT_BUCK_ 0_1 R/W Reserved BUCK1_ PG_INT BUCK1_ SC_INT BUCK1_ ILIM_INT Reserved BUCK0_ PG_INT BUCK0_ SC_INT BUCK0_ ILIM_INT 0x1A INT_BUCK_ 2_3 R/W Reserved BUCK3_ PG_INT BUCK3_ SC_INT BUCK3_ ILIM_INT Reserved BUCK2_ PG_INT BUCK2_ SC_INT BUCK2_ ILIM_INT 0x1B TOP_ STAT R TDIE_SD _STAT TDIE_ WARN_ STAT 0x1C BUCK_0_1_ STAT R BUCK1_ STAT BUCK1_ PG_STAT Reserved BUCK1_ ILIM_ STAT BUCK0_ STAT BUCK0_ PG_STAT Reserved BUCK0_ ILIM_ STAT 0x1D BUCK_2_3_ STAT R BUCK3_ STAT BUCK3_ PG_STAT Reserved BUCK3_ ILIM_STAT BUCK2_ STAT BUCK2_ PG_STAT Reserved BUCK2_ ILIM_STAT 0x1E TOP_ MASK R/W 0x1F BUCK_0_1_ MASK R/W Reserved BUCK1_ PG_MASK Reserved BUCK1_ ILIM_ MASK Reserved BUCK0_ PG_MASK Reserved BUCK0_ ILIM_ MASK 0x20 BUCK_2_3_ MASK R/W Reserved BUCK3_ PG_MASK Reserved BUCK3_ ILIM_ MASK Reserved BUCK2_ PG_MASK Reserved BUCK2_ ILIM_ MASK 0x21 SEL_I_ LOAD R/W Reserved LOAD_CURRENT_ BUCK_SELECT[1:0] 0x22 I_LOAD_2 R/W Reserved BUCK_LOAD_CURRENT[ 9:8] 0x23 I_LOAD_1 R/W Reserved Reserved Reserved TDIE_WARN RESET_ _MASK REG_MASK I_LOAD_ READY_ MASK BUCK_LOAD_CURRENT[7:0] Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 27 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.6.1.1 OTP_REV Address: 0x01 D7 D6 D5 D4 D3 D2 D1 D0 OTP_ID[7:0] Bits Field Type Default 7:0 OTP_ID[7:0] R 0xEA * Description Identification code of the OTP EPROM version. 7.6.1.2 BUCK0_CTRL1 Address: 0x02 D7 D6 D5 D4 D3 D2 D1 D0 EN_BUCK0 EN_PIN_ CTRL0 EN_PIN_ SELECT0 EN_ROOF_ FLOOR0 EN_RDIS0 Reserved BUCK0_FPWM Reserved Bits Field Type Default 7 EN_BUCK0 R/W 1* Enable BUCK0 converter core: 0 - BUCK0 converter core is disabled. 1 - BUCK0 converter core is enabled. 6 EN_PIN_CTRL0 R/W 1* Enable EN1/2 pin control for BUCK0: 0 - only EN_BUCK0 bit controls BUCK0. 1 - EN_BUCK0 bit AND EN1/2 pin control BUCK0. 5 EN_PIN_SELECT0 R/W 0* Select which ENx pin controls BUCK0 if EN_PIN_CTRL0 = 1: 0 - EN1 pin. 1 - EN2 pin. 4 EN_ROOF_ FLOOR0 R/W 0 Enable Roof/Floor control of EN1/2 pin if EN_PIN_CTRL0 = 1: 0 - Enable/Disable (1/0) control. 1 - Roof/Floor (1/0) control. 3 EN_RDIS0 R/W 1 Enable output discharge resistor when BUCK0 is disabled: 0 - Discharge resistor disabled. 1 - Discharge resistor enabled. 2 Reserved R/W 0 1 BUCK0_FPWM R/W 0* 0 Reserved R/W 0 Description Forces the BUCK0 converter core to operate in PWM mode: 0 - Automatic transitions between PFM and PWM modes (AUTO mode). 1 - Forced to PWM operation. 7.6.1.3 BUCK0_CTRL2 Address: 0x03 D7 D6 D5 D4 Reserved Bits 28 D3 D2 D1 ILIM0[2:0] Field Type Default 7:6 Reserved R/W 00 5:3 ILIM0[2:0] R/W 0x6 * D0 SLEW_RATE0[2:0] Description Sets the switch current limit of BUCK0. Can be programmed at any time during operation: 0x2 - 2.5 A 0x3 - 3.0 A 0x4 - 3.5 A 0x5 - 4.0 A 0x6 - 4.5 A 0x7 - 5.0 A Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 Bits Field Type Default Description 2:0 SLEW_RATE0[2:0] R/W 0x4 * Sets the output voltage slew rate for BUCK0 converter core (rising and falling edges): 0x0 - 30 mV/µs 0x1 - 15 mV/µs 0x2 - 10 mV/µs 0x3 - 7.5 mV/µs 0x4 - 3.8 mV/µs 0x5 - 1.9 mV/µs 0x6 - 0.94 mV/µs 0x7 - 0.4 mV/µs 7.6.1.4 BUCK1_CTRL1 Address: 0x04 D7 D6 D5 D4 D3 D2 D1 D0 EN_BUCK1 EN_PIN_ CTRL1 EN_PIN_ SELECT1 EN_ROOF_ FLOOR1 EN_RDIS1 Reserved BUCK1_FPWM Reserved Bits Field Type Default 7 EN_BUCK1 R/W 1* Enable BUCK1 converter core: 0 - BUCK1 converter core is disabled. 1 - BUCK1 converter core is enabled. 6 EN_PIN_CTRL1 R/W 1* Enable EN1/2 pin control for BUCK1: 0 - only EN_BUCK1 bit controls BUCK1. 1 - EN_BUCK1 bit AND EN1/2 pin control BUCK1. 5 EN_PIN_SELECT1 R/W 0* Select which ENx pin controls BUCK1 if EN_PIN_CTRL1 = 1: 0 - EN1 pin 1 - EN2 pin. 4 EN_ROOF_ FLOOR1 R/W 0 Enable Roof/Floor control of EN1/2 pin if EN_PIN_CTRL1 = 1: 0 - Enable/Disable (1/0) control. 1 - Roof/Floor (1/0) control. 3 EN_RDIS1 R/W 1 Enable output discharge resistor when BUCK1 is disabled: 0 - Discharge resistor is disabled. 1 - Discharge resistor is enabled. 2 Reserved R/W 0 1 BUCK1_FPWM R/W 0* 0 Reserved R/W 0 Description Forces the BUCK1 converter core to operate in PWM mode: 0 - Automatic transitions between PFM and PWM modes (AUTO mode). 1 - Forced to PWM operation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 29 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.6.1.5 BUCK1_CTRL2 Address: 0x05 D7 D6 D5 D4 Reserved D3 D2 D1 ILIM1[2:0] D0 SLEW_RATE1[2:0] Bits Field Type Default 7:6 Reserved R/W 00 Description 5:3 ILIM1[2:0] R/W 0x6 * Sets the switch current limit of BUCK1. Can be programmed at any time during operation: 0x2 - 2.5 A 0x3 - 3.0 A 0x4 - 3.5 A 0x5 - 4.0 A 0x6 - 4.5 A 0x7 - 5.0 A 2:0 SLEW_RATE1[2:0] R/W 0x4 * Sets the output voltage slew rate for BUCK1 converter core (rising and falling edges): 0x0 - 30 mV/µs 0x1 - 15 mV/µs 0x2 - 10 mV/µs 0x3 - 7.5 mV/µs 0x4 - 3.8 mV/µs 0x5 - 1.9 mV/µs 0x6 - 0.94 mV/µs 0x7 - 0.4 mV/µs 7.6.1.6 BUCK2_CTRL1 Address: 0x06 D7 D6 D5 D4 D3 D2 D1 D0 EN_BUCK2 EN_PIN_ CTRL2 EN_PIN_ SELECT2 EN_ROOF_ FLOOR2 EN_RDIS2 Reserved BUCK2_FPWM Reserved Bits Field Type Default 7 EN_BUCK2 R/W 1* Enable BUCK2 converter core: 0 - BUCK2 converter core is disabled. 1 - BUCK2 converter core is enabled. 6 EN_PIN_CTRL2 R/W 1* Enable EN1/2 pin control for BUCK2: 0 - only EN_BUCK2 bit controls BUCK2. 1 - EN_BUCK2 bit AND EN1/2 pin control BUCK2. 5 EN_PIN_SELECT2 R/W 1* Select which ENx pin controls BUCK2 if EN_PIN_CTRL2 = 1: 0 - EN1 pin 1 - EN2 pin. 4 EN_ROOF_ FLOOR2 R/W 0 Enable Roof/Floor control of EN1/2 pin if EN_PIN_CTRL2 = 1: 0 - Enable/Disable (1/0) control. 1 - Roof/Floor (1/0) control. 3 EN_RDIS2 R/W 1 Enable output discharge resistor when BUCK2 is disabled: 0 - Discharge resistor is disabled. 1 - Discharge resistor is enabled. 30 2 Reserved R/W 0 1 BUCK2_FPWM R/W 0* 0 Reserved R/W 0 Description Forces the BUCK2 converter core to operate in PWM mode: 0 - Automatic transitions between PFM and PWM modes (AUTO mode). 1 - Forced to PWM operation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.6.1.7 BUCK2_CTRL2 Address: 0x07 D7 D6 D5 D4 Reserved D3 D2 ILIM2[2:0] D1 D0 SLEW_RATE2[2:0] Bits Field Type Default 7:6 Reserved R/W 00 Description 5:3 ILIM2[2:0] R/W 0x6 * Sets the switch current limit of BUCK2. Can be programmed at any time during operation: 0x2 - 2.5 A 0x3 - 3.0 A 0x4 - 3.5 A 0x5 - 4.0 A 0x6 - 4.5 A 0x7 - 5.0 A 2:0 SLEW_RATE2[2:0] R/W 0x4 * Sets the output voltage slew rate for BUCK2 converter core (rising and falling edges): 0x0 - 30 mV/µs 0x1 - 15 mV/µs 0x2 - 10 mV/µs 0x3 - 7.5 mV/µs 0x4 - 3.8 mV/µs 0x5 - 1.9 mV/µs 0x6 - 0.94 mV/µs 0x7 - 0.4 mV/µs 7.6.1.8 BUCK3_CTRL1 Address: 0x08 D7 D6 D5 D4 D3 D2 D1 D0 EN_BUCK3 EN_PIN_ CTRL3 EN_PIN_ SELECT3 EN_ROOF_ FLOOR3 EN_RDIS3 Reserved BUCK3_FPWM Reserved Bits Field Type Default 7 EN_BUCK3 R/W 1* Enable BUCK3 converter core: 0 - BUCK3 converter core is disabled. 1 - BUCK3 converter core is enabled. 6 EN_PIN_CTRL3 R/W 1* Enable EN1/2 pin control for BUCK3: 0 - only EN_BUCK3 bit controls BUCK3 1 - EN_BUCK3 bit AND EN1/2 pin control BUCK3. 5 EN_PIN_SELECT3 R/W 1* Select which ENx pin controls BUCK3 if EN_PIN_CTRL3 = 1: 0 - EN1 pin 1 - EN2 pin. 4 EN_ROOF_ FLOOR3 R/W 0 Enable Roof/Floor control of EN1/2 pin if EN_PIN_CTRL3 = 1: 0 - Enable/Disable (1/0) control 1 - Roof/Floor (1/0) control. 3 EN_RDIS3 R/W 1 Enable output discharge resistor when BUCK3 is disabled: 0 - Discharge resistor is disabled. 1 - Discharge resistor is enabled. 2 Reserved R/W 0 1 BUCK3_FPWM R/W 0* 0 Reserved R/W 0 Description Forces the BUCK3 converter core to operate in PWM mode: 0 - Automatic transitions between PFM and PWM modes (AUTO mode). 1 - Forced to PWM operation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 31 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.6.1.9 BUCK3_CTRL2 Address: 0x09 D7 D6 D5 D4 Reserved D3 D2 D1 ILIM3[2:0] D0 SLEW_RATE3[2:0] Bits Field Type Default 7:6 Reserved R/W 00 Description 5:3 ILIM3[2:0] R/W 0x6 * Sets the switch current limit of BUCK3. Can be programmed at any time during operation: 0x2 - 2.5 A 0x3 - 3.0 A 0x4 - 3.5 A 0x5 - 4.0 A 0x6 - 4.5 A 0x7 - 5.0 A 2:0 SLEW_RATE3[2:0] R/W 0x4 * Sets the output voltage slew rate for BUCK3 converter core (rising and falling edges): 0x0 - 30 mV/µs 0x1 - 15 mV/µs 0x2 - 10 mV/µs 0x3 - 7.5 mV/µs 0x4 - 3.8 mV/µs 0x5 - 1.9 mV/µs 0x6 - 0.94 mV/µs 0x7 - 0.4 mV/µs 7.6.1.10 BUCK0_VOUT Address: 0x0A D7 D6 D5 D4 D3 D2 D1 D0 BUCK0_VSET[7:0] Bits Field Type Default 7:0 BUCK0_VSET[7:0] R/W 0x37 * 32 Description Sets the output voltage of BUCK0 converter core (Default 900 mV) 0.5 V - 0.73 V, 10 mV steps 0x00 - 0.5 V ... 0x17 - 0.73 V 0.73 V - 1.4 V, 5 mV steps 0x18 - 0.735 V ... 0x9D - 1.4 V 1.4 V - 3.36 V, 20 mV steps 0x9E - 1.42 V ... 0xFF - 3.36 V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.6.1.11 BUCK0_FLOOR_VOUT Address: 0x0B D7 D6 D5 D4 D3 D2 D1 D0 BUCK0_FLOOR_VSET[7:0] Bits Field Type Default 7:0 BUCK0_FLOOR_VSET[ 7:0] R/W 0x00 Description Sets the output voltage of BUCK0 converter core when Floor state is used: 0.5 V - 0.73 V, 10 mV steps 0x00 - 0.5 V ... 0x17 - 0.73 V 0.73 V - 1.4 V, 5 mV steps 0x18 - 0.735 V ... 0x9D - 1.4 V 1.4 V - 3.36 V, 20 mV steps 0x9E - 1.42 V ... 0xFF - 3.36 V 7.6.1.12 BUCK1_VOUT Address: 0x0C D7 D6 D5 D4 D3 D2 D1 D0 BUCK1_VSET[7:0] Bits Field Type Default 7:0 BUCK1_VSET[7:0] R/W 0x37 * Description Sets the output voltage of BUCK1 converter core (Default 1200 mV): 0.5 V - 0.73 V, 10 mV steps 0x00 - 0.5 V ... 0x17 - 0.73 V 0.73 V - 1.4 V, 5 mV steps 0x18 - 0.735 V ... 0x9D - 1.4 V 1.4 V - 3.36 V, 20 mV steps 0x9E - 1.42 V ... 0xFF - 3.36 V 7.6.1.13 BUCK1_FLOOR_VOUT Address: 0x0D D7 D6 D5 D4 D3 D2 D1 D0 BUCK1_FLOOR_VSET[7:0] Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 33 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 Bits Field Type Default 7:0 BUCK1_FLOOR_VSET[7:0] R/W 0x00 Description Sets the output voltage of BUCK1 converter core when the Floor state is used: 0.5 V - 0.73 V, 10 mV steps 0x00 - 0.5V ... 0x17 - 0.73 V 0.73 V - 1.4 V, 5 mV steps 0x18 - 0.735 V ... 0x9D - 1.4 V 1.4 V - 3.36 V, 20 mV steps 0x9E - 1.42 V ... 0xFF - 3.36 V 7.6.1.14 BUCK2_VOUT Address: 0x0E D7 D6 D5 D4 D3 D2 D1 D0 BUCK2_VSET[7:0] Bits Field Type Default 7:0 BUCK2_VSET[7:0] R/W 0x37 * Description Sets the output voltage of BUCK2 converter core (Default 1800 mV): 0.5 V - 0.73 V, 10 mV steps 0x00 - 0.5V ... 0x17 - 0.73 V 0.73 V - 1.4 V, 5 mV steps 0x18 - 0.735 V ... 0x9D - 1.4 V 1.4 V - 3.36 V, 20 mV steps 0x9E - 1.42 V ... 0xFF - 3.36 V 7.6.1.15 BUCK2_FLOOR_VOUT Address: 0x0F D7 D6 D5 D4 D3 D2 D1 D0 BUCK2_FLOOR _VSET[7:0] Bits Field Type Default 7:0 BUCK2_FLOOR _VSET[7:0] R/W 0x00 34 Description Sets the output voltage of BUCK2 converter core when the Floor state is used: 0.5 V - 0.73 V, 10 mV steps 0x00 - 0.5 V ... 0x17 - 0.73 V 0.73 V - 1.4 V, 5 mV steps 0x18 - 0.735 V ... 0x9D - 1.4 V 1.4 V - 3.36 V, 20 mV steps 0x9E - 1.42 V ... 0xFF - 3.36 V Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.6.1.16 BUCK3_VOUT Address: 0x10 D7 D6 D5 D4 D3 D2 D1 D0 BUCK3_VSET[7:0] Bits Field Type Default 7:0 BUCK3_VSET[7:0] R/W 0x37 * Description Sets the output voltage of BUCK3 converter core (Default 2700 mV) 0.5 V - 0.73 V, 10 mV steps 0x00 - 0.5 V ... 0x17 - 0.73 V 0.73 V - 1.4 V, 5 mV steps 0x18 - 0.735 V ... 0x9D - 1.4 V 1.4 V - 3.36 V, 20 mV steps 0x9E - 1.42 V ... 0xFF - 3.36 V 7.6.1.17 BUCK3_FLOOR_VOUT Address: 0x11 D7 D6 D5 D4 D3 D2 D1 D0 BUCK3_FLOOR _VSET[7:0] Bits Field Type Default 7:0 BUCK3_FLOOR _VSET[7:0] R/W 0x00 Description Sets the output voltage of BUCK3 converter core when Floor state is used: 0.5 V - 0.73 V, 10 mV steps 0x00 - 0.5 V ... 0x17 - 0.73 V 0.73 V - 1.4 V, 5 mV steps 0x18 - 0.735 V ... 0x9D - 1.4 V 1.4 V - 3.36 V, 20 mV steps 0x9E - 1.42 V ... 0xFF - 3.36 V 7.6.1.18 BUCK0_DELAY Address: 0x12 D7 D6 D5 D4 D3 BUCK0_SHUTDOWN_DELAY[3:0] Bits Field Type Default 7:4 BUCK0_ SHUTDOWN_ DELAY[3:0] R/W 0x0 * D2 D1 D0 BUCK0_STARTUP_DELAY[3:0] Description Shutdown delay of BUCK0 from falling edge of the ENx signal: 0x0 - 0 ms 0x1 - 1 ms ... 0xF - 15 ms Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 35 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 Bits Field Type Default 3:0 BUCK0_ STARTUP_ DELAY[3:0] R/W 0x0 * Description Startup delay of BUCK0 from rising edge of the ENx signal: 0x0 - 0 ms 0x1 - 1 ms ... 0xF - 15 ms 7.6.1.19 BUCK1_DELAY Address: 0x13 D7 D6 D5 D4 D3 BUCK1_SHUTDOWN_DELAY[3:0] D2 D1 D0 BUCK1_STARTUP_DELAY[3:0] Bits Field Type Default 7:4 BUCK1_ SHUTDOWN_ DELAY[3:0] R/W 0x0 * Shutdown delay of BUCK1 from falling edge of the ENx signal: 0x0 - 0 ms 0x1 - 1 ms ... 0xF - 15 ms Description 3:0 BUCK1_ STARTUP_ DELAY[3:0] R/W 0x0 * Startup delay of BUCK1 from rising edge of the ENx signal: 0x0 - 0 ms 0x1 - 1 ms ... 0xF - 15 ms 7.6.1.20 BUCK2_DELAY Address: 0x14 D7 D6 D5 D4 D3 BUCK2_SHUTDOWN_DELAY[3:0] D2 D1 D0 BUCK2_STARTUP_DELAY[3:0] Bits Field Type Default 7:4 BUCK2_ SHUTDOWN_ DELAY[3:0] R/W 0x0 * Shutdown delay of BUCK2 from falling edge of the ENx signal: 0x0 - 0 ms 0x1 - 1 ms ... 0xF - 15 ms Description 3:0 BUCK2_ STARTUP_ DELAY[3:0] R/W 0x0 * Start-up delay of BUCK2 from rising edge of the ENx signal: 0x0 - 0 ms 0x1 - 1 ms ... 0xF - 15 ms 7.6.1.21 BUCK3_DELAY Address: 0x15 D7 D6 D5 D4 D3 BUCK3_SHUTDOWN_DELAY[3:0] Bits Field Type Default 7:4 BUCK3_ SHUTDOWN_ DELAY[3:0] R/W 0x0 * 36 D2 D1 D0 BUCK3_STARTUP_DELAY[3:0] Description Shutdown delay of BUCK3 from falling edge of the ENx signal: 0x0 - 0 ms 0x1 - 1 ms ... 0xF - 15 ms Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 Bits Field Type Default 3:0 BUCK3_ STARTUP_ DELAY[3:0] R/W 0x0 * Description Start-up delay of BUCK3 from rising edge of the ENx signal: 0x0 - 0 ms 0x1 - 1 ms ... 0xF - 15 ms 7.6.1.22 RESET Address: 0x16 D7 D6 D5 D4 D3 D2 Reserved Bits Field Type Default 7:1 Reserved R/W 0000 000 0 SW_RESET R/W 0 D1 D0 SW_RESET Description Software commanded reset. When written to 1, the registers are reset to default values, OTP memory is read, and the I2C interface is reset. The bit is automatically cleared. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 37 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.6.1.23 CONFIG Address: 0x17 D7 D6 D5 D4 Reserved Bits D3 D2 D1 D0 TDIE_WARN_ LEVEL EN2_PD EN1_PD EN_SPREAD _SPEC Field Type Default Description 7:4 Reserved R/W 0000 3 TDIE_WARN_LEVEL R/W 0 Thermal warning threshold level. 0 - 125°C 1 - 105°C 2 EN2_PD R/W 1 Selects the pulldown resistor on the EN2 input pin. 0 - Pulldown resistor is disabled. 1 - Pulldown resistor is enabled. 1 EN1_PD R/W 1 Selects the pull down resistor on the EN1 input pin. 0 - Pulldown resistor is disabled. 1 - Pulldown resistor is enabled. 0 EN_SPREAD_SPEC R/W 0 Enable spread-spectrum feature: 0 - Disabled 1 - Enabled 7.6.1.24 INT_TOP Address: 0x18 D7 D6 D5 D4 D3 D2 D1 D0 INT_BUCK3 INT_BUCK2 INT_BUCK1 INT_BUCK0 TDIE_SD TDIE_WARN RESET_REG I_LOAD_ READY Bits Field Type Default 7 INT_BUCK3 R 0 Interrupt indicating that output BUCK3 has a pending interrupt. The reason for the interrupt is indicated in INT_BUCK3 register. This bit is cleared automatically when INT_BUCK3 register is cleared to 0x00. 6 INT_BUCK2 R 0 Interrupt indicating that output BUCK2 has a pending interrupt. The reason for the interrupt is indicated in INT_BUCK2 register. This bit is cleared automatically when INT_BUCK2 register is cleared to 0x00. 5 INT_BUCK1 R 0 Interrupt indicating that output BUCK1 has a pending interrupt. The reason for the interrupt is indicated in INT_BUCK1 register. This bit is cleared automatically when INT_BUCK1 register is cleared to 0x00. 4 INT_BUCK0 R 0 Interrupt indicating that output BUCK0 has a pending interrupt. The reason for the interrupt is indicated in INT_BUCK0 register. This bit is cleared automatically when INT_BUCK0 register is cleared to 0x00. 3 TDIE_SD R/W 0 Latched status bit indicating that the die junction temperature has exceeded the thermal shutdown level. The converter cores have been disabled if they were enabled. The converter cores cannot be enabled if this bit is active. The actual status of the thermal warning is indicated by the TOP_STAT.TDIE_SD_STAT bit. Write 1 to clear interrupt. 2 TDIE_WARN R/W 0 Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TOP_STAT.TDIE_WARN_STAT bit. Write 1 to clear interrupt. 1 RESET_REG R/W 0 Latched status bit indicating that either startup (NRST rising edge) has done, VANA supply voltage has been below undervoltage threshold level or the host has requested a reset (RESET.SW_RESET). The converter cores have been disabled, and registers are reset to default values and the normal startup procedure is done. Write 1 to clear interrupt. 38 Description Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 Bits Field Type Default 0 I_LOAD_READY R/W 0 Description Latched status bit indicating that the load current measurement result is available in I_LOAD_1 and I_LOAD_2 registers. Write 1 to clear interrupt. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 39 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.6.1.25 INT_BUCK_0_1 Address: 0x19 D7 D6 D5 D4 D3 D2 D1 D0 Reserved BUCK1_PG _INT BUCK1_SC _INT BUCK1_ILIM _INT Reserved BUCK0_PG _INT BUCK0_SC _INT BUCK0_ILIM _INT Bits Field Type Default Description 7 Reserved R/W 0 6 BUCK1_PG_INT R/W 0 Latched status bit indicating that BUCK1 output voltage has reached power-good threshold level. Write 1 to clear. 5 BUCK1_SC_INT R/W 0 Latched status bit indicating that the BUCK1 output voltage has fallen below 0.35-V level during operation or BUCK1 output didn't reach 0.35-V level in 1 ms from enable. Write 1 to clear. 4 BUCK1_ILIM_INT R/W 0 Latched status bit indicating that output current limit has been active. Write 1 to clear. 3 Reserved R/W 0 2 BUCK0_PG_INT R/W 0 Latched status bit indicating that BUCK0 output voltage has reached powergood threshold level. Write 1 to clear. 1 BUCK0_SC_INT R/W 0 Latched status bit indicating that the BUCK0 output voltage has fallen below 0.35-V level during operation or BUCK0 output didn't reach 0.35-V level in 1 ms from enable. Write 1 to clear. 0 BUCK0_ILIM_INT R/W 0 Latched status bit indicating that output current limit has been active. Write 1 to clear. 7.6.1.26 INT_BUCK_2_3 Address: 0x1A D7 D6 D5 D4 D3 D2 D1 D0 Reserved BUCK3_PG _INT BUCK3_SC _INT BUCK3_ILIM _INT Reserved BUCK2_PG _INT BUCK2_SC _INT BUCK2_ILIM _INT Bits Field Type Default 7 Reserved R/W 0 6 BUCK3_PG_INT R/W 0 Latched status bit indicating that BUCK3 output voltage has reached power-good threshold level. Write 1 to clear. 5 BUCK3_SC_INT R/W 0 Latched status bit indicating that the BUCK3 output voltage has fallen below 0.35-V level during operation or BUCK3 output didn't reach 0.35-V level in 1 ms from enable. Write 1 to clear. 4 BUCK3_ILIM_INT R/W 0 Latched status bit indicating that output current limit has been active. Write 1 to clear. 40 Description 3 Reserved R/W 0 2 BUCK2_PG_INT R/W 0 Latched status bit indicating that BUCK2 output voltage has reached powergood threshold level. Write 1 to clear. 1 BUCK2_SC_INT R/W 0 Latched status bit indicating that the BUCK2 output voltage has fallen below 0.35 V level during operation or BUCK2 output didn't reach 0.35-V level in 1 ms from enable. Write 1 to clear. 0 BUCK2_ILIM_INT R/W 0 Latched status bit indicating that output current limit has been active. Write 1 to clear. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.6.1.27 TOP_STAT Address: 0x1B D7 D6 D5 D4 Reserved Bits D3 D2 TDIE_SD _STAT TDIE_WARN _STAT D1 D0 Reserved Field Type Default Description 7:4 Reserved R 0000 3 TDIE_SD_STAT R 0 Status bit indicating the status of thermal shutdown: 0 - Die temperature below the thermal shutdown level. 1 - Die temperature above the thermal shutdown level. 2 TDIE_WARN _STAT R 0 Status bit indicating the status of thermal warning: 0 - Die temperature below the thermal warning level. 1 - Die temperature above the thermal warning level. 1:0 Reserved R 00 7.6.1.28 BUCK_0_1_STAT Address: 0x1C D7 D6 D5 D4 D3 D2 D1 D0 BUCK1_STAT BUCK1_PG _STAT Reserved BUCK1_ILIM _STAT BUCK0_STAT BUCK0_PG _STAT Reserved BUCK0_ILIM _STAT Bits Field Type Default Description 7 BUCK1_STAT R 0 Status bit indicating the enable or disable status of BUCK1: 0 - BUCK1 converter core is disabled. 1 - BUCK1 converter core is enabled. 6 BUCK1_PG_STAT R 0 Status bit indicating BUCK1 output voltage validity (raw status): 0 - BUCK1 output is above power-good threshold level 1 - BUCK1 output is below power-good threshold level. 5 Reserved R 0 4 BUCK1_ILIM _STAT R 0 Status bit indicating BUCK1 current limit status (raw status): 0 - BUCK1 output current is below current limit level. 1 - BUCK1 output current limit is active. 3 BUCK0_STAT R 0 Status bit indicating the enable or disable status of BUCK0: 0 - BUCK0 converter core is disabled. 1 - BUCK0 converter core is enabled. 2 BUCK0_PG_STAT R 0 Status bit indicating BUCK0 output voltage validity (raw status): 0 - BUCK0 output is above the power-good threshold level. 1 - BUCK0 output is below the power-good threshold level. 1 Reserved R 0 0 BUCK0_ILIM _STAT R 0 Status bit indicating BUCK0 current limit status (raw status): 0 - BUCK0 output current is below the current limit level. 1 - BUCK0 output current limit is active. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 41 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.6.1.29 BUCK_2_3_STAT Address: 0x1D D7 D6 D5 D4 D3 D2 D1 D0 BUCK3_STAT BUCK3_PG _STAT Reserved BUCK3_ILIM _STAT BUCK2_STAT BUCK2_PG _STAT Reserved BUCK2_ILIM _STAT Bits Field Type Default Description 7 BUCK3_STAT R 0 Status bit indicating the enable or disable status of BUCK3: 0 - BUCK3 converter core is disabled. 1 - BUCK3 converter core is enabled. 6 BUCK3_PG_STAT R 0 Status bit indicating BUCK3 output voltage validity (raw status): 0 - BUCK3 output is above power-good threshold level. 1 - BUCK3 output is below power-good threshold level. 5 Reserved R 0 4 BUCK3_ILIM _STAT R 0 Status bit indicating BUCK3 current limit status (raw status): 0 - BUCK3 output current is below current limit level. 1 - BUCK3 output current limit is active. 3 BUCK2_STAT R 0 Status bit indicating the enable or disable status of BUCK2: 0 - BUCK2 converter core is disabled. 1 - BUCK2 converter core is enabled. 2 BUCK2_PG_STAT R 0 Status bit indicating BUCK2 output voltage validity (raw status): 0 - BUCK2 output is above power-good threshold level. 1 - BUCK2 output is below power-good threshold level. 1 Reserved R 0 0 BUCK2_ILIM _STAT R 0 Status bit indicating BUCK2 current limit status (raw status): 0 - BUCK2 output current is below current limit level. 1 - BUCK2 output current limit is active. 7.6.1.30 TOP_MASK Address: 0x1E D7 D6 D5 D4 D3 Reserved Bits 42 D2 D1 D0 TDIE_WARN _MASK RESET_REG _MASK I_LOAD_ READY_MASK Field Type Default Description 7:3 Reserved R/W 0000 0 2 TDIE_WARN _MASK R/W 0* Masking for thermal warning interrupt INT_TOP.TDIE_WARN: 0 - Interrupt is generated. 1 - Interrupt is not generated. This bit does not affect TOP_STAT.TDIE_WARN_STAT status bit. 1 RESET_REG _MASK R/W 1* Masking for register reset interrupt INT_TOP.RESET_REG: 0 - Interrupt is generated. 1 - Interrupt is not generated. 0 I_LOAD_ READY_MASK R/W 1* Masking for load current measurement ready interrupt INT_TOP.I_LOAD_READY: 0 - Interrupt is generated. 1 - Interrupt is not generated. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.6.1.31 BUCK_0_1_MASK Address: 0x1F D7 D6 D5 D4 D3 D2 D1 D0 Reserved BUCK1_PG _MASK Reserved BUCK1_ILIM _MASK Reserved BUCK0_PG _MASK Reserved BUCK0_ILIM _MASK Bits Field Type Default 7 Reserved R/W 0 6 BUCK1_PG_MASK R/W 1* 5 Reserved R 0 4 BUCK1_ILIM _MASK R/W 1* 3 Reserved R/W 0 2 BUCK0_PG_MASK R/W 1* 1 Reserved R 0 0 BUCK0_ILIM _MASK R/W 1* Description Masking for BUCK1 power-good interrupt INT_BUCK_0_1.BUCK1_PG_INT: 0 - Interrupt is generated. 1 - Interrupt is not generated. This bit does not affect the BUCK_0_1_STAT.BUCK1_PG_STAT status bit. Masking for BUCK1 current limit detection interrupt INT_BUCK_0_1.BUCK1_ILIM_INT: 0 - Interrupt is generated. 1 - Interrupt is not generated. This bit does not affect the BUCK_0_1_STAT.BUCK1_ILIM_STAT status bit. Masking for BUCK0 power-good interrupt INT_BUCK_0_1.BUCK0_PG_INT: 0 - Interrupt is generated. 1 - Interrupt is not generated. This bit does not affect the BUCK_0_1_STAT.BUCK1_PG_STAT status bit. Masking for BUCK0 current limit detection interrupt INT_BUCK_0_1.BUCK0_ILIM_INT: 0 - Interrupt is generated. 1 - Interrupt is not generated. This bit does not affect the BUCK_0_1_STAT.BUCK1_ILIM_STAT status bit. 7.6.1.32 BUCK_2_3_MASK Address: 0x20 D7 D6 D5 D4 D3 D2 D1 D0 Reserved BUCK3_PG _MASK Reserved BUCK3_ILIM _MASK Reserved BUCK2_PG _MASK Reserved BUCK2_ILIM _MASK Bits Field Type Default 7 Reserved R/W 0 6 BUCK3_PG_MASK R/W 1* 5 Reserved R 0 4 BUCK3_ILIM _MASK R/W 1* 3 Reserved R/W 0 2 BUCK2_PG_MASK R/W 1* 1 Reserved R 0 Description Masking for BUCK3 power-good interrupt INT_BUCK_2_3.BUCK3_PG_INT: 0 - Interrupt is generated. 1 - Interrupt is not generated. This bit does not affect the BUCK_2_3_STAT.BUCK3_PG_STAT status bit. Masking for BUCK3 current limit detection interrupt INT_BUCK_2_3.BUCK3_ILIM_INT: 0 - Interrupt is generated. 1 - Interrupt is not generated. This bit does not affect the BUCK_2_3_STAT.BUCK3_ILIM_STAT status bit. Masking for BUCK2 power-good interrupt INT_BUCK_2_3.BUCK2_PG_INT: 0 - Interrupt is generated. 1 - Interrupt is not generated. This bit does not affect the BUCK_2_3_STAT.BUCK1_PG_STAT status bit. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 43 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 Bits Field Type Default 0 BUCK2_ILIM _MASK R/W 1* 44 Description Masking for BUCK2 current limit detection interrupt INT_BUCK_2_3.BUCK2_ILIM_INT: 0 - Interrupt is generated. 1 - Interrupt is not generated. This bit does not affect the BUCK_2_3_STAT.BUCK1_ILIM_STAT status bit. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 7.6.1.33 SEL_I_LOAD Address: 0x21 D7 D6 D5 D4 D3 D2 Reserved Bits Field Type Default 7:2 Reserved R/W 00 0000 1:0 LOAD_CURRENT_ BUCK_SELECT [1:0] R/W 0x0 D1 D0 LOAD_CURRENT_BUCK _SELECT[1:0] Description Start the current measurement on the selected converter core: 0x0 - BUCK0 0x1 - BUCK1 0x2 - BUCK2 0x3 - BUCK3 The measurement is started when this register is written. 7.6.1.34 I_LOAD_2 Address: 0x22 D7 D6 D5 D4 D3 D2 Reserved Bits Field Type Default 7:2 Reserved R 00 0000 1:0 BUCK_LOAD_ CURRENT[9:8] R 0x0 D1 D0 BUCK_LOAD_CURRENT[9:8] Description This register describes 2 MSB bits of the average load current on the selected converter core with a resolution of 20 mA per LSB and a maximum 20 A current. 7.6.1.35 I_LOAD_1 Address: 0x23 D7 D6 D5 D4 D3 D2 D1 D0 BUCK_LOAD_CURRENT[7:0] Bits Field Type Default 7:0 BUCK_LOAD_ CURRENT[7:0] R 0x0 Description This register describes 8 LSB bits of the average load current on selected converter core with a resolution of 20 mA per LSB and maximum 20-A current. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 45 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information The LP8758-EA is designed for applications powered from a 2.5-V to 5.5-V input supply that require multiple power rails. The device provides four step-down converters. All the step-down converters support dynamic voltage scaling through I2C interface to provide optimum power savings. The power sequencing of the four output voltage rails is programmable. 8.2 Typical Application L0 VIN CIN4 22 µF SW_B0 VIN_B0 CIN5 CIN0 470 nH 10 µF 22 µF VIN_B1 SW_B1 VIN_B2 470 nH CPOL1 22 µF COUT2 22 µF CPOL2 22 µF Load 10 µF FB_B1 VIN_B3 L2 10 µF VIO 10 k 1.8 k 1.8 k CVANA 100 nF SW_B2 470 nH VANA AGND L3 SW_B3 SGND EN2 PGND_B23 nINT NRST PGND_B01 SCL EN1 Load FB_B2 SDA Host Processor COUT1 22 µF L1 10 µF CIN3 CPOL0 22 µF FB_B0 CIN1 CIN2 Load COUT0 22 µF 470 nH Load COUT3 22 µF CPOL3 22 µF FB_B3 Figure 8-1. LP8758-EA Typical Application Circuit 8.2.1 Design Requirements Table 8-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage 3.3 V Output voltages 1000 mV, 1200 mV, 1800 mV, and 2500 mV Converter operation mode Auto mode (PWM-PFM) Maximum load currents 1.5 A, 2.25 A, 3 A, and 3 A Inductor current limits 2.5 A, 3.5 A, 4.5 A, and 4.5 A 8.2.2 Detailed Design Procedure The performance of the LP8758-EA device depends greatly on the care taken in designing the printed circuit board (PCB). The use of low-inductance and low serial-resistance ceramic capacitors is strongly recommended, while proper grounding is crucial. Attention must be given to decoupling the power supplies. Decoupling 46 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 capacitors must be connected close to the device and between the power and ground pins to support high peak currents being drawn from system power rail during turnon of the switching MOSFETs. Keep input and output traces as short as possible, because trace inductance, resistance, and capacitance can easily become the performance limiting items. The separate power pins VIN_Bx are not connected together internally. The VIN_Bx power connections must be connected together outside the package using power plane construction. 8.2.2.1 Application Components 8.2.2.1.1 Inductor Selection DC bias current characteristics of inductors must be considered. Different manufacturers follow different saturation current rating specifications, so attention must be given to details. DC bias curves should be requested from manufacturers as part of the inductor selection process. Minimum effective value of inductance to ensure good performance is 0.33 μH at maximum load current over the operating temperature range of the inductor. The DC resistance of the inductor must be less than 0.05 Ω for good efficiency at high-current condition. The inductor AC loss (resistance) also affects conversion efficiency. Higher Q factor at switching frequency usually gives better efficiency at light load to middle load. See Table 8-2. Shielded inductors are preferred as they radiate less noise. Table 8-2. Recommended Inductors MANUFACTURER PART NUMBER VALUE (µH) DIMENSIONS L × W × H (mm) DCR (mΩ) MURATA DFE201610E-R47M=P2 0.47 2 × 1.6 × 1 26 (typical), 32 (maximum) TDK VLS252010HBX-R47M 0.47 2.5 × 2 × 1 29 (typical), 35 (maximum) TDK TFM2016GHM-0R47M 0.47 2 × 1.6 × 1 46 (maximum) TOKO DFE322512C R47 0.47 3.2 × 2.5 × 1.2 21 (typical), 31 (maximum) 8.2.2.1.2 Input Capacitor Selection A ceramic input capacitor of 10 μF, 6.3 V is sufficient for most applications. Place the power input capacitor as close as possible to the VIN_Bx pin and PGND_Bx pin of the device. A larger value or higher voltage rating may be used to improve input voltage filtering. Use X7R or X5R types; do not use Y5V or F. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0402. Minimum effective input capacitance to ensure good performance is 1.9 μF per buck input at maximum input voltage DC bias including tolerances and over ambient temp range, assuming that there are at least 22 μF of additional capacitance common for all the power input pins on the system power rail. See Table 8-3. The input filter capacitor supplies current to the high-side FET switch in the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor's low equivalent series resistance (ESR) provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with sufficient ripple current rating. The VANA input is used to supply analog and digital circuits in the device. See recommended components from Table 8-4 for VANA input supply filtering. Table 8-3. Recommended Power Input Capacitors (X5R Dielectric) MANUFACTURER PART NUMBER VALUE CASE SIZE DIMENSIONS L × W × H (mm) VOLTAGE RATING (V) Murata GRM188R60J106ME47 10 µF (20%) 0603 1.6 × 0.8 × 0.8 6.3 MANUFACTURER PART NUMBER VALUE CL03A104KP3NNNC 100 nF (10%) 0201 0.6 × 0.3 × 0.3 10 GRM033R61A104KE84 100 nF (10%) 0201 0.6 × 0.3 × 0.3 6.3 Table 8-4. Recommended VANA Supply Filtering Components Samsung Murata CASE SIZE DIMENSIONS L × W × H (mm) VOLTAGE RATING (V) 8.2.2.1.3 Output Capacitor Selection Use ceramic capacitors, X7R or X5R types; do not use Y5V or F. DC bias voltage characteristics of ceramic capacitors must be considered. DC bias characteristics vary from manufacturer to manufacturer, and DC bias curves should be requested from them as part of the capacitor selection process. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 47 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to perform these functions. The minimum effective output capacitance to ensure good performance is 10 μF per output voltage rail at the output voltage DC bias, including tolerances and over ambient temperature range. The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part. See Table 8-5. A higher output capacitance improves the load step behavior and reduces the output voltage ripple as well as decreases the PFM switching frequency. For most applications one 22-μF 0603 capacitor for COUT per voltage rail is suitable. A point-of-load (POL) capacitance CPOL can be added as shown in Figure 8-1. Although the loop compensation of the converter can be programmed to adapt to virtually several hundreds of microfarads COUT, it is preferable for COUT to be < 50 µF . Choosing higher than that is not necessarily of any benefit. Note: the output capacitor may be the limiting factor in the output voltage ramp, especially for very large (> 100 µF) output capacitors. For large output capacitors, the output voltage might be slower than the programmed ramp rate at voltage transitions, because of the higher energy stored on the output capacitance. Also at start-up, the time required to charge the output capacitor to target value might be longer. At shutdown, if the output capacitor is discharged by the internal discharge resistor, more time is required to settle VOUT down as a consequence of the increased time constant. Table 8-5. Recommended Output Capacitors (X5R Dielectric) MANUFACTURER PART NUMBER VALUE CASE SIZE DIMENSIONS L × W × H (mm) VOLTAGE RATING (V) Samsung CL10A226MP8NUNE 22 µF (20%) 0603 1.6 × 0.8 × 0.8 10 Murata GRM188R60J226MEA0 22 µF (20%) 0603 1.6 × 0.8 × 0.8 6.3 48 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 8.2.3 Application Curves Measurements are done using typical application set up with connections shown in Figure 8-1. Graphs may not reflect the OTP default settings. Unless otherwise specified: VIN = 3.7 V, V(NRST) = 1.8 V, TA = 25 °C, ƒSW = 3 MHz, L = 470 nH (TDK VLS252010HBX-R47M), ILIM FWD set to maximum 5 A. 100 100 1000 mV 1200 mV 1800 mV 2500 mV 90 80 95 PFM Operation Efficiency (%) Efficiency (%) 70 60 50 40 90 30 20 PWM Operation 10 85 1000 mV 1200 mV 1800 mV 2500 mV 0 1 10 100 Load Current (mA) 1000 80 2500 5000 3000 D014 3500 4000 4500 Input Voltage (mV) 5000 5500 D002 VIN = 3.7 V Load = 100 mA VOUT settings = 1000 mV, 1200 mV, 1800 mV, and 2500 mV VOUT settings = 1000 mV, 1200 mV, 1800 mV, and 2500 mV Figure 8-2. Efficiency vs Load Current Figure 8-3. Efficiency vs Input Voltage in PFM Mode 100 100 1000 mV 1200 mV 1800 mV 2500 mV Efficiency (%) Efficiency (%) 95 1000 mV 1200 mV 1800 mV 2500 mV 95 90 90 85 80 85 75 80 2500 3000 3500 4000 4500 Input Voltage (mV) 5000 5500 70 2500 D041 3000 3500 4000 4500 Input Voltage (mV) 5000 5500 Load = 1A Load = 3A VOUT settings = 1000 mV, 1200 mV, 1800 mV, and 2500 mV VOUT settings = 1000 mV, 1200 mV, 1800 mV, and 2500 mV Figure 8-4. Efficiency vs Input Voltage in PWM Mode D016 Figure 8-5. Efficiency vs Input Voltage in PWM Mode Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 49 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 1015 0 1000 mV 1200 mV 1800 mV 2500 mV Load Regulation (%) -0.05 PFM Operation Output Voltage (mV) -0.025 -0.075 -0.1 -0.125 -0.15 -0.175 1010 1005 PWM Operation 1000 -0.2 -0.225 995 -0.25 0 500 1000 1500 2000 2500 Output Current (mA) 3000 3500 1 4000 10 D005 Change in Output Voltage from Zero Load (%) 100 Output Current (mA) 1000 5000 D047 VOUT setting = 1000 mV VOUT settings = 1000 mV, 1200 mV, 1800 mV, and 2500 mV Figure 8-6. DC Load Regulation in PWM mode Figure 8-7. Output Voltage vs Load Current in PWM-PFM Mode 2515 0.06 PFM Operation Line Regulation (%) 2510 Output Voltage (mV) 1000mV 1200mV 1800mV 2500mV 0.04 2505 2500 PWM Operation 2495 0.02 0 -0.02 -0.04 2490 1 10 100 Output Current (mA) 1000 5000 -0.06 2500 3000 D046 3500 4000 4500 Input Voltage (mV) Change in Output Voltage from VIN = 3.7 V (%) VOUT setting = 2500 mV 5000 5500 D044 Load = 1 A VOUT settings = 1000 mV, 1200 mV, 1800 mV, and 2500 mV Figure 8-8. Output Voltage vs Load Current in PWM-PFM Mode Figure 8-9. DC Line Regulation in PWM Mode 1010 Output Voltage (mV) V(SW_Bx) (5 V/div) 1005 V(EN1) (1 V/div) 1000 PWM Mode PFM Mode 995 -50 -25 0 25 50 Temperature (qC) 75 100 VOUT (200 mV/div) 125 Time (40 Ps/div) D048 Load = 0 A VOUT setting = 1000 mV Load = 1 A (PWM Mode) and 100 mA (PFM Mode) Figure 8-10. Output Voltage vs Temperature 50 Figure 8-11. Start-up with EN1 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 V(SW_Bx) (5 V/div) V(SW_Bx) (5 V/div) V(EN1) (1 V/div) V(EN1) (1 V/div) ILOAD (500 mA/div) ILOAD (500 mA/div) VOUT (50 mV/div) VOUT (200 mV/div) Time (200 Ps/div) Time (40 Ps/div) Figure 8-13. Start-up With Short on Output Load = 1 A Figure 8-12. Start-up with EN1 VOUT0 (1 V/div) V(SW_Bx) (5 V/div) VOUT1 (1 V/div) VOUT (200 mV/div) VOUT2 (1 V/div) VOUT3 (1 V/div) V(EN1) (1 V/div) Time (10 Ps/div) Time (4 ms/div) Load = 0 A Enable and disable delays = default Load = 0 A VOUT settings = default Figure 8-15. Shutdown with EN1 Figure 8-14. VOUT0,1,2,3: Start-up and Shutdown with Default Register Settings, triggered by EN1. VOUT (10 mV/div) VOUT (10 mV/div) V(SW_B0) (2 V/div) V(SW_B0) (2 V/div) Time (200 ns/div) Time (40 Ps/div) Load = 200 mA Load = 10 mA Figure 8-16. Output Voltage Ripple, PFM Mode Figure 8-17. Output Voltage Ripple, Forced PWM Mode Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 51 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 V(SW_Bx) (2 V/div) V(SW_Bx) (2 V/div) VOUT (10 mV/div) VOUT (10 mV/div) Time (4 Ps/div) Time (4 Ps/div) Figure 8-18. Transient from PFM-to-PWM Mode Figure 8-19. Transient from PWM-to-PFM Mode VIN (500 mV/div) VOUT (20 mV/div) ILOAD (1 A/div) VOUT (10 mV/div) Time (40 Ps/div) Load = 4 A Time (40 Ps/div) VOUT = 1000 mV Load = 0 A → 2 A → 0 A TR = TF = 400 ns VOUT = 1 V VIN stepping 3.3 V ↔ 3.8 V, TR = TF = 10 µs Figure 8-20. Transient Line Response Figure 8-21. Transient Load Step Response, AUTO Mode VOUT (50 mV/div) VOUT (20 mV/div) ILOAD (1 A/div) ILOAD (1 A/div) Time (40 Ps/div) Time (40 Ps/div) Load = 0 A → 2 A → 0 A TR = TF = 400 ns VOUT = 1 V Figure 8-22. Transient Load Step Response, Forced PWM Mode 52 Load = 1A → 4 A → 1A TR = TF = 1 µs VOUT = 1 V Figure 8-23. Transient Load Step Response, Forced PWM Mode Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 VOUT (200 mV/div) VOUT (200 mV/div) Time (400 µs/div) Time (400 µs/div) Figure 8-24. VOUT Transition From 0.6 V to 1.4 V With Different Slew Rate Settings Figure 8-25. VOUT Transition From 1.4 V to 0.6 V With Different Slew Rate Settings 9 Power Supply Recommendations The device is designed to operate from an input voltage supply range between 2.5 V and 5.5 V. This input supply must be well-regulated and able to withstand maximum input current and maintain stable voltage without voltage drop even at load transition condition. The resistance of the input supply rail must be low enough that the input current transient does not cause too high drop in the LP8758-EA supply voltage that can cause false UVLO fault triggering. If the input supply is located more than a few inches from the LP8758-EA additional bulk capacitance may be required in addition to the ceramic bypass capacitors. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 53 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 10 Layout 10.1 Layout Guidelines The high frequency and large switching currents of the LP8758-EA make the choice of layout important. Good power supply results only occur when care is given to proper design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less-than-expected results. With a range of output currents from milliamps to 4 A per converter core, good power supply layout is much more difficult than most general PCB design. The following steps should be used as a reference to ensure the device is stable and maintains proper voltage and current regulation across its intended operating voltage and current range. 1. Place CIN as close as possible to the VIN_Bx pin and the PGND_Bxx pin. Route the VIN trace wide and thick to avoid IR drops. The trace between the positive node of the input capacitor and the LP8758-EA VIN_Bx pin(s), as well as the trace between the input capacitor's negative node and power PGND_Bxx pin(s), must be kept as short as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic inductance on these traces must be kept as tiny as possible for proper device operation. 2. The output filter, consisting of Lx and COUTx, converts the switching signal at SW_Bx to the noiseless output voltage. It must be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Route the traces between the output capacitors of the device and the load (or input capacitors of the load) direct and wide to avoid losses due to the IR drop. 3. Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling capacitor as close to the VANA pin as possible. VANA must be connected to the same power node as VIN_Bx pins. 4. If the load supports remote voltage sensing, connect the feedback pins FB_Bx of the device to the respective sense pins on the load. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND_Bxx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I2C. Avoid both capacitive as well as inductive coupling by keeping the sense lines short and direct. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. 5. PGND_Bxx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers which are not able to withstand interference from noisy PGND_Bxx, VIN_Bx and SW_Bx. Due to the small package of this converter and the overall small solution size, the thermal performance of the PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB designs with vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board (RθJB) thermal resistances and thereby reduces the device junction temperature, TJ. Performing a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process is strongly recommended, using a thermal modeling analysis software. 54 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 10.2 Layout Example Figure 10-1. LP8758-EA Board Layout Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 55 LP8758-EA www.ti.com SNVSC24 – APRIL 2021 11 Device and Documentation Support 11.1 Device Support 11.2 Documentation Support 11.2.1 Related Documentation For related documentation, see the following: • • Texas Instruments, DSBGA Wafer Level Chip Scale Package application report Texas instruments, Using the LP8758EVM Evaluation Module user's guide 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.5 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 Glossary TI Glossary 56 This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA LP8758-EA www.ti.com SNVSC24 – APRIL 2021 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP8758-EA 57 PACKAGE OPTION ADDENDUM www.ti.com 26-Mar-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) LP8758A2EAYFFR ACTIVE DSBGA YFF 35 3000 RoHS & Green SAC396 Level-1-260C-UNLIM -40 to 105 LP8758A2EA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of