LP8863ADCPRQ1

Order Now Product Folder Support & Community Tools & Software Technical Documents Reference Design LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 LP8863-Q1 Automotive Display LED-Backlight Driver With Six 150-mA Channels 1 Features 2 Applications • • • 1 • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Input Voltage Operating Range 3 V to 48 V Six High-Precision Current Sinks – Current Matching 1% (typical) – Dimming Ratio 32 000:1 Using 152-Hz LED Output PWM Frequency – Up to 16-bit LED Dimming Resolution With SPI, I2C, or PWM Input – Automatically Detects Used LED Strings and Adjusts LED-Channel Phase Shift – Independent Current Control for Each Channel Hybrid PWM and Current Dimming Function Up to 47-V VOUT Boost or SEPIC DC/DC Controller – Switching Frequency 300 kHz to 2.2 MHz – Boost Spread Spectrum for Reduced EMI – Boost Sync Input to Set Boost Switching Frequency From an External Clock – Integrated Charge Pump Supports Low VIN Conditions Such as Cold Crank – Output Voltage Automatically Discharged When Boost is Disabled Extensive Fault Diagnostics Q2 RISENSE CIN C1N C2x VOUT COUT RFB1 Q1 GD GD ISNS The boost controller has adaptive output voltage control based on the headroom voltages of the LED current sinks. This feature minimizes the power consumption by adjusting the voltage to the lowest sufficient level in all conditions. A wide-range adjustable frequency allows the LP8863-Q1 to avoid disturbance for AM radio band. The LP8863-Q1 supports built-in hybrid PWM and current dimming, which reduces EMI, extends the LED lifetime, and increases the total optical efficiency. LP8863-Q1 BODY SIZE (NOM) 9.70 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. RFB2 RSENSE 95 ISNSGND CVDD PACKAGE HTSSOP (38) System Efficiency PGND PGND C1P FB VDD DISCHARGE GND VLDO CLDO VDDIO LP8863-Q1 Boost Efficiency (%) VDD SD CPUMP CPUMP VSENSE_P CPUMP VSENSE_N RSD The LP8863-Q1 is an automotive high-efficiency LED driver with boost controller. The six high-precision current sinks support phase shifting that is automatically adjusted based on the number of channels in use. Current sink brightness can be controlled individually and globally through the SPI or I2C interface; brightness can also be globally controlled with PWM input. PART NUMBER D1 L1 3 Description Device Information(1) Simplified Schematic VIN Backlight for: – Automotive Infotainment – Automotive Instrument Clusters – Smart Mirrors – Heads-Up Displays (HUD) – Central Information Displays (CID) – Audio-Video Navigation (AVN) LED0 LED1 IFSEL LED2 EN INT LED3 SDO_PWM LED4 SDI_SDA LED5 SCLK_SCL SS_ADDRSEL BST_SYNC ISET PWM_FSET BST_FSET 90 85 80 VOUT = 29 V VOUT = 36 V VOUT = 42 V VOUT = 46 V RISET RPWM_FSET RBST_FSET Copyright © 2017, Texas Instruments Incorporated 75 0 10 20 30 40 50 60 Brightness (%) 70 80 90 100 D007 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 1 1 1 2 4 5 7 Absolute Maximum Ratings ...................................... 7 ESD Ratings.............................................................. 7 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 8 Electrical Characteristics........................................... 8 Protection Electrical Characteristics ......................... 8 LED Current Sink and LED PWM Electrical Characteristics ........................................................... 9 7.8 Power-Line FET and RISENSE Electrical Characteristics ........................................................... 9 7.9 Input PWM Electrical Characteristics...................... 10 7.10 Boost Converter Electrical Characteristics............ 10 7.11 Oscillator ............................................................... 11 7.12 Charge Pump ........................................................ 11 7.13 Logic Interface Characteristics.............................. 11 7.14 Timing Requirements for SPI Interface................. 12 7.15 Timing Requirements for I2C Interface ................ 12 7.16 Typical Characteristics .......................................... 13 8 Detailed Description ............................................ 14 8.1 8.2 8.3 8.4 8.5 8.6 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming .......................................................... Register Maps ......................................................... 14 15 16 38 42 46 Application and Implementation ........................ 68 9.1 Application Information............................................ 68 9.2 Typical Applications ................................................ 68 10 Power Supply Recommendations ..................... 81 11 Layout................................................................... 82 11.1 Layout Guidelines ................................................. 82 11.2 Layout Example .................................................... 83 12 Device and Documentation Support ................. 84 12.1 12.2 12.3 12.4 12.5 12.6 Device Support...................................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 84 84 84 84 84 84 13 Mechanical, Packaging, and Orderable Information ........................................................... 84 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (June 2017) to Revision B Page • Added top navigator link for TI reference design .................................................................................................................. 1 • Added note "When internal charge pump is disabled and CPUMP pin is used as an input, max rating is 5.5 V same as VDD." ................................................................................................................................................................................ 7 • Added note "When internal charge pump is disabled and CPUMP pin is used as an input, max rating is 5.5V same as VDD." ................................................................................................................................................................................ 7 • Deleted "ƒOSC" row ................................................................................................................................................................. 8 • Deleted "led_driver_headroom = 01b" .................................................................................................................................. 9 • Changed to "325" from "200" ................................................................................................................................................. 9 • Changed to "450" from "400" ................................................................................................................................................. 9 • Changed to "18.6" from "18.8" ............................................................................................................................................. 11 • Changed to "21.4" from "21.2" ............................................................................................................................................. 11 • Added VSDOOL and VSDOOH two rows................................................................................................................................ 11 • Changed Data hold time to rising edge of SCLK in SPI Timing Diagram ........................................................................... 12 • Changed to "VDD" from "EN" .............................................................................................................................................. 14 • Changed to "90%" from "88%" ............................................................................................................................................ 18 • Changed to "1.21 V" from "1.2 V" ........................................................................................................................................ 19 • Changed to "1.21 V" from "1.2 V" ........................................................................................................................................ 20 • Changed to "1.76 V" from "1.423 V" .................................................................................................................................... 20 • Changed to "1.21 V" from "1.2 V" ........................................................................................................................................ 21 • Changed to "ISEL_MAX" from "ISEL_MAX" ............................................................................................................................. 22 • Changed to "1.21 V and 2560" from "1.2 V and 2580" in Equation 11 ................................................................................ 24 2 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 Revision History (continued) • Changed to "DITHER_SELECT[2:0]" from "DITHER_SELECT[1:0]" .................................................................................. 29 • Changed to "110 ms" from "1600 milliseconds" .................................................................................................................. 34 • Changed to "overcurrent" from "undervoltage" .................................................................................................................... 34 • Changed to "Boost does not start up. Fault is cleared by VDD cycling with correct resistor connection at FSET pin." from "Device starts up using fail-safe values." .................................................................................................................... 36 • Changed to "400-ms" from "300-ms" ................................................................................................................................... 39 • Changed to "VDD" from "EN" .............................................................................................................................................. 39 • Added " For proper operation of discharge function, pull the EN pin before VDD pin. VIN and VDDIO can be set low any time after EN low." ........................................................................................................................................................ 41 • Changed to "8B0h' from "B0h" ............................................................................................................................................ 49 • Changed to "R/W-2h' from 'R/W-0h" ................................................................................................................................... 49 • Changed to "2h" from "0h" ................................................................................................................................................... 49 • Changed to "100h" from "0h" ............................................................................................................................................... 57 • Changed to "100h" from "0h" ............................................................................................................................................... 57 • Changed to "100h" from "0h" ............................................................................................................................................... 57 • Changed to "100h" from "0h" ............................................................................................................................................... 58 • Changed to "000h - 0FFh = 0 °C to 255 °C, 100h - 1FFh = –256 °C to –1 °C" from "0h = –1 to –255 °C" ........................ 58 • Changed to "000h - 0FFh = 0 °C to 255 °C, 100h - 1FFh = –256 °C to –1 °C" from "0h = –1 to –255 °C" ....................... 58 • Changed to "000h - 0FFh = 0 °C to 255 °C, 100h - 1FFh = –256 °C to –1 °C" from "0h = –1 to –255 °C" ....................... 58 • Changed to "1C0h" from "0h" .............................................................................................................................................. 63 • Changed to "1C0h" from "0h" .............................................................................................................................................. 63 • Changed to "1C0h" from "0h" .............................................................................................................................................. 63 • Changed to "1C0h" from "0h" .............................................................................................................................................. 64 • Changed to "2882h" from "882h" ......................................................................................................................................... 64 • Changed to "2h" from "0h" ................................................................................................................................................... 64 • Changed to "2h" from "0h" ................................................................................................................................................... 64 • Changed Description of FSM_LIVE_STATUS .................................................................................................................... 65 • Changed to "VIN(min) × D / ( ƒSW × L )" from "VIN(min)× D / ƒSW × L" ....................................................................................... 70 • Changed to "Current set resistor for 100 mA maximum" from "Maximum current set resistor" .......................................... 73 • Changed to "43.5 V" from "40 V" ......................................................................................................................................... 75 • Changed to "10-µF" from "10-µH" ....................................................................................................................................... 78 • Changed to "Current set resistor for 150 mA max" from "Maximum current set resistor" .................................................. 80 Changes from Original (March 2017) to Revision A • Page First public release of full data sheet ..................................................................................................................................... 1 Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 3 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 5 Device Comparison Table LP8863-Q1 LP8860-Q1 LP8862-Q1 LP8861-Q1 TPS61193-Q1 TPS61194-Q1 TPS61196-Q1 3 V to 48 V 3 V to 48 V 4.5 V to 45 V 4.5 V to 45 V 4.5 V to 45 V 4.5 V to 45 V 8 V to 30 V 6 4 2 4 3 4 6 150 mA 150 mA 160 mA 100 mA 100 mA 100 mA 200 mA I2C/SPI support Yes Yes No No No No No SEPIC support Yes No Yes Yes Yes Yes No VIN range Number of LED channels LED current / channel 4 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 6 Pin Configuration and Functions DCP Package 38-Pin HTSSOP Top View VDD 1 38 GND SD 2 37 VLDO VSENSE_N 3 36 NC VSENSE_P 4 35 NC C1N 5 34 PWM_FSET C1P 6 33 BST_FSET CPUMP 7 32 SS_ADDRSEL CPUMP 8 31 SCLK_SCL GD 9 30 SDI_SDA GD 10 29 SDO_PWM PGND 11 28 BST_SYNC PGND 12 27 IFSEL ISNSGND 13 26 INT ISNS 14 25 VDDIO FB 15 24 EN DISCHARGE 16 23 ISET LED5 17 22 LED0 LED4 18 21 LED1 LED3 19 20 LED2 Copyright © 2017–2018, Texas Instruments Incorporated Exposed Pad (GND_LED) Submit Documentation Feedback 5 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com Pin Functions PIN NO. NAME TYPE DESCRIPTION 1 VDD Power Power input for LDO, charge pump, and analog blocks - a 4.7–µF decoupling capacitor is recommended. 2 SD Analog Power line FET control. If unused, leave this pin floating. 3 VSENSE_N Analog Pin for input current sense. If input current sense is not used tie to VSENSE_P. 4 VSENSE_P Analog Pin for OVP/UVLO protection and input current sense. 5 C1N Analog Negative pin for charge pump flying capacitor. If feature not used, leave this pin floating. 6 C1P Analog Positive pin for charge pump flying capacitor. If feature not used, leave this pin floating. 7 CPUMP Power Charge pump output pin. If charge pump is not used connect to VDD. TI recommends a 10–µF decoupling capacitor. 8 CPUMP Power Charge pump output pin. If charge pump is not used connect to VDD. 9 GD Analog Gate driver output for boost FET 10 GD Analog Gate driver output for boost FET 11 PGND Ground Power ground 12 PGND Ground Power ground 13 ISNSGND Ground Current sense resistor GND of boost controller 14 ISNS Analog Boost current sense pin 15 FB Analog Boost feedback input 16 DISCHARGE Analog Boost output voltage discharge pin. Leave floating if unused. 17 LED5 Analog LED current sink output. If unused tie to ground. 18 LED4 Analog LED current sink output. If unused tie to ground. 19 LED3 Analog LED current sink output. If unused tie to ground. 20 LED2 Analog LED current sink output. If unused tie to ground. 21 LED1 Analog LED current sink output. If unused tie to ground. 22 LED0 Analog LED current sink output. If unused tie to ground. 23 ISET Analog LED current setting input 24 EN Input 25 VDDIO Power Supply input for digital IO pins - a 4.7–µF decoupling capacitor is recommended. 26 INT Output LP8863-Q1 device fault interrupt output, open drain. Requires an external pullup resistor to VDDIO - a 10-kΩ pullup resistor is recommended. 27 IFSEL Input Serial control interface selection: low = SPI, high = I2C 28 BST_SYNC Input Input for synchronizing boost. When synchronization is not used, connect this pin to ground to disable spread spectrum or to VDDIO to enable spread spectrum. 29 SDO_PWM Input/Output 30 SDI_SDA Input IFSEL=GND, slave data input for SPI; IFSEL=VDDIO, serial data for I2C 31 SCLK_SCL Input IFSEL=GND, serial clock for SPI; IFSEL=VDDIO, serial clock for I2C 32 SS_ADDRSEL Input IFSEL=GND, slave select for SPI; IFSEL=VDDIO, I2C address selection 33 BST_FSET Analog Resistor for setting boost FSW frequency. Do not leave floating. 34 PWM_FSET Analog Resistor for setting LED PWM frequency. Do not leave floating. 35 NC N/A No connect — leave floating. 36 NC N/A No connect — leave floating. 37 VLDO Power Internal 1.8-V LDO output. Connect bypass capacitor to this pin - a 10–µF decoupling capacitor is recommended. GND Ground Ground for LDO — charge pump and analog blocks GND_LED Ground LED ground connection 38 DAP 6 Submit Documentation Feedback Enable input IFSEL=GND, slave data output for SPI. IFSEL=VDDIO, PWM input for brightness control. Tie to GND if unused. Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Voltage on pins Voltage on pins MIN MAX UNIT V_SENSE_P, VSENSE_N, SD, LED0 to LED5, FB, DISCHARGE -0.3 50 V VDD, EN, ISNS -0.3 5.5 VDDIO, SCLK_SCL, SDI_SDA, SDO_PWM, SS_ADDRSEL, INT, IFSEL, BST_FSET, PWM_FSET, ISET -0.3 3.6 C1P, C1N, CPUMP -0.3 12 (2) , GD VLDO Thermal -0.3 2 Internally limited Internally limited Ambient temperature -40 125 °C Junction temperature -40 150 °C 260 °C 150 °C Continuous power dissipation Maximum lead temperature (soldering) Storage temperature, Tstg (1) (2) V -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. When internal charge pump is disabled and CPUMP pin is used as an input, maximum rating is 5.5 V same as VDD. 7.2 ESD Ratings VALUE Human body model (HBM), per AEC Q100-002, (1) V(ESD) (1) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 UNIT ±2000 All pins ±500 Corner pins ±750 V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted). All voltages are with respect to the potential at the GND pins. Voltage on pins MIN NOM MAX V_SENSE_P, VSENSE_N, SD 3 12 48 Voltage on pins 0 48 EN, ISNS 0 5.5 VDD VDDIO, SCLK_SCL, SDI_SDA, SDO_PWM, SS_ADDRSEL, INT, IFSEL, BST_FSET, PWM_FSET, ISET VLDO C1P, C1N, CPUMP Thermal (1) (1) , GD Ambient temperature 2.7 3.3/5 5.5 1.65 1.8/3.3 3.6 0 1.8 2 0 6.6/10 11 -40 UNIT 125 V °C When internal charge pump is disabled and CPUMP pin is used as an input, maximum rating is 5.5 V same as VDD. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 7 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 7.4 Thermal Information LP8863 THERMAL METRIC (1) DCP (HTSSOP) UNIT 38 PINS RθJA Junction-to-ambient thermal resistance 32.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 19.5 °C/W RθJB Junction-to-board thermal resistance 8.8 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 8.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.5 Electrical Characteristics Limits apply over the full operating ambient temperature range -40°C ≤ TA ≤ +125°C, Unless otherwise specified, VDD = 3.3V, VIN = 12V, VDDIO = 1.8V TYP MAX Shutdown mode current, VDD pin PARAMETER VDD < VPOR, EN = L 0.3 2 μA Standby mode current, VDD pin VDD > VPOR, EN = L 75 300 μA Active mode current , VDD pin LP8863-Q1 enabled, boost enabled (ILED = 150mA), CP enabled, VDD = 3.3V, fSW = 300kHz, Boost FET IPD25N06S4L-30 15 40 (1) mA Power-on reset threshold VDD pin voltage. 2.65 V IQ VPOR (1) TEST CONDITIONS MIN UNIT Ensured by design. 7.6 Protection Electrical Characteristics Limits apply over the full operating ambient temperature range –40°C ≤ TA ≤ +125°C, Unless otherwise specified, VDD = 3.3 V, VIN = 12 V, VDDIO = 1.8 V. PARAMETER VDDUVLO VDD UVLO threshold VDDUVLO_ VDD UVLO hysteresis TEST CONDITIONS VDD falling MIN TYP MAX 2.6 2.7 2.8 0.1 UNIT V V H VINUVLO VIN UVLO threshold VINUVLO_H VIN UVLO hysteresis VINOVP VIN OVP threshold VINOVP _H VIN OVP hysteresis TTSD Thermal shutdown threshold Temperature rising TTSD_H Thermal shutdown hysteresis Temperature falling from TSD threshold TTWR_H Thermal high warning threshold temperature_limit_high = 0x07D 115 125 135 °C TTWR_L Thermal low warning threshold temperature_limit_low = 0x069 95 105 115 °C VDDIO VDDIO supply voltage VDDIOIQ VDDIO supply current VLDO LDO output voltage 8 Submit Documentation Feedback VIN falling 2.7 VIN rising 40.8 2.8 2.9 0.35 43 V 45.2 2.5 155 165 V V 175 °C °C 20 1.65 V 3.6 V 1 μA 1.8 V Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 7.7 LED Current Sink and LED PWM Electrical Characteristics Limits apply over the full operating ambient temperature range -40°C ≤ TA ≤ +125°C, Unless otherwise specified, VDD = 3.3 V, VIN = 12 V, VDDIO = 1.8 V. PARAMETER TEST CONDITIONS ILEAKAGE Leakage current Outputs LED0 to LED5 = VOUT = 45 V, EN = Low IMAX Max LED sink current LED0 to LED5 IACC LED sink current accuracy (1) IOUT = 150 mA, PWM duty =100% IMATCH LED sink current matching (1) IOUT = 150 mA, PWM duty =100% (2) MIN TYP MAX 0.1 2.5 150 −4% µA mA 4% 1% 3.5% 0.4 0.79 VSAT Saturation voltage fPWM_OUT_MIN Minimum LED PWM output frequency 0.152 kHz fPWM_OUT_MAX Maximum LED PWM output frequency 19.5 kHz DIM Dimming ratio VHEADROOM LED sink headroom VHEADROOM_HYST LED sink headroom hysteresis VLEDSHORT LED short detection threshold IOUT = 150 mA UNIT fPWM_OUT = 152 Hz 32000:1 fPWM_OUT = 4.8 kHz with hybrid dimming 8000:1 fPWM_OUT = 4.8 kHz 1000:1 (1) (2) 0.55 V 0.5 V shorted_led_thresh = 000 2.6 shorted_led_thresh = 001 3.0 shorted_led_thresh = 010 3.5 shorted_led_thresh = 011 3.8 shorted_led_thresh = 100 4.1 shorted_led_thresh = 101 4.6 shorted_led_thresh = 110 5.2 shorted_led_thresh = 111 tPWM_OUT V V 5.9 LED output minimum pulse 200 ns Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum difference from the average. For the constant current sinks on the part (LED0 to LED5), the following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Matching number is calculated: (MAX-MIN)/AVG. The typical specification provided is the most likely norm of the matching figure for all parts. LED current sinks were characterized with 1 V headroom voltage. Note that some manufacturers have different definitions in use. Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V. 7.8 Power-Line FET and RISENSE Electrical Characteristics Limits apply over the full operating ambient temperature range -40°C ≤ TA ≤ +125°C, Unless otherwise specified, VDD = 3.3 V, VIN = 12 V, VDDIO = 1.8 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 9.35 11 12.65 A IOCP Input over current threshold RISENSE = 20 mΩ ILEAK_VSENSE_P VSENSE_P pin leakage current VSENSE_P = 48 V 1 µA ILEAK_VSENSE_N VSENSE_N pin leakage current VSENSE_N = 48 V 1 µA ILEAK_SD SD pin leakage current VSD = 48 V 1 µA tSOFT_START Power line FET soft start When RISENSE is used ISD SD Pull-down current RSD = 20 kΩ Copyright © 2017–2018, Texas Instruments Incorporated 50 325 ms 450 Submit Documentation Feedback µA 9 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 7.9 Input PWM Electrical Characteristics Limits apply over the full operating ambient temperature range -40°C ≤ TA ≤ +125°C, Unless otherwise specified, VDD = 3.3V, VIN = 12V, VDDIO = 1.8V PARAMETER fPWM_IN PWM input frequency tPWM_MIN_ON PWM input minimum on time INPWMRES PWM input resolution TEST CONDITIONS MIN TYP 100 MAX 20 000 UNIT Hz 200 ns fPWM_IN = 100 Hz 16 bit fPWM_IN = 20 kHz 10 7.10 Boost Converter Electrical Characteristics Limits apply over the full operating ambient temperature range -40°C ≤ TA ≤ +125°C, Unless otherwise specified, VDD = 3.3V, VIN = 12V, VDDIO = 1.8V PARAMETER VIN TEST CONDITIONS MIN Input voltage VOUT Output voltage ƒSW Switching frequency Max conversion ratio 3 48 20 47 SEPIC mode (RFBTOP = 560 kΩ, RFBBOT = 170 kΩ) 6 24 Boost switching current limit VGD External FET gate drive voltage 303 BST_FSET = 4.75 kΩ 400 BST_FSET = 5.76 kΩ 606 RDSON of internal high side FET to drive gate of external FET GDRDSONL RDSON of internal low side FET to drive gate of external FET tSTART-UP Start-up time TON TOFF V kHz 800 BST_FSET = 11 kΩ 1000 BST_FSET = 17.8 kΩ 1250 BST_FSET = 42.2 kΩ 1667 BST_FSET = 140 kΩ 2200 Boost mode, IOUT = 6 x 150 mA 5.5 (1) Boost mode, IOUT = 6 x 85 mA 10 (1) 5 (1) 0.2 RSENSE = 20 mΩ 9 VDD = 5 V +/-10%, CP Disabled GDRDSONH UNIT V BST_FSET = 3.93 kΩ SEPIC mode IMAX MAX Boost mode (RFBTOP = 910 kΩ, RFBBOT = 100 kΩ) BST_FSET = 7.87 kΩ VOUT/VIN TYP 10 11 4.5 5 5.5 VDD = 3.3 V +/-10%, CP Enabled 6 6.6 7.2 VDD = 5 V +/-10%, CP Enabled 9 10 11 Source, VGD/(GDRDSON + Total resistance to gate input of SW FET) must not be higher than 2.5A A V 1.4 Ω 0.75 Ω 50 ms Minimum switch on time 120 ns Minimum switch off time 70 ns VBST_OVPL BOOST_OVP low threshold at FB pin 1.423 V VBST_OVPH BOOST_OVP high threshold at FB pin 1.76 V (1) 10 Sink, VGD/(GDRDSON + Total resistance to gate input of SW FET) must not be higher than 2.5A Delay from beginning of boost soft start to when LED drivers can begin Ensured by design Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 7.11 Oscillator Limits apply over the full operating ambient temperature range -40°C ≤ TA ≤ +125°C, Unless otherwise specified, VDD = 3.3V, VIN = 12V, VDDIO = 1.8V PARAMETER fOSC TEST CONDITIONS Oscillator frequency MIN TYP MAX UNIT 18.6 20 21.4 MHz 7.12 Charge Pump Limits apply over the full operating ambient temperature range -40°C ≤ TA ≤ +125°C, Unless otherwise specified, VDD = 3.3V, VIN = 12V, VDDIO = 1.8V PARAMETER fCP TEST CONDITIONS Charge pump switching frequency MIN TYP MAX UNIT 387 417 447 kHz 7.13 Logic Interface Characteristics Limits apply over the full operating ambient temperature range -40°C ≤ TA ≤ +125°C, Unless otherwise specified, VDD = 3.3V, VIN = 12V, VDDIO = 1.8V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC INPUT EN VENIL Input low level VENIH Input high level IENI Input current 5 RPDEN EN pin internal pull-down resistance 5 0.4 V 30 µA 1.2 V MΩ LOGIC INPUT SCLK_SCL, SDI_SDA, SS_ADDRSEL, PWM, IF_SEL, BST_SYNC VIL Input low level VIH Input high level II Input current VSDOOL Output low level VSDOOH Output high level 0.2 x VDDIO 0.8 x VDDIO IOUT = 3 mA IOUT = –2 mA V 0.3 0.7 x VDDIO V 5 µA 0.5 V 0.9 x VDDIO V LOGIC OUTPUT SDA VSDAOL Output low level I = 3 mA ISDALEAKAGE Output leakage current V = 5.5 V 0.3 0.5 V 1 μA LOGIC OUTPUT INT VINTOL Output low level IINTLEAK Output leakage current Copyright © 2017–2018, Texas Instruments Incorporated IOUT = 3 mA 0.3 0.5 V 1 μA Submit Documentation Feedback 11 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 7.14 Timing Requirements for SPI Interface MIN 1 Cycle time 2 NOM MAX UNIT 100 ns Enable lead time 50 ns 3 Enable lag time 50 ns 4 Clock low time 45 ns 5 Clock high time 45 ns 6 Data setup time 20 ns 7 Data hold time 20 8 Disable time 30 ns 9 Data valid 35 ns 10 SS inactive time 50 Cb Bus capacitance 5 40 pF ns ns 7.15 Timing Requirements for I2C Interface MIN ƒSCLK Clock frequency 1 Hold time (repeated) START Condition 2 3 NOM MAX UNIT 400 kHz 0.6 µs Clock low time 1.3 µs Clock high time 600 ns 4 Set-up time for a repeated START condition 600 ns 5 Data hold time 50 ns 6 Data setup time 100 7 Rise Time of SDA and SCL 300 ns 8 Fall Time of SDA and SCL 300 ns 9 Set-up time for STOP condition 600 ns 10 Bus free time between a STOP and a START Condition 1.3 µs ns SS t2t t1t 4 t10t 5 3 SCLK 7 6 MSB IN SDI BIT 16 BIT 30 High Impedance SDO BIT 15 9 Address BIT 1 LSB IN 8 9 MSB OUT BIT 1 R/W LSB OUT Data Figure 1. SPI Timing Diagram SDA 10 8 7 6 1 2 8 4 7 9 SCL 1 5 3 Figure 2. I2C Timing Diagram 12 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 7.16 Typical Characteristics Unless otherwise specified: CIN = COUT = 2 × 10-μF ceramic and 2 × 33-μF electrolytic, VDD = 3.3 V, charge pump enabled, TA = 25°C 100 100 95 Boost Efficiency (%) Boost Efficiency (%) 95 90 85 VIN = 9 V VIN = 12 V VIN = 16 V VIN = 24 V 80 90 85 80 75 70 VIN = 9 V VIN = 12 V VIN = 16 V VIN = 24 V 65 60 75 0 10 20 30 ƒSW = 303 kHz L1 = 22 µH 40 50 60 Brightness (%) 70 80 90 0 100 10 20 30 D001 8 LEDs/string 6 strings 150 mA/string ƒSW = 2.2 MHz L1 = 10 µH 85 80 SEPIC Efficiency (%) SEPIC Efficiency (%) 80 90 100 D002 150 mA/string Figure 4. Boost Efficiency 85 80 75 70 65 VIN = 6 V VIN = 12 V VIN = 17 V 75 70 65 60 VIN = 6 V VIN = 12 V VIN = 17 V 55 55 50 0 10 20 30 ƒSW = 303 kHz L1 = 10 µH, L2 = 15 µH 40 50 60 Brightness (%) 70 80 2 LEDs/string 90 100 0 10 20 30 D003 150 mA/string 6 strings ƒSW = 2.2 MHz L1 = L2 = 4.7 µH Figure 5. SEPIC Efficiency 40 50 60 Brightness (%) 70 80 2 LEDs/string 90 100 D004 150 mA/string 6 strings Figure 6. SEPIC Efficiency 150 2.5 15 mA 25 mA 50 mA 80 mA 120 mA 150 mA 120 90 2.0 Current Matching (%) LED String Current (mA) 70 8 LEDs/string 6 strings Figure 3. Boost Efficiency 90 60 40 50 60 Brightness (%) 60 30 1.5 1.0 0.5 0 0.0 0 8192 16384 24576 32768 40960 49152 57344 65536 Brightness Code D005 Figure 7. Current Linearity Copyright © 2017–2018, Texas Instruments Incorporated 0 8192 16384 24576 32768 40960 49152 57344 65536 Brightness Code D006 Figure 8. Current Matching Submit Documentation Feedback 13 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 8 Detailed Description 8.1 Overview The LP8863-Q1 device is a high-voltage LED driver for automotive infotainment, clusters, and other automotive display LED backlight applications. It supports conventional LED backlight applications and cluster-mode applications requiring independent duty and current control of each channel. The LP8863-Q1 device uses the PWM input for brightness control by default. Alternatively, the brightness can also be controlled by I2C or SPI. When two LP8863-Q1 devices are used in the system, individual I2C addresses can be selected independently with the SS_ADDRSEL pin. In cluster-mode applications each of the six LED brightness levels can be individually controlled via the I2C or SPI interface. The boost frequency, LED PWM frequency, and LED string current are configured with external resistors through the BST_FSET, PWM_FSET, and ISET pins. The INT pin is used to report faults to the system. Fault interrupt status can be cleared with the I2C, SPI interface, or is cleared on the falling edge of the VDD pin. The LP8863-Q1 supports pure PWM dimming and hybrid dimming; that is, combined PWM and current brightness control. By default PWM dimming mode is enabled, but can be changed using the I2C or SPI interface. The six LED current drivers provide up to 150 mA per output and can be tied together to support higher current LEDs. The maximum output current of the LED drivers is set with the ISET resistor and can be optionally scaled by the LEDx_CURRENT[11:0] register bits with I2C or SPI interfaces. The LED output PWM frequency is set with a PWM_FSET resistor. The number of connected LED strings is automatically detected, and the device automatically selects the correct phase shift. For example, if four strings are connected, the LED outputs are phase shifted by 90 degrees (= 360 / 4); if 6 strings are connected, the LED outputs are phase shifted by 60 degrees (= 360 / 6). Outputs that are not used must be connected to GND. Unused outputs are disabled and excluded from adaptive voltage and do not generate open/short LED faults. When I2C is available, LED outputs can be re-configured in cluster mode to support up to 6 individually controlled channels or, alternatively, 3 to 5 channels for a display and 3 to 1 individual channels for indicator lights. In this mode all strings can be connected to the boost of LP8863-Q1 or an external boost can be used for indicator channels. A resistor divider connected from VOUT to the FB pin sets the maximum voltage of the boost. For best efficiency the boost voltage is adapted automatically to the minimum necessary level needed to drive the LED strings by monitoring all the LED output voltage drops in real time. The switching frequency of the boost regulator can be set between 300 kHz and 2.2 MHz by the BST_FSET resistor. The boost has a start-up feature that reduces the peak current from the power-line during start-up. The LP8863-Q1 also can control a power-line FET to reduce battery leakage when disabled and provide isolation and protection in the event of a fault. Fault detection features of LP8863-Q1 include: • Open-string and shorted LED detection – LED fault detection prevents system overheating in case of open or short in some of the LED strings • Boost overcurrent • Boost overvoltage • Device undervoltage protection – Threshold sensing from VDD pin • VIN input overvoltage protection (OVP) – Threshold sensing from VSENSE_P pin • VIN input undervoltage protection – Threshold sensing from VSENSE_P pin • VIN input overcurrent protection (OCP) – Threshold sensing across RISENSE resistor • Thermal shutdown in case of die overtemperature • Die temperature read-out and programmable thermal window detector 14 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 8.2 Functional Block Diagram VSENSE_P VSENSE_N SD VDDIO GD Powerline FET Control CPUMP GD CPUMP PGND PGND C1N Charge Pump ISNS C1P + - Boost Controller VDD ISNSGND Analog VLDO FB LDO Discharge Digital OSC 20 MHz PWM_FSET EEPROM DISCHARGE LED0 BST_FSET LED1 6 x LED Current Sinks ADC EN INT Digital Blocks (FSM, Adaptive Voltage Control, Fault Logic, etc.) BST_SYNC LED2 LED3 LED4 IFSEL LED5 SDO_PWM SDI_SDA IFSEL MUX SS_ADDRSEL LED Current Setting ISET SPI / I2C SCLK_SCL Analog Blocks (VREF, TSD, etc.) ADC TEMP Sensor GND Copyright © 2017, Texas Instruments Incorporated Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 15 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 8.3 Feature Description 8.3.1 Control Interface Device control interface includes: • EN is the enable input for the LP8863-Q1 device. • INT is an open-drain fault output (indicating fault condition detection or thermal threshold crossing). • IFSEL is used for selecting between I2C and SPI. – SPI is a 4-wire interface using SCL, SDI, SDO, and SS pins. – When SPI is selected the brightness must be controlled using the DISP_BRT and BRT_MODE registers. – I2C is a 2-wire interface using SCL and SDA pins. – When I2C is selected, the ADDRSEL pin is used to select between two alternate slave addresses. – When I2C is selected, the BRT_MODE register setting is used to select whether the brightness is controlled by the DISP_BRT register or PWM input pin. The PWM pin is selected by default so that an I2C interface is not required. • BST_SYNC is used to input an external clock for the boost switching frequency and control the internal boost clock mode. – The external clock is auto detected at start-up and, if missing, the internal clock is used. – Optionally, the BST_SYNC can be tied to VDDIO to enable the boost spread spectrum function or tied to GND to disable it. • ISET pin to set the maximum LED current level per string. • BST_FSET pin to set the boost switching frequency. • PWM_FSET pin to set the LED output PWM dimming frequency. Control interface is selected with IF_SEL pin according to Table 1. Table 1. Control Interface Selection, SPI or I2C IF_SEL SERIAL INTERFACE VDDIO (1) I2C GND (0) SPI In I2C mode the ADDRSEL is used to select between two unique slave addresses, and the PWM input may be used to control the brightness. 8.3.2 Boost Controller The LP8863-Q1 current-mode-controlled boost DC/DC controller generates the bias voltage for the LEDs. The boost is a current-mode-controlled topology with an 8-A cycle by cycle current limit. The boost converter senses the switch current and across the external sense resistor connected between ISNS and ISNSGND. A 25-mΩ sense resistor results in an 8-A cycle by cycle current limit.. Maximum boost voltage is configured with external FB-pin resistor divider connected between VOUT and FB. The FB-divider equation is described in Boost Adaptive Voltage Control. 16 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 D1 L1 VIN VBOOST CIN COUT OCP ADAPTIVE VOLTAGE CONTROL RFB1 LIGHT LOAD CPUMP OVP FB GM R - RFB2 + R R GD R S GATE DRIVER Q1 PGND BOOST OSCILLATOR BST_FSET ADC RBST_FSET OFF/BLANK TIME PULSE GENERATOR BST_SYNC ISNS CURRENT RAMP GENERATOR MUX G GM ISNS_GND RISENSE Copyright © 2017, Texas Instruments Incorporated Figure 9. Boost Controller Block Diagram The boost switching frequency is adjustable from 300 kHz to 2.2 MHz via an external resistor at BST_FSET (see Table 2). Table 2. Boost Frequency Selection R_BST_FSET (kΩ) BOOST FREQUENCY (kHz) 3.92 303 4.75 400 5.76 606 7.87 800 11 1000 17.8 1250 42.2 1667 140 2200 8.3.2.1 Boost Adaptive Voltage Control The LP8863-Q1 boost DC/DC converter generates the bias voltage for the LEDs. During normal operation, boost output voltage is adjusted automatically based on the LED current sink headroom voltages. This is called adaptive boost control. The number of used LED outputs is auto detected and only the active LED outputs are monitored to control the adaptive boost voltage. Any LED strings with open or short faults are also removed from the adaptive voltage control loop. The LED driver pin voltages are periodically monitored by the control loop and the boost voltage is raised if any of the LED outputs falls below the low headroom threshold. The boost voltage is lowered if all the LED outputs are above the high headroom threshold. See Figure 10 for how the low and high headroom thresholds automatically scale based on the LED string current and VSAT level being used. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 17 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com Adaptive Control makes no change Adaptive Control steps voltage down Adaptive Control steps voltage up Only one output (LED0) above threshold All LED0-5 outputs above threshold One output (LED5) below threshold LED0 Adaptive Control makes no change LED0 LED0-5 PIN VOLTAGE SHORTED_LED_THRESHOLD LED_DRV_HEADROOM +0.5v LED5 LED1 LED5 LED1 LED5 LED1 LED0 LED5 LED1 LED0 LED_DRV_HEADROOM Figure 10. Adaptive Boost Voltage Control Loop Function The external resistive divider (RFB1, RFB2) defines both the minimum and maximum adaptive boost voltage levels. The FB circuit operates the same in boost and SEPIC topologies. Choose maximum boost voltage based on the maximum LED string voltage specification. Before the LED drivers are active the boost starts up to the initial boost level. The initial boost voltage is approximately 90% of maximum boost voltage. Once the LED driver channels are active, the boost output voltage is adjusted automatically based on LED current sink headroom voltage. The FB pin resistor divider also scales the boost OVP and undervoltage levels. 18 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 8.3.2.1.1 FB Divider Using Two-Resistor Method A typical FB-pin circuit uses a two-resistor divider circuit between the boost output voltage and ground. ISNS ISNSGND VBOOST GD VIN + BSTOVPH - VOVPH + BSTOVPL - VOVPL - BSTOCP + VUVP - RFB1 FB COMP + RFB2 + VBG - ISEL[10:0] Figure 11. Two-Resistor FB Divider Circuit Maximum boost voltage can be calculated with Equation 1. The maximum boost voltage can be reached during OPEN string detection or if all LED strings are left disconnected. V VMAXBOOST = (( BG ) + ISEL_MAX )) u RFB1 + VBG RFB2 where • • • VBG = 1.21 V ISEL_MAX = 38.7 µA RFB2 recommended value is 100 kΩ for boost operation and 170 kΩ for SEPIC operation. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback (1) 19 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 50 Maximum Boost Output Voltage (V) 45 40 35 30 25 20 15 10 5 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 R_FB1 (kOhm) RFB2 = 100 kΩ Figure 12. Maximum Boost Output Voltage vs. RFB1 Resistor Value The minimum boost voltage must be less than the minimum LED string voltage. Minimum boost voltage is calculated with Equation 2: V VMINBOOST = ( BG ) u RFB1 + VBG RFB2 where • VBG = 1.21 V (2) When the boost OVP_LOW level is reached the boost controller stops switching the boost FET and the BSTOVPL_STATUS bit is set. The LED drivers are still active during this condition, and the boost resumes normal switching operation once the boost output level falls. The boost OVP low voltage threshold is calculated with Equation 3: V VBOOST _ OVP _ LOW = (( OVPL ) + ISEL_MAX ) u RFB1 + VOVPL RFB2 where • • VOVPL = 1.423 V ISEL_MAX = 38.7 µA (3) When the boost OVP_HIGH level is reached the boost controller enters fault recovery mode, and the BSTOVPH_STATUS bit is set. The boost OVP high-voltage threshold is calculated with Equation 4: V VBOOST _ OVP _ HIGH = (( OVPH ) + ISEL_MAX ) u RFB1 + VOVPH RFB2 where • • VOVPH = 1.76 V ISEL_MAX = 38.7 µA (4) When the boost UVP level is reached the boost controller starts a 100-ms OCP counter. The LP8863-Q1 device enters the fault recovery mode and sets the BSTOCP_STATUS bit if the boost voltage does not rise above the UVP threshold before the timer expires. The boost UVP voltage when adaptive voltage control is at the maximum output voltage is calculated with Equation 5: V VBOOST _ UVP = (( UVP ) + ISEL_MAX ) u RFB1 + VUVP RFB2 where • • 20 VUVP = 0.886 V ISEL_MAX = 38.7 µA Submit Documentation Feedback (5) Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 8.3.2.1.2 FB Divider Using Three-Resistor Method A FB-pin circuit using a three-resistor divider circuit can be used for applications where less than 200-kΩ resistors are required. ISNSGND ISNS VBOOST GD VIN + BSTOVPH - VOVPH + BSTOVPL - VOVPL - BSTOCP + VUVP RFB1 - FB RFB3 COMP + RFB2 + VBG - ISEL[10:0] Figure 13. Three-Resistor FB Divider Circuit Maximum boost voltage can be calculated with Equation 6. The maximum boost voltage can be reached during OPEN string detection or if all LED strings are left disconnected. VMAXBOOST ªªª 1 º )» « « «((ISEL_MAX u RFB3 ) + VBG ) u ( RFB2 ¼ «¬ ¬« ¬ º º ISEL _ MAX » u RFB1» »¼ ¼» (ISEL _ MAX u RFB3 ) VBG where • • • • VBG = 1.21 V ISEL_MAX = 38.7 µA RFB2 recommended value is 6 kΩ for boost operation and 10 kΩ for SEPIC operation RFB3 recommended value is 27 kΩ for boost operation and 30 kΩ for SEPIC operation (6) The minimum boost voltage must be less than the minimum LED string voltage. Minimum boost voltage is calculated with Equation 7: R VMINBOOST (VBG u ( FB1 )) VBG RFB2 (7) Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 21 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com When the boost OVP_LOW level is reached the boost controller stops switching the boost FET, and the BSTOVPL_STATUS bit is set. The LED drivers are still active during this condition, and the boost resumes normal switching operation once the boost output level falls. The boost OVP low voltage threshold is calculated with Equation 8: VBOOST_ OVP _LOW ªªª 1 º )» « « «((ISEL_MAX u RFB3 ) + VOVPL ) u ( RFB2 ¼ «¬ «¬ ¬ º º ISEL _MAX » u RFB1» »¼ »¼ (ISEL _MAX u RFB3 ) VOVPL where • • VOVPL= 1.423 V ISEL_MAX = 38.7 µA (8) When the boost OVP_LOW level is reached the boost controller enters fault recovery mode, and the BSTOVPH_STATUS bit is set. The boost OVP high-voltage threshold is calculated with Equation 9: VBOOST _ OVP _ HIGH ªªª 1 º )» « « «((ISEL_MAX u RFB3 ) + VOVPH ) u ( R «¬ ¬« ¬ FB2 ¼ º º ISEL _ MAX » u RFB1 » »¼ ¼» (ISEL _ MAX u RFB3 ) VOVPH where • • VOVPH = 1.76 V ISEL_MAX = 38.7 µA (9) When the boost UVP level is reached the boost controller starts a 100-ms OCP counter. The LP8863-Q1 device enters the fault recovery mode and sets the BSTOCP_STATUS bit if the boost voltage does not rise above the UVP threshold before the timer expires. The boost UVP voltage is calculated with Equation 10: ªªª º º 1 º VBOOST_UVP )» ISEL _ MAX » u RFB1» (ISEL _ MAX u RFB3 ) VUVP « « «((ISEL_MAX u RFB3 ) + VUVP ) u ( RFB2 ¼ «¬ «¬ ¬ »¼ »¼ where • • VUVP = 0.886 V ISEL_MAX = 38.7 µA (10) 8.3.2.2 Boost Sync and Spread Spectrum The boost controller can be clocked by an external BST_SYNC signal. If the external synchronization clock disappears the boost continues operation at the frequency defined by RBST_FSET resistor. If the external sync clock disappears while the SYNC pin level is low the boost continues operation without spread spectrum. If the external sync clock disappears, and BST_SYNC pin remains high the boost initially stops switching for approximately 256 μs and then begins switching with spread spectrum enabled. If using the external BST_SYNC input, the external frequency must be between 1.2 and 1.5 times higher than the frequency defined by the RBST_SET resistor. The boost converter has also an internal spread spectrum function that reduces EMI noise around the switching frequency and its harmonic frequencies. The internal spread spectrum function modulates the boost frequency ±3% from the central frequency with a 1.875-kHz modulation frequency. The spread-spectrum function cannot be used when an external synchronization clock is used. Table 3. Boost Synchronization Mode 22 BST_SYNC PIN LEVEL BOOST CLOCK MODE Low (GND) Spread spectrum disabled High (VDDIO) Spread spectrum enabled 300-kHz to 2200-kHz clock frequency Spread spectrum disabled, external synchronization mode Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 8.3.2.3 Boost Output Discharge When the boost is disabled, the discharge pin typically sinks 30-mA current in order to discharge the boost output voltage. The boost voltage discharge time depends on output capacitance. The discharge function is enabled for a maximum of 400 ms or until the output voltage falls below 3.3 V. The discharge state is entered when the EN pin goes low. If VDD falls below the power-on reset (POR) level, the LP8863-Q1 device exits the discharge state early and immediately enters the shutdown state. If the discharge feature is unused, leave the DISCHARGE pin floating. 8.3.3 2X Charge Pump An integrated 2X charge pump can be used to supply the gate drive for the external FET of the boost controller. The charge pump is enabled or disabled by automatically detecting the presence of the external C2X capacitor. If VDD is < 4.5 V then use the charge pump to generate a high-enough gate voltage to drive the external boost switching FET. To use the charge pump, a 2.2-µF cap is placed between C1N and C1P. If the charge pump is not required, C1N and C1P must be left unconnected and CPUMP pins tied to VDD. A 10-µF CPUMP capacitor is used to store energy for the gate driver. The CPUMP capacitor is required to be used in both charge pump enabled and disabled conditions and must be placed as close as possible to the CPUMP pins. Figure 14 and Figure 15 show required connections for both use cases. RISENSE D1 L1 Q2 VIN C1N CIN SD CPUMP CPUMP VSENSE_N CPUMP VSENSE_P RSD GD GD Q1 ISNS PGND C2X COUT RFB1 RFB2 RSENSE PGND LP8863-Q1 C1P ISNSGND VDD CVDD FB VDD Figure 14. Charge Pump Enabled Circuit Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 23 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com RISENSE D 1 L1 Q2 VIN C1N CIN SD CPUMP CPUMP VSENSE_N CPUMP VSENSE_P RSD GD GD COUT Q1 ISNS PGND RFB1 RFB2 RSENSE PGND LP8863-Q1 C1P VDD CVDD ISNSGND FB VDD Figure 15. Charge Pump Disabled Circuit The C2X_STAT status bit shows whether a C2X capacitor was detected. The C2X_INT bit shows status of any charge pump faults and generates a INT signal. The C2X_INT bit can be used to prevent the charge-pump fault from causing an interrupt on the INT pin signal. 8.3.4 1.8-V LDO The internal LDO regulator converts the input voltage at VDD to a 1.8-V output voltage at VLDO pin. The LDO regulator supplies internal circuitry. Bypass LDO with a ceramic capacitor of at least 4.7-µF capacitance to ground. Place capacitor as close as possible to the VLDO pin. 8.3.5 LED Current Sinks 8.3.5.1 LED Output Current Setting The maximum output LED current is set by an external resistor value. The LEDx_CURRENT[11:0] registers can also be used to individually adjust each string’s current down from this maximum. The default value for all the LEDx_CURRENT[11:0] registers is the maximum (4095). Equation 11 is used to calculate the current setting of an individual string: 1.21 V LEDx _ CURRENT[11: 0] ILEDx u 2560 u RISET 4095 (11) 24 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 LED0 Current Sink LED0 LED0_CURRENT[11:0] ISET LATCH DIN DOUT LED0_DAC DOUT LED1_DAC LED1 Current Sink LED1 DOUT LED2_DAC LED2 Current Sink LED2 DOUT LED3_DAC LED3 Current Sink LED3 DOUT LED4_DAC LED4 Current Sink LED4 DOUT LED5_DAC LED5 Current Sink LED5 EXTERNAL CURRENT SETTING RISET LED1_CURRENT[11:0] LED2_CURRENT[11:0] LED3_CURRENT[11:0] LED4_CURRENT[11:0] LED5_CURRENT[11:0] LATCH DIN LATCH DIN LATCH DIN LATCH DIN LATCH DIN LOAD_BRT Figure 16. LED Driver Current Setting Circuit The LEDx_CURRENT[11:0] registers updates are also latched by the LOAD_BRT_DB register similar to the individual brightness registers. This is done so all LED currents can be updated simultaneously. The default value for all the LEDx_CURRENT[11:0] registers is FFFh. 8.3.5.2 LED Output PWM Clock Generation The LED PWM frequency is asynchronous from the input PWM frequency. The LED PWM frequency is generated from the internal 20-MHz oscillator and can be set to eight discrete frequencies from 152 Hz to 19.531 kHz. The PWM dimming resolution is highest when the lowest PWM frequency is used. The PWM_FSET resistor determines the LED PWM frequency based on Table 4. PWM resolution in Table 4 is with PWM dither disabled. Table 4. LED PWM Frequency Selection R_PWM_FSET (kΩ) LED PWM FREQUENCY (Hz) PWM DIMMING RESOLUTION (bits) 3.92 152 16 (maximum) 4.75 305 16 5.76 610 15 7.87 1221 14 11 2441 13 17.8 4883 12 42.2 9766 11 140 19 531 10 Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 25 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 8.3.5.3 LED Output String Configuration The six LED driver channels of the LP8863-Q1 device can automatically support applications using six, five, four, three, and two LED strings. The driver channels can also be tied together in groups of two, three, or six channels. This allows the LP8863-Q1 device to drive three 300-mA LED strings, two 450-mA LED strings, or one 900-mA LED string. The LED strings are always appropriately phase shifted for their string configuration. This reduces the ripple seen at the boost output, which allows smaller output capacitors and reduces audible ringing in the capacitors. Phase shift increases the load frequency, which can move potential capacitor noise above the audible band while still keeping PWM frequency low to support a higher dimming ratio. When the LP8863-Q1 device is first powered on the string configuration is automatically detected and the phases of each channel configured. The LED string configuration must not be changed unless the LP8863-Q1 is powered off in shutdown state. The string configurations in Table 5 are valid configurations for auto detection. Any other detected configuration defaults to 6 channel / 60 degree mode. The detected string configuration can be read from the LED_STRING_CONF[2:0] register. Tie unused LEDx pins to ground. Table 5. LED Output String Configuration CONFIGURATION LED5 AUTOMATIC PHASE SHIFT 150 mA 150 mA 60° 150 mA (Tied to GND) 72° 150 mA (Tied to GND) (Tied to GND) 90° 150 mA (Tied to GND) (Tied to GND) (Tied to GND) 120° (Tied to GND) (Tied to GND) (Tied to GND) (Tied to GND) 180° LED0 LED1 LED2 LED3 LED4 6 channels 150 mA 150 mA 150 mA 150 mA 5 channels 150 mA 150 mA 150 mA 150 mA 4 channels 150 mA 150 mA 150 mA 3 channels 150 mA 150 mA 2 channels 150 mA 150 mA 3 channels, 300 mA /channel (tie LED pins together) 300 mA 2 channels, 450 mA /channel (tie LED pins together) 300 mA 300 mA 450 mA 450 mA 1 channel, 900 mA (tied LED pins together) 900 mA 120° 180° None 8.3.5.3.1 Independent Cluster Brightness Control Mode The LP8863-Q1 supports a cluster mode like that found in the LP8860-Q1 LED driver. This mode allows the brightness of each of the six driver channels to be controlled independently using the I2C or SPI interface. This is done by using the six CLUSTER_BRTx[15:0] registers, the six LEDx_GROUP registers and the LED_EXT_SUPPLY[5:0] register. The LEDx_GROUP registers select which CLUSTER_BRTx or DISP_BRT register is used for each of the six LED driver channels. The LED_EXT_SUPPLY[5:0] register selects which channels are used by the adaptive boost voltage control loop. This allows the LP8863-Q1 to drive LED strings that powered with either the integrated boost controller or external supply. If a LED driver channel is driving a string powered from the boost then its corresponding LED_EXT_SUPPLY bit should be set to zero. By default all LED_EXT_SUPPLY bits are 0, and all LEDx_GROUP bits are 000. An example of how the registers would be configured if the application calls for a display backlight with 4 strings and uses the remaining 2 current sinks to drive indicator LEDs where anodes are supplied externally (not from the boost of the LP8863-Q1 device) follows: 26 LED_EXT_SUPPLY[5:0] = 11000b (LED5 and LED4 use external supply ) LED0_GROUP = 000b (LED0 uses DISP_BRT register) LED1_GROUP = 000b (LED1 uses DISP_BRT register) LED2_GROUP = 000b (LED2 uses DISP_BRT register) LED3_GROUP = 000b (LED3 uses DISP_BRT register) LED4_GROUP = 100b (LED4 uses CLUSTER_BRT4 register) LED5_GROUP = 101b (LED5 uses CLUSTER_BRT5 register) Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 8.3.6 Brightness Control The LP8863-Q1 supports global or individual brightness control for each LED string through individual PWM duty cycle control of the LED0 to LED5 driver channels via I2C/SPI registers. An internal 20-MHz clock is used for generating PWM outputs. 8.3.6.1 Brightness Control Signal Path One display brightness path and five individual brightness paths can be used to control the LED driver channel brightness. The LEDx_GROUP registers select whether the display brightness path or the cluster 1 to 5 brightness paths control each LED output. The BRT_MODE register selects whether the input to the display brightness path is the PWM input pin or DISP_BRT register. The brightness control signal path diagram is shown in Figure 17. The display brightness path has sloper and hybrid dimming functions that can be enabled. By default the sloper function is enabled and hybrid dimming function disabled. Both functions can be controlled using the I2C or SPI interface. The sloper function is described in Sloper and hybrid dimming is described in Hybrid Dimming. By default the LP8863-Q1 operates with LED0 to LED5 channels controlled by the display brightness path. To enable individual LED string brightness control the LEDx_GROUP registers must be reconfigured with the SPI/I2C interface. Figure 17. LP8863-Q1 Brightness Path Diagram 8.3.6.2 Hybrid Dimming In addition to pure PWM dimming, LP8863-Q1 supports a hybrid-dimming mode. Hybrid dimming combines PWM and current modes for brightness control for the display brightness path. In hybrid mode PWM dimming is used for the low range of brightness, and current dimming is used for high brightness levels as shown in Figure 18. Current dimming control enables improved optical efficiency due to increased LED efficiency at lower currents. PWM dimming control at low brightness levels ensures linear and accurate control. Hybrid mode can be enabled with the DIMMING_MODE bit in USER_CONFIG1 register. The PWM and current modes transition threshold can be set at 12.5% or at 0% brightness with the DIMMING_MODE bits. The latter selection allows for pure current dimming control mode. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 27 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com Figure 18. 12.5% PWM and Current Hybrid Dimming Diagram 8.3.6.3 Sloper An optional sloper function makes the transition from one brightness value to another optically smooth. By default the advanced sloper is enabled with a 200-ms linear sloper duration. Transition time between two brightness values is programmed with the SLOPE_SELECT[2:0] bits (when 000, sloper is disabled). With advanced sloper enabled the brightness changes are further smoothed to be more pleasing to the human eye. Advanced slope is enabled with ADV_SLOPE_ENABLE register bit. Brightness Sloper Input Time Brightness Sloper Output Advanced Slope Slope Time Linear Slope Time Figure 19. Brightness Sloper 28 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 8.3.6.4 Dither The number of brightness steps when using LED output PWM dimming is equal to the 20-MHz oscillator frequency divided by the LED PWM frequency (set by PWM FSET resistor). The PWM duty cycle dither is a function the LP8863-Q1 uses to increase the number of brightness dimming steps beyond this oscillator clock limitation. The dither function modulates the LED driver output duty cycle over time to create more possible average brightness levels. The DITHER_SELECT[2:0] register bits control the level of dither, disabled, 1, 2, or up to 5 bits using the I2C or SPI interface. By default the dither has 3 bits enabled (default 011b). When the 1-bit dither is selected, the width of every second PWM pulse is increased by one LSB (one 20-MHz clock period). When the 3-bit dither is selected, within a sequence of 8 PWM periods the number of pulses with increased length varies: dither value 000 - all 8 pulses at default length; 001 - one of the 8 pulses is longer; 010 two of the 8 pulses are longer, etc., until at 111 seven of the 8 pulses have increased length. Figure 20 shows one example of PWM output dither. 50.003% 100 Hz Input PWM 1.2 kHz LED PWM Without Dither 50% 50% 50% 50% 1.2 kHz LED PWM With 2bit Dither 50.006% 50% 50.006% 50% Figure 20. PWM Dither Example The dither block also has an additional mode at low brightness levels when LED PWM duty cycle is less than the minimum pulse width (that is, less than the LED driver rise time). In this mode the dither block skips full PWM pulses to reduce the brightness further enabling very high dimming modes. The end result is the LED PWM frequency is reduced as more and more minimum pulses are skipped or dithered out. This function can be enabled using the I2C or SPI interface by programming the EN_MIN_PWM_LIMIT bit to 1. Figure 21 shows how the 2-bit minimum brightness dithering works. 100 Hz Input PWM 305 Hz LED PWM With Minimum Pulse Dither 300 ns = 0.003% 200 ns 300 ns = 0.003% 200 ns No Pulse 3.2 ms 3.2 ms No Pulse 3.2 ms 3.2 ms Average Brightness = 0.003% Figure 21. Minimum Brightness Dither Example 8.3.7 Die Temperature Read-Out and Thermal Window Detector The LP8863-Q1 has two internal thermal sensors: one for protection purposes (device thermal shutdown) and one for die temperature monitoring. The die temperature monitor block includes a 9-bit ADC to convert the analog thermal-sensor output to a temperature reading available in the register JUNCTION_TEMPERATURE. First temperature result is available 2 ms after the activation of the block and conversion rate is 10 Hz. When the temperature monitor block is disabled register JUNCTION_TEMPERATURE content is –256°C. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 29 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com The die temperature monitor also includes a thermal window detector. The TEMPERATURE_LIMIT_HIGH and TEMPERATURE_LIMIT_LOW bits set the high and low limits for the thermal window. These thresholds have ±1°C hysteresis: TEMPERATURE _LIMIT_HIGH + 1°C for increasing and TEMPERATURE_LIMIT_HIGH – 1°C for decreasing, for example. If the die temperature increases above the high limit or reduces below the low limit, a fault interrupt is generated. Die temperature monitor (ADC, thermal sensor, and window detector) can be disabled to minimize power dissipation in STANDBY mode. The thermal sensor for TSD is always active. TSD_STATUS INT INT Interrupts TEMPHIGH_STATUS TEMPLOW_STATUS TEMPERATURE_LIMIT_HIGH TEMPERATURE_LIMIT_LOW TSD Thermal Sensor Temperature Monitor Window Detector Thermal Sensor I2C/SPI JUNCTION_TEMPERATURE TEMP_MON_EN ADC Figure 22. Thermal Shutdown and Sensor Block Diagram Figure 23, Figure 24, and Figure 25 show the INT pin and status behaviors of the TSD, temperature high, and temperature low limits. 30 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 Enters Standby Mode TTSD Thermal Shutdown Returns to Normal Mode TTSD_H hysteresis TEMPERATURE_LIMIT_HIGH TEMPERATURE_LIMIT_LOW Host clears INT Status TEMP_MON_EN INT TEMPHIGH_STATUS TEMPLOW_STATUS TSD_STATUS Figure 23. Thermal Shutdown and Sensor Example 1 Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 31 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com TTSD Thermal Shutdown TTSD_H hysteresis TEMPERATURE_LIMIT_HIGH TEMPERATURE_LIMIT_LOW Host clears INT Status TEMP_MON_EN INT TEMPHIGH_STATUS TEMPLOW_STATUS TSD_STATUS Figure 24. Thermal Shutdown and Sensor Example 2 32 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 TTSD Thermal Shutdown TTSD_H hysteresis TEMPERATURE_LIMIT_HIGH TEMPERATURE_LIMIT_LOW Host clears INT Status TEMP_MON_EN INT TEMPHIGH_STATUS TEMPLOW_STATUS TSD_STATUS Figure 25. Thermal Shutdown and Sensor Example 3 8.3.8 Protection and Fault Detections The LP8863-Q1 device includes fault detections for LED open and short conditions, boost input undervoltage, overvoltage and overcurrent, boost output overvoltage and overcurrent, VDD undervoltage and die overtemperature. Host can monitor the status of the faults in INTERRUPT_STATUS_1 and INTERRUPT_STATUS_2 registers. 8.3.8.1 LED Faults During normal boost operation, boost voltage is raised if any of the LED outputs falls below the low headroom threshold level. Open LED fault is detected if boost output voltage has reached the maximum and at least one LED output is still below the threshold. The open string is then disconnected from the boost adaptive control loop and its output is disabled. Any LED fault sets the status bit LED_STATUS and an interrupt is generated unless LED interrupt is disabled. Reason for the open LED faults can be read from bits OPEN_LED and LEDx_FAULT (x = 0...5, indicating the faulty LED) in INTERRUPT_STATUS_2 register. These bits maintain their value until device power-down while the LED_STATUS bit is cleared by the interrupt clearing procedure. If a new LED fault is detected, LED_STATUS is set and an interrupt generated again. Shorted LED fault is detected if one or more LED outputs are above the SHORTED_LED_THRESHOLD setting and at least one LED output is inside the normal operation widow (see Figure 26). Shorted string is disconnected from the boost adaptive control loop and the LED PWM output is disabled. LED_STATUS status bit is set and an interrupt generated similarly as in open LED case. Shorted LED fault reason can be read from bits SHORT_LED and LEDx_FAULT (x = 0...5, indicating the faulty LED) in INTERRUPT_STATUS_2 register. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 33 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com Figure 26. LED Open and Short Detection Logic 8.3.8.2 Boost Faults Boost overvoltage is detected if the FB pin voltage exceeds the VOVPL threshold. When boost overvoltage is detected, BSTOVPL_STATUS bit is set in the INTERRUPT_STATUS_1 register. The boost FET stops switching, and the output voltage is automatically limited. If the BSTOVPL_STATUS bit is continually set (that is, reappears after clearing), it may indicate an issue in the application. Boost overvoltage low is monitored during device normal operation (ACTIVE mode). A second boost overvoltage high fault is detected if the FB pin voltage exceeds the VOVPH threshold. The LP8863-Q1 device enters the fault recovery state to protect against excessive thermal dissipation caused by high headroom on the LED drivers. When boost overvoltage is detected, BSTOVPH_STATUS bit is set in the INTERRUPT_STATUS_1 register. A fault interrupt is also generated. If the BSTOVPH_STATUS bit is continually set (that is, reappears after clearing), it may indicate an issue in the application. Boost overvoltage high is monitored during device normal operation (ACTIVE mode). Boost overcurrent is detected if the FB pin voltage drops below the VUVP threshold. A boost OCP fault is detected if the undervoltage condition persists for longer than 110 ms. If the boost overcurrent timer expires before the output voltage recovers, the BSTOCP_STATUS bit is set in the INTERRUPT_STATUS_1 register. The fault recovery state is entered, and a fault interrupt is generated. If the BSTOCP_STATUS bit is permanently set, it may indicate an issue in the application. Boost overcurrent is monitored from the boost start, and fault may trigger during boost start-up. 8.3.8.3 Power-Line Faults If during operation of the LP8863-Q1 device the VIN (VSENSE_P pin) voltage falls below the VINUVLO falling level, the boost, LED outputs, and power-line FET are turned off, and the device enters STANDBY mode. The VINUVLO_STATUS bit is also set, and the INT pin is triggered. When the VINUVLO voltage rises above the rising threshold level the LP8863-Q1 device exits STANDBY and begins the start-up sequence. If during LP8863-Q1 device operation VIN (VSENSE_P pin) voltage rises above the VINOVP rising level, boost, LED outputs, and power-line FET are turned off, and the device enters STANDBY mode. The VINOVP_STATUS bit is also set, and the INT pin is triggered. When the VINOVP voltage falls below the falling threshold level the LP8863-Q1 exits STANDBY and begins the start-up sequence. The VIN OCP protection detects overcurrent by measuring voltage of the RISENSE resistor connected between VSENSE_P and VSENSE_N pins. VIN OCP sensing begins once the LP8863-Q1 enters the PL FET soft-start state. Fault is detected if overcurrent condition duration lasts for at least 10 μs, minimum. The VINOCP_STATUS bit is also set, and the INT pin is triggered. To trip at a lower current limit a larger sense resistor can be used to create a 220-mV voltage difference across the sense resistor. 34 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 8.3.8.4 VDD Undervoltage Fault If during LP8863-Q1 device operation VDD falls below VDDUVLO falling level, boost, PL FET, and LED outputs are turned off, and the device enters STANDBY mode. The VDDUVLO_STATUS fault bit is set, and the INT pin is triggered. The LP8863-Q1 recovers automatically to ACTIVE mode when VDD rises above VDDUVLO rising threshold. If VDD falls below VPOR the LP8863-Q1 device enters SHUTDOWN mode. 8.3.8.5 Thermal Shutdown If the die temperature of LP8863-Q1 reaches the thermal shutdown threshold TTSD, the boost, PL FET, and LED outputs on LP8863-Q1 device shut down to protect the device from damage. Fault status bit TSD_STATUS bit is set, and the INT pin is triggered. The device restarts the PL FET, the boost, and LED outputs when temperature drops by TTSD_H amount. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 35 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 8.3.8.6 Overview of the Fault/Protection Schemes FAULT NAME STATUS BIT CONDITION TRIGGER FAULT INTERRUPT ENTER FAULT RECOVERY ACTION Boost overcurrent BSTOCP_STATUS FB pin voltages falls below VUVP level for > 110 ms Yes Yes Device goes to standby and then attempts to restart 200 ms after fault occurs. Boost overvoltage low BSTOVPLOW_STATUS FB pin voltages rises above VOVPL level No No Boost stops switching until boost voltage level falls. The device remains in normal mode with LED drivers operational. Boost OVP high BSTOVPH_STATUS FB pin voltages rises above VOVPH level Yes Yes Device goes to standby and waits until output voltage falls below threshold before restarting. Boost sync clock invalid BSTSYNC_STATUS Device is enabled while a valid external SYNC clock is running. Then SYNC stops or changes to invalid frequency. Valid range is 1.2× to 1.5× of frequency selected by BST_FSET resistor. No No Device defaults to internal clock frequency selected by BST_FSET resistor. If SYNC input is held high then spread spectrum is enabled. If SYNC input is held low then spread spectrum is disabled. VIN overvoltage VINOVP_STATUS VIN voltage rises above 43 V. Yes No Device goes to standby and waits until output voltage falls below threshold before restarting. VIN undervoltage VINUVLO_STATUS VIN voltage falls below 2.8 V. Yes No Device goes to standby and then attempts to restart once the input voltage rises above threshold. VIN overcurrent VINOCP_STATUS Voltage across RISENSE exceeds 220 mV Yes Yes Device goes to standby and then attempts to restart 200 ms after fault occurs. VDD undervoltage VDDUVLO_STATUS VDD level falls below VDDUVLO threshold. Yes No Device restarts once VDD level rises above VDDUVLO threshold. Thermal shutdown TSD_STATUS Junction temperature rises above TTSD threshold. Yes No Device goes to standby and then attempts to restart once die temperature falls below threshold. Open LED string LED_STATUS OPEN_LED Headroom voltage on one or more channels is below minimum level and boost has adapted to maximum level. Yes No Faulted LED string is disabled and removed from adaptive boost control loop. String is re-enabled next power cycle. LED_STATUS Headroom voltage on one or more channels is above the SHORTED_LED_THRESHOLD for > 5 ms while the headroom of at least one channel is still below this threshold. Yes No Faulted LED string is disabled and removed from adaptive boost control loop. String is re-enabled next power cycle. Invalid LED string detected INVSTRING_STATUS LED string detection does not match one of 8 valid configurations Yes No Device defaults to six LED string phase shift mode. String detection reoccurs next power cycle. FSET detection fault FSET_STATUS BST_FSET or PWM_FSET are missing or an invalid value Yes No Boost does not start up. Fault is cleared by VDD cycling with correct resistor connection at FSET pin. Charge pump fault CP_STATUS Charge pump voltage level is abnormal. No No Device functions normally, if possible. If charge pump issue is severe, it is likely boost overcurrent fault will trip. Shorted LED 36 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com Charge pump components CPCAP_STATUS missing Copyright © 2017–2018, Texas Instruments Incorporated SNVSAB6B – MARCH 2017 – REVISED JULY 2018 Charge pump is missing components. No No Device functions normally, if possible. If charge pump issue is severe, it is likely boost overcurrent fault will trip. Submit Documentation Feedback 37 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 8.4 Device Functional Modes 8.4.1 State Diagram From Any State VDD < POR SHUTDOWN VDD > POR DEVICE INIT STANDBY EN=1 FAULT RECOVERY PL FET SOFTSTART 200 ms and PL_PRECHARGE_READY 50 ms and BOOST_OK=0 50 ms and PL_PRECHARGE_COMPLETE BOOST STARTUP FAULT LATCH FAULT 50 ms and BOOST_OK=1 NORMAL All LED channels have been disabled due to open or short faults. EN=0 DISCHARGE DISCHARGE_DONE and EN=0 Figure 27. State Machine Diagram 8.4.2 Shutdown When VDD is below POR threshold device is in shutdown state. 8.4.3 Device Initialization After POR is released device initialization begins. During this state the LDO is started up, EEPROM default and trim configurations are loaded, BOOST_FSET and PWM_FSET resistors are detected, and the LED string configuration is detected. 38 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 Device Functional Modes (continued) 8.4.4 Standby Mode In standby the LP8863-Q1 device can be accessed with I2C or SPI to change any configuration registers. Analog blocks are disabled to save power. 8.4.5 Power-line FET Soft Start Power-line FET is enabled, and boost input and output capacitors are charged to VIN level. VIN faults for OCP, OVP, and UVP are enabled. 8.4.6 Boost Start-Up Boost voltage is ramped to maximum voltage level with reduced current limit. Start-up exits when boost reaches initial target voltage. All boost faults are now enabled. 8.4.7 Normal Mode LED drivers are enabled when brightness is greater than zero. All LED faults are active. 8.4.8 Discharge Mode When EN goes low from normal mode the boost output voltage is discharged. This state exits when boost voltage falls below 3.3 V or when the 400-ms timer expires. 8.4.9 Fault Recovery Non-LED faults can trigger fault recover state. LED drivers, boost converter, and power-line FET are disabled for 200 ms, and the device attempts to restart from standby mode if EN is still high. 8.4.10 Latch Fault If all LED strings are disabled due to faults then the LP8863-Q1 enters the latch fault mode. This state can be exited by toggling the VDD pin. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 39 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com Device Functional Modes (continued) 8.4.11 Start-Up Sequence STATE SHUTDOWN DEVICE INIT STANDBY PL FET PRECHARGE BOOST SOFTSTART NORMAL VIN VDD VDDIO EN PWM Input Pin VINIT VADAPT Boost VOUT LEDx VIN 50 ms 50 ms Figure 28. Start-Up Sequence Diagram 40 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 Device Functional Modes (continued) 8.4.12 Shutdown Sequence STATE NORMAL DISCHARGE SHUTDOWN VIN VDD VDDIO EN PWM Input Pin Boost VOUT 3.3 V 0V LEDx < 400 ms Figure 29. Shutdown Sequence Diagram For proper operation of discharge function, pull the EN pin before VDD pin. VIN and VDDIO can be set low any time after EN low. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 41 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 8.5 Programming 8.5.1 Serial Interface Selection The serial interface type is selected by connecting the IFSEL pin to VDDIO or GND. The LP8863-Q1 device checks the IFSEL pin state as part of device startup. Device start-up occurs after VDD and VDDIO POR levels are reached. Table 6 shows how to connect the IFSEL pin to select between the SPI and I2C-compatible interfaces. Table 6. Serial Control Interface Selection PIN NAME IFSEL PIN = VDDIO SS_ADDRSEL ADDRSEL IFSEL PIN = GND SS SCLK_SCL SCL SCLK SDI_SDA SDA SDI SDO_PWM PWM SDO 8.5.2 SPI Interface In SPI mode host can address as many unique LP8863-Q1 devices as there are slave select pins on host. The complete 10-bit register space in LP8863-Q1 device can be accessed using SPI interface. The LP8863-Q1 device is compatible with SPI serial-bus specification and operates as a slave device. The transmission consists of 32-bit write and read cycles. One cycle consists of a 15-bit register address (10 bits used), 1 read/write (R/W) bit and 16-bit data to maintain compatibility with 16-bit SPI. The R/W bit high state defines a write cycle and low defines a read cycle. The SDO output is normally in a highimpedance state. When the slave-select pin SS for the device is active (that is, low) the SDO output is pulled low. During write cycle SDO stays in high-impedance state. The address and data bits are transmitted MSB first. The slave-select signal SS must be low during the cycle transmission. SS resets the interface when high, and it has to be taken high between successive cycles, except when using auto- increment mode. Data is clocked in on the rising edge of the SCLK clock signal, while data is clocked out on the falling edge of SCLK. Figure 30. SPI Write Figure 31. SPI Read 42 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 8.5.3 I2C-Compatible Interface Two LP8863-Q1 slave devices may share the same I2C bus. The SS_ADDRSEL pin selects between the two possible base slave addresses. Table 7. I2C Address Selection SS_ADDRSEL PIN 7-BIT I2C BASE SLAVE ADDRESS GND 0x2C VDDIO 0x3C The LP8863-Q1 uses a 10-bit register address space. The 10-bit register address space is accessed as four separate 8-bit address spaces. Four different slave addresses are used to access each of the four 8-bit address register spaces. Table 8. I2C Address Registers Selection SS_ADDRSEL PIN GND VDDIO 7-BIT BASE ADDRESS 0x2C 0x3C 7-BIT SLAVE ADDRESS ACCESSIBLE 10-BIT REGISTERS 0x2C 0x000 to 0x0FF 0x2D 0x100 to 0x1FF 0x2E 0x200 to 0x2FF 0x2F 0x300 to 0x3FF 0x3C 0x000 to 0x0FF 0x3D 0x100 to 0x1FF 0x3E 0x200 to 0x2FF 0x3F 0x300 to 0x3FF Write I2C transactions are made up of 4 bytes. The first byte includes the 7-bit slave address and Write bit. The 7-bit slave address selects the LP8863-Q1 slave device and one of four 8-bit register address sections. The second byte includes eight LSB bits of the 10-bit register address. The last two bytes are the 16-bit register value. Read I2C transactions are made up of five bytes. The first byte includes the 7-bit slave address and Write bit. The 7-bit slave address selects the LP8863-Q1 slave device and one of four 8-bit register address sections. The second byte includes eight LSB bits of the 10-bit register address. The third byte includes the 7-bit slave address and Read bit. The last two bytes are the 16-bit register value returned from the slave. Figure 32. I2C Write Figure 33. I2C Read Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 43 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 8.5.4 Programming Examples 8.5.4.1 General Configuration Registers The LP8863-Q1 does not require any serial interface configuration. It can be simply controlled with the EN pin and PWM pin. Most of the device configuration is accomplished using external resistor values or automatic detection. If a serial interface is available then extended configuration is possible. The configuration registers can be written in standby state as shown in Table 9. Table 9. Configuration Registers REGISTER NAME FUNCTION BRT_MODE Selects PWM pin or DISPLAY_BRT register for brightness control. SHORTED_LED_THRESHOLD Selects voltage level for shorted LED Fault. DITHER_SELECT Selects up to 3 bits of PWM dither for added dimming resolution. EN_MIN_PWM_LIMIT Enables 200-ns PWM pulse limit and frequency dither to reach lower minimum brightness levels. SLOPE_SELECT Selects duration for linear brightness sloper. ADV_SLOPE_ENABLE Enables advance sloper S-shape smoothing function. DIMMING_MODE Select between PWM, hybrid or current LED ouput dimming types. TEMP_MON_EN Enables temperature window monitor function. TEMPERATURE_LIMIT_HIGH Sets HIGH threshold level for temperature window function. TEMPERATURE_LIMIT_LOW Sets LOW threshold level for temperature window function. 8.5.4.2 Clearing Fault Interrupts The LP8863-Q1 has an INT pin to alert the host when a fault occurs. If a serial interface is available, the Interrupt Fault Status registers can be read back to learn which fault(s) have been detected. These status bits are located in the INTERRUPT_STATUS_1, INTERRUPT_STATUS_2, and INTERRUPT_STATUS_3 registers. Each interrupt status has a STATUS bit and a CLEAR bit. If a fault interrupt has been detected, a 1 is read back from its STATUS bit. To clear a fault interrupt status a 1 must be written to both the STATUS bit and CLEAR bit at the same time. 8.5.4.3 Disabling Fault Interrupts By default most of the LP8863-Q1 faults trigger the INT pin. Each fault has two INT_EN bits. These bits are located in the INTERRUPT_ENABLE_1, INTERRUPT_ENABLE_2, and INTERRUPT_ENABLE_3 registers. If the INT_EN bit is read and returns a 1, the INT pin is triggered when that fault occurs. The fault interrupt can be disabled by writing 01 to its INT_EN bits, or it can be enabled by writing 11 to its INT_EN bits. There is also a GLOBAL fault interrupt that can be disabled to prevent any faults from triggering the INT pin. 8.5.4.4 Diagnostic Registers The LP8863-Q1 contains several diagnostic registers than can be read with the serial interface for debugging or additional device information. Table 10 is a summary of the available registers. Table 10. Diagnostic Registers REGISTER NAME FUNCTION JUNCTION_TEMPERATURE 9-bit die junction temperature in 2s complement form — 1°C per LSB FSM_LIVE_STATUS Current state of the functional state machine PWM_INPUT_STATUS Measured 6-bit duty cycle of the PWM pin input LED_PWM_STATUS 16-bit LED0 PWM duty cycle from state machine LED_CURRENT_STATUS 12-bit LED0 current DAC value from state machine VBOOST_STATUS 10-bit value for adaptive boost voltage target — value is linear between VBOOST_MIN and VBOOST_MAX calculations AUTO_PWM_FREQ_SEL LED PWM frequency value from PWM_FSET detection AUTO_BOOST_FREQ_SEL Boost switching frequency value from PWM_FSET detection AUTO_LED_STRING_CFG LED string phase configuration detected from LED pin configuration 44 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 8.5.4.5 Cluster Mode Configuration and Control Registers The LP8863-Q1 device supports a cluster mode where the duty cycles and LED current of the six LED current drivers can be controlled independently. This mode can also select which LED current driver’s headroom levels are used by the adaptive boost voltage control loop. If the anode of an LED string is supplied by an external supply and not the integrated boost controller then its LED_EXT_SUPPLY bit is set to 1. The cluster mode configuration registers are summarized in Table 11. More details can be found in Register Maps. Table 11. Cluster Mode Configuration Registers REGISTER NAME FUNCTION LED0_GROUP...LED5_GROUP Selects which of the five CLUSTERx_BRT or DISPLAY_BRT registers control each LED current driver. CLUSTER1_BRT…CLUSTER5_BRT Five 16-bit brightness values that can be used in addition to the DISPLAY_BRT register. LED0_CURRENT…LED5_CURRENT Six 12-bit current registers allow LED current to be independently scaled from maximum level for LED current driver. LOAD_BRT_DB Load BRT bit is written to 1 in order to update the CLUSTERx_BRT and LEDx_CURRENT registers at the same time. LED_EXT_SUPPLY Six bits to select which LED current driver is powered from an external supply and not the boost converter. LED0_SHORT_DISABLE… LED5_SHORT_DISABLE Six bits to individually disable LED short detection for each LED current driver. Used if LED current value is set to lower value than other strings. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 45 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 8.6 Register Maps 8.6.1 FullMap Registers Table 12 lists the memory-mapped registers for the FullMap registers. All register offset addresses not listed in Table 12 should be considered as reserved locations and the register contents should not be modified. Table 12. FULLMAP Registers Offset Acronym Register Name Section 20h BL_MODE Brightness Mode Go 28h DISP_BRT Display Brightness Go 30h GROUPING1 Brightness Grouping 1 Go 32h GROUPING2 Brightness Grouping 2 Go 40h USER_CONFIG1 User Config 1 Go 42h USER_CONFIG2 User Config 2 Go 4Eh INTERRUPT_ENABLE_3 Fault Interrupt Enable 3 Go 50h INTERRUPT_ENABLE_1 Fault Interrupt Enable 1 Go 52h INTERRUPT_ENABLE_2 Fault Interrupt Enable 2 Go 54h INTERRUPT_STATUS_1 Fault Interrupt Status 1 Go 56h INTERRUPT_STATUS_2 Fault Interrupt Status 2 Go 58h INTERRUPT_STATUS_3 Fault Interrupt Status 3 Go E8h JUNCTION_TEMPERATURE Die Junction Temperature Go ECh TEMPERATURE_LIMIT_HIGH Temperature High Limit Go EEh TEMPERATURE_LIMIT_LOW Temperature Low Limit Go 13Ch CLUSTER1_BRT Cluster 1 Brightness Go 148h CLUSTER2_BRT Cluster 2 Brightness Go 154h CLUSTER3_BRT Cluster 3 Brightness Go 160h CLUSTER4_BRT Cluster 4 Brightness Go 16Ch CLUSTER5_BRT Cluster 5 Brightness Go 178h BRT_DB_CONTROL Cluster Brightness and Current Load Bit Go 1C2h LED0_CURRENT LED0 Current Go 1C4h LED1_CURRENT LED1 Current Go 1C6h LED2_CURRENT LED2 Current Go 1C8h LED3_CURRENT LED3 Current Go 1CAh LED4_CURRENT LED4 Current Go 1CCh LED5_CURRENT LED5 Current Go 288h BOOST_CONTROL Boost Control Go 28Ah SHORT_THRESH Shorted LED Threshold Go 2A4h FSM_DIAGNOSTICS Device State Diagnostics Go 2A6h PWM_INPUT_DIAGNOSTICS PWM Input Diagnostics Go 2A8h PWM_OUTPUT_DIAGNOSTICS PWM Output Diagnostics Go 2AAh LED_CURR_DIAGNOSTICS LED Current Diagnostics Go 2ACh ADAPT_BOOST_DIAGNOSTICS Adaptive Boost Diagnostics Go 2AEh AUTO_DETECT_DIAGNOSTICS Auto Detect Diagnstics Go Complex bit access types are encoded to fit into small table cells. Table 13 shows the codes that are used for access types in this section. Table 13. FullMap Access Type Codes Access Type Code Description R Read Read Type R 46 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 Table 13. FullMap Access Type Codes (continued) Access Type Code Description W Write Write Type W Reset or Default Value -n Value after reset or the default value 8.6.1.1 BL_MODE Register (Offset = 20h) [reset = 300h] BL_MODE is shown in Figure 34 and described in Table 14. Return to Summary Table. Figure 34. BL_MODE Register 15 14 13 12 11 10 9 8 3 2 1 0 brightness_mode R/W-0h RESERVED R/W-C0h 7 6 5 4 RESERVED R/W-C0h Table 14. BL_MODE Register Field Descriptions Field Type Reset Description 15-2 Bit RESERVED R/W C0h These bits are reserved. 1-0 brightness_mode R/W 0h 0h = Brightness controlled by PWM Input 1h = Reserved 2h = Brightness controlled by DISPLAY_BRT Register 3h = Reserved 8.6.1.2 DISP_BRT Register (Offset = 28h) [reset = 0h] DISP_BRT is shown in Figure 35 and described in Table 15. Return to Summary Table. Figure 35. DISP_BRT Register 15 14 13 12 11 10 9 8 7 DISPLAY_BRT R/W-0h 6 5 4 3 2 1 0 Table 15. DISP_BRT Register Field Descriptions Bit 15-0 Field Type Reset Description DISPLAY_BRT R/W 0h Display Brightness Register 8.6.1.3 GROUPING1 Register (Offset = 30h) [reset = 0h] GROUPING1 is shown in Figure 36 and described in Table 16. Return to Summary Table. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 47 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com Figure 36. GROUPING1 Register 15 14 13 12 11 10 LED3_GROUP R/W-0h 7 6 9 8 1 0 9 8 1 0 LED2_GROUP R/W-0h 5 4 3 2 LED1_GROUP R/W-0h LED0_GROUP R/W-0h Table 16. GROUPING1 Register Field Descriptions Bit 15-12 Field Type Reset Description LED3_GROUP R/W 0h LED Output 3 Brightness Control Mapping 0h = DISP_BRT/PWM 1h = CLUSTER1_BRT 2h = CLUSTER3_BRT 3h = CLUSTER3_BRT 4h = CLUSTER4_BRT 5h = CLUSTER5_BRT 11-8 LED2_GROUP R/W 0h LED Output 2 Brightness Control Mapping 0h = DISP_BRT/PWM 1h = CLUSTER1_BRT 2h = CLUSTER3_BRT 3h = CLUSTER3_BRT 4h = CLUSTER4_BRT 5h = CLUSTER5_BRT 7-4 LED1_GROUP R/W 0h LED Output 1 Brightness Control Mapping 0h = DISP_BRT/PWM 1h = CLUSTER1_BRT 2h = CLUSTER3_BRT 3h = CLUSTER3_BRT 4h = CLUSTER4_BRT 5h = CLUSTER5_BRT 3-0 LED0_GROUP R/W 0h LED Output 0 Brightness Control Mapping 0h = DISP_BRT/PWM 1h = CLUSTER1_BRT 2h = CLUSTER3_BRT 3h = CLUSTER3_BRT 4h = CLUSTER4_BRT 5h = CLUSTER5_BRT 8.6.1.4 GROUPING2 Register (Offset = 32h) [reset = 0h] GROUPING2 is shown in Figure 37 and described in Table 17. Return to Summary Table. Figure 37. GROUPING2 Register 15 14 13 12 11 10 3 2 RESERVED R/W-0h 7 6 5 LED5_GROUP R/W-0h 48 Submit Documentation Feedback 4 LED4_GROUP R/W-0h Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 Table 17. GROUPING2 Register Field Descriptions Field Type Reset Description 15-8 Bit RESERVED R/W 0h These bits are reserved. 7-4 LED5_GROUP R/W 0h LED Output 5 Brightness Control Mapping 0h = DISP_BRT/PWM 1h = CLUSTER1_BRT 2h = CLUSTER3_BRT 3h = CLUSTER3_BRT 4h = CLUSTER4_BRT 5h = CLUSTER5_BRT 3-0 LED4_GROUP R/W 0h LED Output 4 Brightness Control Mapping 0h = DISP_BRT/PWM 1h = CLUSTER1_BRT 2h = CLUSTER3_BRT 3h = CLUSTER3_BRT 4h = CLUSTER4_BRT 5h = CLUSTER5_BRT 8.6.1.5 USER_CONFIG1 Register (Offset = 40h) [reset = 8B0h] USER_CONFIG1 is shown in Figure 38 and described in Table 18. Return to Summary Table. Figure 38. USER_CONFIG1 Register 15 14 DITHER_SELECT 13 12 5 4 ADV_SLOPE_ ENABLE R/W-1h R/W-0h 7 11 RESERVED 10 9 TEMP_MON_E N R/W-0h R/W-2h 6 SLOPE_SELECT R/W-5h 3 2 8 RESERVED R/W-0h RESERVED 1 0 DIMMING_MODE R/W-0h R/W-0h Table 18. USER_CONFIG1 Register Field Descriptions Bit 15-13 Field Type Reset DITHER_SELECT R/W 0h Description 0h = Dither Disabled 1h = 1-bit Dither 2h = 2-bit Dither 3h = 3-bit Dither 4h = 4-bit Dither 5h = 5-bit Dither 6h = Unused 7h = Unused 12-10 RESERVED R/W 2h 9 TEMP_MON_EN R/W 0h 8 RESERVED R/W 0h These bits are reserved. 0h = Temperature Monitor Disabled 1h = Temperature Monitor Enabled Copyright © 2017–2018, Texas Instruments Incorporated This bit is reserved. Submit Documentation Feedback 49 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com Table 18. USER_CONFIG1 Register Field Descriptions (continued) Bit Field Type Reset 7-5 SLOPE_SELECT R/W 5h Description 0h = 0ms 1h = 1ms 2h = 2ms 3h = 50ms 4h = 100ms 5h = 200ms 6h = 300ms 7h = 500ms Times are for linear slope mode. Advanced sloper will increase durations while adding additional smoothing to brightness transitions. 1ms and 2ms sloper times are intended to be used only in linear mode. 50ms to 500ms sloper durations may be used with or without advanced sloper function. 4 ADV_SLOPE_ENABLE R/W 1h 3-2 RESERVED R/W 0h These bits are reserved. 1-0 DIMMING_MODE R/W 0h LED Output Dimming Mode 0h = Linear Sloping 1h = Advanced Sloping 0h = PWM Mode 1h = 12.5% Hybrid Mode 2h = Unused 3h = 12-bit Constant Current Mode 8.6.1.6 USER_CONFIG2 Register (Offset = 42h) [reset = 0h] USER_CONFIG2 is shown in Figure 39 and described in Table 19. Return to Summary Table. Figure 39. USER_CONFIG2 Register 15 EN_MIN_PWM _LIMIT R/W-0h 14 7 6 13 12 11 RESERVED 10 9 8 2 1 0 R/W-0h 5 4 3 RESERVED R/W-0h Table 19. USER_CONFIG2 Register Field Descriptions Bit Field Type Reset Description 15 EN_MIN_PWM_LIMIT R/W 0h Allows PWM pulses to be dithered to reduce lower minimum brightness. When enabled brightness levels that map to less than 200ns pulse width will cause pulses to be skipped. 0h = Disabled 1h = Enabled 14-0 RESERVED R/W 0h These bits are reserved. 8.6.1.7 INTERRUPT_ENABLE_3 Register (Offset = 4Eh) [reset = 200Ah] INTERRUPT_ENABLE_3 is shown in Figure 40 and described in Table 20. Return to Summary Table. 50 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 Figure 40. INTERRUPT_ENABLE_3 Register 15 14 BSTSYNC_INT_EN R/W-0h 13 12 VINOCP_INT_EN R/W-2h 11 10 CPCAP_INT_EN R/W-0h 9 7 5 4 INVSTRING_INT_EN R/W-0h 3 2 VINOVP_INT_EN R/W-2h 1 0 VINUVP_INT_EN R/W-2h 6 FSET_INT_EN R/W-0h 8 CP_INT_EN R/W-0h Table 20. INTERRUPT_ENABLE_3 Register Field Descriptions Field Type Reset Description 15-14 Bit BSTSYNC_INT_EN R/W 0h Missing Boost Sync Interrupt Enable Read: 0h = Interrupt is currently disabled 2h = Interrupt is currently enabled Write: 1h = Disable Interrupt 3h = Enable Interrupt 13-12 VINOCP_INT_EN R/W 2h VIN Over-Current Interrupt Enable Read: 0h = Interrupt is currently disabled 2h = Interrupt is currently enabled Write: 1h = Disable Interrupt 3h = Enable Interrupt 11-10 CPCAP_INT_EN R/W 0h Charge Pump Cap Missing Interrupt Enable Read: 0h = Interrupt is currently disabled 2h = Interrupt is currently enabled Write: 1h = Disable Interrupt 3h = Enable Interrupt 9-8 CP_INT_EN R/W 0h Charge Pump Interrupt Enable Read: 0h = Interrupt is currently disabled 2h = Interrupt is currently enabled Write: 1h = Disable Interrupt 3h = Enable Interrupt 7-6 FSET_INT_EN R/W 0h Missing FSET Resistor Interrupt Enable Read: 0h = Interrupt is currently disabled 2h = Interrupt is currently enabled Write: 1h = Disable Interrupt 3h = Enable Interrupt 5-4 INVSTRING_INT_EN R/W 0h Invalid LED String Configuration Interrupt Enable Read: 0h = Interrupt is currently disabled 2h = Interrupt is currently enabled Write: 1h = Disable Interrupt 3h = Enable Interrupt Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 51 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com Table 20. INTERRUPT_ENABLE_3 Register Field Descriptions (continued) Bit Field Type Reset Description 3-2 VINOVP_INT_EN R/W 2h VIN Over-Voltage Interrupt Enable Read: 0h = Interrupt is currently disabled 2h = Interrupt is currently enabled Write: 1h = Disable Interrupt 3h = Enable Interrupt 1-0 VINUVP_INT_EN R/W 2h VIN Under-Voltage Interrupt Enable Read: 0h = Interrupt is currently disabled 2h = Interrupt is currently enabled Write: 1h = Disable Interrupt 3h = Enable Interrupt 8.6.1.8 INTERRUPT_ENABLE_1 Register (Offset = 50h) [reset = A02Ah] INTERRUPT_ENABLE_1 is shown in Figure 41 and described in Table 21. Return to Summary Table. Figure 41. INTERRUPT_ENABLE_1 Register 15 14 GLOBAL_INT_EN R/W-2h 13 12 BSTOVPH_INT_EN R/W-2h 11 10 TEMP_INT_EN R/W-0h 9 7 6 BSTOVPL_INT_EN R/W-0h 5 4 BSTOCP_INT_EN R/W-2h 3 2 VDDUVLO_INT_EN R/W-2h 1 8 RESERVED R/W-0h 0 TSD_INT_EN R/W-2h Table 21. INTERRUPT_ENABLE_1 Register Field Descriptions Bit Field Type Reset Description 15-14 GLOBAL_INT_EN R/W 2h Global Interrupt Enable Read: 0h = Interrupt is currently disabled 2h = Interrupt is currently enabled Write: 1h = Disable Interrupt 3h = Enable Interrupt 13-12 BSTOVPH_INT_EN R/W 2h Boost OVP High Interrupt Enable Read: 0h = Interrupt is currently disabled 2h = Interrupt is currently enabled Write: 1h = Disable Interrupt 3h = Enable Interrupt 11-10 TEMP_INT_EN R/W 0h Temperature Interrupt Enable Read: 0h = Interrupt is currently disabled 2h = Interrupt is currently enabled Write: 1h = Disable Interrupt 3h = Enable Interrupt RESERVED R/W 0h These bits are reserved. 9-8 52 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 Table 21. INTERRUPT_ENABLE_1 Register Field Descriptions (continued) Bit Field Type Reset Description 7-6 BSTOVPL_INT_EN R/W 0h Boost OVP Low Interrupt Enable Read: 0h = Interrupt is currently disabled 2h = Interrupt is currently enabled Write: 1h = Disable Interrupt 3h = Enable Interrupt 5-4 BSTOCP_INT_EN R/W 2h Boost Over-Current Interrupt Enable Read: 0h = Interrupt is currently disabled 2h = Interrupt is currently enabled Write: 1h = Disable Interrupt 3h = Enable Interrupt 3-2 VDDUVLO_INT_EN R/W 2h VDD UVLO Interrupt Enable Read: 0h = Interrupt is currently disabled 2h = Interrupt is currently enabled Write: 1h = Disable Interrupt 3h = Enable Interrupt 1-0 TSD_INT_EN R/W 2h Thermal Shutdown Interrupt Enable Read: 0h = Interrupt is currently disabled 2h = Interrupt is currently enabled Write: 1h = Disable Interrupt 3h = Enable Interrupt 8.6.1.9 INTERRUPT_ENABLE_2 Register (Offset = 52h) [reset = 80h] INTERRUPT_ENABLE_2 is shown in Figure 42 and described in Table 22. Return to Summary Table. Figure 42. INTERRUPT_ENABLE_2 Register 15 14 13 12 11 10 9 8 2 1 0 RESERVED R/W-0h 7 6 5 4 LED_INT_EN R/W-2h 3 RESERVED R/W-0h Table 22. INTERRUPT_ENABLE_2 Register Field Descriptions Field Type Reset Description 15-8 Bit RESERVED R/W 0h These bits are reserved. 7-6 LED_INT_EN R/W 2h LED Open / Short Interrupt Enable Read: 0h = Interrupt is currently disabled 2h = Interrupt is currently enabled Write: 1h = Disable Interrupt 3h = Enable Interrupt 5-0 RESERVED R/W 0h Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 53 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 8.6.1.10 INTERRUPT_STATUS_1 Register (Offset = 54h) [reset = 0h] INTERRUPT_STATUS_1 is shown in Figure 43 and described in Table 23. Return to Summary Table. Figure 43. INTERRUPT_STATUS_1 Register 15 BSTOVPH_ST ATUS R/W-0h 14 BSTOVPH_CL EAR R/W-0h 13 12 11 10 TEMPHIGH_ST TEMPHIGH_CL TEMPLOW_ST TEMPLOW_CL ATUS EAR ATUS EAR R/W-0h R/W-0h R/W-0h R/W-0h 7 6 BSTOVPL_STA BSTOVPL_CLE TUS AR R/W-0h R/W-0h 5 BSTOCP_STA TUS R/W-0h 4 BSTOCP_CLE AR R/W-0h 3 VDDUVLO_ST ATUS R/W-0h 2 VDDUVLO_CL EAR R/W-0h 9 8 RESERVED R/W-0h 1 TSD_STATUS 0 TSD_CLEAR R/W-0h R/W-0h Table 23. INTERRUPT_STATUS_1 Register Field Descriptions Bit Field Type Reset Description 15 BSTOVPH_STATUS R/W 0h Boost OVP High Status 0h = No Fault 1h = Fault 14 BSTOVPH_CLEAR R/W 0h Boost OVP High Fault Clear Write "1" to both Status bit and Clear bit at same time to clear interrupt register status and interrupt pin status. 13 TEMPHIGH_STATUS R/W 0h Temperature High Status 0h = No Fault 1h = Fault 12 TEMPHIGH_CLEAR R/W 0h Temperature High Fault Clear Write "1" to both Status bit and Clear bit at same time to clear interrupt register status and interrupt pin status. 11 TEMPLOW_STATUS R/W 0h Temperature Low Status 0h = No Fault 1h = Fault 10 TEMPLOW_CLEAR R/W 0h Temperature Low Fault Clear Write "1" to both Status bit and Clear bit at same time to clear interrupt register status and interrupt pin status. 9-8 RESERVED R/W 0h These bits are reserved. BSTOVPL_STATUS R/W 0h Boost OVP Low Status 7 0h = No Fault 1h = Fault 6 BSTOVPL_CLEAR R/W 0h Boost OVP Low Fault Clear Write "1" to both Status bit and Clear bit at same time to clear interrupt register status and interrupt pin status. 5 BSTOCP_STATUS R/W 0h Boost Over-Current Status 0h = No Fault 1h = Fault 4 BSTOCP_CLEAR R/W 0h Boost Over-Current Fault Clear Write "1" to both Status bit and Clear bit at same time to clear interrupt register status and interrupt pin status. 3 VDDUVLO_STATUS R/W 0h VDD UVLO Status 0h = No Fault 1h = Fault 54 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 Table 23. INTERRUPT_STATUS_1 Register Field Descriptions (continued) Bit Field Type Reset Description 2 VDDUVLO_CLEAR R/W 0h VDD UVLO Fault Clear Write "1" to both Status bit and Clear bit at same time to clear interrupt register status and interrupt pin status. 1 TSD_STATUS R/W 0h Thermal Shutdown Status 0h = No Fault 1h = Fault 0 TSD_CLEAR R/W 0h Thermal Shutdown Fault Clear Write "1" to both Status bit and Clear bit at same time to clear interrupt register status and interrupt pin status. 8.6.1.11 INTERRUPT_STATUS_2 Register (Offset = 56h) [reset = 0h] INTERRUPT_STATUS_2 is shown in Figure 44 and described in Table 24. Return to Summary Table. Figure 44. INTERRUPT_STATUS_2 Register 15 LED5_FAULT R/W-0h 14 LED4_FAULT R/W-0h 13 LED3_FAULT R/W-0h 12 LED2_FAULT R/W-0h 11 LED1_FAULT R/W-0h 10 LED0_FAULT R/W-0h 9 OPEN_LED R/W-0h 8 SHORT_LED R/W-0h 7 LED_STATUS R/W-0h 6 LED_CLEAR R/W-0h 5 4 3 2 1 0 RESERVED R/W-0h Table 24. INTERRUPT_STATUS_2 Register Field Descriptions Bit Field Type Reset Description 15 LED5_FAULT R/W 0h LED5 Status 0h = No Fault 1h = Fault Status is cleared with LED_STATUS bit 14 LED4_FAULT R/W 0h LED4 Status 0h = No Fault 1h = Fault Status is cleared with LED_STATUS bit 13 LED3_FAULT R/W 0h LED3 Status 0h = No Fault 1h = Fault Status is cleared with LED_STATUS bit 12 LED2_FAULT R/W 0h LED2 Status 0h = No Fault 1h = Fault Status is cleared with LED_STATUS bit 11 LED1_FAULT R/W 0h LED1 Status 0h = No Fault 1h = Fault Status is cleared with LED_STATUS bit 10 LED0_FAULT R/W 0h LED0 Status 0h = No Fault 1h = Fault Status is cleared with LED_STATUS bit Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 55 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com Table 24. INTERRUPT_STATUS_2 Register Field Descriptions (continued) Bit 9 Field Type Reset Description OPEN_LED R/W 0h LED Open Status 0h = No Fault 1h = Fault Status is cleared with LED_STATUS bit 8 SHORT_LED R/W 0h LED Short Status 0h = No Fault 1h = Fault Status is cleared with LED_STATUS bit 7 LED_STATUS R/W 0h LED Open / Short Fault Status 0h = No Fault 1h = Fault 6 LED_CLEAR R/W 0h LED Open / Short Fault Clear Write "1" to both Status bit and Clear bit at same time to clear interrupt register status and interrupt pin status. 5-0 RESERVED R/W 0h These bits are reserved. 8.6.1.12 INTERRUPT_STATUS_3 Register (Offset = 58h) [reset = 0h] INTERRUPT_STATUS_3 is shown in Figure 45 and described in Table 25. Return to Summary Table. Figure 45. INTERRUPT_STATUS_3 Register 15 BSTSYNC_ST ATUS R/W-0h 14 BSTSYNC_CL EAR R/W-0h 13 12 VINOCP_STAT VINOCP_CLEA US R R/W-0h R/W-0h 11 CPCAP_STAT US R/W-0h 7 FSET_STATUS 6 FSET_CLEAR R/W-0h R/W-0h 5 INVSTRING_S TATUS R/W-0h 3 2 1 VINOVP_STAT VINOVP_CLEA VINUVP_STAT US R US R/W-0h R/W-0h R/W-0h 4 INVSTRING_C LEAR R/W-0h 10 CPCAP_CLEA R R/W-0h 9 CP_STATUS 8 CP_CLEAR R/W-0h R/W-0h 0 VINUVP_CLEA R R/W-0h Table 25. INTERRUPT_STATUS_3 Register Field Descriptions Bit Field Type Reset Description 15 BSTSYNC_STATUS R/W 0h Missing Boost Sync Fault Status 0h = No Fault 1h = Fault 14 BSTSYNC_CLEAR R/W 0h Missing Boost Sync Fault Clear Write "1" to both Status bit and Clear bit at same time to clear interrupt register status and interrupt pin status. 13 VINOCP_STATUS R/W 0h VIN Over-Current Fault Status 0h = No Fault 1h = Fault 12 VINOCP_CLEAR R/W 0h VIN Over-Current Fault Clear Write "1" to both Status bit and Clear bit at same time to clear interrupt register status and interrupt pin status. 11 CPCAP_STATUS R/W 0h Missing Charge Pump Capacitor Fault Status 0h = No Fault 1h = Fault 56 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 Table 25. INTERRUPT_STATUS_3 Register Field Descriptions (continued) Bit Field Type Reset Description 10 CPCAP_CLEAR R/W 0h Missing Charge Pump Capacitor Fault Clear Write "1" to both Status bit and Clear bit at same time to clear interrupt register status and interrupt pin status. 9 CP_STATUS R/W 0h Charge Pump Fault Status 0h = No Fault 1h = Fault 8 CP_CLEAR R/W 0h Charge Pump Fault Fault Clear Write "1" to both Status bit and Clear bit at same time to clear interrupt register status and interrupt pin status. 7 FSET_STATUS R/W 0h Missing Boost / PWM FSET Resistor Fault Status 0h = No Fault 1h = Fault 6 FSET_CLEAR R/W 0h Missing Boost / PWM FSET Resistor Fault Clear Write "1" to both Status bit and Clear bit at same time to clear interrupt register status and interrupt pin status. 5 INVSTRING_STATUS R/W 0h Invalid LED String Configuration Fault Status 0h = No Fault 1h = Fault 4 INVSTRING_CLEAR R/W 0h Invalid LED String Configuration Fault Clear Write "1" to both Status bit and Clear bit at same time to clear interrupt register status and interrupt pin status. 3 VINOVP_STATUS R/W 0h VIN Over-Voltage Fault Status 0h = No Fault 1h = Fault 2 VINOVP_CLEAR R/W 0h VIN Over-Voltage Fault Clear Write "1" to both Status bit and Clear bit at same time to clear interrupt register status and interrupt pin status. 1 VINUVP_STATUS R/W 0h VIN Under-Voltage Fault Status 0h = No Fault 1h = Fault 0 VINUVP_CLEAR R/W 0h VIN Under-Voltage Fault Clear Write "1" to both Status bit and Clear bit at same time to clear interrupt register status and interrupt pin status. 8.6.1.13 JUNCTION_TEMPERATURE Register (Offset = E8h) [reset = 100h] JUNCTION_TEMPERATURE is shown in Figure 46 and described in Table 26. Return to Summary Table. Figure 46. JUNCTION_TEMPERATURE Register 15 14 13 12 RESERVED 11 10 9 8 JUNCTION_TE MPERATURE R-100h 2 1 0 R-0h 7 6 5 Copyright © 2017–2018, Texas Instruments Incorporated 4 3 JUNCTION_TEMPERATURE R-100h Submit Documentation Feedback 57 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com Table 26. JUNCTION_TEMPERATURE Register Field Descriptions Field Type Reset Description 15-9 Bit RESERVED R 0h These bits are reserved. 8-0 JUNCTION_TEMPERATU R RE 100h Junction Temperature ADC Measurement 2's complement number. 000h - 0FFh = 0 °C to 255 °C 100h - 1FFh = –256 °C to –1 °C 8.6.1.14 TEMPERATURE_LIMIT_HIGH Register (Offset = ECh) [reset = 7Dh] TEMPERATURE_LIMIT_HIGH is shown in Figure 47 and described in Table 27. Return to Summary Table. Figure 47. TEMPERATURE_LIMIT_HIGH Register 15 14 13 12 RESERVED 11 10 9 8 TEMPERATUR E_LIMIT_HIGH R/W-7Dh 2 1 0 R-0h 7 6 5 4 3 TEMPERATURE_LIMIT_HIGH R/W-7Dh Table 27. TEMPERATURE_LIMIT_HIGH Register Field Descriptions Field Type Reset Description 15-9 Bit RESERVED R 0h These bits are reserved. 8-0 TEMPERATURE_LIMIT_ HIGH R/W 7Dh High Limit for Junction Temperature Monitor 2's complement number. 000h - 0FFh = 0 °C to 255 °C 100h - 1FFh = –256 °C to –1 °C 8.6.1.15 TEMPERATURE_LIMIT_LOW Register (Offset = EEh) [reset = 69h] TEMPERATURE_LIMIT_LOW is shown in Figure 48 and described in Table 28. Return to Summary Table. Figure 48. TEMPERATURE_LIMIT_LOW Register 15 14 13 7 6 5 12 RESERVED 11 10 9 8 TEMPERATUR E_LIMIT_LOW R/W-69h 2 1 0 R-0h 4 3 TEMPERATURE_LIMIT_LOW R/W-69h Table 28. TEMPERATURE_LIMIT_LOW Register Field Descriptions Bit Field Type Reset Description 15-9 RESERVED R 0h These bits are reserved. 8-0 TEMPERATURE_LIMIT_L R/W OW 69h Low Limit for Junction Temperature Monitor 2's complement number. 000h - 0FFh = 0 °C to 255 °C 100h - 1FFh = –256 °C to –1 °C 58 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 8.6.1.16 CLUSTER1_BRT Register (Offset = 13Ch) [reset = FFFFh] CLUSTER1_BRT is shown in Figure 49 and described in Table 29. Return to Summary Table. Figure 49. CLUSTER1_BRT Register 15 14 13 12 11 10 9 8 7 CLUSTER1_BRT R/W-FFFFh 6 5 4 3 2 1 0 Table 29. CLUSTER1_BRT Register Field Descriptions Bit 15-0 Field Type Reset Description CLUSTER1_BRT R/W FFFFh CLUSTER1 Brightness Control. This register controls LED output duty cycle for the LED outputs assigned to LED GROUP 1. This register is buffered, write LOAD_BRT_DB bit to update. 8.6.1.17 CLUSTER2_BRT Register (Offset = 148h) [reset = FFFFh] CLUSTER2_BRT is shown in Figure 50 and described in Table 30. Return to Summary Table. Figure 50. CLUSTER2_BRT Register 15 14 13 12 11 10 9 8 7 CLUSTER2_BRT R/W-FFFFh 6 5 4 3 2 1 0 Table 30. CLUSTER2_BRT Register Field Descriptions Bit 15-0 Field Type Reset Description CLUSTER2_BRT R/W FFFFh CLUSTER2 Brightness Control. This register controls LED output duty cycle for the LED outputs assigned to LED GROUP 2. This register is buffered, write LOAD_BRT_DB bit to update. 8.6.1.18 CLUSTER3_BRT Register (Offset = 154h) [reset = FFFFh] CLUSTER3_BRT is shown in Figure 51 and described in Table 31. Return to Summary Table. Figure 51. CLUSTER3_BRT Register 15 14 13 12 11 10 9 8 7 CLUSTER3_BRT R/W-FFFFh 6 5 4 3 2 1 0 Table 31. CLUSTER3_BRT Register Field Descriptions Bit 15-0 Field Type Reset Description CLUSTER3_BRT R/W FFFFh CLUSTER3 Brightness Control. This register controls LED output duty cycle for the LED outputs assigned to LED GROUP 3. This register is buffered, write LOAD_BRT_DB bit to update. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 59 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 8.6.1.19 CLUSTER4_BRT Register (Offset = 160h) [reset = FFFFh] CLUSTER4_BRT is shown in Figure 52 and described in Table 32. Return to Summary Table. Figure 52. CLUSTER4_BRT Register 15 14 13 12 11 10 9 8 7 CLUSTER4_BRT R/W-FFFFh 6 5 4 3 2 1 0 Table 32. CLUSTER4_BRT Register Field Descriptions Bit 15-0 Field Type Reset Description CLUSTER4_BRT R/W FFFFh CLUSTER4 Brightness Control. This register controls LED output duty cycle for the LED outputs assigned to LED GROUP 4. This register is buffered, write LOAD_BRT_DB bit to update. 8.6.1.20 CLUSTER5_BRT Register (Offset = 16Ch) [reset = FFFFh] CLUSTER5_BRT is shown in Figure 53 and described in Table 33. Return to Summary Table. Figure 53. CLUSTER5_BRT Register 15 14 13 12 11 10 9 8 7 CLUSTER5_BRT R/W-FFFFh 6 5 4 3 2 1 0 Table 33. CLUSTER5_BRT Register Field Descriptions Bit 15-0 Field Type Reset Description CLUSTER5_BRT R/W FFFFh CLUSTER5 Brightness Control. This register controls LED output duty cycle for the LED outputs assigned to LED GROUP 5. This register is buffered, write LOAD_BRT_DB bit to update. 8.6.1.21 BRT_DB_CONTROL Register (Offset = 178h) [reset = 0h] BRT_DB_CONTROL is shown in Figure 54 and described in Table 34. Return to Summary Table. Figure 54. BRT_DB_CONTROL Register 15 14 13 12 11 10 9 8 3 2 1 0 LOAD_BRT_D B R/W-0h RESERVED R/W-0h 7 6 5 4 RESERVED R/W-0h Table 34. BRT_DB_CONTROL Register Field Descriptions Bit 15-1 0 60 Field Type Reset Description RESERVED R/W 0h These bits are reserved. LOAD_BRT_DB R/W 0h Write this bit to "1" to update CLUSTERx_BRT registers and LEDx_CURRENT registers (those registers are buffered). Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 8.6.1.22 LED0_CURRENT Register (Offset = 1C2h) [reset = FFFh] LED0_CURRENT is shown in Figure 55 and described in Table 35. Return to Summary Table. Figure 55. LED0_CURRENT Register 15 LED0_SHORT_ DISABLE R/W-0h 14 7 6 13 RESERVED 12 11 10 9 LED0_CURRENT R/W-0h 8 R/W-FFFh 5 4 3 LED0_CURRENT R/W-FFFh 2 1 0 Table 35. LED0_CURRENT Register Field Descriptions Bit Field Type Reset Description 15 LED0_SHORT_DISABLE R/W 0h Short Fault Disable for LED0 0h = Short LED Faults are detected for LED0 output 1h = Short LED Faults are not detected for LED0 output 14-12 RESERVED R/W 0h 11-0 LED0_CURRENT R/W FFFh Individual LED Current control for LED0 Output 8.6.1.23 LED1_CURRENT Register (Offset = 1C4h) [reset = FFFh] LED1_CURRENT is shown in Figure 56 and described in Table 36. Return to Summary Table. Figure 56. LED1_CURRENT Register 15 LED1_SHORT_ DISABLE R/W-0h 14 7 6 13 RESERVED 12 11 10 9 LED1_CURRENT R/W-0h 8 R/W-FFFh 5 4 3 LED1_CURRENT R/W-FFFh 2 1 0 Table 36. LED1_CURRENT Register Field Descriptions Bit Field Type Reset Description 15 LED1_SHORT_DISABLE R/W 0h Short Fault Disable for LED1 0h = Short LED Faults are detected for LED1 output 1h = Short LED Faults are not detected for LED1 output 14-12 RESERVED R/W 0h 11-0 LED1_CURRENT R/W FFFh Individual LED Current control for LED1 Output 8.6.1.24 LED2_CURRENT Register (Offset = 1C6h) [reset = FFFh] LED2_CURRENT is shown in Figure 57 and described in Table 37. Return to Summary Table. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 61 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com Figure 57. LED2_CURRENT Register 15 LED2_SHORT_ DISABLE R/W-0h 14 7 6 13 RESERVED 12 11 10 9 LED2_CURRENT R/W-0h 8 R/W-FFFh 5 4 3 LED2_CURRENT R/W-FFFh 2 1 0 Table 37. LED2_CURRENT Register Field Descriptions Bit Field Type Reset Description 15 LED2_SHORT_DISABLE R/W 0h Short Fault Disable for LED2 0h = Short LED Faults are detected for LED2 output 1h = Short LED Faults are not detected for LED2 output 14-12 RESERVED R/W 0h 11-0 LED2_CURRENT R/W FFFh Individual LED Current control for LED2 Output 8.6.1.25 LED3_CURRENT Register (Offset = 1C8h) [reset = FFFh] LED3_CURRENT is shown in Figure 58 and described in Table 38. Return to Summary Table. Figure 58. LED3_CURRENT Register 15 LED3_SHORT_ DISABLE R/W-0h 14 7 6 13 RESERVED 12 11 10 9 LED3_CURRENT R/W-0h 8 R/W-FFFh 5 4 3 LED3_CURRENT R/W-FFFh 2 1 0 Table 38. LED3_CURRENT Register Field Descriptions Bit Field Type Reset Description 15 LED3_SHORT_DISABLE R/W 0h Short Fault Disable for LED3 0h = Short LED Faults are detected for LED3 output 1h = Short LED Faults are not detected for LED3 output 14-12 RESERVED R/W 0h 11-0 LED3_CURRENT R/W FFFh Individual LED Current control for LED3 Output 8.6.1.26 LED4_CURRENT Register (Offset = 1CAh) [reset = FFFh] LED4_CURRENT is shown in Figure 59 and described in Table 39. Return to Summary Table. Figure 59. LED4_CURRENT Register 15 LED4_SHORT_ DISABLE R/W-0h 14 7 6 62 13 RESERVED 12 11 10 9 LED4_CURRENT R/W-0h Submit Documentation Feedback 5 8 R/W-FFFh 4 3 LED4_CURRENT R/W-FFFh 2 1 0 Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 Table 39. LED4_CURRENT Register Field Descriptions Bit Field Type Reset Description 15 LED4_SHORT_DISABLE R/W 0h Short Fault Disable for LED4 0h = Short LED Faults are detected for LED4 output 1h = Short LED Faults are not detected for LED4 output 14-12 RESERVED R/W 0h 11-0 LED4_CURRENT R/W FFFh Individual LED Current control for LED4 Output 8.6.1.27 LED5_CURRENT Register (Offset = 1CCh) [reset = FFFh] LED5_CURRENT is shown in Figure 60 and described in Table 40. Return to Summary Table. Figure 60. LED5_CURRENT Register 15 LED5_SHORT_ DISABLE R/W-0h 14 7 6 13 RESERVED 12 11 10 9 LED5_CURRENT R/W-0h 8 R/W-FFFh 5 4 3 LED5_CURRENT R/W-FFFh 2 1 0 Table 40. LED5_CURRENT Register Field Descriptions Bit Field Type Reset Description 15 LED5_SHORT_DISABLE R/W 0h Short Fault Disable for LED5 0h = Short LED Faults are detected for LED5 output 1h = Short LED Faults are not detected for LED5 output 14-12 RESERVED R/W 0h 11-0 LED5_CURRENT R/W FFFh Individual LED Current control for LED5 Output 8.6.1.28 BOOST_CONTROL Register (Offset = 288h) [reset = 1C0h] BOOST_CONTROL is shown in Figure 61 and described in Table 41. Return to Summary Table. Figure 61. BOOST_CONTROL Register 15 7 14 6 13 12 LED_EXT_SUPPLY R/W-0h 5 11 10 9 8 RESERVED R/W-1C0h 4 3 2 1 0 RESERVED R/W-1C0h Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 63 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com Table 41. BOOST_CONTROL Register Field Descriptions Bit 15-10 Field Type Reset Description LED_EXT_SUPPLY R/W 0h Selects whether external LED voltage supply is used for a LED output. Bit 15 = LED5 Bit 14 = LED4 Bit 13 = LED3 Bit 12 = LED2 Bit 11 = LED1 Bit 10 = LED0 0h = LP8863 Boost Converter Supply is used 1h = External Supply is used. 9-0 RESERVED R/W 1C0h These bits are reserved. 8.6.1.29 SHORT_THRESH Register (Offset = 28Ah) [reset = 2882h] SHORT_THRESH is shown in Figure 62 and described in Table 42. Return to Summary Table. Figure 62. SHORT_THRESH Register 15 14 13 12 5 4 11 RESERVED R/W-2h 7 6 10 9 SHORTED_LED_THRESHOLD R/W-4h 3 2 1 8 RESERVED R/W-82h 0 RESERVED R/W-82h Table 42. SHORT_THRESH Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R/W 2h This bit is reserved. 11-9 SHORTED_LED_THRES HOLD R/W 4h Threshold for detecting Shorted LED Fault on LED outputs. Fault is detected when LEDx pin voltage (referenced to ground) exceeds selected threshold when LED driver is enabled. 0h = 2.6V 1h = 3.0V 2h = 3.4V 3h = 3.8V 4h = 4.2V 5h = 4.8V 6h = 5.2V 7h = 6.0V 8-0 RESERVED R/W 82h These bits are reserved. 8.6.1.30 FSM_DIAGNOSTICS Register (Offset = 2A4h) [reset = 0h] FSM_DIAGNOSTICS is shown in Figure 63 and described in Table 43. Return to Summary Table. Figure 63. FSM_DIAGNOSTICS Register 15 14 13 12 11 10 9 8 RESERVED R-0h 64 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 7 6 RESERVED R-0h 5 4 3 2 FSM_LIVE_STATUS R-0h 1 0 Table 43. FSM_DIAGNOSTICS Register Field Descriptions Field Type Reset Description 15-5 Bit RESERVED R 0h These bits are reserved. 4-0 FSM_LIVE_STATUS R 0h Current status of Device state machine. 1h = LDO_STARTUP 2h = EEPROM_READ 3h = STANDBY 4h - Ch = BOOST_START Dh = NORMAL Eh = DISCHARGE Fh = SHUTDOWN 10h = FAULT_RECOVERY 11h = ALL_LED_FAULT 8.6.1.31 PWM_INPUT_DIAGNOSTICS Register (Offset = 2A6h) [reset = 0h] PWM_INPUT_DIAGNOSTICS is shown in Figure 64 and described in Table 44. Return to Summary Table. Figure 64. PWM_INPUT_DIAGNOSTICS Register 15 14 13 12 11 10 9 8 7 6 PWM_INPUT_STATUS R-0h 5 4 3 2 1 0 1 0 Table 44. PWM_INPUT_DIAGNOSTICS Register Field Descriptions Bit 15-0 Field Type Reset Description PWM_INPUT_STATUS R 0h 16bit value for detected duty cycle of PWM input signal. 8.6.1.32 PWM_OUTPUT_DIAGNOSTICS Register (Offset = 2A8h) [reset = 0h] PWM_OUTPUT_DIAGNOSTICS is shown in Figure 65 and described in Table 45. Return to Summary Table. Figure 65. PWM_OUTPUT_DIAGNOSTICS Register 15 14 13 12 11 10 9 8 7 6 LED_PWM_STATUS R-0h 5 4 3 2 Table 45. PWM_OUTPUT_DIAGNOSTICS Register Field Descriptions Bit 15-0 Field Type Reset Description LED_PWM_STATUS R 0h 16-bit PWM Duty Code that Brightness path is driving to LED0 output. 8.6.1.33 LED_CURR_DIAGNOSTICS Register (Offset = 2AAh) [reset = 0h] LED_CURR_DIAGNOSTICS is shown in Figure 66 and described in Table 46. Return to Summary Table. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 65 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com Figure 66. LED_CURR_DIAGNOSTICS Register 15 14 13 12 11 RESERVED R-0h 7 6 5 10 9 LED_CURRENT_STATUS R-0h 4 3 LED_CURRENT_STATUS R-0h 2 8 1 0 Table 46. LED_CURR_DIAGNOSTICS Register Field Descriptions Field Type Reset Description 15-12 Bit RESERVED R 0h These bits are reserved. 11-0 LED_CURRENT_STATU S R 0h 12-bit Current DAC Code that Brightness path is driving to LED0 output. 8.6.1.34 ADAPT_BOOST_DIAGNOSTICS Register (Offset = 2ACh) [reset = 0h] ADAPT_BOOST_DIAGNOSTICS is shown in Figure 67 and described in Table 47. Return to Summary Table. Figure 67. ADAPT_BOOST_DIAGNOSTICS Register 15 14 13 RESERVED R-0h 7 6 5 12 11 10 9 VBOOST_STATUS R-0h 8 4 3 VBOOST_STATUS R-0h 2 1 0 Table 47. ADAPT_BOOST_DIAGNOSTICS Register Field Descriptions Bit Field Type Reset Description 15-11 RESERVED R 0h These bits are reserved. 10-0 VBOOST_STATUS R 0h 11-bit Boost Voltage Code that Adaptive Voltage Control Loop is sending to Analog Boost Block. Boost Output Voltage = ((R_FB1/R_FB2)*1.2)+(R_FB1*18.75nA*VBOOST_STATUS) 8.6.1.35 AUTO_DETECT_DIAGNOSTICS Register (Offset = 2AEh) [reset = 0h] AUTO_DETECT_DIAGNOSTICS is shown in Figure 68 and described in Table 48. Return to Summary Table. Figure 68. AUTO_DETECT_DIAGNOSTICS Register 15 14 13 12 RESERVED 11 10 9 3 2 1 AUTO_LED_STRING_CFG R-0h R-0h 7 6 AUTO_PWM_FREQ_SEL R-0h 66 Submit Documentation Feedback 5 4 AUTO_BOOST_FREQ_SEL R-0h 8 AUTO_PWM_F REQ_SEL R-0h 0 Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 Table 48. AUTO_DETECT_DIAGNOSTICS Register Field Descriptions Field Type Reset Description 15-9 Bit RESERVED R 0h These bits are reserved. 8-6 AUTO_PWM_FREQ_SEL R 0h PWM Frequency Setting based on PWM_FSET resistor detection. 0h = 152Hz 1h = 305Hz 2h = 610 Hz 3h = 1.22kHz 4h = 2.44kHz 5h = 4.88kHz 6h = 9.77kHz 7h = 19.53kHz 5-3 AUTO_BOOST_FREQ_S EL R 0h Boost Frequency Setting based on BST_FSET resistor detection. 0h = 303kHz 1h = 400kHz 2h = 606kHz 3h = 800kHz 4h = 1MHz 5h = 1.25 MHz 6h = 1.67MHz 7h = 2.2MHz 2-0 AUTO_LED_STRING_CF G R 0h Detected LED string configuration. 0h = 6 separate strings 1h = 5 separate strings 2h = 4 separate strings 3h = 3 separate strings 4h = 2 separate strings 5h = outputs connected in groups of 2 to drive 3 strings 6h = outputs connected in groups of 3 to drive 2 strings 7h = all outputs connected together to drive one string Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 67 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LP8863-Q1 device is designed for automotive applications, and an input voltage VIN is intended to be connected to the vehicle battery. Depending on the input voltage, the device may be used in either boost mode or SEPIC mode. The device is internally powered from the VDD pin, and voltage must be in 2.7-V to 5.5-V range. The device has flexible configurability through external components or by an SPI or I2C interface. If the VDD voltage is not high enough to drive an external nMOSFET gate, an internal charge pump must be used to power the gate driver (GD pin). NOTE For applications where VIN voltage is below the output voltage, use a boost converter topology. Maximum operating voltage for VIN is 48 V, and the boost converter can achieve output voltage up to 47 V. Conversion ratio of 5.5 (full load) or 10 (half load) must be taken into account. If VIN voltage is expected to be below or above output voltage, a SEPIC converter can be implemented. The SEPIC converter can achieve maximum output voltage up to 24 V, and maximum conversion ratio for SEPIC mode is 5. 9.2 Typical Applications 9.2.1 Full Feature Application for Display Backlight Figure 69 shows a full application for the LP8863-Q1 device in a boost topology. It supports 6 LED strings in display mode, each at 100 mA, with an automatic 60° phase shift. Brightness control register is used for LED dimming method through I2C communication. The charge pump is enabled for a 400-kHz boost switching frequency with spread spectrum. 68 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 Typical Applications (continued) Q2 RISENSE VIN C1N VOUT COUT CIN SD VSENSE_N CPUMP CPUMP VSENSE_P RSD CPUMP D1 L1 PGND C2x RFB1 Q1 GD GD ISNS RSENSE PGND RFB2 ISNSGND C1P VDD FB VDD CVDD CLDO DISCHARGE GND VLDO VDDIO LED0 LP8863-Q1 LED1 IFSEL LED2 HOST EN LED3 INT I2C SDO_PWM LED4 SDI_SDA LED5 SCLK_SCL ISET SS_ADDRSEL PWM_FSET BST_SYNC VDDIO RISET BST_FSET RPWM RBST Copyright © 2017, Texas Instruments Incorporated Figure 69. Full Feature Application for Display Backlight 9.2.1.1 Design Requirements This typical LED-driver application is designed to meet the parameters listed in Table 49: Table 49. LP8863-Q1 Full-Feature Design Parameters DESIGN PARAMETER VALUE VIN voltage range 3 V to 20 V VDD voltage 3.3 V LED strings configuration 6 strings, 7 LEDs in series Charge pump Enabled Brightness control I2C Output configuration LED0 to LED5 are in display mode (phase shift 60°) LED string current 100 mA Boost frequency 400 kHz Inductor 22 µH at 12-A saturation current RISENSE 20 mΩ Power-line FET Enabled RSENSE 20 mΩ Input/Output capacitors CIN and COUT: 2 × 33-µF electrolytic + 2 × 10-µF ceramic Spread spectrum Enabled Discharge function Enabled Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 69 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 9.2.1.2 Detailed Design Procedure 9.2.1.2.1 Inductor Selection There are a few things to consider when choosing an inductor: inductance, current rating, and DC resistance (DCR). Table 50 shows recommended inductor values for each operating frequency. The LP8863-Q1 device automatically sets internal boost compensation controls depending on the selected switching frequency. Table 50. Inductance Values for Boost Switching Frequencies SW FREQUENCY (kHz) INDUCTANCE (µH) 300 22 400 22 600 15 800 15 1000 10 1250 10 1667 10 2200 10 The current rating of inductor must be at least 25% higher than maximum boost switching current ISW(max), which can be calculated with Equation 12. TI recommends a current rating of 12 A for most applications; use an inductor with low DCR to achieve good efficiency. Efficiency varies with load condition, switching frequency, and components, but 80% can be use as safe estimation. Power Stage Designer™ Tools can be used for the boost calculation: http://www.ti.com/tool/powerstage-designer IOUT(max) 'IL ISW(max) + 2 1- D where • • • • • • • • • • • ΔIL = VIN(min) × D / ( ƒSW × L ) D = 1 – VIN(min) × η / VOUT ISW(max): Maximum switching current ΔIL: Inductor ripple current IOUT(max): Maximum output current D: Boost duty cycle VIN(min): Minimum input voltage ƒSW: Minimum switching frequency of the converter L: Inductance VOUT: Output voltage η: Efficiency of boost converter (12) 9.2.1.2.2 Output Capacitor Selection Recommended voltage rating for output capacitors is 50% higher than maximum output voltage level — 100-V voltage rating is recommended. Capacitance value determines voltage ripple and boost stability. The DC-bias effect can reduce the effective capacitance significantly, by up to 80%, a consideration for capacitance value selection. Effective capacitance must be at least 50 µF for full load/maximum conversion ratio applications and must be used to achieve good phase and gain margin levels. TI recommends using two 33-µF Al-polymer electrolytic capacitors and two 10-µF ceramic capacitors in parallel to reduce ripple, increase stability, and reduce ESR effect. 9.2.1.2.3 Input Capacitor Selection Recommended input capacitance is the same as output capacitance although input capacitors are not as critical to boost operation. Input capacitance can be reduced but must ensure enough filtering for input power. 70 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 9.2.1.2.4 Charge Pump Output Capacitor TI recommends a ceramic capacitor with at least 16-V voltage rating for the output capacitor of the charge pump. A 10-μF capacitor can be used for most applications. 9.2.1.2.5 Charge Pump Flying Capacitor TI recommends a ceramic capacitor with at least 16-V voltage rating for the flying capacitor of the charge pump. One 2.2-μF capacitor connecting C1P and C1N pins can be used for most applications. 9.2.1.2.6 Output Diode A Schottky diode must be used for the boost output diode. Current rating must be at least 25% higher than the maximum output current; TI recommends a 12-A current rating for most applications. Schottky diodes with a low forward drop and fast switching speeds are ideal for increasing efficiency. At maximum current, the forward voltage must be as low as possible; less than 0.5 V is recommended. Reverse breakdown voltage of the Schottky diode must be significantly larger than the output voltage, 25% higher voltage rating is recommended. Do not use ordinary rectifier diodes, because slow switching speeds and long recovery times cause efficiency and load regulation to suffer. 9.2.1.2.7 Switching FET Gate-drive voltage for the FET is VDD with charge pump bypassed, or about double VDD, if the charge pump is enabled. Switching FET is a critical component for determining power efficiency of the boost converter. Several aspects need to be considered when selecting switching FET such as voltage and current rating, RDSON, power dissipation, thermal resistance and rise/fall times. An N type MOSFET with at least 25% higher voltage rating than maximum output voltage must be used. Current rating of switching FET should be same or higher than inductor rating. RDSON must be as low as possible, less than 20 mΩ is recommended. Thermal resistance (RθJA) must also be low to dissipate heat from power loss on switching FET. TI recommends typical rise/fall time values less than 10 ns. 9.2.1.2.8 Boost Sense Resistor The RSENSE resistor determines the boost overcurrent limit and is sensed every boost switching cycle. A highpower 20-mΩ resistor can be used for sensing the boost SW current and setting maximum current limit at 10 A (typical). RSENSE can be increased to lower this limit and can be calculated with Equation 13, but this should be done carefully because it may also affect stability. Boost overcurrent limit must not be set below 4 A, therefore RSENSE must not exceed 50 mΩ. Power rating can be calculated from the inductor current and sense resistor resistance value. 200 mV RSENSE IBOOST _ OCP where • • RSENSE: boost sense resistor (mΩ) IBOOST_OCP: boost overcurrent limit (13) 9.2.1.2.9 Power-Line FET A power line FET can be used to disconnect input power from boost input to protect the LP8863-Q1 device and boost components in case an overcurrent event occurs. A P type MOSFET is used for the power-line FET. Voltage rating must be at least 25% higher than maximum input voltage level. Low RDSON is important to reduce power loss on the FET — less than 20 mΩ is recommended. Current rating for the FET must be at least 25% higher than input peak current. Gate-to-source voltage (VGS) for open transistor must be less than minimum input voltage; use a 20-kΩ resistor between the pFET gate and source. 9.2.1.2.10 Input Current Sense Resistor A high-power resistor can be used for sensing the boost input current. Overcurrent condition is detected when the voltage across RISENSE reaches 220 mV. Typical 20 mΩ sense resistor is used to set 11-A input current limit. Sense resistor value can be increased to lower overcurrent limit for application as needed. Power rating can be calculated from the input current and resistance value. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 71 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 9.2.1.2.11 Feedback Resistor Divider Feedback resistors RFB1 and RFB2 determine the maximum boost output level. Output voltage can be calculated as in Equation 14: · § V VOUT_ MAX = ¨ BG + ISEL_MAX ¸ u RFB1 + VBG © RFB2 ¹ where • • • VBG = 1.21 V ISEL_MAX = 38.7 µA RFB2 = 100 kΩ (recommended for boost mode) (14) 9.2.1.2.12 Critical Components for Design Figure 70 shows the critical part of circuitry: boost components, the LP8863-Q1 internal charge pump for gatedriver powering, and powering/grounding of LP8863-Q1. Schematic example is shown in Figure 70. Q2 RISENSE VIN C1N C2x VOUT COUT CIN SD CPUMP CPUMP VSENSE_P CPUMP VSENSE_N RSD D1 L1 RFB1 Q1 GD GD ISNS PGND RSENSE PGND RFB2 ISNSGND C1P VDD FB VDD CVDD CLDO DISCHARGE GND VLDO VDDIO LP8863-Q1 LED0 LED1 IFSEL LED2 HOST EN INT I2C SDO_PWM LED4 SDI_SDA LED5 SCLK_SCL SS_ADDRSEL BST_SYNC VDDIO LED3 ISET PWM_FSET BST_FSET RISET RPWM RBST Copyright © 2017, Texas Instruments Incorporated Figure 70. Critical Components for Full Feature Design 72 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 Table 51. Recommended Component Values for Full Feature Design Example REFERENCE DESIGNATOR DESCRIPTION NOTE RISENSE 20 mΩ, 3 W Input current sensing resistor RSD 20 kΩ, 0.1 W Power-line FET gate pullup resistor RSENSE 20 mΩ, 3 W Boost current sensing resistor RFB2 100 kΩ, 0.1 W Bottom feedback divider resistor RFB1 910 kΩ, 0.1 W Top feedback divider resistor RBST 4.77 kΩ, 0.1 W Boost frequency set resistor RISET 31.2 kΩ, 0.1 W Current set resistor for 100 mA maximum Output PWM frequency set resistor RPWM 42.2 kΩ, 0.1 W CPUMP 10-µF, 16-V ceramic Charge-pump output capacitor C2X 2.2-µF, 25-V ceramic Flying capacitor CVDD 4.7-µF + 0.1-µF, 10-V ceramic VDD bypass capacitor CLDO 4.7-µF + 0.1-µF, 10-V ceramic VLDO bypass capacitor CIN 2 × 33-µF, 63-V electrolytic + 2 × 10-µF, 100-V ceramic Boost input capacitor COUT 2 × 33-µF, 63-V electrolytic + 2 × 10-µF, 100-V ceramic Boost output capacitor L1 22-μH saturation current 23 A D1 100 V, 10-A Schottky diode Boost inductor Q1 60-V, 25-A nMOSFET Boost nMOSFET Q2 60-V, 30-A pMOSFET Power-line FET Boost Schottky diode 9.2.1.3 Application Curves FLED_PWM = 300 Hz Phase Shift 60° 6 Strings Figure 71. LED String Currents Showing Phase Shift PWM Operation Copyright © 2017–2018, Texas Instruments Incorporated ƒSW = 400 kHz 100 mA/String CIN = COUT = 2 × 33 μF (electrolytic) + 2 × 10 μF (ceramic) Figure 72. Typical Start-Up Submit Documentation Feedback 73 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 9.2.2 Application With Basic/Minimal Operation The LP8863-Q1 needs only a few external components for basic functionality if material cost and PCB area for a solution need to be minimized. In this example LP8863-Q1 is configured with external components and no I2C or SPI communication. The power-line FET is removed, as is input current sensing. Internal charge pump is not used, and all external synchronization functions and special features are disabled. Only 5 LED strings are enabled. D1 L1 VIN VOUT COUT C1N SD CPUMP CPUMP VSENSE_P CPUMP VSENSE_N CIN PGND RSENSE PGND C1P ISNSGND VDD FB DISCHARGE RFB1 Q1 GD GD ISNS RFB2 RFB3 VDD CVDD CLDO GND VLDO VDDIO LP8863-Q1 LED0 LED1 IFSEL LED2 EN INT SDO_PWM SDI_SDA SCLK_SCL SS_ADDRSEL BST_SYNC LED3 LED4 LED5 ISET PWM_FSET BST_FSET RISET RPWM RBST Copyright © 2017, Texas Instruments Incorporated Figure 73. Minimal Solution/Minimum Components Application 74 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 9.2.2.1 Design Requirements This typical LED-driver application is designed to meet the parameters listed in Table 52: Table 52. LP8863-Q1 Minimal Solution Design Parameters DESIGN PARAMETER VALUE VIN voltage range 5 V to 30 V VDD voltage 5 V (note: 5 V required when charge pump disabled.) LED strings configuration 5 strings, 10 LEDs in series 3-resistor feedback network RFB1 = 100 kΩ, RFB2 = 6 kΩ , RFB3 = 27 kΩ (maximum output voltage set to 43.5 V) Charge pump Disabled Brightness control PWM input Output configuration LED0 to LED4 are in display mode (phase shift 72°); LED5 is not used (GND) LED string current 150 mA Boost frequency 300 kHz Inductor 22 µH at 12-A saturation current Power-line FET Disabled RSENSE 20 mΩ Power-line FET Enabled RSENSE 20 mΩ Input/Output capacitors CIN and COUT: 2 × 33-µF electrolytic + 2 × 10-µF ceramic Spread spectrum Disabled Discharge function Disabled 9.2.2.2 Detailed Design Procedure See Detailed Design Procedure 9.2.2.3 Application Curves See Application Curves Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 75 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 9.2.3 SEPIC Mode Application When LED string voltage can be above and below the input voltage level, use the SEPIC configuration. In SEPIC mode, the SW pin detects a maximum voltage equal to the sum of the input and output voltages, a consideration when selecting components. This fact limits the maximum output voltage to 24 V. External frequency can be used to synchronize boost or SEPIC switching frequency through the BST_SYNC pin. CS2 Q2 RISENSE VIN RSD RS D1 L1 VOUT CIN COUT CS1 C1N C2x SD CPUMP CPUMP VSENSE_P CPUMP VSENSE_N L2 RFB1 Q1 GD GD ISNS PGND RSENSE PGND RFB2 ISNSGND C1P VDD FB VDD CVDD CLDO DISCHARGE GND VLDO VDDIO LP8863-Q1 LED0 LED1 IFSEL LED2 HOST EN INT SPI LED3 SDO_PWM LED4 SDI_SDA LED5 SCLK_SCL SS_ADDRSEL ISET PWM_FSET BST_SYNC BST_FSET RISET RPWM RBST Copyright © 2017, Texas Instruments Incorporated Figure 74. SEPIC Mode with Three LEDs in Series 76 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 9.2.3.1 Design Requirements This typical LED-driver application is designed to meet the parameters listed in Table 53: Table 53. LP8863-Q1 SEPIC Mode Design Parameters DESIGN PARAMETER VALUE VIN voltage range 3 V to 48 V VDD voltage 3.3 V LED strings configuration 6 strings, 3 LEDs in series Charge pump Enabled Brightness control SPI Output configuration LED0 to LED5 are in display mode (phase shift 60°) LED string current 150 mA BST_SYNC external signal frequency 2.2 MHz (Note: BST_SYNC frequency must be 0.2 to 0.5% higher than frequency set by BST_FSET resistor.) BST_FSET resistor 42.2 kΩ (sets boost frequency to 1.6 MHz) Inductor 10 µH at 12-A saturation current RISENSE 20 mΩ Power-line FET Enabled RSENSE 20 mΩ Input/Output capacitors CIN and COUT: 2 × 33-µF electrolytic + 2 × 10-µF ceramic Spread spectrum Disabled Discharge function Enabled Boost synchronization Enabled . 9.2.3.2 Detailed Design Procedure 9.2.3.2.1 Inductor Selection Inductance for both inductors can be selected from Table 54, depending on operating frequency for the application. Current rating is recommended to be at least 25% higher than maximum inductor peak current. Peak-to-peak ripple current can be estimated to be approximately 40% of the maximum input current and and inductor peak current can be calculated with Equation 15, Equation 16, and Equation 17: Table 54. Inductance Values for SEPIC Switching Frequencies SW FREQUENCY (kHz) INDUCTANCE (µH) 300 15 400 15 600 10 800 10 1000 6.8 1250 6.8 1667 4.7 2200 4.7 Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 77 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 IL1(peak) = IOUT u www.ti.com VOUT VD 40% · § u ¨1 + VIN(min) 2 ¹¸ © where • • • • • IL1(peak): Peak current for inductor 1 IOUT: Maximum output current VOUT: Output voltage VD: Diode forward voltage drop VIN(min): Minimum input voltage (15) 40% · § IL2(peak) = IOUT u ¨ 1 + 2 ¹¸ © where • • IL2(peak): Peak current for inductor 2 IOUT: Maximum output current 'IL = IIN u 40% = IOUT (16) VOUT u u 40% VIN(min) where • • • • ΔIL: Inductor ripple current IIN: Input current VOUT: Output voltage VIN(min): Minimum input voltage (17) 9.2.3.2.2 Coupling Capacitor Selection The coupling capacitors Cs isolate the input from the output and provide protection against a shorted load. The selection of SEPIC capacitors, Cs, depends mostly on the RMS current, which can be calculated with Equation 18. The capacitors must be rated for a large RMS current relative to the output power; TI recommends at least 25% higher rating for IRMS. When using uncoupled inductors, use one 10-µF ceramic capacitor in parallel with one 33-µF electrolytic capacitor and series 2-Ω resistor. If coupled inductors are used, then use only one 10µF ceramic capacitor. ICs(rms) = IOUT u VOUT VD VIN(min) where • • • • • ICs(rms): RMS current of Cs capacitor IOUT: Output current VOUT: Output voltage VD: Diode forward voltage drop VIN(min): Minimum input voltage (18) 9.2.3.2.3 Output Capacitor Selection See Detailed Design Procedure 9.2.3.2.4 Input Capacitor Selection See Detailed Design Procedure 9.2.3.2.5 Charge Pump Output Capacitor See Detailed Design Procedure 9.2.3.2.6 Charge Pump Flying Capacitor See Detailed Design Procedure 78 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 9.2.3.2.7 Switching FET Gate-drive voltage for the FET is VDD or about 2 × VDD, if the charge pump is enabled. Use an N-type MOSFET for the switching FET. The switching FET for SEPIC mode sees a maximum voltage of VIN(max) + VOUT, 25% higher rating is recommended. Current rating is also recommended to be 25% higher than peak current, which can be calculated with Equation 19. RDSON must be as low as possible — less than 20 mΩ is recommended. Thermal resistance (RθJA) must also be low to dissipate heat from power loss on switching FET. Typical rise/fall time values recommended are less than 10 ns. IQ1(peak) = IL1(peak) IL2(peak) where • • • IQ1(peak): Peak current for switching FET IL1(peak): Peak current for inductor 1 IIL2(peak): : Peak current for inductor 2 BOOST_OCP (19) 9.2.3.2.8 Output Diode A Schottky diode must be used for the SEPIC output diode. Current rating must be at least 25% higher than the maximum current, which is the same as switch peak current. Schottky diodes with a low forward drop and fast switching speeds are ideal for increasing efficiency. At maximum current, the forward voltage must be as low as possible; TI recommends less than 0.5 V. Reverse breakdown voltage of the Schottky diode must be able to withstand VIN(max) + VOUT(max); at least 25% higher voltage rating is recommended. Do not use ordinary rectifier diodes, because slow switching speeds and long recovery times cause efficiency and load regulation to suffer. 9.2.3.2.9 Switching Sense Resistor See Detailed Design Procedure 9.2.3.2.10 Power-Line FET See Detailed Design Procedure 9.2.3.2.11 Input Current Sense Resistor See Detailed Design Procedure 9.2.3.2.12 Feedback Resistor Divider Feedback resistors RFB1 and RFB2 determine the maximum boost output level. Output voltage can be calculated as follows: · §V VOUT _ MAX = ¨ BG + ISEL_MAX ¸ u RFB1 + VBG © RFB2 ¹ where • • • VBG = 1.21 V ISEL_MAX = 38.7 µA RFB2 = 170 kΩ (recommended for SEPIC Mode) (20) 9.2.3.2.13 Critical Components for Design Figure 75 shows the critical part of circuitry: SEPIC components, the LP8863-Q1 internal charge pump for gatedriver powering, and powering/grounding of LP8863-Q1. Schematic example is shown in Figure 70. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 79 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com CS2 Q2 RISENSE VIN RS D1 L1 RSD VOUT CIN COUT CS1 C1N RFB1 SD CPUMP CPUMP VSENSE_N CPUMP VSENSE_P L2 Q1 GD GD ISNS PGND C2x RSENSE PGND RFB2 ISNSGND C1P VDD FB VDD CVDD CLDO DISCHARGE GND VLDO LP8863-Q1 VDDIO LED0 LED1 IFSEL LED2 HOST EN LED3 INT SDO_PWM LED4 SDI_SDA LED5 SCLK_SCL SS_ADDRSEL SPI ISET PWM_FSET BST_SYNC RISET RPWM BST_FSET RBST Copyright © 2017, Texas Instruments Incorporated Figure 75. Critical Components for SEPIC Mode Design Table 55. Recommended Components for SEPIC Design Example 80 REFERENCE DESIGNATOR DESCRIPTION RISENSE 20 mΩ, 3 W Input current sensing resistor NOTE RSD 20 kΩ, 0.1 W Power-line FET gate pullup resistor RSENSE 20 mΩ, 3 W SEPIC current sensing resistor RFB2 170 kΩ, 0.1 W Bottom feedback divider resistor RFB1 560 kΩ, 0.1 W Top feedback divider resistor RBST 140 kΩ, 0.1 W SEPIC frequency set resistor RISET 20.5 kΩ, 0.1 W Current set resistor for 150 mA max RPWM 140 kΩ, 0.1 W Output PWM frequency set resistor CPUMP 10-µF, 16-V ceramic Charge pump output capacitor Flying capacitor C2x 2.2-µF, 25-V ceramic CVDD 4.7-µF + 0.1-µF, 10-V ceramic VDD bypass capacitor CLDO 10-µF + 0.1-µF, 10-V ceramic VLDO bypass capacitor CIN 2 × 33-µF, 63-V electrolytic SEPIC input capacitor COUT 2 × 33-µF, 63-V electrolytic SEPIC output capacitor CS1 10-µF, 100-V ceramic SEPIC coupling capacitor CS2 33-µF, 63-V electrolytic SEPIC coupling capacitor RS 2 Ω, 0.125 W SEPIC resistor L1 10-µH saturation current 15.5 A SEPIC inductor L2 10-µH saturation current 15.5 A SEPIC inductor D1 100-V 10-A Schottky diode Q1 60-V, 25-A nMOSFET SEPIC nMOSFET Q2 60-V, 30-A pMOSFET Power-line FET Submit Documentation Feedback SEPIC Schottky diode Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 9.2.3.3 Application Curves See Application Curves 10 Power Supply Recommendations The LP8863-Q1 is designed to operate from a car battery. The VIN input must be protected from reverse voltage and voltage dump condition over 48 V. The impedance of the input supply rail must be low enough that the input current transient does not cause drop below VIN UVLO level. If the input supply is connected with long wires, additional bulk capacitance may be required in addition to normal input capacitor. The voltage range for VDD is 3 V to 5.5 V. A ceramic capacitor must be placed as close as possible to the VDD pin. The boost gate driver is powered from the CPUMP pins. A ceramic capacitor must be placed as close to the CPUMP pins as possible. Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 81 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 11 Layout 11.1 Layout Guidelines Figure 76 shows a layout recommendation for the LP8863-Q1 used to illustrate the principles of good layout. This layout can be adapted to the actual application layout if and where possible. It is important that all boost components are close to each other and to the chip; the high-current traces must be wide enough. VDD must be as noise-free as possible. Place a VDD bypass capacitor near the VDD and GND pins and ground it to a lownoise ground. A charge-pump capacitor, boost input capacitors, and boost output capacitors must be connected to PGND. Place the charge-pump capacitors close to the device. The main points to guide the PCB layout design: • Current loops need to be minimized: – For low frequency the minimal current loop can be achieved by placing the boost components as close as possible to each other. Input and output capacitor grounds need to be close to each other to minimize current loop size. – Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact under the current traces. High frequency return currents follow the route with minimum impedance, which is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when return current flows just under the positive current route in the ground plane, if the ground plane is intact under the route. – For high frequency the copper area capacitance must be taken into account. For example, the copper area for the drain of boost nMOSFET is a tradeoff between capacitance and the cooling capacity of the components. • GND plane must be intact under the high-current-boost traces to provide shortest possible return path and smallest possible current loops for high frequencies. • Current loops when the boost switch is conducting and not conducting must be in the same direction in optimal case. • Inductors must be placed so that the current flows in the same direction as in the current loops. Rotating the inductor 180° changes current direction. • Use separate power and noise-free grounds. PGND is used for boost converter return current. Use a lownoise ground for more sensitive signals, like VDD bypass capacitor grounding as well as grounding the GND pins of the LP8863-Q1 device itself. • Route boost output voltage (VOUT) to LEDs from output capacitors not straight from the diode cathode. • A small bypass capacitor (TI recommends a 39-pF capacitor) must be placed close to the FB pin to suppress high frequency noise • VDD line must be separated from the high current supply path to the boost converter to prevent high frequency ripple affecting the chip behavior. A separate 1-µF bypass capacitor is used for the VDD pin, and it is grounded to noise-free ground. • Capacitor connected to charge pump output CPUMP must have 10-µF capacitance, grounded by the shortest way to boost a switch-current-sensing resistor. This capacitor must be as close as possible to CPUMP pin. This capacitor provides a greater peak current for gate driver and must be used even if the charge pump is disabled. If the charge pump is disabled, the VDD and CPUMP pins must be tied together. • Input and output capacitors need low-impedence grounding (wide traces with many vias to PGND plane). • If two or more output capacitors are used, symmetrical layout must be used to get all capacitors working ideally. • Input/output ceramic capacitors have DC-bias effect. If the output capacitance is too low, it can cause boost to become unstable under certain load conditions. DC bias characteristics should be obtained from the component manufacturer; DC bias is not taken into account on component tolerance. TI recommends X5R/X7R capacitors. 82 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LP8863-Q1 www.ti.com SNVSAB6B – MARCH 2017 – REVISED JULY 2018 11.2 Layout Example Figure 76. LP8863-Q1 Layout Guidelines Copyright © 2017–2018, Texas Instruments Incorporated Submit Documentation Feedback 83 LP8863-Q1 SNVSAB6B – MARCH 2017 – REVISED JULY 2018 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 84 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LP8863ADCPRQ1 ACTIVE HTSSOP DCP 38 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 LP8863AQ1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of