Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
LPV321-N, LPV324-N, LPV358-N
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
LPV321-N Single, LPV358-N Dual, and LPV324-N Quad General-Purpose, Low Voltage,
Low Power, Rail-to-Rail Output Operational Amplifiers
1 Features
3 Description
•
•
•
The LPV3xx-N are low power (9-µA per channel at
5 V) versions of the LMV3xx op amps. This is another
addition to the LMV family of commodity op amps.
1
•
•
•
•
•
Specified 2.7-V and 5-V Performance
No Crossover Distortion
Space-Saving Package
– 5-Pin SC70 2 × 2.1 × 1 mm
Industrial Temperature Range: −40°C to 85°C
Gain-Bandwidth Product: 152 kHz
Low Supply Current
– LPV321-N: 9 µA
– LPV358-N: 15 µA
– LPV324-N: 28 µA
Rail-to-Rail Output Swing at 100 kΩ Load:
– V+ − 3.5 mV
– V− + 90 mV
VCM, −0.2 V to V+− 0.8 V
2 Applications
•
•
•
Active Filters
General-Purpose Low Voltage Applications
General-Purpose Portable Devices
The LPV3xx-N are the most cost effective solutions
for the applications where low voltage, low power
operation, space saving and low price are needed.
The LPV3xx-N have rail-to-rail output swing capability
and the input common-mode voltage range includes
ground. They all exhibit excellent speed-power ratio,
achieving 152 kHz of bandwidth with a supply current
of only 9 µA.
The LPV321-N is available in space saving 5-Pin
SC70, which is approximately half the size of 5-Pin
SOT-23. The small package saves space on PC
boards, and enables the design of small portable
electronic devices. It also allows the designer to place
the device closer to the signal source to reduce noise
pickup and increase signal integrity.
The chips are built with Texas Instruments's
advanced submicron silicon-gate BiCMOS process.
The LPV3xx-N have bipolar input and output stages
for improved noise performance and higher output
current drive.
Device Information(1)
PART NUMBER
LPV321-N
LPV358-N
LPV324-N
PACKAGE
BODY SIZE (NOM)
SC70 (5)
2.00 mm × 1.25 mm
SOT-23 (5)
2.90 mm × 1.60 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Micropower Supply Current
Rail-to-Rail Output Swing
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LPV321-N, LPV324-N, LPV358-N
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
DC Electrical Characteristics – 2.7 V........................
AC Electrical Characteristics – 2.7 V ........................
DC Electrical Characteristics – 5 V...........................
AC Electrical Characteristics – 5 V ...........................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1 Overview ................................................................ 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 14
8
Application and Implementation ........................ 16
8.1 Application Information .......................................... 16
8.2 Typical Applications ................................................ 16
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2013) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Deleted Soldering temperature (235°C maximum)................................................................................................................. 4
•
Changed Thermal Resistance, RθJA, values From: 478 To: 296.7 (SC70), From: 265 To: 206.6 (SOT-23), From: 190
To: 130.1 (8-Pin SOIC), From: 235 To: 187.5 (VSSOP), From: 145 To: 103.9 (14-Pin SOIC), From: 155 To: 132.7
(TSSOP) ................................................................................................................................................................................. 4
Changes from Revision C (March 2013) to Revision D
•
2
Page
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1
Submit Documentation Feedback
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
LPV321-N, LPV324-N, LPV358-N
www.ti.com
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
5 Pin Configuration and Functions
DBV or DCK Package
5-Pin SC70 or SOT-23
Top View
IN+
1
V-
2
IN-
3
D or DGK Package
8-Pin SOIC or VSSOP
Top View
5
V+
4
OUT
D or PW Package
14-Pin SOIC or TSSOP
Top View
OUT A
1
8
V+
-IN A
2
7
+IN A
3
V-
4
OUT A
1
14
OUT D
OUT B
-IN A
2
13
-IN D
6
-IN B
+IN A
3
12
+IN D
5
+IN B
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
Pin Functions
PIN
SC70 or
SOT-23
SOIC or
VSSOP
SOIC or
TSSOP
TYPE (1)
+IN
1
—
—
I
Noninverting input
IN A+
—
3
3
I
Noninverting input, channel A
IN B+
—
5
5
I
Noninverting input, channel B
IN C+
—
—
10
I
Noninverting input, channel C
IN D+
—
—
12
I
Noninverting input, channel D
–IN
3
—
—
I
Inverting input
IN A–
—
2
2
I
Inverting input, channel A
IN B–
—
6
6
I
Inverting input, channel B
IN C–
—
—
9
I
Inverting input, channel C
IN D–
—
—
13
I
Inverting input, channel D
OUTPUT
4
—
—
O
Output
OUT A
—
1
1
O
Output, channel A
OUT B
—
7
7
O
Output, channel B
OUT C
—
—
8
O
Output, channel C
OUT D
—
—
14
O
Output, channel D
V+
5
8
4
P
Positive (highest) power supply
V–
2
4
11
P
Negative (lowest) power supply
NAME
(1)
DESCRIPTION
I = Input, O = Output, P = Power
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
Submit Documentation Feedback
3
LPV321-N, LPV324-N, LPV358-N
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Differential input voltage
MAX
Supply voltage (V+– V −)
Output short circuit to V +
(2)
(3)
(4)
V
150
°C
150
°C
See (3)
(4)
Storage temperature, Tstg
(1)
5.5
See (2)
Output short circuit to V −
Junction temperature, TJ(MAX)
UNIT
±Supply voltage
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Shorting output to V+ will adversely affect reliability.
Shorting output to V− will adversely affect reliability.
The maximum power dissipation is a function of TJ(MAX) and RθJA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
6.2 ESD Ratings
VALUE
UNIT
LPV321-N in DBV and DCK Packages
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1500
Machine model
±100
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1500
Machine model
±100
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Machine model
±100
V
LPV358-N in D and DGK Packages
V(ESD)
Electrostatic discharge
V
LPV324-N in D and PW Packages
V(ESD)
(1)
Electrostatic discharge
V
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Supply voltage
2.7
5
V
Operating temperature
–40
85
°C
6.4 Thermal Information
LPV321-N
THERMAL METRIC
(1)
LPV358-N
LPV324-N
DBV
(SOT-23)
DCK
(SC70)
DGK
(VSSOP)
D
(SOIC)
D
(SOIC)
PW
(TSSOP)
5 PINS
5 PINS
8 PINS
8 PINS
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
206.6
296.7
187.5
130.1
103.9
132.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
167.2
128.1
77.7
74.3
61.6
59.1
°C/W
RθJB
Junction-to-board thermal resistance
65.5
74.3
108
70.7
58.4
75.1
°C/W
ψJT
Junction-to-top characterization parameter
50.2
6.5
15.2
23.1
21.2
10.8
°C/W
ψJB
Junction-to-board characterization parameter
65.1
73.6
106.5
70.2
58.1
74.58
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
—
—
—
—
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
LPV321-N, LPV324-N, LPV358-N
www.ti.com
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
6.5 DC Electrical Characteristics – 2.7 V
TJ = 25°C, V+ = 2.7 V, V− = 0 V, VCM = 1 V, VO = V+/2, and R L > 1 MΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
MAX (1)
1.2
7
UNIT
VOS
Input offset voltage
TCVOS
Input offset voltage average drift
IB
Input bias current
1.7
50
nA
IOS
Input offset current
0.6
40
nA
CMRR
Common mode rejection ratio
0 V ≤ VCM ≤ 1.7 V
50
70
dB
PSRR
Power supply rejection ratio
2.7 V ≤ V+ ≤ 5 V, VO = 1 V, VCM = 1 V
50
65
dB
0
−0.2
VCM
Input common-mode voltage
For CMRR ≥ 50 dB
VO
Output swing
RL = 100 kΩ to 1.35 V
IS
Supply current
µV/°C
1.9
V+ − 100
V
1.7
V+ − 3
80
mV
180
LPV321-N
4
8
LPV358-N, both amplifiers
8
16
16
24
LPV324-N, all four amplifiers
(1)
(2)
mV
2
µA
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
6.6 AC Electrical Characteristics – 2.7 V
TJ = 25°C, V+ = 2.7 V, V− = 0 V, VCM = 1 V, VO = V+/2, and R L > 1 MΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
UNIT
GBWP
Gain-bandwidth product
Φm
Phase margin
Gm
Gain margin
35
dB
en
Input-referred voltage noise
f = 1 kHz
178
nV/√Hz
in
Input-referred current noise
f = 1 kHz
0.5
pA/√Hz
(1)
(2)
CL = 22 pF
MAX (1)
112
kHz
97
°
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
6.7 DC Electrical Characteristics – 5 V
TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = 2 V, VO = V+/2, and R L > 1 MΩ (unless otherwise noted)
PARAMETER
VOS
Input offset voltage
TCVOS
Input offset voltage average
drift
IB
Input bias current
IOS
Input offset current
CMRR
Common mode rejection
ratio
PSRR
(1)
(2)
Power supply rejection ratio
TEST CONDITIONS
MIN (1)
TJ = 25°C
TYP (2)
MAX (1)
1.5
7
TJ = –40°C to 85°C
10
2
TJ = 25°C
2
TJ = –40°C to 85°C
0.6
TJ = –40°C to 85°C
0 V ≤ VCM ≤ 4 V
+
2.7 V ≤ V ≤ 5 V, VO = 1 V, VCM = 1 V
mV
µV/°C
50
60
TJ = 25°C
UNIT
40
50
nA
nA
50
71
dB
50
65
dB
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
Submit Documentation Feedback
5
LPV321-N, LPV324-N, LPV358-N
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
www.ti.com
DC Electrical Characteristics – 5 V (continued)
TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = 2 V, VO = V+/2, and R L > 1 MΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCM
Input common-mode voltage
For CMRR ≥ 50 dB
AV
Large signal voltage gain (3)
RL = 100 kΩ
VO
Output short circuit current
sourcing
IO
Output short circuit current
sinking
(3)
Supply current
0
−0.2
TJ = 25°C
15
TJ = –40°C to 85°C
10
TJ = 25°C
Sinking
RL = 100 kΩ to 2.5 V
TJ = 25°C
MAX (1)
V+ −100
90
180
mV
220
16
LPV321-N, VO = 5 V
20
60
11
16
LPV324-N and LPV358-N, VO = 5 V
TJ = 25°C
9
TJ = –40°C to 85°C
TJ = 25°C
V/mV
V −200
2
LPV324-N,
All four amplifiers
V
V+ −3.5
TJ = –40°C to 85°C
TJ = 25°C
UNIT
+
TJ = –40°C to 85°C
LPV358-N,
Both amplifiers
4
100
LPV3xx-N, VO = 0 V
LPV321-N
IS
TYP (2)
4.2
Sourcing
RL = 100 kΩ to 2.5 V
Output swing
MIN (1)
mA
12
15
15
TJ = –40°C to 85°C
20
24
28
TJ = –40°C to 85°C
µA
42
46
-
RL is connected to V . The output voltage is 0.5 V ≤ VO ≤ 4.5 V.
6.8 AC Electrical Characteristics – 5 V
TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = 2 V, VO = V+/2, and R L > 1MΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN (1)
(3)
TYP (2)
MAX (1)
UNIT
SR
Slew rate
GBWP
Gain-bandwidth product
Φm
Phase margin
Gm
Gain margin
19
dB
en
Input-referred voltage noise
f = 1 kHz
146
nV/√Hz
in
Input-referred current noise
f = 1 kHz
0.3
pA/√Hz
(1)
(2)
(3)
6
CL = 22 pF
0.1
V/µs
152
kHz
87
°
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Connected as voltage follower with 3V step input. Number specified is the slower of the positive and negative slew rates.
Submit Documentation Feedback
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
LPV321-N, LPV324-N, LPV358-N
www.ti.com
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
6.9 Typical Characteristics
VS = 5 V, single supply, and TA = 25°C (unless otherwise noted)
Figure 1. Supply Current vs Supply Voltage (LPV321-N)
Figure 2. Input Current vs Temperature
Figure 3. Sourcing Current vs Output Voltage
Figure 4. Sourcing Current vs Output Voltage
Figure 5. Sinking Current vs Output Voltage
Figure 6. Sinking Current vs Output Voltage
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
Submit Documentation Feedback
7
LPV321-N, LPV324-N, LPV358-N
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
www.ti.com
Typical Characteristics (continued)
VS = 5 V, single supply, and TA = 25°C (unless otherwise noted)
Figure 7. Output Voltage Swing vs Supply Voltage
Figure 8. Input Voltage Noise vs Frequency
8
Figure 9. Input Current Noise vs Frequency
Figure 10. Input Current Noise vs Frequency
Figure 11. Crosstalk Rejection vs Frequency
Figure 12. PSRR vs Frequency
Submit Documentation Feedback
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
LPV321-N, LPV324-N, LPV358-N
www.ti.com
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
Typical Characteristics (continued)
VS = 5 V, single supply, and TA = 25°C (unless otherwise noted)
Figure 13. CMRR vs Frequency
Figure 14. CMRR vs Input Common Mode Voltage
Figure 15. CMRR vs Input Common Mode Voltage
Figure 16. ΔVOS vs VCM
Figure 17. ΔVOS vs VCM
Figure 18. Input Voltage vs Output Voltage
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
Submit Documentation Feedback
9
LPV321-N, LPV324-N, LPV358-N
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
www.ti.com
Typical Characteristics (continued)
VS = 5 V, single supply, and TA = 25°C (unless otherwise noted)
10
Figure 19. Input Voltage vs Output Voltage
Figure 20. Open-Loop Frequency Response
Figure 21. Open-Loop Frequency Response
Figure 22. Gain and Phase vs Capacitive Load
Figure 23. Gain and Phase vs Capacitive Load
Figure 24. Slew Rate vs Supply Voltage
Submit Documentation Feedback
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
LPV321-N, LPV324-N, LPV358-N
www.ti.com
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
Typical Characteristics (continued)
VS = 5 V, single supply, and TA = 25°C (unless otherwise noted)
Figure 25. Noninverting Large Signal Pulse Response
Figure 26. Noninverting Small Signal Pulse Response
Figure 27. Inverting Large Signal Pulse Response
Figure 28. Inverting Small Signal Pulse Response
Figure 29. Stability vs Capacitive Load
Figure 30. Stability vs Capacitive Load
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
Submit Documentation Feedback
11
LPV321-N, LPV324-N, LPV358-N
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
www.ti.com
Typical Characteristics (continued)
VS = 5 V, single supply, and TA = 25°C (unless otherwise noted)
12
Figure 31. Stability vs Capacitive Load
Figure 32. Stability vs Capacitive Load
Figure 33. THD vs Frequency
Figure 34. Open-Loop Output Impedance vs Frequency
Figure 35. Short Circuit Current vs Temperature (Sinking)
Figure 36. Short Circuit Current vs Temperature (Sourcing)
Submit Documentation Feedback
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
LPV321-N, LPV324-N, LPV358-N
www.ti.com
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
7 Detailed Description
7.1 Overview
The LPV321-N, LPV358-N, and LPV324-N devices are micropower (10-µA) versions of the popular LMV3xx-N.
The LPV321-N is the single-channel version. The LPV358-N is the dual, and the LPV324-N is the quad. The
LPV32x-N are the most cost effective solution for applications where low power and low voltage operation, space
efficiency, and low-price are important. The LPV3x-N have rail-to-rail output swing capability and the input
common-mode voltage range includes ground. They all exhibit excellent speed to power ratio, achieving 152 kHz
of bandwidth and 0.1-V/µs slew rate with 10 mA of supply current.
7.2 Functional Block Diagram
V
IN –
IN +
+
_
OUT
+
V
–
Copyright © 2016,
Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Size
The small footprints of the LPV3xx-N packages save space on printed circuit boards, and enable the design of
smaller electronic products (such as cellular phones, pagers, or other portable systems). The low profile of the
LPV3xx-N make them possible to use in PCMCIA type III cards.
7.3.2 Signal Integrity
Signals can pick up noise between the signal source and the amplifier. By using a physically smaller amplifier
package, the LPV3xx-N can be placed closer to the signal source, reducing noise pickup and increasing signal
integrity.
7.3.3 Simplified Board Layout
These products help avoid using long printed-circuit traces in the PCB. This means no additional components,
such as capacitors and resistors, are needed to filter out unwanted signals due to the interference between the
long printed-circuit traces.
7.3.4 Low Supply Current
These devices help maximize battery life. They are ideal for battery powered systems.
7.3.5 Low Supply Voltage
TI provides ensured performance at 2.7 V and 5 V. These specifications ensure operation throughout the battery
lifetime.
7.3.6 Rail-to-Rail Output
Rail-to-rail output swing provides maximum possible dynamic range at the output. This is particularly important
when operating on low-supply voltages.
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
Submit Documentation Feedback
13
LPV321-N, LPV324-N, LPV358-N
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
www.ti.com
Feature Description (continued)
7.3.7 Input Includes Ground
Allows direct sensing near GND in single supply operation.
The differential input voltage may be larger than V+ without damaging the device. Protection should be provided
to prevent the input voltages from going negative more than −0.3 V (at 25°C). An input clamp diode with a
resistor to the IC input terminal can be used.
7.4 Device Functional Modes
The LPV3xx-N can be operated as a single-supply or a dual-supply operational amplifier depending on the
application.
7.4.1 Capacitive Load Tolerance
The LPV3xx-N can directly drive 200 pF in unity-gain without oscillation. The unity-gain follower is the most
sensitive configuration to capacitive loading. Direct capacitive loading reduces the phase margin of amplifiers.
The combination of the amplifier's output impedance and the capacitive load induces phase lag. This results in
either an underdamped pulse response or oscillation. To drive a heavier capacitive load, circuit in Figure 37 can
be used.
Figure 37. Indirectly Driving A Capacitive Load Using Resistive Isolation
In Figure 37, the isolation resistor (RISO) and the load capacitor (CL) form a pole to increase stability by adding
more phase margin to the overall system. The desired performance depends on the value of RISO. The bigger the
RISO resistor value, the more stable VOUT is. Figure 38 is an output waveform of Figure 37 using 100 kΩ for RISO
and 1000 pF for CL.
Figure 38. Pulse Response of the LPV324 Circuit in Figure 37
14
Submit Documentation Feedback
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
LPV321-N, LPV324-N, LPV358-N
www.ti.com
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
Device Functional Modes (continued)
The circuit in Figure 39 is an improvement to the one in Figure 37 because it provides DC accuracy as well as
AC stability. If there were a load resistor in Figure 37, the output would be voltage divided by RISO and the load
resistor. Instead, in Figure 39, RF provides the DC accuracy by using feed-forward techniques to connect VIN to
RL. Caution is needed in choosing the value of RF due to the input bias current of the LPV3xx-N. CF and RISO
serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back
to the amplifier's inverting input, thereby preserving phase margin in the overall feedback loop. Increased
capacitive drive is possible by increasing the value of CF. This in turn slows down the pulse response.
Figure 39. Indirectly Driving A Capacitive Load With DC Accuracy
7.4.2
Input Bias Current Cancellation
The LPV3xx-N family has a bipolar input stage. The typical input bias current of LPV3xx-N is 1.5 nA with 5-V
supply. Thus a 100-kΩ input resistor causes 0.15 mV of error voltage. By balancing the resistor values at both
inverting and noninverting inputs, the error caused by the amplifier's input bias current is reduced. The circuit in
Figure 40 shows how to cancel the error caused by input bias current.
Figure 40. Cancelling the Error Caused by Input Bias Current
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
Submit Documentation Feedback
15
LPV321-N, LPV324-N, LPV358-N
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LPV3xx-N family of amplifiers is specified for operation from 2.7 V to 5 V (±1.35 V to ±2.5 V). Many of the
specifications apply from –40°C to 125°C. They provide ground-sensing inputs as well as rail-to-rail output swing.
Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in
the Typical Characteristics.
8.2 Typical Applications
8.2.1 Simple Low-Pass Active Filter
A simple low-pass filter is shown in Figure 41.
Figure 41. Simple Low-Pass Active Filter Schematic
8.2.1.1 Design Requirements
The low-pass filter is shown in Figure 41 passes low frequencies and attenuate frequencies above corner
frequency (fc) at a roll-off rate of 20 dB/Decade.
8.2.1.2 Detailed Design Procedure
The low-frequency gain (ω → o) is defined by −R3/R1. This allows low-frequency gains other than unity to be
obtained. The filter has a −20 dB/decade roll-off after its corner frequency fc. R2 must be chosen equal to the
parallel combination of R1 and R3 to minimize errors due to bais current. The frequency response of the filter is
shown in Figure 42.
R3
AL
R1
16
fc
1
2SR3C1
R2
R1 II R3
Submit Documentation Feedback
(1)
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
LPV321-N, LPV324-N, LPV358-N
www.ti.com
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
Typical Applications (continued)
Note that the single op amp active filters are used in to the applications that require low quality factor, Q (≤ 10),
low frequency (≤ 5 kHz), and low gain (≤ 10), or a small value for the product of gain times Q (≤ 100). The op
amp must have an open loop voltage gain at the highest frequency of interest at least 50 times larger than the
gain of the filter at this frequency. In addition, the selected op amp must have a slew rate that meets the
requirements in Equation 2.
Slew Rate ≥ 0.5 × (ωHV OPP) × 10−6V/µsec
where
•
•
ωH is the highest frequency of interest
VOPP is the output peak-to-peak voltage
(2)
8.2.1.3 Application Curve
Figure 42. Frequency Response of Simple Low-pass Active Filter
8.2.2 Difference Amplifier
The difference amplifier allows the subtraction of two voltages or, as a special case, the cancellation of a signal
common to two inputs. It is useful as a computational amplifier in making a differential to single-ended conversion
or in rejecting a common mode signal.
Figure 43. Difference Amplifier Schematic
R2
§ R1 R2 · R4
§ R1 R2 · R3 V
¨ R3 R4 ¸ R1 V2 R1 V1 ¨ R3 R4 ¸ R1 u 2
©
¹
©
¹
for R1 R3 and R2 R4
VOUT
VOUT
R2
V2
R1
V1
V
2
(3)
8.2.3 Instrumentation Circuits
The input impedance of the previous difference amplifier is set by the resistor R1, R2, R3, and R4. To eliminate
the problems of low input impedance, one way is to use a voltage follower ahead of each input as shown in the
following two instrumentation amplifiers.
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
Submit Documentation Feedback
17
LPV321-N, LPV324-N, LPV358-N
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
www.ti.com
Typical Applications (continued)
8.2.3.1 Three Operating Amplifier Instrumentation
The quad LPV324 can be used to build a three-op-amp instrumentation amplifier as shown in Figure 44
Figure 44. Three-op-amp Instrumentation Amplifier Schematic
The first stage of this instrumentation amplifier is a differential-input, differential-output amplifier, with two voltage
followers. These two voltage followers assure that the input impedance is over 100 MΩ. The gain of this
instrumentation amplifier is set by the ratio of R2/R1. R3 should equal R1 and R4 equal R2. Matching of R3 to R1
and R4 to R2 affects the CMRR. For good CMRR over temperature, low drift resistors should be used. Making R4
Slightly smaller than R 2 and adding a trim pot equal to twice the difference between R 2 and R4 will allow the
CMRR to be adjusted for optimum.
8.2.3.2
Two Operating Amplifier Instrumentation
A two-op-amp instrumentation amplifier can also be used to make a high-input-impedance DC differential
amplifier (Figure 45). As in the three-op-amp circuit, this instrumentation amplifier requires precise resistor
matching for good CMRR. R4 should equal to R1 and R3 must equal R2.
Figure 45. Two-op-amp Instrumentation Amplifier Schematic
§ R4 ·
¨ 1 R3 ¸ V2 V1 ,where R1 R4 and R2 R3
©
¹
As shown : VO 2 V2 V1
VO
(4)
8.2.3.3 Single-Supply Inverting Amplifier
There may be cases where the input signal going into the amplifier is negative. Because the amplifier is
operating in single supply voltage, a voltage divider using R3 and R4 is implemented to bias the amplifier so the
input signal is within the input common-common voltage range of the amplifier. The capacitor C1 is placed
between the inverting input and resistor R1 to block the DC signal going into the AC signal source, VIN. The
values of R1 and C1 affect the cutoff frequency in Equation 5.
fc = 1/2π R 1C1
18
Submit Documentation Feedback
(5)
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
LPV321-N, LPV324-N, LPV358-N
www.ti.com
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
Typical Applications (continued)
As a result, the output signal is centered around mid-supply (if the voltage divider provides V+/2 at the noninverting input). The output can swing to both rails, maximizing the signal-to-noise ratio in a low voltage system.
Figure 46. Single-Supply Inverting Amplifier
VOUT
R2
VIN
R1
(6)
9 Power Supply Recommendations
The LPV3xx-N is specified for operation from 2.7 V to 5.5 V; many specifications apply from –40°C to 125°C.
Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in
the Typical Characteristics.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, see Layout Guidelines
section.
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
Submit Documentation Feedback
19
LPV321-N, LPV324-N, LPV358-N
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
www.ti.com
10 Layout
10.1 Layout Guidelines
For best operational performance, use good PCB layout practices including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational
amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power
sources local to the analog circuitry.
• Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply
applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, see
Circuit Board Layout Techniques (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Figure 47.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
Figure 47. Operational Amplifier Board Layout for Noninverting Configuration
20
Submit Documentation Feedback
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
LPV321-N, LPV324-N, LPV358-N
www.ti.com
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
• LPV321-N PSPICE Model (SNOM026)
• LPV358-N PSPICE Model (SNOM022)
• LPV324-N PSPICE Model (SNOM027)
• TINA-TI SPICE-Based Analog Simulation Program
• DIP Adapter Evaluation Module
• TI Universal Operational Amplifier Evaluation Module
• TI Filterpro Software
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Handbook of Operational Amplifier Applications (SBOA092)
• Compensate Transimpedance Amplifiers Intuitively (SBOA055)
• Circuit Board Layout Techniques (SLOA089)
• AN-1803 Design Considerations for a Transimpedance Amplifier (SNOA515)
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LPV321-N
Click here
Click here
Click here
Click here
Click here
LPV324-N
Click here
Click here
Click here
Click here
Click here
LPV358-N
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
Submit Documentation Feedback
21
LPV321-N, LPV324-N, LPV358-N
SNOS413E – AUGUST 2000 – REVISED NOVEMBER 2016
www.ti.com
11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
Submit Documentation Feedback
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: LPV321-N LPV324-N LPV358-N
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LPV321M5/NOPB
ACTIVE
SOT-23
DBV
5
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
A27A
LPV321M5X/NOPB
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
A27A
LPV321M7
NRND
SC70
DCK
5
1000
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
-40 to 85
A19
LPV321M7/NOPB
ACTIVE
SC70
DCK
5
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
A19
LPV321M7X/NOPB
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
A19
LPV324M/NOPB
ACTIVE
SOIC
D
14
55
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LPV324M
LPV324MT/NOPB
ACTIVE
TSSOP
PW
14
94
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LPV324
MT
LPV324MTX
NRND
TSSOP
PW
14
2500
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
-40 to 85
LPV324
MT
LPV324MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LPV324
MT
LPV324MX
NRND
SOIC
D
14
2500
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
-40 to 85
LPV324M
LPV324MX/NOPB
ACTIVE
SOIC
D
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LPV324M
LPV358M/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
LPV358MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
P358
LPV358MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
P358
LPV358MX
NRND
SOIC
D
8
2500
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
-40 to 85
LPV
358M
LPV358MX/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LPV
358M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
LPV
358M
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
