LVDS-18B-EVK

18-Bit SerDes Evaluation Kit USER MANUAL Part Number: LVDS-18B-EVK January 2007 Rev 0.3 National Semiconductor Corporation Interface Applications Group 18-Bit SerDes Evaluation Board User Manual 18-Bit SerDes Evaluation Kit User Manual TABLE OF CONTENTS 18-Bit SerDes Evaluation Kit ......................................................................................................................... 1 USER MANUAL ............................................................................................................................................. 1 1.0 Overview .......................................................................................................................................... 3 1.0 Overview .......................................................................................................................................... 3 2.0 Evaluation Kit Contents.................................................................................................................... 3 3.0 Board Description............................................................................................................................. 3 3.1 Traces ............................................................................................................................................... 5 3.2 Board Stack up ................................................................................................................................. 5 3.3 Power and Ground Rails................................................................................................................... 5 4.0 Test Configuration Examples with Typical Results ......................................................................... 6 4.1 Configuration 1 – Evaluating the SCAN921821 .............................................................................. 6 4.2 Configuration 2 – Evaluating the DS92LV18 .................................................................................. 7 4.3 Configuration 3 – Evaluating the SCAN921821 with the DS92LV18 Receiver .............................. 8 5.0 18-Bit SerDes Evaluation Board Schematic ................................................................................... 11 5.1 18-Bit SerDes Evaluation Board Schematic (cont.) ....................................................................... 12 5.2 18-Bit SerDes Evaluation Board Schematic (cont.) ....................................................................... 13 5.3 18-Bit SerDes Evaluation Board Schematic (cont.) ....................................................................... 14 6.0 Bill of Materials:............................................................................................................................. 15 6.1 Bill of Materials: (cont.) ................................................................................................................. 16 Page 2 of 16 18-Bit SerDes Evaluation Kit User Manual 1.0 Overview The LVDS-18B-EVK is a complete kit for evaluation of National Semiconductor’s 18-bit SerDes devices (DS92LV18 and SCAN921821) with low cost twisted pair cables as well as other 100ohm differential cables. The purpose of this document is to: familiarize you with the 18-Bit SerDes Evaluation Kit, suggest the test setup procedures and instrumentation, and to guide you through some typical measurements that will demonstrate the performance of the devices in typical applications. 2.0 Evaluation Kit Contents • 18-Bit SerDes Evaluation Board – The board features a single SCAN921821 and two DS92LV18 devices. • EVK User Manual (this document) • EBLA 3.0 Board Description The Figure 1 below represents the top drawing of the board with the silkscreen annotations. It is a large 5 x 10 inch PCB that has a three-device layout capable of demonstrating the cable driving performance, control, and testability functions of the SCAN921821 and DS92LV18 devices. Page 3 of 16 18-Bit SerDes Evaluation Kit User Manual Figure 1: LVDS-18B-EVK Evaluation Board Top View Page 4 of 16 18-Bit SerDes Evaluation Kit User Manual 3.1 Traces All LVDS inputs and outputs have been designed to maintain 100 ohms differential impedance from the SMA connector to the device inputs and outputs. A taper is used to minimize any discontinuity associated with the reduced trace separation near the device inputs. The traces have been routed for equal length between pairs. The SCNA921821 input traces are 50 ohm single-ended. They have been routed to +/-250mils in length. The DS92LV18 LVCMOS input and output traces have been designed as 60-ohm single-ended impedance. This impedance value is common in actual systems and is the result of using the same strip-line or micro-strip width as a 100-ohm differential pair. Without any coupling to an adjacent signal the single-ended impedance rises to about 60 ohms. For DS92LV18 designs, transmission line impedance should have a target range of 60-65 ohms. 3.2 Board Stack up Figure 2 is a detailed drawing of the board cross-section showing the layers and layer spacing. Figure 2: Board Stack up Detail 3.3 Power and Ground Rails There are 3 separate VDD and Ground rails in the board stack up. The 3.3V VDD rail is used to supply power to the SCAN921821. A separate supply plane called VDD2 (also 3.3V) is used to supply power to the DS92LV18’s on the board. The GND planes for both supply voltages are common across the board. Page 5 of 16 18-Bit SerDes Evaluation Kit User Manual 4.0 Test Configuration Examples with Typical Results This section provides a quick reference for setting up some typical test configurations using the LVDS-18B-EVK that will enable you to evaluate the SCAN921821 and DS92LV18 as a standalone devices as well as a SerDes chipset in cable drive applications. 4.1 Configuration 1 – Evaluating the SCAN921821 The LVDS-18B-EVK can be used to evaluate the SCAN921821 as a standalone transmitter. In this case, a BERT receiver or an oscilloscope may be used to evaluate the transmitter output signals. Figure 3 is a simplified block diagram of the configuration. Figure 3. Test Setup for the SCAN921821 Only You may follow these steps to set up the device for bench testing and performance measurements: 1. Provide 3.3 V between the U9 (VDD) and U8 (GND) banana jack receptacles. This will bring power to the SCAN921821 device only. 2. Power-up channel A or B of the device by setting the corresponding PWDN pin to high. This is accomplished by placing a jumper across VDD and PWDN pins on the connector CON6 for channel A, or CON7 for channel B. 3. Enable the outputs of channel A or B by setting the corresponding EN pin to high. This is accomplished by placing a jumper across VDD and EN pins on the connector CON6 for channel A, or CON7 for channel B. 4. Select pre-emphasis levels for the outputs of channel A or B by setting the corresponding PEM pins to high or low. This is accomplished by placing jumpers across VDD and PEM pins on the connector CON3 for channel A, or CON4 for channel B. As a reminder, the pre-emphasis has the lowest level when all three PEM pins are set to low, and it has the highest level when all three pins are set to high. 5. Disable PRBS generation of the outputs by placing jumpers across BIST and GND pins on the connector CON5. 6. Provide a 15-66 MHz TTL clock to the TXCLK pin (pin#40 of the connector CON1) from a signal generator. 7. Provide 18 bit TTL data signals to the transmitter inputs (DIN0-DIN17). For channels A and B of the device, the inputs are accessible through the connectors, CON1 and CON2, respectively. All data signals should be in phase and synchronous to the TXCLK. 8. Connect the outputs, DO+ and DO- (SMA1 and SMA2 for the channel A, and SMA3 and SMA4 for the channel B outputs) directly to an oscilloscope or a serial BERT receiver using coaxial cables. You may also use probes to sense the output signals, but first Page 6 of 16 18-Bit SerDes Evaluation Kit User Manual make sure that the device has proper termination (usually 100 ohms between the output pins). The differential probes (>3GHz, 3GHz, 3GHz, 3GHz,