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OPA2132U/2K5G4

OPA2132U/2K5G4

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOIC8_150MIL

  • 描述:

    General Purpose Amplifier 2 Circuit 8-SOIC

  • 数据手册
  • 价格&库存
OPA2132U/2K5G4 数据手册
Product Folder Sample & Buy Support & Community Tools & Software Technical Documents OPA132, OPA2132, OPA4132 SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 OPAx132 High-Speed FET-Input Operational Amplifiers 1 Features 3 Description • • • • • • • • • The OPAx132 series of FET-input operational amplifiers provides highspeed and excellent DC performance. The combination of high slew rate and wide bandwidth provide fast settling time. Single, dual, and quad versions have identical specifications for maximum design flexibility. High performance grades are available in the single and dual versions. All are ideal for general-purpose, audio, data acquisition and communications applications, especially where high source impedance is encountered. 1 FET input: IB = 50 pA Maximum Wide Bandwidth: 8 MHz High Slew Rate: 20 V/µs Low Noise: 8nV/√Hz (1 kHz) Low Distortion: 0.00008%) High Open-loop Gain: 130 dB (600-Ω load) Wide Supply Range: ±2.5 to ±18V Low Offset Voltage: 500 µV Maximum Single, Dual, and Quad Versions The OPAx132 operational amplifiers are easy to use and free from phase inversion and overload problems often found in common FET-input operational amplifiers. Input cascode circuitry provides excellent common-mode rejection and maintains low input bias current over its wide input voltage range. The OPAx132 series of operational amplifiers are stable in unity gain and provide excellent dynamic behavior over a wide range of load conditions, including high load capacitance. Dual and quad versions feature completely independent circuitry for lowest crosstalk and freedom from interaction, even when overdriven or overloaded. 2 Applications • • • • • • SAR ADC Driver Voltage Reference Buffer Trans-impedance Amplifier Photodiode Amplifier Active Filters Integrators Low Noise JFET Input Current Noise (fA/√Hz) Voltage Noise (nV/√Hz) 1k Single and dual versions are available in 8-pin DIP and SO-8 surface-mount packages. Quad is available in 14-pin DIP and SO-14 surface-mount packages. All are specified for –40°C to 85°C operation 100 Voltage Noise Device Information(1) PART NUMBER 10 OPAx132 Current Noise 1 OPA2132 1 10 100 1k Frequency (Hz) 10k 100k 1M OPA4132 PACKAGE BODY SIZE (NOM) PDIP (8) (P) 9.81 mm × 6.35 mm SOIC (8) (D) 4.90 mm × 3.91 mm PDIP (8) (P) 9.81 mm × 6.35 mm SOIC (8) (D) 4.90 mm × 3.91 mm PDIP (14) (N) 19.30 mm × 6.35 mm SOIC (14) (D) 8.65 mm × 3.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. OPA132, OPA2132, OPA4132 SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 4 4 4 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 10 10 10 8 Application and Implementation ........................ 11 8.1 Application Information............................................ 11 8.2 Typical Application ................................................. 12 9 Power Supply Recommendations...................... 14 10 Layout................................................................... 14 10.1 Layout Guidelines ................................................. 14 10.2 Layout Example .................................................... 15 11 Device and Documentation Support ................. 16 11.1 11.2 11.3 11.4 11.5 11.6 Device Support .................................................... Documentation Support ........................................ Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 16 16 16 16 17 17 12 Mechanical, Packaging, and Orderable Information ........................................................... 17 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (June 2004) to Revision B • 2 Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 Submit Documentation Feedback Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: OPA132 OPA2132 OPA4132 OPA132, OPA2132, OPA4132 www.ti.com SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 5 Pin Configuration and Functions OPA132: P and D Packages 8-Pin PDIP and 8-Pin SOIC Top View 1 Offset Trim Out A Offset Trim 8 2 –In OPA2132: P and D Packages 8-Pin PDIP and 8-Pin SOIC Top View –In A V+ 7 +In 3 6 Output V– 4 5 NC 1 A 2 +In A 3 V– 4 B 8 V+ 7 Out B 6 –In B 5 +In B 8-Pin DIP, SO-8 8-Pin DIP, SO-8 OPA4132: P and D Packages 14-Pin PDIP and 14-Pin SOIC Top View Out A 1 –In A 2 A 14 Out D 13 –In D D +In A 3 12 +In D V+ 4 11 V– +In B 5 10 +In C B C –In B 6 9 –In C Out B 7 8 Out C 14-Pin DIP SO-14 Pin Functions OPA132 PIN NAME I/O NO. DESCRIPTION Offset Trim 1 I Input offset voltage adjust –In 2 I Inverting input +In 3 I Noninverting input V– 4 — Negative power supply NC 5 — No internal connection. Can be left floating. Output 6 O Output V+ 7 — Positive power supply Offset Trim 8 I Input offset voltage adjust Pin Functions OPA2132 and OPA4132 PIN NAME OPA2132 NO. OPA4132 NO. I/O DESCRIPTION Out A 1 1 O Output channel A –In A 2 2 I Inverting input channel A +In A 3 3 I Noninverting input channel A V+ 8 4 — +In B 5 5 I Noninverting input channel B –In B 6 6 I Inverting input channel B Out B 7 7 O Output channel B Out C – 8 O Output channel C –In C – 9 I Inverting input channel C Positive power supply Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: OPA132 OPA2132 OPA4132 Submit Documentation Feedback 3 OPA132, OPA2132, OPA4132 SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 www.ti.com Pin Functions OPA2132 and OPA4132 (continued) PIN I/O DESCRIPTION NAME OPA2132 NO. OPA4132 NO. +In C – 10 I V– 4 11 — +In D – 12 I Noninverting input channel D –In D – 13 I Inverting input channel D Out D – 14 O Output channel D Noninverting input channel C Negative power supply 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT 36 V (V+) +0.7 V Supply voltage, V+ to V– Input voltage Output short-circuit (V–) –0.7 (2) Continuous Operation temperature –40 Junction temperature Tstg (1) (2) Storage temperature –55 125 °C 150 °C 125 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Short-circuit to ground, one amplifier per package. 6.2 ESD Ratings VALUE UNIT Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 V Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±200 OPA132 in PDIP and SOIC Package, OPA2132 and OPA4132 in PDIP Package V(ESD) Electrostatic discharge OPA2132 in SOIC Package V(ESD) Electrostatic discharge V OPA4132 in SOIC Package V(ESD) (1) (2) Electrostatic discharge V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX ±15 ±18 V 85 °C VS Supply voltage, VS = (V+) – (V–) ±2.5 TA Specified temperature range –40 4 Submit Documentation Feedback UNIT Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: OPA132 OPA2132 OPA4132 OPA132, OPA2132, OPA4132 www.ti.com SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 6.4 Electrical Characteristics At TA = 25°C, VS = ±15 V, unless otherwise noted. PARAMETER TEST CONDITIONS OPAx132PA, UA OPA2132PA, UA OPA4132PA, UA OPAx132P, U OPA2132P, U MIN MIN TYP UNIT TYP MAX MAX ±0.25 ±0.5 ±0.5 ±2 mV ±2 ±10 ±2 ±10 µV/°C 5 15 5 30 µV/V OFFSET VOLTAGE Input Offset Voltage vs Temperature (1) Operating temperature range vs Power Supply VS = ±2.5 V to ±18 V Channel Separation (dual and quad) RL = 2 kΩ 0.2 0.2 µV/V INPUT BIAS CURRENT Input Bias Current (2) VCM = 0 V 5 vs Temperature Input Offset Current (2) ±50 See Figure 5 VCM = 0 V 5 ±50 pA ±50 pA See Figure 5 ±2 ±50 ±2 NOISE Input Voltage Noise Noise Density Current Noise Density, f = 10 Hz 23 23 f = 100 H 10 10 f = 1 kHz 8 8 f = 10 kHz 8 8 f = 1 kHz 3 3 nV/√Hz fA/√Hz INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection VCM = –12.5 V to 12.5 V (V–) +2.5 ±13 96 100 (V+) –2.5 (V–) +2.5 ±13 86 94 (V+) –2.5 V dB INPUT IMPEDANCE 1013 || 2 Differential Common-Mode 13 VCM = –12.5 V to 12.5 V 10 || 6 1013 || 2 Ω || pF 1013 || 6 Ω || pF OPEN-LOOP GAIN Open-Loop Voltage Gain RL = 10 kΩ, VO = –14.5 V to 13.8 V 110 120 104 120 RL = 2 kΩ, VO = –13.8 V to 13.5 V 110 126 104 120 RL = 600 Ω, VO = –12.8 V to 12.5 V 110 130 104 120 dB FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate 8 MHz ±20 ±20 V/µs 0.1% G = –1, 10 V Step, CL = 100 pF 0.7 0.7 µs 0.01% G = –1, 10 V Step, CL = 100 pF 1 1 µs µs Settling Time: Overload Recovery Time Total Harmonic Distortion + Noise (1) (2) 8 G=± 1 kHz, G = 1, VO = 3.5 Vrms 0.5 0.5 RL = 2 kΩ 0.00008% 0.00008% RL = 600 Ω 0.00009% 0.00009% Specified by wafer test. High-speed test at TJ = 25°C. Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: OPA132 OPA2132 OPA4132 Submit Documentation Feedback 5 OPA132, OPA2132, OPA4132 SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 www.ti.com Electrical Characteristics (continued) At TA = 25°C, VS = ±15 V, unless otherwise noted. PARAMETER TEST CONDITIONS OPAx132PA, UA OPA2132PA, UA OPA4132PA, UA OPAx132P, U OPA2132P, U MIN TYP (V+) –1.2 Negative Positive MAX MIN TYP (V+) –0.9 (V+) –1.2 (V+) –0.9 (V–) +0.5 (V–) +0.3 (V–) +0.5 (V–) +0.3 (V+) –1.5 (V+) –1.1 (V+) –1.5 (V+) –1.1 Negative (V–) +1.2 (V–) +0.9 (V–) +1.2 (V–) +0.9 Positive (V+) –2.5 (V+) –2.0 (V+) –2.5 (V+) –2.0 (V–) +2.2 (V–) +1.5 (V–) +2.2 (V–) +1.5 UNIT MAX OUTPUT Positive RL = 10 kΩ Voltage Output RL= 2 kΩ RL = 600 Ω Negative Short-Circuit Current ±40 Capacitive Load Drive (Stable Operation) V ±40 See Figure 17 mA See Figure 17 POWER SUPPLY Specified Operating Voltage ±15 Operating Voltage Range Quiescent Current (per amplifier) ±2.5 IO = 0 ±15 ±18 ±4 ±2.5 ±4.8 ±4 V ±18 V ±4.8 mA TEMPERATURE RANGE Operating Range –40 85 –40 85 °C Storage –40 125 –40 125 °C 6 Submit Documentation Feedback Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: OPA132 OPA2132 OPA4132 OPA132, OPA2132, OPA4132 www.ti.com SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 6.5 Typical Characteristics At TA = 25°C, VS = ±15 V, RL = 2 kΩ, unless otherwise noted. 160 120 0 140 100 –PSR 100 Φ 80 –90 60 40 –135 PSR, CMR (dB) –45 Phase Shift (°) Voltage Gain (dB) 120 80 60 40 +PSR G 20 CMR 20 0 –180 0 –20 0.1 1 10 100 1k 10k 100k 1M 10 10M 100 1k Frequency (Hz) 10k 100k 1M Frequency (Hz) Figure 1. Open-Loop Gain and Phase vs Frequency Figure 2. Power Supply and Common-Mode Rejection vs Frequency 1k 160 Channel Separation (dB) Current Noise (fA/√Hz) Voltage Noise (nV/√Hz) RL = ∞ 100 Voltage Noise 10 140 120 100 Current Noise 1 80 10 1 100 1k 10k 100k 1M 100 1k Frequency (Hz) 10k 100k Frequency (Hz) Figure 3. Input Voltage and Current Noise Spectral Density vs Frequency Figure 4. Channel Separation vs Frequency 10 100k High Speed Test Warmed Up 9 Input Bias Current (pA) 10k Input Bias Current (pA) RL = 2kΩ Dual and quad devices. G = 1, all channels. Quad measured channel A to D or B to C—other combinations yield improved rejection. 1k Quad 100 Dual 10 1 Single High Speed Test 8 7 6 5 4 3 2 1 0 0.1 –75 –50 –25 0 25 50 75 100 125 –15 –10 Ambient Temperature ( °C) Figure 5. Input Bias Current vs Temperature –5 0 5 10 15 Common-Mode Voltage (V) Figure 6. Input Bias Current vs Input Common-Mode Voltage Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: OPA132 OPA2132 OPA4132 Submit Documentation Feedback 7 OPA132, OPA2132, OPA4132 SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) Open-Loop Gain 110 PSR 100 CMR 90 4.3 60 4.2 50 4.1 4.0 3.9 20 –50 –25 0 25 50 75 100 125 10 –75 –50 –25 Ambient Temperature ( °C) 50 75 100 125 12 Typical production distribution of packaged units. Single, dual and quad units included. Typical production distribution of packaged units. Single, dual and quad units included. 10 Percent of Amplifiers (%) 8 6 4 2 0 8 6 4 2 8.0 7.0 7.5 6.0 6.5 5.0 5.5 4.0 4.5 3.0 3.5 2.0 1.0 1.5 0.0 1400 1000 1200 600 800 200 400 – 1400 – 1200 – 1000 – 800 – 600 – 400 – 200 0 0 0.5 Percent of Amplifiers (%) 25 Figure 8. Quiescent Current and Short-Circuit Current vs Temperature 12 10 0 Ambient Temperature ( °C) Figure 7. AOL, CMR, PSR vs Temperature Offset Voltage Drift (µV/°C) Offset Voltage (µV) Figure 10. Offset Voltage Drift Production Distribution Figure 9. Offset Voltage Production Distribution 30 0.01 RL 2kΩ 600Ω 0.001 G = +10 0.0001 G = +1 20 10 VS = ±5V VO = 3.5Vrms 0.00001 VS = ±2.5V 0 10 100 Maximum output voltage without slew-rate induced distortion VS = ±15V Output Voltage (Vp-p) THD+Noise (%) 30 ±I Q 3.8 –75 1k 10k 100k 10k 100k Frequency (Hz) Figure 11. Total Harmonic Distortion + Noise vs Frequency 8 40 ±I SC 2.5 AOL, CMR, PSR (dB) 120 Quiescent Current Per Amp (mA) 130 Short-Circuit Current (mA) At TA = 25°C, VS = ±15 V, RL = 2 kΩ, unless otherwise noted. Submit Documentation Feedback 1M 10M Frequency (Hz) Figure 12. Maximum Output Voltage vs Frequency Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: OPA132 OPA2132 OPA4132 OPA132, OPA2132, OPA4132 www.ti.com SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 Typical Characteristics (continued) 5V/div 50mV/div At TA = 25°C, VS = ±15 V, RL = 2 kΩ, unless otherwise noted. 200ns/div G=1 1μs/div CL = 100pF G=1 Figure 13. Small-Signal Step Response Figure 14. Large-Signal Step Response 100 60 50 0.01% 10 Overshoot (%) Settling Time (µs) CL = 100pF FPO 0.1% 1 G = +1 40 G = –1 30 20 G = ±10 10 0 100pF 0.1 ±1 ±10 ±100 ±1000 1nF 10nF Closed-Loop Gain (V/V) Load Capacitance Figure 15. Settling Time vs Closed-Loop Gain Figure 16. Small-Signal Overshoot vs Load Capacitance 15 VIN = 15V Output Voltage Swing (V) 14 –55°C 13 12 25°C 25°C 125°C 85°C 11 10 –10 85°C 125°C –11 –12 25°C –13 –55°C –14 VIN = –15V –15 0 10 20 30 40 50 60 Output Current (mA) Figure 17. Output Voltage Swing vs Output Current Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: OPA132 OPA2132 OPA4132 Submit Documentation Feedback 9 OPA132, OPA2132, OPA4132 SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 www.ti.com 7 Detailed Description 7.1 Overview The OPAx132 series of FET-input operational amplifiers provides highspeed and excellent dc performance. The combination of high slew rate and wide bandwidth provide fast settling time. Single, dual, and quad versions have identical specifications for maximum design flexibility. High performance grades are available in the single and dual versions. All are ideal for general-purpose, audio, data acquisition and communications applications, especially where high source impedance is encountered. 7.2 Functional Block Diagram Input Offset Adjust (OPA132 only) +IN -IN + ± Input Offset Adjust (OPA132 only) Output Compensation 7.3 Feature Description The OPAx132 series of JFET operational amplifiers combine low noise and wide bandwidth with precision and low input bias current to make them the ideal choice for applications with a high source impedance. The OPAx132 is unity-gain stable and features high slew rate (±20 V/μs) and wide bandwidth (8 MHz). 7.4 Device Functional Modes The OPAx132 has a single functional mode and is operational when the power-supply voltage is greater than 5 V (±2.5 V). The maximum power supply voltage for the OPAx132 is 36 V (±18 V). 10 Submit Documentation Feedback Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: OPA132 OPA2132 OPA4132 OPA132, OPA2132, OPA4132 www.ti.com SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The OPAx132 series operational amplifiers are unity-gain stable and suitable for a wide range of generalpurpose applications. Power supply pins should be bypassed with 10-nF ceramic capacitors or larger. The OPAx132 series operational amplifiers are free from unexpected output phase reversal common with FET operational amplifiers. Many FET-input operational amplifiers exhibit phase-reversal of the output when the input common-mode voltage range is exceeded. This can occur in voltage-follower circuits, causing serious problems in control loop applications. The OPAx132 series of operational amplifiers are free from this undesirable behavior. All circuitry is completely independent in dual and quad versions, assuring normal behavior when one amplifier in a package is overdriven or short-circuited. 8.1.1 Operating Voltage The OPAx132 series of operation amplifiers operate with power supplies from ±2.5 V to ±18 V with excellent performance. Although specifications are production tested with ±15 V supplies, most behavior remains unchanged throughout the full operating voltage range. Parameters which vary significantly with operating voltage are shown in the Typical Characteristics section. 8.1.2 Offset Voltage Trim Offset voltage of the OPAx132 series of amplifiers is laser trimmed and usually requires no user adjustment. The OPAx132 amplifier (single op amp version) provides offset voltage trim connections on pins 1 and 8. Offset voltage can be adjusted by connecting a potentiometer as shown in Figure 18. This adjustment should be used only to null the offset of the operational amplifier, not to adjust system offset or offset produced by the signal source. Nulling offset could degrade the offset voltage drift behavior of the operational amplifier. While it is not possible to predict the exact change in drift, the effect is usually small. V+ Trim Range: ±4mV typ 10nF 100kΩ 7 1 2 8 3 10nF OPA132 4 6 OPA132 single op amp only. Use offset adjust pins only to null offset voltage of op amp—see text. V– Figure 18. OPAx132 Offset Voltage Trim Circuit 8.1.3 Input Bias Current The FET-inputs of the OPAx132 series provide very low input bias current and cause negligible errors in most applications. For applications where low input bias current is crucial, junction temperature rise should be minimized. The input bias current of FET-input operational amplifiers increases with temperature as shown in Figure 5. The OPAx132 series may be operated at reduced power supply voltage to minimize power dissipation and temperature rise. Using ±3 V supplies reduces power dissipation to one-fifth that at ±15 V. Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: OPA132 OPA2132 OPA4132 Submit Documentation Feedback 11 OPA132, OPA2132, OPA4132 SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 www.ti.com Application Information (continued) The dual and quad versions have higher total power dissipation than the single, leading to higher junction temperature. Thus, a warmed-up quad will have higher input bias current than a warmed-up single. Furthermore, an SOIC will generally have higher junction temperature than a DIP at the same ambient temperature because of a larger θJA. Printed-circuit-board layout can also help minimize junction temperature rise. Temperature rise can be minimized by soldering the devices to the circuit board rather than using a socket. Wide copper traces will also help dissipate the heat by acting as an additional heat sink. Input stage cascode circuitry assures that the input bias current remains virtually unchanged throughout the full input common-mode range of the OPAx132 series. See Figure 6. 8.2 Typical Application The OPAx132 family offers outstanding dc precision and ac performance. These devices operate up to 36-V supply rails and offer ultralow input bias current and input bias current noise, as well as 8-MHz bandwidth and high capacitive load drive. These features make the OPAx132 a robust, high-performance operational amplifier for high-voltage industrial applications with high source impedance. 2.94 k 590 499 Input 1 nF ± 39 nF Output + Figure 19. OPA132 2nd Order 30 kHz, Low Pass Filter Schematic 8.2.1 Design Requirements Use the following parameters for this application: • Gain = 5 V/V • Low pass cutoff frequency = 30 kHz • -40 db/dec filter response • Maintain less than 3-dB gain peaking in the gain versus frequency response 8.2.2 Detailed Design Procedure WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners. Available as a web based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to design, optimize, and simulate complete multistage active filter solutions within minutes. 12 Submit Documentation Feedback Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: OPA132 OPA2132 OPA4132 OPA132, OPA2132, OPA4132 www.ti.com SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 Typical Application (continued) 8.2.3 Application Curve 20 Gain (db) 0 -20 -40 -60 100 1k 10k Frequency (Hz) 100k 1M Figure 20. OPA132 2nd Order 30-kHz, Low Pass Filter Response Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: OPA132 OPA2132 OPA4132 Submit Documentation Feedback 13 OPA132, OPA2132, OPA4132 SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 www.ti.com 9 Power Supply Recommendations The OPAx132 is specified for operation from 5 V to 36 V (±2.5 V to ±18 V); many specifications apply from –40°C to 85°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. CAUTION Supply voltages larger than 36 V can permanently damage the device; see the Absolute Maximum Ratings. Place 10-nF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout Guidelines. 10 Layout 10.1 Layout Guidelines For best operational performance of the device, use good PCB layout practices, including: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and operational amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 10 nF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. For more detailed information refer to Circuit Board Layout Techniques, SLOA089. • In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace. • Place the external components as close to the device as possible. As shown in Layout Example, keeping RF and RG close to the inverting input minimizes parasitic capacitance. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. • Cleaning the PCB following board assembly is recommended for best performance. • Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances. 14 Submit Documentation Feedback Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: OPA132 OPA2132 OPA4132 OPA132, OPA2132, OPA4132 www.ti.com SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 10.2 Layout Example + VIN VOUT RG RF (Schematic Representation) Run the input traces as far away from the supply lines as possible Place components close to device and to each other to reduce parasitic errors VS+ RF Offset trim Offset trim GND ±IN V+ VIN +IN OUTPUT V± NC RG Use low-ESR, ceramic bypass capacitor GND GND Use low-ESR, ceramic bypass capacitor VOUT VS± Ground (GND) plane on another layer Figure 21. OPA132 Layout Example for the Noninverting Configuration Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: OPA132 OPA2132 OPA4132 Submit Documentation Feedback 15 OPA132, OPA2132, OPA4132 SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 WEBENCH Filter Designer Tool WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners. 11.1.1.2 TINA-TI™ (Free Software Download) TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. NOTE These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. 11.1.1.3 TI Precision Designs The OPAx132 is featured in several TI Precision Designs, available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation, see the following: • EMI Rejection Ratio of Operational Amplifiers, SBOA128 • Circuit Board Layout Techniques, SLOA089 11.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY OPA132 Click here Click here Click here Click here Click here OPA2132 Click here Click here Click here Click here Click here OPA4132 Click here Click here Click here Click here Click here 11.4 Trademarks TINA-TI is a trademark of Texas Instruments. TINA, DesignSoft are trademarks of DesignSoft, Inc. All other trademarks are the property of their respective owners. 16 Submit Documentation Feedback Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: OPA132 OPA2132 OPA4132 OPA132, OPA2132, OPA4132 www.ti.com SBOS054B – JANUARY 1995 – REVISED SEPTEMBER 2015 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 1995–2015, Texas Instruments Incorporated Product Folder Links: OPA132 OPA2132 OPA4132 Submit Documentation Feedback 17 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) OPA132U ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR OPA 132U Samples OPA132U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-3-260C-168 HR OPA 132U Samples OPA132UA ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 OPA 132U A OPA132UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 OPA 132U A OPA132UAE4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 OPA 132U A OPA132UAG4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 OPA 132U A OPA132UG4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR OPA2132P ACTIVE PDIP P 8 50 RoHS & Green Call TI OPA2132PA ACTIVE PDIP P 8 50 RoHS & Green OPA2132PAG4 ACTIVE PDIP P 8 50 OPA2132U ACTIVE SOIC D 8 OPA2132U/2K5 ACTIVE SOIC D OPA2132U/2K5E4 ACTIVE SOIC OPA2132U/2K5G4 ACTIVE OPA2132UA ACTIVE Samples Samples Samples Samples OPA 132U Samples N / A for Pkg Type OPA2132P Samples Call TI N / A for Pkg Type OPA2132P A Samples RoHS & Green Call TI N / A for Pkg Type OPA2132P A Samples 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 OPA 2132U Samples 8 2500 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 OPA 2132U Samples D 8 2500 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 OPA 2132U Samples SOIC D 8 2500 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 OPA 2132U Samples SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 OPA 2132U A Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) OPA2132UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 OPA 2132U A OPA2132UA/2K5E4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 OPA 2132U A OPA2132UAE4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 OPA 2132U A OPA2132UAG4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 OPA 2132U A OPA2132UE4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 OPA 2132U Samples OPA2132UG4 ACTIVE SOIC D 8 75 RoHS & Green Call TI Level-3-260C-168 HR -40 to 125 OPA 2132U Samples OPA4132UA ACTIVE SOIC D 14 50 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4132UA Samples OPA4132UA/2K5 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4132UA Samples OPA4132UA/2K5E4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4132UA Samples OPA4132UAG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4132UA Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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