OPA210, OPA2210
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
OPAx210 2.2-nV/√Hz Precision, Low-Power, 36-V Operational Amplifiers
1 Features
3 Description
•
The OPA210 and OPA2210 (OPAx210) are the next
generation of OPAx209 operational amplifier (op
amp). The OPAx210 precision op amps are built
on TI's precision, super-beta, complementary bipolar
semiconductor process, which offers ultra-low flicker
noise, low offset voltage, and low offset voltage
temperature drift.
•
•
•
•
•
•
•
•
•
•
Precision super beta input performance:
– Low offset voltage: 5 µV (typical)
– Ultra-low drift: 0.1 µV/°C (typical)
– Low input bias current: 0.3 nA (typical)
Ultra-low noise:
– Low 0.1-Hz to 10-Hz noise: 90 nVPP
– Low voltage noise: 2.2 nV/√ Hz at 1 kHz
High CMRR: 132 dB (minimum)
Gain bandwidth product: 18 MHz
Slew rate: 6.4 V/µs
Low quiescent current: 2.5 mA/channel (maximum)
Short-circuit current: ±65 mA
Wide supply range: ±2.25 V to ±18 V
No phase reversal
Rail-to-rail output
Industry-standard packages
2 Applications
Ultrasound scanner
Multiparameter patient monitor
Merchant network and server PSU
Semiconductor test
Spectrum analyzer
Lab and field instrumentation
Data acquisition (DAQ)
Professional microphone and wireless systems
In precision data-acquisition applications, the
OPAx210 provide fast settling time to 16-bit
accuracy, even for 10-V output swings. Excellent ac
performance, combined with only 35 μV (maximum)
of offset and 0.6 µV/°C (maximum) drift over
temperature, makes the OPAx210 an excellent choice
for high-speed, high-precision applications.
The OPAx210 are specified over a wide dual powersupply range of ±2.25 V to ±18 V, or single-supply
operation from 4.5 V to 36 V, are specified from –40°C
to +125°C.
Device Information
PART NUMBER
OPA210
OPA2210
(1)
PACKAGE(1)
BODY SIZE (NOM)
SOIC (8)
2.90 mm × 1.60 mm
SOT-23 (5)
2.90 mm × 1.60 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
WSON (8)
3.00 mm × 3.00 mm
For all available packages, see the package option
addendum at the end of the data sheet.
20%
17.5%
Total Amplifiers (%)
Input Voltage Noise (50 nV/div)
•
•
•
•
•
•
•
•
The OPAx210 achieve very low voltage noise
density (2.2 nV/√Hz) while consuming only 2.5 mA
(maximum) per amplifier. These devices also offer
rail-to-rail output swing, which helps maximize
dynamic range.
15%
12.5%
10%
7.5%
5%
2.5%
Time (1 s/div)
OPAx210 0.1-Hz to 10-Hz Noise
0
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6
Offset Voltage Drift (PV/qC)
OPAx210 Offset Voltage Drift Distribution
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information: OPA210 ................................... 5
6.5 Thermal Information: OPA2210 ................................. 5
6.6 Electrical Characteristics ............................................6
6.7 Typical Characteristics................................................ 8
7 Detailed Description......................................................15
7.1 Overview................................................................... 15
7.2 Functional Block Diagram......................................... 15
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................18
8 Application and Implementation.................................. 19
8.1 Application Information............................................. 19
8.2 Typical Application.................................................... 21
8.3 System Example....................................................... 22
9 Power Supply Recommendations................................23
10 Layout...........................................................................23
10.1 Layout Guidelines................................................... 23
10.2 Layout Example...................................................... 23
11 Device and Documentation Support..........................24
11.1 Device Support........................................................24
11.2 Documentation Support.......................................... 25
11.3 Receiving Notification of Documentation Updates.. 25
11.4 Support Resources................................................. 25
11.5 Trademarks............................................................. 25
11.6 Electrostatic Discharge Caution.............................. 25
11.7 Glossary.................................................................. 25
12 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (April 2021) to Revision H (August 2021)
Page
• Changed OPA210 DBV (SOT-23-5) and DGK (VSSOP-8) packages from advanced information (preview) to
production data (active)...................................................................................................................................... 1
Changes from Revision F (January 2021) to Revision G (April 2021)
Page
• Changed OPA210 D (SOIC-8) package from advanced information (preview) to production data (active)....... 1
• Added OPA210 DBV (SOT-23-5) package as advanced information (preview)................................................. 1
Changes from Revision E (Novembver 2020) to Revision F (January 2021)
Page
• Added OPA210 device with D and DGK packages as advanced information (preview).................................... 1
Changes from Revision D (January 2020) to Revision E (November 2020)
Page
• Changed OPA2210 DRG package from advanced information (preview) to production data (active)............... 1
Changes from Revision C (September 2019) to Revision D (January 2020)
Page
• Added OPA2210 DRG package to data sheet as advanced information (preview)............................................1
Changes from Revision B (March 2019) to Revision C (September 2019)
Page
• Changed super-ß to super beta for easier searching ........................................................................................ 1
• Added SOIC package......................................................................................................................................... 1
Changes from Revision A (December 2018) to Revision B (February 2019)
Page
• Changed "OPAx145" to "OPA2210"..................................................................................................................19
• Fixed link to TIDA-01427 ................................................................................................................................. 22
Changes from Revision * (September 2018) to Revision A (December 2018)
Page
• First release of production-data data sheet ....................................................................................................... 1
2
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
5 Pin Configuration and Functions
–IN
2
+IN
3
V–
4
8
NC
–
7
V+
+
6
OUT
5
NC
OUT
1
V±
2
+IN
3
5
V+
4
±IN
±
1
+
NC
Not to scale
Figure 5-2. OPA210: DBV (5-Pin SOT-23) Package,
Top View
Not to scale
Figure 5-1. OPA210: D (8-Pin SOIC) and DGK (8-Pin
VSSOP) Packages, Top View
Table 5-1. Pin Functions: OPA210
PIN
NAME
SOIC, VSSOP
SOT-23
2
4
–IN
I/O
DESCRIPTION
I
Inverting input
Noninverting input
+IN
3
3
I
NC
1, 5, 8
—
—
No internal connection
OUT
6
1
O
Output
V–
4
2
—
Negative (lowest) power supply
V+
7
5
—
Positive (highest) power supply
OUT A
1
-IN A
2
+IN A
3
V-
4
A
B
8
V+
7
OUT B
6
-IN B
5
+IN B
Figure 5-3. OPA2210: D (SOIC-8), DGK (VSSOP-8), and DRG (WSON-8) Packages, Top View
Table 5-2. Pin Functions: OPA2210
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative (lowest) power supply
V+
8
—
Positive (highest) power supply
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
3
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
Supply voltage, VS = (V+) – (V–)
Signal input pins(2)
Voltage
(V–) – 0.5
Signal input pins
(1)
(2)
(3)
V
1
–10
Output short circuit(3)
Temperature
(V+) + 0.5
Differential
Signal input pins(2)
Current
UNIT
40
10
mA
Continuous
Junction, TJ
150
Storage temperature, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the de vice. Theseare stress
ratings only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated
under Recommended OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device
reliability.
For input voltages beyond the power-supply rails, voltage orcurrent must be limited.
Short circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
±2.25
±18
V
Specified temperature
–40
125
°C
Operating temperature, TA
–55
150
°C
Specified voltage, VS
4
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
6.4 Thermal Information: OPA210
OPA210
THERMAL METRIC(1)
D (SOIC)
DGK (VSSOP)
DBV (SOT-23)
8 PINS
8 PINS
5 PINS
UNIT
180.4
°C/W
RθJA
Junction-to-ambient thermal resistance
131.2
171.3
RθJC(top)
Junction-to-case (top) thermal resistance
71.6
64.7
67.9
°C/W
RθJB
Junction-to-board thermal resistance
74.6
92.4
102.1
°C/W
ψJT
Junction-to-top characterization parameter
22.4
10.4
10.4
°C/W
ψJB
Junction-to-board characterization parameter
73.8
90.9
100.3
°C/W
RθJC(bottom)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application
report.
6.5 Thermal Information: OPA2210
OPA2210
THERMAL METRIC(1)
D (SOIC)
DGK (VSSOP)
DRG (SON)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
126.1
132.7
52.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
65.7
38.5
51.8
°C/W
RθJB
Junction-to-board thermal resistance
69.5
52.1
24.8
°C/W
ψJT
Junction-to-top characterization parameter
17.4
2.4
1.1
°C/W
ψJB
Junction-to-board characterization parameter
68.9
52.8
24.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
9.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
5
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
6.6 Electrical Characteristics
at VS = ±15 V, TA = 25°C, RL = 10 kΩ connected to midsupply, and VCM =VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VS = ±15 V, VCM = 0 V
dVOS/dT
Input offset voltage drift
TA = –40°C to 125°C
VOS -
Input offset voltage matching
matching
PSRR
vs power supply
VS = ±2.25 V to ±18 V
Channel separation
DC
TA = 25°C
±5
±35
µV
±0.1
±0.5
µV/°C
±5
±35
µV
0.05
0.5
TA = –40°C to 125°C
±1
±0.1
µV/V
µV/V
INPUT BIAS OPERATION
TA = 25°C
IB
Input bias current
VCM = 0 V
±0.3
TA = –40°C to 85°C
±4
TA = –40°C to 125°C
±7
TA = 25°C
IOS
Input offset current
VCM = 0 V
±2
±0.1
nA
±2
TA = –40°C to 85°C
±4
TA = –40°C to 125°C
±7
nA
NOISE
en p-p
Input voltage noise
en
Noise density
In
Input current noise density
f = 0.1 Hz to 10 Hz
0.09
f = 10 Hz
2.5
f = 100 Hz
2.25
f = 1 kHz
2.2
f = 1 kHz
400
µVPP
nV/√Hz
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
range
CMRR
Common-mode rejection
ratio
(V–) + 1.5
(V+) – 1.5
(V–) + 1.5 V < VCM < (V+) – 1.5 V
132
140
(V–) + 1.5 V < VCM < (V+) – 1.5 V,
TA = –40°C to 125°C
120
130
V
dB
INPUT IMPEDANCE
Differential
Common-mode
400 || 9
kΩ || pF
109 || 0.5
Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 0.2 V < VO < (V+) – 0.2
V, RL = 10 kΩ
TA = 25°C
126
TA = –40°C to 125°C
120
(V–) + 0.6 V < VO < (V+) – 0.6
V, RL = 600 Ω(1)
TA = 25°C
114
TA = –40°C to 85°C
110
132
120
dB
FREQUENCY RESPONSE
GBW
Gain bandwidth product
SR
Slew rate
6
MHz
6.4
V/µs
RL = 10 kΩ, CL = 25 pF
80
degrees
0.1%, G = –1, 10-V step, CL = 100 pF
2.1
0.0015% (16-bit), G = –1, 10-V step, CL = 100 pF
2.6
Overload recovery time
G = –10
0.5
µs
Total harmonic distortion +
noise (THD+N)
G = +1, f = 1 kHz, VO = 20 VPP, 600 Ω
0.000025
%
Phase margin (Φm)
tS
18
Settling time
Submit Document Feedback
µs
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
6.6 Electrical Characteristics (continued)
at VS = ±15 V, TA = 25°C, RL = 10 kΩ connected to midsupply, and VCM =VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Voltage output swing
RL = 10 kΩ, AOL > 130 dB
(V–) + 0.2
(V+) – 0.2
RL = 600 Ω, AOL > 114 dB
(V–) + 0.6
(V+) – 0.6
RL = 10 kΩ, AOL > 120 dB, TA = –40°C to 125°C
(V–) + 0.2
(V+) – 0.2
ISC
Short-circuit current
CLOAD
Capacitive load drive
(stable operation)
VS = ±18 V
±65
See Section 6.7
ZO
Open-loop output impedance
See Section 6.7
V
mA
POWER SUPPLY
IQ
(1)
Quiescent current
(per amplifier)
IO = 0 A
TA = 25°C
TA = –40°C to 125°C
2.2
2.5
3.25
mA
Temperature range limited by thermal performance of the package.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
7
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
6.7 Typical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
15%
20%
Total Amplifiers (%)
Total Amplifiers (%)
17.5%
10%
5%
15%
12.5%
10%
7.5%
5%
2.5%
0
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6
Offset Voltage Drift (PV/qC)
0
-35 -30 -25 -20 -15 -10 -5 0
5 10 15 20 25 30 35
Input-Referred Offset Voltage (PV)
Figure 6-2. Offset Voltage Drift Distribution
Figure 6-1. Offset Voltage Production Distribution
10
Current Noise Density (pA/—Hz)
10
1
100m
1
10
100
1k
Frequency (Hz)
10k
0.1
100m
100k
Figure 6-3. Input Voltage Noise Spectral Density vs Frequency
1
1
10
100
1k
Frequency (Hz)
10k
Figure 6-4. Input Current Noise Spectral Density vs Frequency
Input Voltage Noise (50 nV/div)
Total Harmonic Distortion Noise ( )
0.01
-80
G 1
G 1
0.001
-100
0.0001
-120
1E-5
-140
100
Time (1 s/div)
VOUT = 3.5 VRMS
Figure 6-5. 0.1-Hz to 10-Hz Voltage Noise
8
100k
Total Harmonic Distortion Noise (dB)
Voltage Noise Density (nV/—Hz)
100
1k
Frequency (Hz)
10k
RL = 600 Ω
Figure 6-6. THD+N Ratio vs Frequency
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
120
0.1
-60
0.01
-80
0.001
-100
0.0001
-120
-140
1E-5
10m
100m
1
Output Amplitude (VRMS)
f = 1 kHz
Input-referred Offset Voltage (PV)
-40
G 1
G 1
Total Harmonic Distortion + Noise (dB)
90
60
30
0
-30
-60
-90
10
-120
-50
RL = 600 Ω
25
50
Temperature (qC)
75
100
125
Figure 6-8. Input Offset Voltage vs Temperature
50
50
Vcm = -13.5 V
Vcm = 13.5 V
Input-Referred Offset Voltage (PV)
Input-referred Offset Voltage (PV)
0
5 typical units
Figure 6-7. THD+N vs Output Amplitude
30
10
-10
-30
-50
-15
40
30
20
10
0
-10
-20
-30
-40
-50
-10
-5
0
5
Input Common-mode Voltage (V)
10
15
0
5 typical units
8
12
16
20
24
Supply Voltage (V)
28
PSRR
PSRR
140
120
100
80
60
40
20
10
100
1k
10k
Frequency (Hz)
100k
Figure 6-11. PSSR vs Frequency
1M
10M
Power Supply Rejection Ratio (dB)
160
1
32
36
Figure 6-10. Offset Voltage vs Supply Voltage
160
0
100m
4
5 typical units
Figure 6-9. Offset Voltage vs Common-Mode Voltage
Power-Supply Rejection Ratio (dB)
-25
0.01
150
140
0.1
130
120
-50
-25
0
25
50
Temperature (qC)
75
100
Power Supply Rejection Ratio (PV/V)
Total Harmonic Distortion Noise (%)
1
1
125
Figure 6-12. PSRR vs Temperature
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
9
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
140
120
100
80
60
40
20
100
1k
10k
100k
Frequency (Hz)
1M
0.01
150
140
0.1
130
120
-50
10M
-25
Figure 6-13. CMRR vs Frequency
0
25
50
Temperature (qC)
75
Figure 6-14. CMRR vs Temperature
140
1000
180
Gain
Phase 160
120
Zo (:)
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
140
80
120
60
100
40
80
20
60
0
40
-20
100m
100M
Figure 6-15. Open-Loop Output Impedance vs Frequency
160
100
Phase (q)
Gain (dB)
100
1
10
1
125
100
Common-mode Rejection Ratio (PV/V)
160
CMRR
Common-mode Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
160
20
1
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
Figure 6-16. Open-Loop Gain and Phase vs Frequency
20%
0.01
0.1
130
600 : Load
120
1
Total Amplifiers (%)
10 k: Load
140
Open-loop Gain (PV/V)
Open-loop Gain (dB)
150
15%
10%
5%
110
100
-50
-25
0
25
50
Temperature (qC)
75
100
10
125
Figure 6-17. Open-Loop Gain vs Temperature
10
0
-2
-1.5
-1
-0.5
0
0.5
1
Positive Input Bias Current (nA)
1.5
2
Figure 6-18. Positive Input Bias Current Production Distribution
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
20%
20%
Total Amplifiers (%)
Total Amplifiers (%)
16%
12%
8%
15%
10%
5%
4%
0
-2
-1.5
-1
-0.5
0
0.5
1
Negative Input Bias Current (nA)
1.5
0
-2
2
Figure 6-19. Negative Input Bias Current Production
Distribution
-1.5
-1
-0.5
0
0.5
Input Offset Current (nA)
1
1.5
2
Figure 6-20. Input Offset Current Production Distribution
1.2
1000
800
600
Input Bias Current (pA)
Ib+, Ib- and Ios (nA)
0.9
Ib+
0.6
Ib0.3
200
0
-200
-400
-600
0
-800
Ios
-0.3
-75
-50
-25
0
25
50
75
Temperature (qC)
100
125
-1000
-14 -12 -10 -8 -6 -4 -2 0
2
4
6
8
Input Common-mode Voltage (V)
150
Figure 6-21. Input Bias and Input Offset Currents vs
Temperature
1000
1000
800
800
600
600
400
200
0
-200
-400
-600
-800
10 12 14
Figure 6-22. Positive Input Bias Current vs Common-Mode
Voltage
Input Offset Current (pA)
Input Bias Current (pA)
400
400
200
0
-200
-400
-600
-800
-1000
-14 -12 -10 -8 -6 -4 -2 0
2
4
6
8
Input Common-mode Voltage (V)
10 12 14
Figure 6-23. Negative Input Bias Current vs Common-Mode
Voltage
-1000
-14 -12 -10 -8 -6 -4 -2 0
2
4
6
8
Input Common-mode Voltage (V)
10 12 14
Figure 6-24. Input Offset Current vs Common-Mode Voltage
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
11
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
3.25
2.4
3
2.3
2.75
Quiescent Current (mA)
Quiescent Current (mA)
2.5
2.2
2.1
2
1.9
1.8
1.7
2.5
2.25
2
1.75
1.5
1.25
1.6
1
-50
1.5
0
4
8
12
16
20
24
Supply Voltage (V)
28
32
36
-25
0
25
50
Temperature (qC)
75
100
125
Figure 6-26. Quiescent Current vs Temperature
Figure 6-25. Quiescent Current vs Supply Voltage
15
-12
25qC
-12.5
14.5
Output Voltage (V)
Output Voltage (V)
-40qC
14
13.5
85qC
13
-13
125qC
-13.5
85qC
-14
-40qC
125qC
-14.5
12.5
25qC
-15
12
0
10
20
30
40
Output Current (mA)
50
0
60
10
20
30
40
Output Current (mA)
50
60
A.
A.
Figure 6-27. Output Voltage vs Output Current (Sourcing)
Figure 6-28. Output Voltage vs Output Current (Sinking)
Vin (V)
Vout (V)
60
Voltage (5V/div)
Short Circuit Current (mA)
65
55
50
45
Sinking
Sourcing
40
-50
-25
0
25
50
Temperature (qC)
75
100
Figure 6-29. Short-Circuit Current vs Temperature
12
125
Time (100 Ps/div)
Figure 6-30. No Phase Reversal
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
Voltage (5 V/div)
Voltage (5 V/div)
VOUT
VIN
VOUT
VIN
Time (500 ns/div)
Time (500 ns/div)
G = –10
G = –10
Figure 6-32. Negative Overload Recovery
Voltage (5 mV/div)
Voltage (5 mV/div)
Figure 6-31. Positive Overload Recovery
Time (1 Ps/div)
G = +1
Time (1 Ps/div)
10-mV step, CL = 100 pF, RL = 600 Ω
G = –1
Figure 6-34. Small-Signal Step Response
Voltage (2 V/div)
Voltage (2 V/div)
Figure 6-33. Small-Signal Step Response
10-mV step, CL = 100 pF, RL = 600 Ω
Time (1 Ps/div)
G = +1
Time (1 Ps/div)
10-V step, CL = 100 pF, RL = 600 Ω
Figure 6-35. Large-Signal Step Response
G = –1
10-V step, CL = 100 pF, RL = 600 Ω
Figure 6-36. Large-Signal Step Response
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
13
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
80
Falling
Rising
G 1
G 1
Output (1 mV/div)
Overshoot ( )
60
40
20
0
20
100
Capactiance (pF)
1000
2000
Time (4 Ps/div)
10-V step
Figure 6-38. Settling Time
Figure 6-37. Small-Signal Overshoot vs Capacitive Load
140
130
120
EMIRR IN+ (dB)
110
100
90
80
70
60
50
40
30
20
10M
100M
Frequency (Hz)
1G
PRF = –10 dBm
Figure 6-39. EMIRR vs Frequency
14
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
7 Detailed Description
7.1 Overview
The OPAx210 are the next generation of the OPAx209 operational amplifiers. The OPAx210 offer improved
input offset voltage, offset voltage temperature drift, input bias current, and lower 1/f noise corner frequency.
In addition, these devices offer excellent overall performance with high CMRR, PSRR, and AOL.The OPAx210
precision operational amplifiers are unity-gain stable, and free from unexpected output and phase reversal.
Applications with noisy or high-impedance power supplies require decoupling capacitors placed close to the
device pins. In most cases, 0.1-µF capacitors are adequate. Section 7.2 shows a simplified schematic of the
OPAx210. The die uses a SiGe bipolar process and contains 180 transistors.
7.2 Functional Block Diagram
V+
Pre-Output Driver
OUT
IN-
IN+
V-
Copyright © 2016, Texas Instruments Incorporated
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
15
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
7.3 Feature Description
7.3.1 Operating Voltage
The OPAx210 op amps can be used with single or dual supplies within an operating range of VS = 4.5 V (±2.25
V) up to 36 V (±18 V).
CAUTION
Supply voltages greater than 40 V total can permanently damage the device.
In addition, key parameters are specified over the temperature range of TA = –40°C to +125°C. Parameters that
vary significantly with operating voltage or temperature are shown in Section 6.7.
7.3.2 Input Protection
The input pins of the OPAx210 are protected from excessive differential voltage with back-to-back diodes, as
shown in Figure 7-1. In most circuit applications, the input protection circuitry has no consequence. However, in
low-gain or G = 1 circuits, fast-ramping input signals can forward-bias these diodes because the output of the
amplifier cannot respond rapidly enough to the input ramp. This effect is illustrated in Figure 6-35 and Figure
6-36 in Section 6.7. If the input signal is fast enough to create this forward-bias condition, the input signal current
must be limited to 10 mA or less. If the input signal current is not inherently limited, an input series resistor can
be used to limit the signal input current. This input series resistor degrades the low-noise performance of the
OPAx210. See Section 7.3.3 for further information on noise performance.
Figure 7-1 shows an example configuration that implements a current-limiting feedback resistor.
RF
-
Output
RI
Input
+
Figure 7-1. Pulsed Operation
7.3.3 Noise Performance
Figure 7-2 shows the total circuit noise for varying source impedances with the op amp in a unity-gain
configuration (no feedback resistor network, and therefore, no additional noise contributions). Two different op
amps are shown with the total circuit noise calculated. The OPAx210 have very low voltage noise, making these
devices a great choice for low source impedances (less than 2 kΩ). As a comparable, precision FET-input op
amp (very low current noise), the OPA827 has somewhat higher voltage noise, but lower current noise. The
device provides excellent noise performance at moderate to high source impedance (10 kΩ and up). For source
impedance lower than 300 Ω, the OPA211 may provide lower noise.
The equation in Figure 7-2 shows the calculation of the total circuit noise, with these parameters:
• en = voltage noise,
• in = current noise,
• RS = source impedance,
• k = Boltzmann's constant = 1.38 × 10–23 J/K, and
• T = temperature in kelvins
For more details on calculating noise, see Section 8.1.1.
16
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
OPA210, OPA2210
www.ti.com
Votlage Noise Spectral Density, EO (VRMS)
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
10k
EO
1k
RS
OPAx210
100
OPA827
Resistor Noise
10
2
2
2
EO = en + (in RS) + 4kTRS
1
100
1k
10k
100k
1M
Source Resistance, RS (Ω)
Figure 7-2. Noise Performance of the OPAx210 and OPA827 in Unity-Gain Buffer Configuration
7.3.4 Phase-Reversal Protection
The OPAx210 have internal phase-reversal protection. Many FET- and bipolar-input op amps exhibit a phase
reversal when the input is driven beyond the linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input circuitry of the OPAx210 prevents phase reversal
with excessive common-mode voltage; instead, the output limits into the appropriate rail (see Figure 6-30).
7.3.5 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
It is helpful to have a good understanding of this basic ESD circuitry and its relevance to an electrical overstress
event. See Figure 7-3 for an illustration of the ESD circuits contained in the OPAx210 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where they meet at an absorption device internal
to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, highcurrent pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent it from being damaged. The energy
absorbed by the protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or
more of the steering diodes. Depending on the path that the current takes, the absorption device may activate.
The absorption device has a trigger, or threshold voltage, that is greater than the normal operating voltage of
the OPAx210 but less than the device breakdown voltage level. After this threshold is exceeded, the absorption
device quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit such as the one Figure 7-3 shows, the ESD protection
components are intended to remain inactive and not become involved in the application circuit operation.
However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin.
If this condition occur, there is a risk that some of the internal ESD protection circuits may be biased on, and
conduct current. Any such current flow occurs through steering diode paths and rarely involves the absorption
device.
Figure 7-3 depicts a specific example where the input voltage, VIN, exceeds the positive supply voltage, +VS,
by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can
sink the current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
17
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier,
and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise
to levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
power supplies +VS, –VS, or both are at 0 V.
Again, the answer depends on the supply characteristic while at 0 V, or at a level less than the input signal
amplitude. If the supplies appear as high impedance, then the operational amplifier supply current may be
supplied by the input source through the current steering diodes. This state is not a normal bias condition; the
amplifier will not operate normally. If the supplies are low impedance, then the current through the steering
diodes can become quite high. The current level depends on the ability of the input source to deliver current, and
any resistance in the input path.
If there is an uncertainty about the ability of the supply to absorb this current, external transient voltage
suppressor (TVS) diodes may be added to the supply pins as shown in Figure 7-3. The breakdown voltage
must be selected so that the diode does not turn on during normal operation. However, the breakdown voltage
must be low enough so that the TVS diode conducts if the supply pin begins to rise to greater than the safe
operating supply voltage level.
TVS(2)
RF
+VS
+V
OPAx210
RI
ESD CurrentSteering Diodes
-In
RS(3)
+In
Op Amp
Core
Edge-Triggered ESD
Absorption Circuit
ID
VIN(1)
Out
RL
-V
-VS
TVS(2)
(1) VIN = +VS + 500 mV.
(2) TVS: +VS(max) > VTVSBR (Min) > +VS.
(3) Suggested value approximately 1 kΩ.
Figure 7-3. Equivalent Internal ESD Circuitry and Relation to a Typical Circuit Application
7.4 Device Functional Modes
The OPAx210 are operational when the power-supply voltage is greater than 4.5 V (±2.25 V). The maximum
power-supply voltage for the OPAx210 is 36 V (±18 V).
18
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The OPAx210 are unity-gain stable, precision operational amplifiers with very low noise. Applications with noisy
or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF
capacitors are adequate.
8.1.1 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in
many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the
circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. This function is plotted in Figure 7-2. The source impedance is usually fixed; consequently, select the
op amp and the feedback resistors to minimize the respective contributions to the total noise.
Figure 8-1 illustrates both noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit
configurations with gain, the feedback network resistors also contribute noise. In general, the current noise of the
op amp reacts with the feedback resistors to create additional noise components. However, the extremely low
current noise of the OPAx210 means that the device current noise contribution can be neglected.
Generally, the feedback resistor values are chosen to make these noise sources negligible. Low impedance
feedback resistors load the output of the amplifier. The equations for total noise are shown for both
configurations.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
19
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
(A) Noise in Noninverting Gain Configuration
R1
Noise at the output is given as EO, where
R2
GND
±
EO
+
RS
+
±
VS
Source
GND
'1 = l1 +
:2;
A5 = ¥4 „ G$ „ 6(-) „ 45
d
:3;
A41 æ42 = ¨4 „ G$ „ 6(-) „ d
8
41 „ 42
h d
h
41 + 42
¾*V
Thermal noise of R1 || R2
:4;
G$ = 1.38065 „ 10F23
Boltzmann Constant
:5;
,
h
-
6(-) = 237.15 + 6(°%)
(B) Noise in Inverting Gain Configuration
R1
RS
R2
h
>-?
Thermal noise of RS
Temperature in kelvins
:45 + 41 ; „ 42
42
2
p „ ¨:A0 ;2 + kA41 +45 æ42 o + FE0 „ H
IG
45 + 41
45 + 41 + 42
:6;
'1 = l1 +
+
:7;
:45 + 41 ; „ 42
8
I d
A41 +45 æ42 = ¨4 „ G$ „ 6(-) „ H
h
45 + 41 + 42
¾*V Thermal noise of (R1 + RS) || R2
GND
:8;
G$ = 1.38065 „ 10F23
:9;
6(-) = 237.15 + 6(°%)
±
+
±
d
8
¾*V
> 84/5 ?
Noise at the output is given as EO, where
EO
VS
42
41 „ 42 2
2
p „ ¨:A5 ;2 + :A0 ;2 + kA41 æ42 o + :E0 „ 45 ;2 + lE0 „ d
hp
41
41 + 42
:1;
Source
GND
d
,
h
-
2
> 84/5 ?
Boltzmann Constant
>-?
Temperature in kelvins
Copyright © 2017, Texas Instruments Incorporated
Where eN is the voltage noise of the amplifier. For the OPAx210 op amp, eN = 2.2 nV/√Hz at 1 kHz.
Where iN is the current noise of the amplifier. For the OPAx210 op amp, iN = 400 fA/√Hz at 1 kHz.
NOTE: For additional resources on noise calculations visit the TI Precision Labs Series.
Figure 8-1. Noise Calculation in Gain Configurations
20
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
8.2 Typical Application
R4
2.94 k
C5
1 nF
R1
590
R3
499
C2
39 nF
±
Output
+
OPAx210
Figure 8-2. Low-Pass Filter
8.2.1 Design Requirements
Low-pass filters are commonly used in signal processing applications to reduce noise and prevent aliasing. The
OPAx210 are designed to construct high-speed, high-precision active filters. Figure 8-2 shows a second-order,
low-pass filter commonly encountered in signal-processing applications.
Use the following parameters for this design example:
•
•
•
Gain = 5 V/V (inverting gain)
Low-pass cutoff frequency = 25 kHz
Second-order Chebyshev filter response with 3-dB gain peaking in the pass band
8.2.2 Detailed Design Procedure
The infinite-gain, multiple-feedback circuit for a low-pass network function is shown in Figure 8-2. Use Equation
1 to calculate the voltage transfer function.
-1/ R1R3C2C5
Output
(s) = 2
Input
s + (s / C2 )(1/ R1 + 1/ R3 + 1/ R 4 ) + 1/ R3R 4C2C5
(1)
This circuit produces a signal inversion. For this circuit, the gain at dc and the low-pass cutoff frequency are
calculated by Equation 2:
Gain =
fc =
R4
R1
1
(1/ R3R 4C2C5 )
2p
(2)
8.2.3 Application Curve
Figure 8-3. OPAx210 Second-Order, 25-kHz, Chebyshev, Low-Pass Filter
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
21
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
8.3 System Example
8.3.1 Time Gain Control System for Ultrasound Applications
During an ultrasound send-receive cycle, the magnitude of reflected signal depends on the depth of penetration.
The ultrasound signal incident on the receiver decreases in amplitude as a function of the time elapsed
since transmission. The time gain control (TGC) system helps achieve the best possible signal-to-noise ratio
(SNR), even with the decreasing signal amplitude. When the image is displayed, similar materials have similar
brightness, regardless of depth. Linear-in-dB gain, which means the decibel gain is a linear function of the
control voltage (VCNTL), is used to generate this image.
There are multiple approaches for a TGC control circuit that are based on the type of DAC. Figure 8-4 shows a
high-level block diagram for the topology using a current-output multiplying DAC (MDAC) to generate the drive
for VCNTL. The op amp used for current-to-voltage (I-to-V) conversion must have low-voltage noise, as well as
low-current noise density. The current density helps reduce the overall noise performance because of the DAC
output configuration. The DAC output can go up to ±10 V; therefore, the op amp must have bipolar operation.
The OPAx210 is used here because of the low-voltage noise density of 2.2 nV/√Hz, low-current noise density
of 500 fA/√Hz, rail-to-rail output, and the ability to accept a wide supply range of ±2.25 V to ±18 V and provide
rail-to-rail output. The low offset voltage and offset drift of the OPAx210 facilitate excellent dc accuracy for the
circuit.
The OPAx210 is used to filter and buffer the 10-V reference voltage generated by the REF5010. The REF5010
serves as the reference voltage for the DAC8802, which generates a current output on IOUT corresponding to
the digital input code. The IOUT pin of the DAC8802 is connected to the virtual ground (negative terminal) of the
OPAx210; the feedback resistor (RFB is internal to the DAC8802) is connected to the output of the OPAx210, and
results in a current-to-voltage conversion. The output of the OPAx210 has a range of –10 V to 0 V, which is fed
to the THS4130 configured as a Sallen-Key filter. Finally, the 10-V range is attenuated down to a 1.5-V range,
with a common-mode voltage of 0.75 V using a resistive attenuator. See the 2.3-nV/√Hz, Differential, Time Gain
Control DAC Reference Design for Ultrasound for an in-depth analysis of Figure 8-4.
I-to-V Converters
2nd Order Filter (fc = 150
kHz)
+13 V -13 V
+5 V
FPGA or
Controller
Interface
Connector
+13 V -13 V
VCNTL-P
SPI
DAC8802
OPA2210
Passive VCNTL (0 to 1.5V)
with
Attenuator
VCM (0.75V)
THS4130
VCM
VCNTL-M
REF+ REF+13 V -13 V
Required
VCM as
per AFE
+13 V
10V from
REF5010
10 V
REF5010
Resistor
Divider
10 V
0.75 V
OPA2210
-10 V
+5 V to 12 V
LM5160
Used only if +/-15 V is not
available
+15 V
-15 V
TPS7A39
+13 V
-13 V
TPS7A47
+5 V
Figure 8-4. Block Diagram for Time Gain Control System for Ultrasound
22
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
9 Power Supply Recommendations
The OPAx210 are specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –
40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in Section 6.7.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including
the following guidelines:
•
•
•
•
•
•
•
•
•
Noise from the amplifier can propagate into other analog circuits through the power pins of the amplifiers.
Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply
applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than running
in parallel with the noisy trace.
Place the external components as close to the device as possible.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
For best performance, clean the PCB following board assembly.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, bake the PCB to remove moisture introduced into
the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30
minutes is sufficient for most circumstances.
10.2 Layout Example
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
OUT A
V+
GND
±IN A
OUT B
VIN
+IN A
±IN B
V±
+IN B
GND
RG
Use a low-ESR,
ceramic bypass capacitor
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
VOUT A
Figure 10-1. OPA2210 Layout Example
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
23
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ Simulation Software (Free Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™
simulation software is a free, fully-functional version of the TINA software, preloaded with a library of macro
models in addition to a range of both passive and active models. TINA-TI simulation software provides all the
conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer
the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
Note
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI software from the TINA-TI software folder.
11.1.1.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small, surface-mount integrated circuits
(ICs). The EVM includes footprint options for the following TI packages:
•
•
•
•
•
•
D or U (SOIC-8)
PW (TSSOP-8)
DGK (VSSOP-8)
DBV (SOT23-6, SOT23-5 and SOT23-3)
DCK (SC70-6 and SC70-5)
DRL (SOT563-6)
The DIP Adapter EVM may also be used with terminal strips or may be wired directly to existing circuits.
11.1.1.3 Universal Operational Amplifier EVM
The Universal Op Amp evalutaion module (EVM) is a series of general-purpose, blank circuit boards that simplify
prototyping circuits for a variety of IC package types. The EVM board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
The PDIP, SOIC, VSSOP, TSSOP, and SOT-23 packages are all supported.
Note
These boards are unpopulated, so users must provide their own ICs. TI recommends requesting
several op amp device samples when ordering the Universal Op Amp EVM.
11.1.1.4 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts. These designs
offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of
materials, and measured performance of many useful circuits.
11.1.1.5 WEBENCH® Filter Designer
The WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The
WEBENCH® Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers
and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, the WEBENCH® Filter Designer allows you
to design, optimize, and simulate complete multistage active filter solutions within minutes.
24
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
OPA210, OPA2210
www.ti.com
SBOS924H – SEPTEMBER 2018 – REVISED AUGUST 2021
11.2 Documentation Support
11.2.1 Related Documentation
The following documents are relevant to using the OPAx210 and recommended for reference. All are available
for download at www.ti.com (unless otherwise noted):
•
•
•
•
•
•
•
Texas Instruments, OPA827 Low-Noise, High-Precision, JFET-Input Operational Amplifier data sheet
Texas Instruments, OPA2x11 1.1-nv/√Hz Noise, Low-Power, Precision Operational Amplifier data sheet
Texas Instruments, OPA210, OPA2210, OPA4210 EMI Immunity Performance technical brief
Texas Instruments, OPAx209 2.2-nV/√Hz, Low-Power, 36-V Operational Amplifier data sheet
Texas Instruments, Microcontroller PWM to 12-Bit Analog Out design guide
Texas Instruments, Capacitive Load Drive Solution Using an Isolation Resistor design guide
Texas Instruments, Noise Measurement Post Amp design guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TINA™ is a trademark of DesignSoft, Inc.
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: OPA210 OPA2210
25
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA210IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
26T2
OPA210IDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
26T2
OPA210IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2D5J
OPA210IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2D5J
OPA210IDR
ACTIVE
SOIC
D
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA210
OPA210IDT
ACTIVE
SOIC
D
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA210
OPA2210ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP2210
OPA2210IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1OHQ
OPA2210IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1OHQ
OPA2210IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP2210
OPA2210IDRGR
ACTIVE
SON
DRG
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O2210
OPA2210IDRGT
ACTIVE
SON
DRG
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O2210
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
