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OPA277, OPA2277, OPA4277
SBOS079B – MARCH 1999 – REVISED JUNE 2015
OPAx277 High Precision Operational Amplifiers
1 Features
•
•
•
•
•
•
•
•
•
•
1
Ultralow Offset Voltage: 10 μV
Ultralow Drift: ±0.1 μV/°C
High Open-Loop Gain: 134 dB
High Common-Mode Rejection: 140 dB
High Power Supply Rejection: 130 dB
Low Bias Current: 1-nA maximum
Wide Supply Range: ±2 V to ±18 V
Low Quiescent Current: 800 μA/amplifier
Single, Dual, and Quad Versions
Replaces OP-07, OP-77, and OP-177
2 Applications
•
•
•
•
•
•
•
Transducer Amplifiers
Bridge Amplifiers
Temperature Measurements
Strain Gage Amplifiers
Precision Integrators
Battery-Powered Instruments
Test Equipment
OPAx277 series operational amplifiers operate from
±2-V to ±18-V supplies with excellent performance.
Unlike most operational amplifiers which are specified
at only one supply voltage, the OPAx277 series is
specified for real-world applications; a single limit
applies over the ±5-V to ±15-V supply range. High
performance is maintained as the amplifiers swing to
their specified limits. Because the initial offset voltage
(±20 μV maximum) is so low, user adjustment is
usually not required. However, the single version
(OPA277) provides external trim pins for special
applications.
OPA277 operational amplifiers are easy to use and
free from phase inversion and the overload problems
found in some other operational amplifiers. They are
stable in unity gain and provide excellent dynamic
behavior over a wide range of load conditions. Dual
and quad versions feature completely independent
circuitry for lowest crosstalk and freedom from
interaction, even when overdriven or overloaded.
Device Information(1)
PART NUMBER
OPA277
OPA2277
3 Description
OPA4277
BODY SIZE (NOM)
VSON (8)
4.00 mm × 4.00 mm
SOIC (8)
3.91 mm × 4.90 mm
PDIP (8)
6.35 mm × 9.81 mm
SOIC (14)
3.91 mm × 8.65 mm
PDIP (14)
6.35 mm × 19.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
0.1 Hz to 10 Hz Noise
Noise signal is bandwidth limited to
lie between 0.1Hz and 10Hz.
50nV/div
The OPAx277 series precision operational amplifiers
replace the industry standard OP-177. They offer
improved noise, wider output voltage swing, and are
twice as fast with half the quiescent current. Features
include ultralow offset voltage and drift, low bias
current, high common-mode rejection, and high
power supply rejection. Single, dual, and quad
versions have identical specifications, for maximum
design flexibility.
PACKAGE
1s/div
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA277, OPA2277, OPA4277
SBOS079B – MARCH 1999 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings ...................................... 6
ESD Ratings ............................................................ 6
Recommended Operating Conditions....................... 6
Thermal Information for OPA277 .............................. 6
Thermal Information for OPA2277 ............................ 6
Thermal Information for OPA4277 ............................ 7
Electrical Characteristics for OPAx277P, OPAx277U,
and OPAx277xA ........................................................ 7
6.8 Electrical Characteristics for OPAx277AIDRM ......... 9
6.9 Typical Characteristics ............................................ 12
7
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 19
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Applications ............................................... 20
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
10.3 DFN Package........................................................ 24
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2005) to Revision B
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
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Copyright © 1999–2015, Texas Instruments Incorporated
Product Folder Links: OPA277 OPA2277 OPA4277
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SBOS079B – MARCH 1999 – REVISED JUNE 2015
5 Pin Configuration and Functions
OPA277 P and D Packages
8-Pin PDIP and SOIC
Top View
OPA277 DRM Package
8-Pin VSON
Top View
Offset Trim
1
8
Offset Trim
–In
2
7
V+
+In
3
6
Output
V–
4
5
NC(1)
Offset Trim
1
Pin 1
Indicator
8
Offset Trim
7
V+
−In
2
+In
3
6
Output
V−
4
5
NC
Thermal Pad
on Bottom
(Connect to V−)
Pin Functions: OPA277
PIN
NO.
NAME
I/O
DESCRIPTION
1
Offset Trim
I
Input offset voltage trim (leave floating if not used)
2
–In
I
Inverting input
3
+In
I
Noninverting input
4
V–
—
Negative (lowest) power supply
5
NC
—
No internal connection (can be left floating)
6
Output
O
Output
7
V+
—
Positive (highest) power supply
8
Offset Trim
—
Input offset voltage trim (leave floating if not used)
Copyright © 1999–2015, Texas Instruments Incorporated
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SBOS079B – MARCH 1999 – REVISED JUNE 2015
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OPA2277 P and D Packages
8-Pin PDIP and SOIC
Top View
Out A
1
–In A
2
+In A
3
V–
4
A
B
8
V+
7
Out B
6
–In B
5
+In B
OPA2277 DRM Package
8-Pin VSON
Top View
Out A
1
Pin 1
Indicator
8
Out B
7
V+
−In A
2
+In A
3
6
−In B
V−
4
5
+In B
Thermal Pad
on Bottom
(Connect to V−)
Pin Functions: OPA2277
PIN
I/O
DESCRIPTION
NAME
PDIP,
SOIC NO.
DFN NO.
Out A
1
1
O
Output channel A
–In A
2
2
I
Inverting input channel A
+In A
3
3
I
Noninverting input channel A
V–
4
4
—
+In B
5
5
I
Noninverting input channel B
–In B
6
6
I
Inverting input channel B
Out B
7
8
O
Output channel B
V+
8
7
—
Positive (highest) power supply
4
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Negative (lowest) power supply
Copyright © 1999–2015, Texas Instruments Incorporated
Product Folder Links: OPA277 OPA2277 OPA4277
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SBOS079B – MARCH 1999 – REVISED JUNE 2015
OPA4277 P and D Packages
14 Pins PDIP and SOIC
Top View
Out A
1
14
Out D
–In A
2
13
–In D
A
D
+In A
3
12
+In D
V+
4
11
V–
+In B
5
10
+In C
B
C
–In B
6
9
–In C
Out B
7
8
Out C
Pin Functions: OPA4277
PIN
I/O
DESCRIPTION
NO.
NAME
1
Out A
O
Output channel A
2
–In A
I
Inverting input channel A
3
+In A
I
Noninverting input channel A
4
V+
—
5
+In B
I
Noninverting input channel B
6
–In B
I
Inverting input channel B
7
Out B
O
Output channel B
8
Out C
O
Output channel C
9
–In C
I
Inverting input channel C
10
+In C
I
Noninverting input channel C
11
V–
—
12
+In D
I
Noninverting input channel D
13
–In D
I
Inverting input channel D
14
Out D
O
Output channel D
Positive (highest) power supply
Negative (lowest) power supply
Copyright © 1999–2015, Texas Instruments Incorporated
Product Folder Links: OPA277 OPA2277 OPA4277
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SBOS079B – MARCH 1999 – REVISED JUNE 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
36
V
(V+) +0.7
V
Supply voltage, Vs = (V+) – (V–)
Input voltage
(V–) –0.7
Output short-circuit (2)
Continuous
Operating temperature
–55
125
°C
Junction temperature
150
°C
Lead temperature
300
°C
125
°C
Storage temperature, Tstg
(1)
(2)
–55
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vs = (V+) – (V–)
Specified temperature
MIN
NOM
MAX
4 (±2)
30 (±15)
36 (±18)
V
+85
°C
–40
UNIT
6.4 Thermal Information for OPA277
OPA277
THERMAL METRIC (1)
P (PDIP)
D (SOIC)
DRM (VSON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
49.2
110.1
40.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
39.4
52.2
41.3
°C/W
RθJB
Junction-to-board thermal resistance
26.4
52.3
16.7
°C/W
ψJT
Junction-to-top characterization parameter
15.4
10.4
0.6
°C/W
ψJB
Junction-to-board characterization parameter
26.3
51.5
16.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
3.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information for OPA2277
OPA2277
THERMAL METRIC
(1)
P (PDIP)
D (SOIC)
DRM (VSON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
47.2
107.4
39.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
36.0
45.8
36.9
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBOS079B – MARCH 1999 – REVISED JUNE 2015
Thermal Information for OPA2277 (continued)
OPA2277
THERMAL METRIC (1)
P (PDIP)
D (SOIC)
DRM (VSON)
UNIT
8 PINS
RθJB
Junction-to-board thermal resistance
24.4
47.9
15.4
°C/W
ψJT
Junction-to-top characterization parameter
13.4
5.7
0.4
°C/W
ψJB
Junction-to-board characterization parameter
24.3
47.3
15.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
2.2
°C/W
6.6 Thermal Information for OPA4277
OPA4277
THERMAL METRIC
(1)
D (SOIC)
P (PDIP)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
67.0
66.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
24.1
20.5
°C/W
RθJB
Junction-to-board thermal resistance
22.5
26.8
°C/W
ψJT
Junction-to-top characterization parameter
2.2
2.1
°C/W
ψJB
Junction-to-board characterization parameter
22.1
26.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.7 Electrical Characteristics for OPAx277P, OPAx277U, and OPAx277xA
At TA = 25°C, and RL = 2 kΩ, unless otherwise noted
PARAMETER
TEST
CONDITIONS
OPA277PA, UA
OPA2277PA, UA
OPA4277PA, UA
OPA277P, U
OPA2277P, U
MIN
(1)
MAX
±10
±20
TYP
MIN
UNIT
(1)
MAX
±20
±50
TYP
OFFSET VOLTAGE
V0S
Input Offset Voltage
OPA277P, U
(high-grade,
single)
Input Offset
Voltage Over
Temperature
OPA2277P, U
(high-grade, dual)
µV
±30
TA = –40°C to
85°C
±50
µV
All PA, UA,
Versions
±100
AIDRM Versions
OPA277P, U
(high-grade,
single)
dV0S/dT
Input Offset
Voltage Drift
OPA2277P, U
(high-grade, dual)
TA = –40°C to
85°C
±0.1
±0.15
±0.1
±0.25
All PA, UA,
AIDRM Versions
±0.15
vs Time
Input Offset
Voltage: (all
models)
vs Power Supply
(PSRR)
Channel Separation (dual, quad)
(1)
(2)
µV/°C
0.2
VS = ±2 V to ±18
V
±0.3
See
(2)
±1
µV/mo
±1
µV/V
TA = –40°C to
85°C
DC
±0.5
See
(2)
±0.5
0.1
±1
See
(2)
µV/V
VS = ±15 V
Specifications are the same as OPA277P, U.
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Electrical Characteristics for OPAx277P, OPAx277U, and OPAx277xA (continued)
At TA = 25°C, and RL = 2 kΩ, unless otherwise noted
PARAMETER
TEST
CONDITIONS
OPA277PA, UA
OPA2277PA, UA
OPA4277PA, UA
OPA277P, U
OPA2277P, U
MIN
TYP (1)
MAX
±1
MIN
UNIT
TYP
(1)
MAX
See
(2)
±2.8
INPUT BIAS CURRENT
IB
Input Bias Current
TA = –40°C to
85°C
±0.5
IOS
Input Offset Current
TA = –40°C to
85°C
±0.5
±2
±4
±1
See
(2)
±2.8
±2
±4
nA
nA
NOISE
Input Voltage Noise, f = 0.1 to 10 Hz
en
in
Input Voltage
Noise Density
0.22
See
(2)
f = 10 Hz
12
See
(2)
f = 100 Hz
8
See
(2)
f = 1 kHz
8
See
(2)
f = 10 kHz
8
See
(2)
0.2
See
(2)
Current Noise Density, f = 1 kHz
µVPP
nV/√Hz
pA/√Hz
INPUT VOLTAGE RANGE
VCM
CMRR
Common-Mode Voltage Range
Common-Mode Rejection
(V–)+2
VCM = (V–) +2 V
to (V+) –2 V
130
TA = –40°C to
85°C
128
(V+)–2
140
See
(2)
115
See
See
(2)
V
(2)
dB
115
INPUT IMPEDANCE
Differential
100 || 3
Common-Mode
See
(2)
MΩ || pF
GΩ || pF
VCM = (V–) +2 V
to (V+) –2 V
250 || 3
See
(2)
VO = (V–)+0.5 V
to
(V+)–1.2 V,
RL = 10 kΩ
140
See
(2)
OPEN-LOOP GAIN
AOL
Open-Loop Voltage Gain
VO = (V–)+1.5 V
to
(V+)–1.5 V,
RL = 2 kΩ
VO = (V–)+1.5 V
to
(V+)–1.5 V,
RL = 2 kΩ
dB
126
134
126
See
(2)
See
(2)
See
(2)
dB
TA = –40°C to
85°C
FREQUENCY RESPONSE
GBW
Gain-Bandwidth Product
SR
Slew Rate
(2)
MHz
See
(2)
V/µs
VS = ±15 V,
G = 1,
10-V Step
14
See
16
See
(2)
Overload Recovery Time
VIN × G = VS
3
See
(2)
Total Harmonic Distortion + Noise
1 kHz, G = 1,
VO = 3.5 Vrms
See
(2)
0.1%
8
See
(2)
Settling Time
THD+N
1
0.8
0.01%
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0.002%
µs
µs
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SBOS079B – MARCH 1999 – REVISED JUNE 2015
Electrical Characteristics for OPAx277P, OPAx277U, and OPAx277xA (continued)
At TA = 25°C, and RL = 2 kΩ, unless otherwise noted
PARAMETER
OPA277PA, UA
OPA2277PA, UA
OPA4277PA, UA
OPA277P, U
OPA2277P, U
TEST
CONDITIONS
MIN
TYP (1)
MAX
MIN
TYP
UNIT
(1)
MAX
OUTPUT
VO
Voltage Output
ISC
Short-Circuit Current
CLOAD
Capacitive Load Drive
ZO
Open-loop output impedance
RL = 10 kΩ
(V–)+0.5
(V+)–1.2
See
(2)
See
(2)
TA = –40°C to
+85°C
(V–)+0.5
(V+)–1.2
See
(2)
See
(2)
RL = 2 kΩ
(V–)+1.5
(V+)–1.5
See
(2)
See
(2)
TA = –40°C to
+85°C
(V–)+1.5
(V+)–1.5
See
(2)
See
(2)
±35
See
f = 1 MHz
V
See
(2)
mA
See
(2)
Ω
(3)
40
POWER SUPPLY
VS
Specified Voltage Range
±5
Operating Voltage Range
±2
IO = 0
IQ
±15
Quiescent Current (per amplifier)
±18
±790
TA = –40°C to
85°C
See
(2)
See
(2)
V
See
(2)
See
(2)
V
See
(2)
See
(2)
±825
See
±900
(2)
µA
TEMPERATURE RANGE
Specified Range
–40
Operating Range
(3)
–55
85
125
See
(2)
See
(2)
°C
See
(2)
See
(2)
°C
See Typical Characteristics
6.8 Electrical Characteristics for OPAx277AIDRM
At TA = 25°C, and RL = 2 kΩ, unless otherwise noted
PARAMETER
TEST CONDITIONS
OPA277AIDRM
OPA2277AIDRM
MIN
UNIT
TYP (1)
MAX
±35
±100
OFFSET VOLTAGE
V0S
Input Offset Voltage
µV
OPA277P, U (high-grade,
single)
Input Offset Voltage
Over Temperature
OPA2277P, U (high-grade,
dual)
TA = –40°C to 85°C
µV
All PA, UA, Versions
AIDRM Versions
±165
OPA277P, U (high-grade,
single)
dV0S/dT
Input Offset Voltage
Drift
OPA2277P, U (high-grade,
dual)
TA = –40°C to 85°C
All PA, UA, AIDRM
Versions
±0.15
vs Time
Input Offset Voltage:
(all models)
vs Power Supply (PSRR)
Channel Separation (dual, quad)
(1)
(2)
µV/°C
VS = ±2 V to ±18 V
See
(2)
See
(2)
See
(2)
TA = –40°C to 85°C
DC
±1
µV/mo
±1
±1
µV/V
µV/V
VS = ±15 V
Specifications are the same as OPA277P, U.
Copyright © 1999–2015, Texas Instruments Incorporated
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Electrical Characteristics for OPAx277AIDRM (continued)
At TA = 25°C, and RL = 2 kΩ, unless otherwise noted
PARAMETER
OPA277AIDRM
OPA2277AIDRM
TEST CONDITIONS
MIN
TYP (1)
UNIT
MAX
INPUT BIAS CURRENT
IB
Input Bias Current
TA = –40°C to 85°C
IOS
Input Offset Current
TA = –40°C to 85°C
±2.8
±4
±2.8
±4
nA
nA
NOISE
See
(2)
f = 10 Hz
See
(2)
f = 100 Hz
See
(2)
f = 1 kHz
See
(2)
f = 10 kHz
See
(2)
See
(2)
Input Voltage Noise, f = 0.1 to 10 Hz
Input Voltage Noise
Density
en
in
Current Noise Density, f = 1 kHz
µVPP
nV/√Hz
pA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-Mode Voltage Range
CMRR
See
Common-Mode Rejection
(2)
VCM = (V–) +2 V to
(V+) –2 V
115
TA = –40°C to 85°C
115
See
(2)
V
See
(2)
See
(2)
MΩ || pF
VCM = (V–) +2 V to
(V+) –2 V
See
(2)
GΩ || pF
VO = (V–)+0.5 V to
(V+)–1.2 V,
RL = 10 kΩ
See
(2)
See
(2)
dB
INPUT IMPEDANCE
Differential
Common-Mode
OPEN-LOOP GAIN
AOL
Open-Loop Voltage Gain
VO = (V–)+1.5 V to
(V+)–1.5 V,
RL = 2 kΩ
VO = (V–)+1.5 V to
(V+)–1.5 V,
RL = 2 kΩ
dB
See
(2)
See
(2)
dB
TA = –40°C to 85°C
FREQUENCY RESPONSE
GBW
Gain-Bandwidth Product
See
(2)
MHz
SR
Slew Rate
See
(2)
V/µs
VS = ±15 V,
G = 1,
10-V Step
See
(2)
See
(2)
Overload Recovery Time
VIN × G = VS
See
(2)
Total Harmonic Distortion + Noise
1 kHz, G = 1,
VO = 3.5 Vrms
See
(2)
0.1%
Settling Time
THD+N
0.01%
µs
µs
OUTPUT
See
(2)
See
(2)
See
(2)
See
(2)
RL = 2 kΩ
See
(2)
See
(2)
TA = –40°C to +85°C
See
(2)
See
(2)
RL = 10 kΩ
VO
Voltage Output
ISC
Short-Circuit Current
CLOAD
Capacitive Load Drive
ZO
Open-loop output impedance
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TA = –40°C to +85°C
f = 1 MHz
V
See
(2)
mA
See
(2)
Ω
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Electrical Characteristics for OPAx277AIDRM (continued)
At TA = 25°C, and RL = 2 kΩ, unless otherwise noted
PARAMETER
OPA277AIDRM
OPA2277AIDRM
TEST CONDITIONS
MIN
TYP (1)
UNIT
MAX
POWER SUPPLY
VS
IQ
Specified Voltage Range
See
(2)
See
(2)
V
Operating Voltage Range
See
(2)
See
(2)
V
See
(2)
See
(2)
See
(2)
°C
See
(2)
°C
IO = 0
Quiescent Current (per amplifier)
See
TA = –40°C to 85°C
(2)
µA
TEMPERATURE RANGE
Specified Range
Operating Range
See
(2)
See
(2)
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6.9 Typical Characteristics
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
140
140
G
120
CL = 0
CL = 1500pF
0
–60
φ
60
–90
40
–120
20
–150
0
–180
PSR, CMR (dB)
80
+PSR
–PSR
–30
Phase (°)
AOL (dB)
100
120
100
80
CMR
60
40
20
–20
0
0.1
1
10
100
1k
10k
100k
1M
10M
0.1
1
10
Frequency (Hz)
100
1k
10k
100k
1M
Frequency (Hz)
Figure 1. Open-Loop Gain and Phase vs Frequency
Figure 2. Power Supply and Common-Mode Rejection vs
Frequency
INPUT NOISE AND CURRENT NOISE
SPECTRAL DENSITY vs FREQUENCY
Noise signal is bandwidth limited to
lie between 0.1Hz and 10Hz.
Current Noise
50nV/div
Voltage Noise (nV/√Hz)
Current Noise (fA/√Hz)
1000
100
Voltage Noise
10
1
1
0.1
10
100
1k
1s/div
Frequency (Hz)
Figure 3. Input Noise and Current Noise Spectral Density
vs Frequency
Figure 4. Input Noise Voltage vs Time
140
1
120
THD+Noise (%)
Channel Separation (dB)
VOUT = 3.5Vrms
100
Dual and quad devices. G = 1,
all channels. Quad measured
channel A to D or B to C —other
combinations yield similar or
improved rejection.
80
60
0.1
G = 10, RL = 2kΩ, 10kΩ
0.01
G = 1, RL = 2kΩ, 10kΩ
0.001
40
10
100
1k
10k
100k
1M
10
100
Frequency (Hz)
Figure 5. Channel Separation vs Frequency
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1k
10k
100k
Frequency (Hz)
Figure 6. Total Harmonic Distortion + Noise vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
35
16
Typical distribution
of packaged units.
Single, dual, and
quad included.
12
10
8
6
4
25
20
15
10
5
2
0
0
0
– 50– 45– 40– 35– 30– 25– 20– 15– 10– 5 0 5 10 15 20 25 30 35 40 45 50
Offset Voltage (µV)
0.1
0.2
0.3
0.5
0.6
0.7
0.8
0.9
1.0
Figure 8. Offset Voltage Drift Production Distribution
3
160
2
150
CMR
AOL, CMR, PSR (dB)
1
0
–1
140
AOL
130
PSR
120
110
–2
100
–75
–3
15
30
45
60
75
90
105
120
–50
–25
0
25
50
75
100
125
Temperature ( °C)
Time from Power Supply Turn-On (s)
Figure 9. Warm-Up Offset Voltage Drift
Figure 10. AOL, CMR, PSR vs Temperature
1000
100
4
950
90
3
900
80
Quiescent Current (µA)
5
2
1
0
–1
–2
Curves represent typical
production units.
–3
–4
–5
–75
–50
–25
0
25
50
75
100
125
70
850
±I Q
800
50
–ISC
700
40
+ISC
650
30
600
20
550
10
500
–75
0
–50
–25
0
25
50
75
100
125
Temperature (°C)
Temperature ( °C)
Figure 11. Input Bias Current vs Temperature
60
750
Short-Circuit Current (mA)
0
Input Bias Current (nA)
0.4
Offset Voltage (µV/°C)
Figure 7. Offset Voltage Production Distribution
Offset Voltage Change (µV)
Typical distribution
of packaged units.
Single, dual, and
quad included.
30
Percent of Amplifiers (%)
Percent of Amplifiers (%)
14
Figure 12. Quiescent Current and Short-Circuit Current vs
Temperature
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
2.0
2.0
Curve shows normalized change in
bias current with respect to VS = ±10V
(+20V). Typical I B may range from
–0.5nA to +0.5nA at V S = ±10V.
1.5
1.0
VS = ±5V
0.5
0.0
∆IB (nA)
∆IB (nA)
1.0
Curve shows normalized change in bias current
with respect to VCM = 0V. Typical I B may range
from –05.nA to +0.5nA at V CM = 0V.
1.5
VCM = 0V
0.5
0.0
–0.5
–0.5
–1.0
–1.0
–1.5
–1.5
VS = ±15V
–2.0
–2.0
0
5
10
15
20
25
30
35
40
–15
–10
Supply Voltage (V)
Figure 13. Change in Input Bias Current vs
Power Supply Voltage
5
10
15
100
10V step
CL = 1500pF
per amplifier
Settling Time (µs)
900
800
700
50
0.01%
0.1%
20
600
10
500
0
±5
±10
±15
±20
±1
±10
Supply Voltage (V)
±100
Gain (V/V)
Figure 15. Quiescent Current vs Supply Voltage
Figure 16. Settling Time vs Closed-Loop Gain
30
(V+)
(V+) – 1
Output Voltage Swing (V)
VS = ±15V
25
Output Voltage (V PP)
0
Figure 14. Change in Input Bias Current vs
Common-Mode Voltage
1000
Quiescent Current (µA)
–5
Common-Mode Voltage (V)
20
15
10
VS = ±5V
5
–55°C
(V+) – 2
(V+) – 3
125°C
(V+) – 4
25°C
(V+) – 5
(V–) + 5
25°C
125°C
(V–) + 4
(V–) + 3
(V–) + 2
–55°C
(V–) + 1
0
(V–)
1k
10k
100k
1M
0
±5
Frequency (Hz)
Figure 17. Maximum Output Voltage vs Frequency
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±10
±15
±20
±25
±30
Output Current (mA)
Figure 18. Output Voltage Swing vs Output Current
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Typical Characteristics (continued)
At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
60
Gain = –1
50
Overshoot (%)
40
2V/div
Gain = +1
30
20
Gain = ±10
10
0
10
100
1k
10k
100k
10µs/div
Load Capacitance (pF)
Figure 20. Large-Signal Step Response
G = 1, CL = 1500 pF, VS = ±15 V
20mV/div
20mV/div
Figure 19. Small-Signal Overshoot vs Load Capacitance
1µs/div
1µs/div
Figure 21. Small-Signal Step Response
G= +1, CL = 0, VS = ±15 V
Figure 22. Small-Signal Step Response
G= 1, CL = 1500 pF, VS = ±15 V
100
70
50
Impedance (:)
30
20
10
7
5
3
2
1
1k
10k
100k
Frequency (Hz)
1M
Figure 23. Open-Loop Output Impedance
VS = ±15 V
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7 Detailed Description
7.1 Overview
The OPAx277 series precision operational amplifiers replace the industry standard OP-177. They offer improved
noise, wider output voltage swing, and are twice as fast with half the quiescent current. Features include ultralow
offset voltage and drift, low bias current, high common-mode rejection, and high power supply rejection. Single,
dual, and quad versions have identical specifications, for maximum design flexibility.
7.2 Functional Block Diagram
Input Offset
Adjust
(OPA277 only)
+IN
-IN
+
±
Input Offset
Adjust
(OPA277 only)
Output
Compensation
7.3 Feature Description
The OPAx277 series is unity-gain stable and free from unexpected output phase reversal, making it easy to use
in a wide range of applications. Applications with noisy or high-impedance power supplies may require
decoupling capacitors close to the device pins. In most cases 0.1-μF capacitors are adequate.
The OPAx277 series has low offset voltage and drift. To achieve highest performance, the circuit layout and
mechanical conditions should be optimized. Offset voltage and drift can be degraded by small thermoelectric
potentials at the operational amplifier inputs. Connections of dissimilar metals generate thermal potential, which
can degrade the ultimate performance of the OPAx277 series. These thermal potentials can be made to cancel
by assuring that they are equal in both input terminals.
• Keep the thermal mass of the connections to the two input terminals similar
• Locate heat sources as far as possible from the critical input circuitry
• Shield operational amplifier and input circuitry from air currents, such as cooling fans
7.3.1 Operating Voltage
OPAx277 series operational amplifiers operate from ±2-V to ±18-V supplies with excellent performance. Unlike
most operational amplifiers, which are specified at only one supply voltage, the OPA277 series is specified for
real-world applications; a single limit applies over the ±5-V to ±15-V supply range. This allows a customer
operating at VS = ±10 V to have the same assured performance as a customer using ±15-V supplies. In addition,
key parameters are assured over the specified temperature range, –40°C to 85°C. Most behavior remains
unchanged through the full operating voltage range (±2 V to ±18 V). Parameters which vary significantly with
operating voltage or temperature are shown in Typical Characteristics.
7.3.2 Offset Voltage Adjustment
The OPAx277 series is laser-trimmed for low offset voltage and drift, so most circuits do not require external
adjustment. However, offset voltage trim connections are provided on pins 1 and 8. Offset voltage can be
adjusted by connecting a potentiometer, as shown in Figure 24. Only use this adjustment to null the offset of the
operational amplifier. This adjustment should not be used to compensate for offsets created elsewhere in a
system, because this can introduce additional temperature drift.
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Feature Description (continued)
V+
Trim Range: Exceeds
Offset Voltage Specification
0.1µF
20kΩ
7
1
2
8
3
0.1µF
OPA277
4
6
OPA277 single op amp only.
Use offset adjust pins only to null
offset voltage of op amp—see text.
V–
Figure 24. OPA277 Offset Voltage Trim Circuit
7.3.3 Input Protection
The inputs of the OPAx277 series are protected with 1-kΩ series input resistors and diode clamps. The inputs
can withstand ±30-V differential inputs without damage. The protection diodes conduct current when the inputs
are over-driven. This may disturb the slewing behavior of unity-gain follower applications, but will not damage the
operational amplifier.
1 k
+
1 k
±
Figure 25. OPAx277 Input Protection
7.3.4 Input Bias Current Cancellation
The input stage base current of the OPAx277 series is internally compensated with an equal and opposite
cancellation circuit. The resulting input bias current is the difference between the input stage base current and
the cancellation current. This residual input bias current can be positive or negative.
When the bias current is canceled in this manner, the input bias current and input offset current are
approximately the same magnitude. As a result, it is not necessary to use a bias current cancellation resistor, as
is often done with other operational amplifiers (see Figure 26). A resistor added to cancel input bias current
errors may actually increase offset voltage and noise.
R2
R2
R1
R1
Op Amp
OPA277
RB = R2 || R1
No bias current
cancellation resistor
(see text)
(a)
(b)
Conventional op amp with external bias
current cancellation resistor.
OPA277 with no external bias current
cancellation resistor.
Figure 26. Input Bias Current Cancellation
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Feature Description (continued)
7.3.5 EMI Rejection Ratio (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many operational amplifiers is a change in the offset voltage as a
result of RF signal rectification. An operational amplifier that is more efficient at rejecting this change in offset as
a result of EMI has a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in
many ways, but this report provides the EMIRR IN+, which specifically describes the EMIRR performance when
the RF signal is applied to the noninverting input pin of the operational amplifier. In general, only the noninverting
input is tested for EMIRR for the following three reasons:
1. Operational amplifier input pins are known to be the most sensitive to EMI, and typically rectify RF signals
better than the supply or output pins.
2. The noninverting and inverting operational amplifier inputs have symmetrical physical layouts and exhibit
nearly matching EMIRR performance.
3. EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input terminal
can be isolated on a printed circuit board (PCB). This isolation allows the RF signal to be applied directly to
the noninverting input terminal with no complex interactions from other components or connecting PCB
traces.
A more formal discussion of the EMIRR IN+ definition and test method is provided in application report
SBOA128, EMI Rejection Ratio of Operational Amplifiers, available for download at www.ti.com. The EMIRR IN+
of the OPA277 is plotted versus frequency as shown in Figure 27.
120
EMIRR IN+ (db)
PRF = -10 dbm
VS = r2.5 V
100 VCM = 0 V
80
60
40
20
0
10
100
1k
Frequency (MHz)
10k
Figure 27. OPA277 EMIRR IN+ vs Frequency
If available, any dual and quad operational amplifier device versions have nearly similar EMIRR IN+
performance. The OPA277 unity-gain bandwidth is 1 MHz. EMIRR performance below this frequency denotes
interfering signals that fall within the operational amplifier bandwidth.
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Feature Description (continued)
Table 1 shows the EMIRR IN+ values for the OPA277 at particular frequencies commonly encountered in realworld applications. Applications listed in Table 1 may be centered on or operated near the particular frequency
shown. This information may be of special interest to designers working with these types of applications, or
working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,
and medical (ISM) radio band.
Table 1. OPA277 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION/ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite/space operation, weather, radar, UHF
59.1 dB
900 MHz
GSM, radio com/nav./GPS (to 1.6 GHz), ISM, aeronautical mobile,
UHF
77.9 dB
1.8 GHz
GSM, mobile personal comm. broadband, satellite, L-band
91.3 dB
2.4 GHz
802.11b/g/n, Bluetooth™, mobile personal comm., ISM, amateur
radio/satellite, S-band
93.3 dB
3.6 GHz
Radiolocation, aero comm./nav., satellite, mobile, S-band
105.9 dB
5.0 GHz
802.11a/n, aero comm./nav., mobile comm., space/satellite
operation, C-band
107.5 dB
7.3.5.1 EMIRR IN+ Test Configuration
Figure 28 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the
operational amplifier noninverting input terminal using a transmission line. The operational amplifier is configured
in a unity gain buffer topology with the output connected to a low-pass filter (LPF) and a digital multimeter
(DMM). Note that a large impedance mismatch at the operational amplifier input causes a voltage reflection;
however, this effect is characterized and accounted for when determining the EMIRR IN+. The resulting dc offset
voltage is sampled and measured by the multimeter. The LPF isolates the multimeter from residual RF signals
that may interfere with multimeter accuracy. Refer to SBOA128 for more details.
Ambient temperature: 25Û&
+VS
±
50
Low-Pass Filter
+
RF source
DC Bias: 0 V
Modulation: None (CW)
Frequency Sweep: 201 pt. Log
-VS
Sample /
Averaging
Not shown: 0.1 µF and 10 µF
supply decoupling
Digital Multimeter
Figure 28. EMIRR IN+ Test Configuration Schematic
7.4 Device Functional Modes
The OPAx277 has a single functional mode and is operational when the power-supply voltage is greater than 4 V
(±2 V). The maximum power supply voltage for the OPAx277 is 36 V (±18 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx277 family offers outstanding dc precision and ac performance. These devices operate up to 36-V
supply rails and offer ultralow offset voltage and offset voltage drift, as well as 1-MHz bandwidth and high
capacitive load drive. These features make the OPAx277 a robust, high-performance operational amplifier for
high-voltage industrial applications.
8.2 Typical Applications
8.2.1 Second-Order Lowpass Filter
2.25 k
2.25 k
1.13 k
Input
1 nF
±
4 nF
Output
+
Figure 29. Second-Order Lowpass Filter
8.2.1.1 Design Requirements
•
Gain = 1 V/V
•
•
Lowpass cutoff frequency = 50 kHz
–40 db/dec filter response
•
Maintain less than 3-dB gain peaking in the gain versus frequency response
8.2.1.2 Detailed Design Procedure
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
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Typical Applications (continued)
8.2.1.3 Application Curve
20
Gain (db)
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 30. OPA277 Second-Order 50-kHz, Lowpass Filter
8.2.2 Load Cell Amplifier
V+
1/2
OPA2277
VOUT = (V1 – V2)(1 +
R2
R1
)
R2
V–
R–∆R
Load
Cell
V1
R+∆R
V+
R+∆R
V2
R1
1/2
OPA2277
R–∆R
V–
R2
R1
For integrated solution see: INA126, INA2126 (dual)
INA125 (on-board reference)
INA122 (single-supply)
Figure 31. Load Cell Amplifier
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Typical Applications (continued)
8.2.3 Thermocouple Low-Offset, Low-Drift Loop Measurement With Diode Cold Junction Compensation
IREG ∼ 1mA
5V
12
V+
Type J
VLIN
1/2
OPA2277
13
RF
10kΩ
4
R
412Ω
+
VIN
1
IR1
3
11
VREG
10
V+
RG
RG
1250Ω
RF
10kΩ
14
IR2
XTR105
B
E
RG
9
8
IO
1/2
OPA2277
1kΩ
2
25Ω
7
IRET
V–
50Ω
–
VIN
+
–
IO = 4mA + (V IN – VIN) 40
RG
6
RCM = 1250Ω
(G = 1 +
2RF
= 50)
R
0.01µF
Figure 32. Thermocouple Low-Offset, Low-Drift Loop Measurement With Diode Cold Junction
Compensation
9 Power Supply Recommendations
The OPAx277 is specified for operation from 4 V to 36 V (±2 V to ±18 V); many specifications apply from –40°C
to +85°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are
presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 36 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and operational
amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
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Layout Guidelines (continued)
•
•
•
•
•
•
•
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
Circuit Board Layout Techniques, SLOA089.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible. As shown in Layout Example, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
(DFN package only) The leadframe die pad should be soldered to a thermal pad on the PCB. The mechanical
drawings located at the end of this data sheet list the physical dimensions for the package and pad.
(DFN package only) Soldering the exposed pad significantly improves board-level reliability during
temperature cycling, key push, package shear, and similar board-level tests. Even with applications that have
low-power dissipation, the exposed pad must be soldered to the PCB to provide structural integrity and long
term reliability.
10.2 Layout Example
+
VIN
VOUT
RG
RF
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
Offset trim
Offset trim
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
RG
Use low-ESR,
ceramic bypass
capacitor
GND
GND
Use low-ESR, ceramic
bypass capacitor
VOUT
VS±
Ground (GND) plane on another layer
Figure 33. OPA277 Layout Example for the Noninverting Configuration
Copyright © 1999–2015, Texas Instruments Incorporated
Product Folder Links: OPA277 OPA2277 OPA4277
Submit Documentation Feedback
23
OPA277, OPA2277, OPA4277
SBOS079B – MARCH 1999 – REVISED JUNE 2015
www.ti.com
10.3 DFN Package
The OPAx277 series uses the 8-lead DFN (also known as SON), a QFN package with contacts on only two sides
of the package bottom. This leadless, near-chip-scale package maximizes board space and enhances thermal
and electrical characteristics through an exposed pad.
DFN packages are physically small, have a smaller routing area, improved thermal performance, and improved
electrical parasitics, with a pinout scheme that is consistent with other commonly-used packages, such as SO
and MSOP. Additionally, the absence of external leads eliminates bent-lead issues.
The DFN package can be easily mounted using standard printed-circuit-board (PCB) assembly techniques. See
QFN/SON PCB Attachment (SLUA271) and Quad Flatpack No-Lead Logic Packages (SCBA017), both available
for download at www.ti.com.
The exposed leadframe die pad on the bottom of the package should be connected to V–.
24
Submit Documentation Feedback
Copyright © 1999–2015, Texas Instruments Incorporated
Product Folder Links: OPA277 OPA2277 OPA4277
OPA277, OPA2277, OPA4277
www.ti.com
SBOS079B – MARCH 1999 – REVISED JUNE 2015
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 WEBENCH Filter Designer Tool
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
11.1.1.2 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.3 TI Precision Designs
The OPA277 is featured in several TI Precision Designs, available online at
http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s
precision analog applications experts and offer the theory of operation, component selection, simulation,
complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• QFN/SON PCB Attachment, SLUA271
• Quad Flatpack No-Lead Logic Packages, SCBA017
• EMI Rejection Ratio of Operational Amplifiers, SBOA128
• Circuit Board Layout Techniques, SLOA089
11.2.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA277
Click here
Click here
Click here
Click here
Click here
OPA2277
Click here
Click here
Click here
Click here
Click here
OPA4277
Click here
Click here
Click here
Click here
Click here
Copyright © 1999–2015, Texas Instruments Incorporated
Product Folder Links: OPA277 OPA2277 OPA4277
Submit Documentation Feedback
25
OPA277, OPA2277, OPA4277
SBOS079B – MARCH 1999 – REVISED JUNE 2015
www.ti.com
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
Submit Documentation Feedback
Copyright © 1999–2015, Texas Instruments Incorporated
Product Folder Links: OPA277 OPA2277 OPA4277
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2277AIDRMT
ACTIVE
VSON
DRM
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
BHZ
OPA2277AIDRMTG4
ACTIVE
VSON
DRM
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
BHZ
OPA2277P
ACTIVE
PDIP
P
8
50
RoHS & Green
Call TI
N / A for Pkg Type
OPA2277P
OPA2277PA
ACTIVE
PDIP
P
8
50
RoHS & Green
Call TI
N / A for Pkg Type
OPA2277P
A
OPA2277PAG4
ACTIVE
PDIP
P
8
50
RoHS & Green
Call TI
N / A for Pkg Type
OPA2277P
A
OPA2277U
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-3-260C-168 HR
OPA2277U/2K5
ACTIVE
SOIC
D
8
2500
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
OPA
2277U
OPA2277U/2K5G4
ACTIVE
SOIC
D
8
2500
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
OPA
2277U
OPA2277UA
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
OPA
2277U
A
OPA2277UA/2K5
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
OPA
2277U
A
OPA2277UA/2K5E4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
OPA
2277U
A
OPA2277UAE4
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
OPA
2277U
A
OPA2277UAG4
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
OPA
2277U
A
OPA2277UG4
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
OPA
2277U
OPA277AIDRMR
ACTIVE
VSON
DRM
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Addendum-Page 1
OPA
2277U
NSS
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA277AIDRMT
ACTIVE
VSON
DRM
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
OPA277P
ACTIVE
PDIP
P
8
50
RoHS & Green
Call TI
N / A for Pkg Type
OPA277P
OPA277PA
ACTIVE
PDIP
P
8
50
RoHS & Green
Call TI
N / A for Pkg Type
OPA277P
A
OPA277PAG4
ACTIVE
PDIP
P
8
50
RoHS & Green
Call TI
N / A for Pkg Type
OPA277P
A
OPA277U
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-3-260C-168 HR
OPA
277U
OPA277U/2K5
ACTIVE
SOIC
D
8
2500
RoHS & Green
Call TI
Level-3-260C-168 HR
OPA
277U
OPA277U/2K5G4
ACTIVE
SOIC
D
8
2500
RoHS & Green
Call TI
Level-3-260C-168 HR
OPA
277U
OPA277UA
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
OPA
277U
A
OPA277UA/2K5
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
OPA
277U
A
OPA277UA/2K5E4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
OPA
277U
A
OPA277UAE4
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
OPA
277U
A
OPA277UAG4
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-3-260C-168 HR
-40 to 85
OPA
277U
A
OPA277UG4
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-3-260C-168 HR
OPA4277PA
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
OPA4277UA
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU-DCC
Level-3-260C-168 HR
-40 to 85
OPA4277UA
OPA4277UA/2K5
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU-DCC
Level-3-260C-168 HR
-40 to 85
OPA4277UA
Addendum-Page 2
NSS
OPA
277U
OPA4277PA
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
7-Oct-2021
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
OPA4277UA/2K5E4
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU-DCC
Level-3-260C-168 HR
-40 to 85
OPA4277UA
OPA4277UAE4
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU-DCC
Level-3-260C-168 HR
-40 to 85
OPA4277UA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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