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OPA320, OPA2320, OPA320S, OPA2320S
SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
OPAx320x Precision, 20-MHz, 0.9-pA, Low-Noise, RRIO,
CMOS Operational Amplifier With Shutdown
1 Features
3 Description
•
The OPA320 (single) and OPA2320 (dual) are a new
generation
of
precision,
low-voltage
CMOS
operational amplifiers optimized for very low noise
and wide bandwidth while operating on a low
quiescent current of only 1.45 mA.
1
•
•
•
•
•
•
•
•
•
Precision with Zero-Crossover Distortion:
– Low Offset Voltage: 150 µV (Maximum)
– High CMRR: 114 dB
– Rail-to-Rail I/O
Low Input Bias Current: 0.9 pA (Maximum)
Low Noise: 7 nV/√Hz at 10 kHz
Wide Bandwidth: 20 MHz
Slew Rate: 10 V/µs
Quiescent Current: 1.45 mA/Ch
Single-Supply Voltage Range: 1.8 V to 5.5 V
OPA320S and OPA2320S:
– IQ in Shutdown Mode: 0.1 µA
Unity-Gain Stable
Small Packages:
– SOT-23, VSSOP, SON, and SOIC
The OPA320 features a linear input stage with zerocrossover distortion that delivers excellent commonmode rejection ratio (CMRR) of typically 114 dB over
the full input range. The input common mode range
extends 100 mV beyond the negative and positive
supply rails. The output voltage typically swings within
10 mV of the rails.
In addition, the OPAx320 has a wide supply voltage
range from 1.8 V to 5.5 V with excellent PSRR
(106 dB) over the entire supply range, making them
suitable for precision, low-power applications that run
directly from batteries without regulation.
2 Applications
•
•
•
•
•
•
•
•
The OPA320 series is ideal for low-power, singlesupply applications. Low-noise (7 nV/√Hz) and highspeed operation also make them well-suited for
driving sampling analog-to-digital converters (ADCs).
Other applications include signal conditioning and
sensor amplification.
High-Z Sensor Signal Conditioning
Transimpedance Amplifiers
Test and Measurement Equipment
Programmable Logic Controllers (PLCs)
Motor Control Loops
Communications
Input/Output ADC/DAC Buffers
Active Filters
The OPA320 (single version) is available in a 5-pin
SOT23 package; the OPA320S shutdown single
version is available in an 6-pin SOT23 package. The
dual OPA2320 is offered in 8-pin SOIC, VSSOP, and
SON packages, and the OPA2320S (dual with
shutdown) in a 10-pin VSSOP package.
Device Information(1)
Block Diagram
PART NUMBER
V+
Low Noise Charge
Pump
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
OPA320S
SOT-23 (6)
2.90 mm × 1.60 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.91 mm
SON (10)
3.00 mm × 3.00 mm
VSSOP (10)
3.00 mm × 3.00 mm
OPA2320
OPA2320S
Bias Circuitry
PACKAGE
OPA320
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
+IN
-IN
OUT
Input Stage Load
Bias Circuitry
VCopyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA320, OPA2320, OPA320S, OPA2320S
SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
1
1
1
2
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information: OPA320 and OPA320S .......... 6
Thermal Information: OPA2320 ................................ 7
Thermal Information: OPA2320S.............................. 7
Electrical Characteristics........................................... 7
Typical Characteristics ............................................ 10
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 21
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application .................................................. 26
9 Power Supply Recommendations...................... 28
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 28
11 Device and Documentation Support ................. 29
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support ....................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
30
30
30
30
30
30
31
12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (June 2013) to Revision F
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed package families throughout data sheet: DFN to SON, MSOP to VSSOP, and SO to SOIC ................................ 1
Changes from Revision D (November 2011) to Revision E
Page
•
Deleted Ordering Information table ........................................................................................................................................ 1
•
Changed Shutdown, VIH and VIL parameters in Electrical Characteristics table .................................................................... 8
•
Added Figure 29 and Figure 30............................................................................................................................................ 13
•
Added Figure 31 and Figure 32............................................................................................................................................ 14
Changes from Revision C (August 2011) to Revision D
•
Page
Changed status of OPA2320 SO-8 (D) to production data from product preview. ................................................................ 1
Changes from Revision B (March 2010) to Revision C
Page
•
Deleted D (SO-8) package pinout drawing from Pin Configurations and Functions .............................................................. 4
•
Changed names of pins 2 and 6 for DGS (MSOP-10) package ........................................................................................... 5
•
Added values to Thermal Information tables, moved to new page, and updated format....................................................... 6
•
Added SHDN value to Electrical Characteristics condition line.............................................................................................. 7
•
Added new test condition row for Input Bias Current Over Temperature parameter ............................................................. 7
•
Changed test condition for Phase Margin parameter in Electrical Characteristics ................................................................ 8
•
Added test condition to Short-Circuit Current parameter in Electrical Characteristics ........................................................... 8
2
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Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: OPA320 OPA2320 OPA320S OPA2320S
OPA320, OPA2320, OPA320S, OPA2320S
www.ti.com
SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
•
Changed Shutdown subsection of Electrical Characteristics along with associated notes.................................................... 8
•
Changed Power Supply subsection of Electrical Characteristics ........................................................................................... 9
•
Changed Figure 4................................................................................................................................................................. 10
•
Changed Figure 18............................................................................................................................................................... 11
•
Changed 100 µs to 100 ns in first paragraph of Overload Recovery Time section ............................................................. 20
•
Changed Figure 38............................................................................................................................................................... 20
•
Changed Figure 39............................................................................................................................................................... 20
•
Changed R2 value in Figure 44 from 500Ω to 50kΩ............................................................................................................. 25
Copyright © 2010–2016, Texas Instruments Incorporated
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3
OPA320, OPA2320, OPA320S, OPA2320S
SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
www.ti.com
5 Pin Configuration and Functions
OPA320 DBV Package
5-Pin SOT-23
Top View
OUT
1
V-
2
+IN
3
OPA320S DBV Package
6-Pin SOT-23
Top View
V+
5
4
-IN
VOUT
1
6
V+
V-
2
5
SHDN
+IN
3
4
-IN
Pin Functions: OPA320 and OPA320S
PIN
NAME
I/O
DESCRIPTION
OPA320
OPA320S
–IN
4
4
I
Negative (inverting) input
+IN
3
3
I
Positive (noninverting) input
OUT, VOUT
1
1
O
Output
SHDN
—
5
I
Shutdown, active low
V–
2
2
—
Negative (lowest) power supply
V+
5
6
—
Positive (highest) power supply
OPA2320 D and DGK Packages
8-Pin SOIC and VSSOP
Top View
OPA2320 DRG Package
8-Pin SON With Exposed Thermal Pad
Top View
OUT A
1
8
V+
OUT A
1
-IN A
2
7
OUT B
-IN A
2
+IN A
3
6
-IN B
+IN A
3
V-
4
5
+IN B
V-
4
Exposed
Thermal
Die Pad
on
Underside(2)
(1)
No internal connection.
(2)
Connect thermal pad to V–.
8
V+
7
OUT B
6
-IN B
5
+IN B
Pin Functions: OPA2320
PIN
I/O
DESCRIPTION
NAME
SOIC,
VSSOP
SON
–IN A
2
2
I
Inverting input, channel A
+IN A
3
3
I
Noninverting input, channel A
–IN B
6
6
I
Inverting input, channel B
+IN B
5
5
I
Noninverting input, channel B
OUT A,
VOUT A
1
1
O
Output, channel A
OUT B,
VOUT B
7
7
O
Output, channel B
SHDN A
—
—
I
Shutdown, active low, channel A
SHDN B
—
—
I
Shutdown, active low, channel B
V–
4
4
—
Negative (lowest) power supply
V+
8
8
—
Positive (highest) power supply
4
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SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
OPA2320S DGS Package
10-Pin VSSOP
Top View
VOUT A
1
-IN A
2
10 V+
9
VOUT B
8
-IN B
A
+IN A
3
B
V-
4
7
+IN B
SHDN A
5
6
SHDN B
Pin Functions: OPA2320S
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
8
I
Inverting input, channel B
+IN B
7
I
Noninverting input, channel B
OUT A,
VOUT A
1
O
Output, channel A
OUT B,
VOUT B
9
O
Output, channel B
SHDN A
5
I
Shutdown, active low, channel A
SHDN B
6
I
Shutdown, active low, channel B
V–
4
—
Negative (lowest) power supply
V+
10
—
Positive (highest) power supply
Copyright © 2010–2016, Texas Instruments Incorporated
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5
OPA320, OPA2320, OPA320S, OPA2320S
SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Voltage
Current
Signal input pin (2)
(V–) – 0.5
(V+) + 0.5
Signal input pin (2)
–10
10
Operating range, TA
(3)
–40
V
mA
Continuous
150
Junction, TJ
150
Storage, Tstg
(2)
UNIT
6
Output short-circuit current (3)
Temperature
(1)
MAX
Supply, VS = (V+) – (V–)
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model (MM)
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VS
Specified voltage
1.8
5.5
UNIT
V
TA
Specified temperature
–40
125
°C
6.4 Thermal Information: OPA320 and OPA320S
THERMAL METRIC
OPA320
OPA320S
DBV (SOT-23)
DBV (SOT-23)
5 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance (1)
219.3
177.5
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
107.5
108.9
°C/W
RθJB
Junction-to-board thermal resistance
57.5
27.4
°C/W
ψJT
Junction-to-top characterization parameter
7.4
13.3
°C/W
ψJB
Junction-to-board characterization parameter
56.9
26.9
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
—
—
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the application report, Semiconductor and IC Package Thermal
Metrics.
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SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
6.5 Thermal Information: OPA2320
OPA2320
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
DRG (SON)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
122.6
174.8
50.6
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
67.1
43.9
54.9
°C/W
RθJB
Junction-to-board thermal resistance
64
95
25.2
°C/W
ψJT
Junction-to-top characterization parameter
13.2
2
0.6
°C/W
ψJB
Junction-to-board characterization parameter
63.4
93.5
25.3
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
—
—
5.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the application report, Semiconductor and IC Package Thermal
Metrics.
6.6 Thermal Information: OPA2320S
OPA2320S
THERMAL METRIC (1)
DGS (VSSOP)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
171.5
°C/W
43
°C/W
RθJB
ψJT
Junction-to-board thermal resistance
91.4
°C/W
Junction-to-top characterization parameter
1.9
°C/W
ψJB
Junction-to-board characterization parameter
89.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.7 Electrical Characteristics
At VS = 1.8 V to 5.5 V or ±0.9 V to ±2.75 V, TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and
SHDN x = VS+ (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
40
150
µV
1.5
5
5
20
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage
vs temperature
PSR
Input offset voltage
vs power supply
VS = 1.8 V to 5.5 V, TA = 25°C
Channel separation
1 kHz
VS = 5.5 V, TA = –40°C to 125°C
VS = 1.8 V to 5.5 V, TA = –40°C to 125°C
15
130
µV/°C
µV/V
dB
INPUT VOLTAGE
VCM
Common-mode voltage
(V–) – 0.1
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V, TA = 25°C
CMRR
100
Common-mode rejection ratio VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V, TA = –40°C to
125°C
(V+) + 0.1
V
114
dB
96
INPUT BIAS CURRENT
TA = 25°C
IB
Input bias current
±0.2
TA = –40°C to 85°C
TA = –40°C to 125°C
±50
OPA2320 and OPA2320S
±400
OPA320 and OPA320S
Input offset current
±0.2
±0.9
TA = –40°C to 85°C
±50
TA = –40°C to 125°C
±400
Copyright © 2010–2016, Texas Instruments Incorporated
pA
±600
TA = 25°C
IOS
±0.9
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pA
7
OPA320, OPA2320, OPA320S, OPA2320S
SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
www.ti.com
Electrical Characteristics (continued)
At VS = 1.8 V to 5.5 V or ±0.9 V to ±2.75 V, TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and
SHDN x = VS+ (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
NOISE
Input voltage noise
en
Input voltage noise density
in
Input current noise density
f = 0.1 Hz to 10 Hz
2.8
f = 1 kHz
8.5
f = 10 kHz
µVPP
nV/√Hz
7
f = 1 kHz
0.6
fA/√Hz
INPUT CAPACITANCE
Differential
5
pF
Common mode
4
pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ, TA = 25°C
114
132
0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ, TA = –40°C to 125°C
100
130
0.2 V < VO < (V+) – 0.2 V, RL = 2 kΩ, TA = 25°C
108
123
96
130
0.2 V < VO < (V+) – 0.2 V, RL = 2 kΩ, TA = –40°C to 125°C
PM
Phase margin
VS = 5 V, CL = 50 pF
dB
47
°
FREQUENCY RESPONSE, VS = 5 V, CL = 50 pF
GBP
Gain bandwidth product
Unity gain
20
MHz
SR
Slew rate
G = +1
10
V/µs
tS
Settling time
to 0.1%, 2-V step, G = +1
0.25
to 0.01%, 2-V step, G = +1
0.32
to 0.0015%, 2-V step, G = +1 (1)
THD+N
µs
0.5
Overload recovery time
VIN × G > VS
Total harmonic distortion +
noise (2)
VO = 4 VPP, G = 1, f = 10 kHz, RL = 10 kΩ
0.0005%
100
VO = 2 VPP, G = 1, f = 10 kHz, RL = 600 Ω
0.0011%
ns
OUTPUT
VO
Voltage output swing from
both rails
ISC
Short-circuit current
CL
Capacitive load drive
RO
Open-loop output resistance
RL = 10 kΩ, TA = 25°C
10
20
RL = 2 kΩ, TA = 25°C
25
35
RL = 10 kΩ, TA = –40°C to 125°C
30
RL = 2 kΩ, TA = –40°C to 125°C
SHUTDOWN
IQSD
IO = 0 mA, f = 1 MHz
90
Quiescent current per
amplifier
All amplifiers disabled, SHDN = V–
0.1
OPA2320S only, SHDN A = VS–, SHDN B = VS+
1.6
OPA2320S only, SHDN A = VS+, SHDN B = VS–
1.6
Amplifier enabled, VS– + 0.7 [(VS+) + |VS–|]
Low-level input voltage
Amplifier disabled, VS– + 0.3 [(VS+) + |VS–|]
Amplifier enable time (4)
Amplifier disable time
(4)
SHDN pin input bias current
(per pin)
(5)
8
mA
Ω
(3)
High-level input voltage
(1)
(2)
(3)
(4)
±65
See Typical Characteristics
VIL
tOFF
45
VS = 5.5 V
VIH
tON
mV
0.7 × VS+
0.5
mA
5.5
0.3 × VS+
G = 1, VOUT = 0.1 × VS/2, full shutdown (5)
20
OPA2320S only, partial shutdown (5)
µA
V
V
µs
6
G = 1, VOUT = 0.1 × VS/2
3
VIH = 5 V
0.13
VIL = 0 V
0.04
µs
µA
Based on simulation.
Third-order filter; bandwidth = 80 kHz at –3 dB.
Specified by design and characterization; not production tested.
Disable time (tOFF) and enable time (tON) are defined as the time between the 50% point of the signal applied to the SHDN pin and the
point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
Full shutdown refers to the dual OPA2320S having both A and B channels disabled (SHDN A = SHDN B = VS–). For partial shutdown,
only one SHDN pin is exercised; in this mode, the internal biasing and oscillator remain operational and the enable time is shorter.
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SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
Electrical Characteristics (continued)
At VS = 1.8 V to 5.5 V or ±0.9 V to ±2.75 V, TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and
SHDN x = VS+ (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.5
1.75
UNIT
POWER SUPPLY
VS
IQ
Specified voltage
1.8
Quiescent current per
amplifier,
OPA320 and OPA320S
IO = 0 mA, VS = 5.5 V, TA = 25°C
Quiescent current per
amplifier,
OPA2320 and OPA2320S
IO = 0 mA, VS = 5.5 V, TA = 25°C
Power-on time
V+ = 0 V to 5 V, to 90% IQ level
5.5
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C
1.85
1.45
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C
Copyright © 2010–2016, Texas Instruments Incorporated
mA
1.6
1.7
28
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V
mA
µs
9
OPA320, OPA2320, OPA320S, OPA2320S
SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
www.ti.com
6.8 Typical Characteristics
At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted).
14
25
20
Number of Amplifiers
Number of Amplifiers (%)
12
10
8
6
4
15
10
5
2
0
0
0.5
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
0.1
0.9
1.3
1.7
2.1
2.5
2.9
Offset Drift (mV/°C)
Offset Voltage (mV)
Figure 2. Offset Voltage Drift Distribution
100
160
80
140
60
120
40
0
VS = ±2.5V
CL = 50pF
-40
Gain (dB)
100
20
0
-20
-60
Phase
80
-80
60
-100
-120
40
-40
Gain
20
-60
Representative Units
VS = ±2.75V
-80
-3 -2.5 -2 -1.5 -1 -0.5 0
0.5
1
1.5
2
2.5
-140
-160
0
-100
3
-20
-20
Phase (°)
Offset Voltage (mV)
Figure 1. Offset Voltage Production Distribution
1
10
100
1k
Common-Mode Voltage (V)
10k
100k
1M
10M
-180
100M
Frequency (Hz)
Figure 3. Offset Voltage vs Common-Mode Voltage
Figure 4. Open-Loop Gain/Phase vs Frequency
1.5
140
+125°C
135
Quiescent Current (mA/Ch)
Open-Loop Gain (dB)
10kW Load
130
125
2kW Load
120
115
110
1.45
+85°C
1.4
+25°C
1.35
-40°C
1.3
105
100
1.25
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 5. Open-Loop Gain vs Temperature
10
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150
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
Figure 6. Quiescent Current vs Supply Voltage
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Typical Characteristics (continued)
1
6
0.8
5
4
0.6
Input Bias Current (pA)
Input Bias Current (pA)
At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted).
0.4
0.2
0
-0.2
-0.4
-0.6
-1
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
1
0
-1
-2
-3
IB+
IBIOS
-5
-6
2.9
2.7
2
-4
IBIB+
-0.8
3
-3 -2.5 -2 -1.5 -1 -0.5 0
Supply Voltage (±V)
Figure 7. Input Bias Current vs Supply Voltage
Input Bias Current (pA)
35
30
25
20
15
10
5
0.2
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
-100
1.5
2
3
2.5
IOS
IB+
IB-
IB
-50
0.25
0.1
0.15
0
0.05
-0.1
-0.05
-0.2
-0.15
-0.3
-0.25
0
-0.35
1
Figure 8. Input Bias Current vs Common-Mode Voltage
40
Number of Amplifiers (%)
0.5
Common-Mode Voltage (V)
-25
0
25
50
75
100
IOS
125
150
Temperature (°C)
Input Bias Current (pA)
Figure 10. Input Bias Current vs Temperature
Figure 9. Input Bias Current Distribution
130
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
140
120
CMRR
100
80
60
40
PSRR
20
0
VS = 1.8V to 5.5V
125
120
115
110
105
100
PSRR
CMRR
95
90
100
1k
10k
100k
1M
10M
-50
-25
0
25
Frequency (Hz)
Figure 11. CMRR and PSRR vs Frequency
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50
75
100
125
150
Temperature (°C)
Figure 12. CMRR and PSRR vs Temperature
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Typical Characteristics (continued)
At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted).
6
VS = 1.8V to 5.5V
5
4
3
100
Voltage (mV)
Voltage Noise (nV/ÖHz)
1000
10
2
1
0
-1
-2
-3
1
-4
10
100
1k
10k
1M
100k
0
1
2
3
4
Frequency (Hz)
Figure 13. Input Voltage Noise Spectral Density
vs Frequency
60
7
8
60
VS = +1.8V
RL = 10kW
CL = 50pF
G = +100V/V
20
G = +10V/V
0
6
10
9
Figure 14. 0.1-Hz to 10-Hz Input Voltage Noise
VS = +5.5V
RL = 10kW
CL = 50pF
G = +100V/V
40
Gain (dB)
Gain (dB)
40
5
Time (1s/div)
20
G = +10V/V
0
G = +1V/V
-20
G = +1V/V
-20
10k
100k
1M
10M
10k
100M
100k
Frequency (Hz)
1M
100M
10M
Frequency (Hz)
Figure 15. Closed-Loop Gain vs Frequency
Figure 16. Closed-Loop Gain vs Frequency
6
3
5.5VS
2
4
Output Voltage (V)
Output Voltage (VPP)
5
3.3VS
3
2
-40°C
+25°C
+125°C
0
-1
1.8VS
1
-2
RL = 10kW
CL = 50pF
VS = ±2.75 V
0
-3
10k
100k
1M
10M
Frequency (Hz)
Figure 17. Maximum Output Voltage vs Frequency
12
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0
10
20
30
40
50
60
70
80
Output Current (mA)
Figure 18. Output Voltage Swing vs Output Current
(8-Pin VSSOP)
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Typical Characteristics (continued)
At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted).
1000
70
G = 1, VS = 1.8V
VS = ±2.75V
G = 1, VS = 5.5V
G = 10, VS = 1.8V
50
Overshoot (%)
Impedance (W)
60
100
G = 10, VS = 5.5V
40
30
20
10
0
10
1
10
100
1k
10k
100k
1M
10M
100M
500
0
1000
Frequency (Hz)
0.1
0.01
Load = 600W
0.001
Frequency = 10kHz
VS = ±2.5V
G = +1V/V
Load = 10kW
0.1
0.1
Load = 600W
0.001
Load = 10kW
0.0001
10
1
10
100
1k
10k
100k
Frequency (Hz)
Figure 22. THD+N vs Frequency
0
Frequency = 10kHz
VIN = 4VPP
VS = ±2.5V
G = +1V/V
VS = ±2.75V
-20
Channel Separation (dB)
Total Harmonic Distortion and Noise (%)
3000
0.01
Figure 21. THD+N vs Amplitude
0.01
Load = 600W
0.001
-40
-60
-80
-100
-120
Load = 10kW
0.0001
2500
Frequency = 10kHz
VIN = 2VPP
VS = ±2.5V
G = +1V/V
VIN (VPP)
0.1
2000
Figure 20. Small-Signal Overshoot vs Load Capacitance
Total Harmonic Distortion and Noise (%)
Total Harmonic Distortion and Noise (%)
Figure 19. Open-Loop Output Impedance vs Frequency
0.0001
0.01
1500
Capacitive Load (pF)
-140
10
100
1k
10k
Frequency (Hz)
Figure 23. THD+N vs Frequency
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100k
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 24. Channel Separation vs Frequency
(for Dual Versions)
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Typical Characteristics (continued)
At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted).
0.1
12
CL = 50pF
0.075
11.5
Voltage (V)
Slew Rate (V/ms)
0.05
11
Rise
10.5
Fall
10
Gain = +1
VS = ±2.75V
VIN = 100mVPP
0.025
0
-0.025
-0.05
9.5
VOUT
VIN
-0.075
9
1.6
2
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2
-0.1
-0.8
5.6
-0.4
0
0.4
Supply Voltage (V)
Figure 25. Slew Rate vs Supply Voltage
1.5
0.075
VIN
Gain = -1
VS = ±2.75V
VIN = 100mVPP
Voltage (V)
Voltage (V)
Gain = +1
VS = ±2.75V
VIN = 2VPP
1
0.05
0
1.6
1.2
Figure 26. Small-Signal Step Response
0.1
0.025
0.8
Time (ms)
-0.025
0.5
VOUT
0
-0.5
-0.05
-0.1
-1.6
-1
VOUT
VIN
-0.075
-1.2
-0.8
-0.4
0
0.4
0.8
-1.5
-0.4
0
Time (ms)
0.4
0.8
1.6
Figure 28. Large-Signal Step Response vs Time
Voltage (1 V/div)
Voltage (500 mV/div)
Figure 27. Small-Signal Step Response
G = 1 V/V
VS = 1.8V
VIN = 1.5V
Output Pin
Enable Pin
G = 1 V/V
VS = 5.5V
VIN = 4V
Output Pin
Enable Pin
Time (5 s/div)
Time (2.5 s/div)
C001
Figure 29. Enable Start-Up
14
1.2
Time (ms)
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C001
Figure 30. Enable Start-Up
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Typical Characteristics (continued)
Voltage (1 V/div)
Voltage (500 mV/div)
At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted).
G = 1 V/V
VS = 1.8V
VIN = 1.5V
Output Pin
Enable Pin
G = 1 V/V
VS = 5.5V
VIN = 4V
Output Pin
Enable Pin
Time (5 s/div)
Time (2.5 s/div)
C001
Figure 31. Enable Shutdown
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C001
Figure 32. Enable Shutdown
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7 Detailed Description
7.1 Overview
The OPA320 family of operational amplifiers (op amps) are high-speed, precision amplifiers, perfectly suited to
drive 12-, 14-, and 16-bit analog-to-digital converters. Low output impedance with flat frequency characteristics
and zero-crossover distortion circuitry enable high linearity over the full input common mode range, achieving
true rail-to-rail input from a 1.8-V to 5.5-V single supply.
7.2 Functional Block Diagram
V+
Low Noise Charge
Pump
Bias Circuitry
+IN
-IN
OUT
Input Stage Load
Bias Circuitry
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7.3 Feature Description
7.3.1 Operating Voltage
The OPA320 series op amps are unity-gain stable and can operate on a single-supply voltage (1.8 V to 5.5 V), or
a split-supply voltage (±0.9 V to ±2.75 V), making them highly versatile and easy to use. The power-supply pins
should have local bypass ceramic capacitors (typically 0.001 µF to 0.1 µF). The OPA320 amplifiers are fully
specified from 1.8 V to 5.5 V and over the extended temperature range of –40°C to 125°C. Parameters that can
exhibit variance with regard to operating voltage or temperature are presented in the Typical Characteristics.
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Feature Description (continued)
7.3.2 Input and ESD Protection
The OPA320 incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case of
input and output pins, this protection primarily consists of current-steering diodes connected between the input
and power-supply pins. These ESD protection diodes also provide in-circuit input overdrive protection, provided
that the current is limited to 10 mA as stated in the Absolute Maximum Ratings. Many input signals are inherently
current-limited to less than 10 mA; therefore, a limiting resistor is not required. Figure 33 shows how a series
input resistor (RS) may be added to the driven input to limit the input current. The added resistor contributes
thermal noise at the amplifier input and the value should be kept to the minimum in noise-sensitive applications.
V+
IOVERLOAD
10mA, Max
VOUT
OPA320
VIN
RS
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Figure 33. Input Current Protection
7.3.3 Rail-to-Rail Input
The OPA320 product family features true rail-to-rail input operation, with supply voltages as low as ±0.9 V
(1.8 V). The design of the OPA320 amplifiers include an internal charge-pump that powers the amplifier input
stage with an internal supply rail at approximately 1.6 V above the external supply (VS+). This internal supply rail
allows the single differential input pair to operate and remain very linear over a very wide input common mode
range. A unique zero-crossover input topology eliminates the input offset transition region typical of many rail-torail, complementary input stage operational amplifiers. This topology allows the OPA320 to provide superior
common-mode performance (CMRR > 110 dB, typical) over the entire common-mode input range, which extends
100 mV beyond both power-supply rails. When driving analog-to-digital converters (ADCs), the highly linear VCM
range of the OPA320 assures maximum linearity and lowest distortion.
7.3.4 Phase Reversal
The OPA320 op amps are designed to be immune to phase reversal when the input pins exceed the supply
voltages, therefore providing further in-system stability and predictability. Figure 34 shows the input voltage
exceeding the supply voltage without any phase reversal.
4
VIN
VS = ±2.5V
3
Voltage (V)
2
VOUT
1
0
-1
-2
-3
-4
-500
-250
0
250
500
750
1000
Time (ms)
Figure 34. No Phase Reversal
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Feature Description (continued)
7.3.5 Feedback Capacitor Improves Response
For optimum settling time and stability with high-impedance feedback networks, it may be necessary to add a
feedback capacitor across the feedback resistor, RF, as shown in Figure 35. This capacitor compensates for the
zero created by the feedback network impedance and the OPA320 input capacitance (and any parasitic layout
capacitance). The effect becomes more significant with higher impedance networks.
CF
RIN
RF
VIN
V+
CIN
RIN ´ CIN = RF ´ CF
OPA320
VOUT
CL
CIN
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Where CIN is equal to the OPA320 input capacitance (approximately 9 pF) plus any parasitic layout capacitance.
Figure 35. Feedback Capacitor Improves Dynamic Performance
For the circuit shown in Figure 35, the value of the variable feedback capacitor should be chosen so that the
input resistance times the input capacitance of the OPA320 (typically 9 pF) plus the estimated parasitic layout
capacitance equals the feedback capacitor times the feedback resistor calculated with Equation 1.
RIN × CIN = RF × CF
where
•
CIN is equal to the OPA320 input capacitance (sum of differential and common mode) plus the layout
capacitance.
(1)
The capacitor value can be adjusted until optimum performance is obtained.
7.3.6 EMI Susceptibility and Input Filtering
Operational amplifiers vary in susceptibility to electromagnetic interference (EMI). If conducted EMI enters the
operational amplifier, the dc offset observed at the amplifier output may shift from the nominal value while EMI is
present. This shift is a result of signal rectification associated with the internal semiconductor junctions. While all
operational amplifier pin functions can be affected by EMI, the input pins are likely to be the most susceptible.
The OPA320 operational amplifier family incorporates an internal input low-pass filter that reduces the amplifiers
response to EMI. Both common mode and differential mode filtering are provided by the input filter. The filter is
designed for a cutoff frequency of approximately 580 MHz (–3 dB), with a roll-off of 20 dB per decade.
7.3.7 Output Impedance
The open-loop output impedance of the OPA320 common-source output stage is approximately 90 Ω. When the
op amp is connected with feedback, this value is reduced significantly by the loop gain. For example, with 130 dB
(typical) of open-loop gain, the output impedance is reduced in unity-gain to less than 0.03 Ω. For each decade
rise in the closed-loop gain, the loop gain is reduced by the same amount, which results in a ten-fold increase in
effective output impedance. While the OPA320 output impedance remains very flat over a wide frequency range,
at higher frequencies the output impedance rises as the open-loop gain of the op amp drops. However, at these
frequencies the output also becomes capacitive as a result of parasitic capacitance. This architecture in turn
prevents the output impedance from becoming too high, which can cause stability problems when driving large
capacitive loads. As mentioned previously, the OPA320 has excellent capacitive load drive capability for an op
amp with its bandwidth.
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Feature Description (continued)
7.3.8 Capacitive Load and Stability
The OPA320 is designed to be used in applications where driving a capacitive load is required. As with all op
amps, there may be specific instances where the OPA320 can become unstable. The particular op amp circuit
configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an
amplifier is stable in operation. An op amp in the unity-gain (1-V/V) buffer configuration and driving a capacitive
load exhibits a greater tendency to become unstable than an amplifier operated at a higher noise gain. The
capacitive load, in conjunction with the op amp output resistance, creates a pole within the feedback loop that
degrades the phase margin. The degradation of the phase margin increases as the capacitive loading increases.
When operating in the unity-gain configuration, the OPA320 remains stable with a pure capacitive load up to
approximately 1 nF.
The equivalent series resistance (ESR) of some very large capacitors (CL > 1 µF) is sufficient to alter the phase
characteristics in the feedback loop such that the amplifier remains stable. Increasing the amplifier closed-loop
gain allows the amplifier to drive increasingly larger capacitance. This increased capability is evident when
observing the overshoot response of the amplifier at higher voltage gains, as shown in Figure 37. One technique
for increasing the capacitive load drive capability of the amplifier operating in unity gain is to insert a small
resistor (RS), typically 10 Ω to 20 Ω, in series with the output, as shown in Figure 36.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. A possible
problem with this technique is that a voltage divider is created with the added series resistor and any resistor
connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output that
reduces the output swing. The error contributed by the voltage divider may be insignificant. For instance, with a
load resistance, RL = 10 kΩ and RS = 20 Ω, the gain error is only about 0.2%. However, when RL is decreased to
600 Ω, which the OPA320 is able to drive, the error increases to 7.5%.
V+
RS
VOUT
OPA320
VIN
10W to
20W
RL
CL
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Figure 36. Improving Capacitive Load Drive
70
G = 1, VS = 1.8V
60
G = 1, VS = 5.5V
G = 10, VS = 1.8V
Overshoot (%)
50
G = 10, VS = 5.5V
40
30
20
10
0
0
500
1000
1500
2000
2500
3000
Capacitive Load (pF)
Figure 37. Small-Signal Overshoot vs Capacitive Load (100-mVPP Output Step)
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Feature Description (continued)
7.3.9 Overload Recovery Time
Overload recovery time is the time it takes the output of the amplifier to come out of saturation and recover to the
linear region. Overload recovery is particularly important in applications where small signals must be amplified in
the presence of large transients. Figure 38 and Figure 39 show the positive and negative overload recovery
times of the OPA320, respectively. In both cases, the time elapsed before the OPA320 comes out of saturation is
less than 100 ns. In addition, the symmetry between the positive and negative recovery times allows excellent
signal rectification without distortion of the output signal.
1
3
VS = ±2.75V
G = -10
2.5
0.5
Input
2
0
1.5
-0.5
Voltage (V)
Voltage (V)
Output
1
0.5
0
-1.5
-2
Input
Output
VS = ±2.75V
G = -10
-2.5
-0.5
-1
9.75
-1
10
10.25
10.5
10.75
Time (250ns/div)
Figure 38. Positive Recovery Time
11
-3
9.75
10
10.25
10.5
10.75
11
Time (250ns/div)
Figure 39. Negative Recovery Time
7.3.10 Shutdown Function
The SHDN (enable) pin function of the OPAx320S is referenced to the negative supply voltage of the operational
amplifier. A logic level high enables the op amp. A valid logic high is defined as voltage [(V+) – 0.1 V], up to (V+),
applied to the SHDN pin. A valid logic low is defined as [(V–) + 0.1 V], down to (V–), applied to the enable pin.
The maximum allowed voltage applied to SHDN is 5.5 V with respect to the negative supply, independent of the
positive supply voltage. This pin must either be connected to a valid high or a low voltage or driven, and not left
as an open circuit.
The logic input is a high-impedance CMOS input. Dual op amp versions are independently controlled and quad
op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be
used to greatly reduce the average current and extend battery life. The enable time is 10 µs for full shutdown of
all channels; disable time is 3 μs. When disabled, the output assumes a high-impedance state. This architecture
allows the OPAx320S to be operated as a gated amplifier (or to have the device output multiplexed onto a
common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases with increased
load resistance. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to midsupply (VS / 2) is required. If using the OPAx320S without a load, the resulting turn-off time is significantly
increased.
7.3.11 Leadless SON Package
The OPA320 series uses the SON style package (also known as SON), which is a QFN with contacts on only
two sides of the package bottom. This leadless package maximizes printed circuit board (PCB) space and offers
enhanced thermal and electrical characteristics through an exposed pad. One of the primary advantages of the
SON package is its low height (0.8 mm).
SON packages are physically small, have a smaller routing area, improved thermal performance, reduced
electrical parasitics, and a pinout scheme that is consistent with other commonly-used packages (such as SOIC
and VSSOP). Additionally, the absence of external leads eliminates bent-lead issues.
The SON package can easily be mounted using standard PCB assembly techniques. See Application Report,
QFN/SON PCB Attachment (SLUA271) and Application Report, Quad Flatpack No-Lead Logic Packages
(SCBA017), both available for download at www.ti.com.
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Feature Description (continued)
NOTE
The exposed leadframe die pad on the bottom of the SON package should be connected
to the most negative potential (V–).
7.4 Device Functional Modes
The OPA320 family of operational amplifiers are operational when power-supply voltages between 1.8 V to 5.5 V
are applied. Devices with an S suffix have a shutdown capability. For a detailed description of the shutdown
function, see Shutdown Function.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA320 family offers outstanding DC and AC performance. These devices operate up to a 5.5-V power
supply and offer ultra-low input bias current and 20-MHz bandwidth. These features make the OPA320 family a
robust operational amplifier for both battery-powered and industrial applications.
8.1.1 Transimpedance Amplifier
Wide gain bandwidth, low-input bias current, low input voltage, and current noise make the OPA320 an ideal
wideband photodiode transimpedance amplifier. Low-voltage noise is important because photodiode capacitance
causes the effective noise gain of the circuit to increase at high frequency.
The key elements to a transimpedance design, as shown in Figure 40, are the expected diode capacitance (CD),
which should include the parasitic input common mode and differential-mode input capacitance (4 pF + 5 pF for
the OPA320); the desired transimpedance gain (RF); and the gain-bandwidth (GBW) for the OPA320 (20 MHz).
With these three variables set, the feedback capacitor value (CF) can be set to control the frequency response.
CF includes the stray capacitance of RF, which is 0.2 pF for a typical surface-mount resistor.
(1)
CF
< 1pF
RF
10MW
V+
l
CD
OPA320
VOUT
VCopyright © 2016, Texas Instruments Incorporated
(1)
CF is optional to prevent gain peaking. It includes the stray capacitance of RF.
Figure 40. Dual-Supply Transimpedance Amplifier
To achieve a maximally-flat, second-order Butterworth frequency response, the feedback pole should be set as
shown in Equation 2.
1
=
2pRFCF
GBW
4pRFCD
(2)
Bandwidth is calculated by Equation 3.
f-3dB =
GBW
2pRFCD
(Hz)
(3)
For even higher transimpedance bandwidth, consider the high-speed CMOS OPA380 (90-MHz GBW), OPA354
(100-MHz GBW), OPA300 (180-MHz GBW), OPA355 (200-MHz GBW), or OPA656/57 (400-MHz GBW).
22
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SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
Application Information (continued)
For single-supply applications, the +IN input can be biased with a positive dc voltage to allow the output to reach
true zero when the photodiode is not exposed to any light, and respond without the added delay that results from
coming out of the negative rail; this configuration is shown in Figure 41. This bias voltage also appears across
the photodiode, providing a reverse bias for faster operation.
(1)
CF
< 1pF
RF
10MW
V+
l
OPA320
VOUT
+VBIAS
Copyright © 2016, Texas Instruments Incorporated
(1)
CF is optional to prevent gain peaking. It includes the stray capacitance of RF.
Figure 41. Single-Supply Transimpedance Amplifier
For additional information, see the Application Bulletin Compensate Transimpedance Amplifiers Intuitively
(SBOA055), available for download at www.ti.com.
8.1.2 Optimizing the Transimpedance Circuit
To achieve the best performance, components should be selected according to the following guidelines:
1. For lowest noise, select RF to create the total required gain. Using a lower value for RF and adding gain after
the transimpedance amplifier generally produces poorer noise performance. The noise produced by RF
increases with the square-root of RF, whereas the signal increases linearly. Therefore, signal-to-noise ratio
improves when all the required gain is placed in the transimpedance stage.
2. Minimize photodiode capacitance and stray capacitance at the summing junction (inverting input). This
capacitance causes the voltage noise of the op amp to be amplified (increasing amplification at high
frequency). Using a low-noise voltage source to reverse-bias a photodiode can significantly reduce its
capacitance. Smaller photodiodes have lower capacitance. Use optics to concentrate light on a small
photodiode.
3. Noise increases with increased bandwidth. Limit the circuit bandwidth to only that required. Use a capacitor
across the RF to limit bandwidth, even if not required for stability.
4. Circuit board leakage can degrade the performance of an otherwise well-designed amplifier. Clean the circuit
board carefully. A circuit board guard trace that encircles the summing junction and is driven at the same
voltage can help control leakage.
For additional information, refer to the Application Bulletins Noise Analysis of FET Transimpedance Amplifiers
(SBOA060), and Noise Analysis for High-Speed Op Amps (SBOA066), available for download at www.ti.com.
Copyright © 2010–2016, Texas Instruments Incorporated
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SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
www.ti.com
Application Information (continued)
8.1.3 High-Impedance Sensor Interface
Many sensors have high source impedances that may range up to 10 MΩ, or even higher. The output signal of
sensors often must be amplified or otherwise conditioned by means of an amplifier. The input bias current of this
amplifier can load the sensor output and cause a voltage drop across the source resistance, as shown in
Figure 42, where (VIN+ = VS – IBIAS × RS). The last term, IBIAS × RS, shows the voltage drop across RS. To prevent
errors introduced to the system as a result of this voltage, an op amp with very low input bias current must be
used with high impedance sensors. This low current keeps the error contribution by IBIAS × RS less than the input
voltage noise of the amplifier, so that it does not become the dominant noise factor. The OPA320 series of op
amps feature very low input bias current (typically 200 fA), and are therefore ideal choices for such applications.
RS
100kW
IB
VIN+
V+
VOUT
OPA320
V-
RF
RG
Figure 42. Noise as a Result of IBIAS
8.1.4 Driving ADC'S
The OPA320 series op amps are well-suited for driving sampling analog-to-digital converters (ADC's) with
sampling speeds up to 1 MSPS. The zero-crossover distortion input stage topology allows the OPA320 to drive
ADC's without degradation of differential linearity and THD.
The OPA320 can be used to buffer the ADC switched input capacitance and resulting charge injection while
providing signal gain. Figure 44 shows the OPA320 configured to drive the ADS8326.
+5V
50kW
(2.5V)
8
RG
REF1004-2.5
4
R1
100kW
R2
25kW
+5V
+5V
1/2
OPA2320
R3
25kW
R4
100kW
1/2
OPA2320
G=5+
VOUT
RL
10kW
200kW
RG
Copyright © 2016, Texas Instruments Incorporated
Figure 43. Two Op Amp Instrumentation Amplifier With
Improved High-Frequency Common-Mode Rejection
24
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SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
Application Information (continued)
+5V
C1
100nF
+5V
(1)
R1
100W
V+
+IN
OPA320
(1)
C3
1nF
VVIN
0 to 4.096V
-IN
ADS8326
16-Bit
250kSPS
REF IN
Optional
R2
50kW
(2)
+5V
SD1
BAS40
-5V
C2
100nF
REF3240
4.096V
C4
100nF
Copyright © 2016, Texas Instruments Incorporated
(1)
Suggested value; may require adjustment based on specific application.
(2)
Single-supply applications lose a small number of ADC codes near ground as a result of op amp output swing
limitation. If a negative power supply is available, this simple circuit creates a –0.3-V supply to allow output swing to
true ground potential.
Figure 44. Driving the ADS8326
8.1.5 Active Filter
The OPA320 is well-suited for active filter applications that require a wide bandwidth, fast slew rate, low-noise,
single-supply operational amplifier. Figure 45 shows a 500-kHz, second-order, low-pass filter using the multiplefeedback (MFB) topology. The components have been selected to provide a maximally-flat Butterworth response.
Beyond the cutoff frequency, roll-off is –40 dB/dec. The Butterworth response is ideal for applications requiring
predictable gain characteristics, such as the anti-aliasing filter used in front of an ADC.
One point to observe when considering the MFB filter is that the output is inverted, relative to the input. If this
inversion is not required, or not desired, a noninverting output can be achieved through one of these options:
1. Adding an inverting amplifier;
2. Adding an additional second-order MFB stage; or
3. Using a noninverting filter topology, such as the Sallen-Key (shown in Figure 46).
MFB and Sallen-Key, low-pass and high-pass filter synthesis is quickly accomplished using TI’s FilterPro™
program. This software is available as a free download at www.ti.com.
Copyright © 2010–2016, Texas Instruments Incorporated
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25
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SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
www.ti.com
Application Information (continued)
R3
549W
C2
150pF
R1
549W
V+
R2
1.24kW
VIN
VOUT
OPA320
C1
1nF
V-
Copyright © 2016, Texas Instruments Incorporated
Figure 45. Second-Order, Butterworth, 500-kHz, Low-Pass Filter
220pF
V+
1.8kW
19.5kW
150kW
VIN = 1VRMS
3.3nF
47pF
VOUT
OPA320
VCopyright © 2016, Texas Instruments Incorporated
Figure 46. OPA320 Configured as a Three-Pole, 20-kHz Sallen-Key Filter
8.2 Typical Application
2.25 k
2.25 k
1.13 k
Input
1 nF
±
4 nF
Output
+
Figure 47. Second-Order, Low-Pass Filter Schematic
8.2.1 Design Requirements
•
•
•
•
26
Gain = 1 V/V
Low-pass cutoff frequency = 50 kHz
–40-db/dec filter response
Maintain less than 3-dB gain peaking in the gain versus frequency response
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SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
Typical Application (continued)
8.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in. Use Equation 4 to
calculate the voltage transfer function.
1 R1R3C2C5
Output
s
2
Input
s
s C2 1 R1 1 R3 1 R4 1 R3R4C2C5
(4)
This circuit produces a signal inversion. For this circuit, the gain at DC and the lowpass cutoff frequency are
calculated by Equation 5.
R4
Gain
R1
fC
1
2S
1 R3R 4 C2C5
(5)
®
Software tools are readily available to simplify filter design. WEBENCH Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH® Filter Designer lets you create optimized filter
designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH Design Center, WEBENCH Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
8.2.3 Application Curve
20
Gain (db)
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 48. OPA320 Second-Order, 50-kHz, Low-Pass Filter
Copyright © 2010–2016, Texas Instruments Incorporated
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27
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www.ti.com
9 Power Supply Recommendations
The OPA320 family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply
from –40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 6 V can permanently damage the device; see the Absolute
Maximum Ratings.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see Layout.
10 Layout
10.1 Layout Guidelines
The OPA320 is a wideband amplifier. To realize the full operational performance of the device, good highfrequency PCB layout practices are required. The bypass capacitors must be connected between each supply
pin and ground as close to the device as possible. The bypass capacitor traces should be designed for minimum
inductance.
10.2 Layout Example
VS+
VOUT
VS±
V+
OUT
GND
V±
Use a low-ESR,
ceramic bypass
capacitor.
Use a low-ESR,
ceramic bypass
capacitor.
RG
VIN
+IN
GND
±IN
GND
Run the input traces
as far away from
the supply lines
as possible.
RF
Place components
close to the device
and to each other to
reduce parasitic
errors.
Copyright © 2016, Texas Instruments Incorporated
Figure 49. Layout Example
28
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SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a
range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount ICs. The evaluation
tool these TI packages: D or U (8-pin SOIC), PW (8-pin TSSOP), DGK (8-pin VSSOP), DBV (6-pin SOT-23, 5pin SOT23, and 3-pin SOT-23), DCK (6-pin SC-70 and 5-pin SC-70), and DRL (6-pin SOT-563). The DIP
Adapter EVM may also be used with terminal strips or may be wired directly to existing circuits.
11.1.1.3 Universal Op Amp EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of IC package types. The evaluation module board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, VSSOP, TSSOP and SOT-23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own ICs. TI recommends
requesting several op amp device samples when ordering the Universal Op Amp EVM.
11.1.1.4 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
11.1.1.5 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
Copyright © 2010–2016, Texas Instruments Incorporated
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SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
www.ti.com
11.2 Documentation Support
11.2.1 Related Documentation
The following documents are relevant to using the OPAx320 and OPAx320S, and recommended for reference.
All are available for download at www.ti.com (unless otherwise noted):
• OPA320, OPA320S, OPA2320, OPA2320S EMI Immunity Performance (SBOZ017)
• Software Pacemaker Detection Design Guide (TIDUB75)
• TIDA-00378 Schematic and Block Diagram (TIDRJ21)
• PM2.5/PM10 Particle Sensor Analog Front-End for Air Quality Monitoring Design (TIDUB65)
• QFN/SON PCB Attachment (SLUA271)
• Quad Flatpack No-Lead Logic Packages (SCBA017)
• Compensate Transimpedance Amplifiers Intuitively (SBOA055)
• Noise Analysis of FET Transimpedance Amplifiers (SBOA060)
• Noise Analysis for High-Speed Op Amps (SBOA066)
11.3 Related Links
Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA320
Click here
Click here
Click here
Click here
Click here
OPA2320
Click here
Click here
Click here
Click here
Click here
OPA320S
Click here
Click here
Click here
Click here
Click here
OPA2320S
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
FilterPro, TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
30
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SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2010–2016, Texas Instruments Incorporated
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31
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
OPA2320AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2320A
Samples
OPA2320AIDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
Call TI | NIPDAUAG
| NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OCLQ
Samples
OPA2320AIDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
Call TI | NIPDAUAG
| NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OCLQ
Samples
OPA2320AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2320A
Samples
OPA2320AIDRGR
ACTIVE
SON
DRG
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OCMQ
Samples
OPA2320AIDRGT
ACTIVE
SON
DRG
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OCMQ
Samples
OPA2320SAIDGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPAI
Samples
OPA2320SAIDGST
ACTIVE
VSSOP
DGS
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPAI
Samples
OPA320AIDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAC
Samples
OPA320AIDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAC
Samples
OPA320SAIDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAE
Samples
OPA320SAIDBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAE
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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