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OPA2333-Q1
SBOS463B – DECEMBER 2008 – REVISED FEBRUARY 2020
OPA2333-Q1 Automotive, 1.8-V, Micropower, CMOS, Zero-Drift Operational Amplifier
1 Features
3 Description
•
The OPA2333-Q1 CMOS operational amplifiers use a
proprietary
autocalibration
technique
to
simultaneously provide very low offset voltage (10 μV,
max), and near-zero drift over time and temperature.
These miniature high-precision low-quiescent-current
amplifiers offer high-impedance inputs that have a
common-mode range 100 mV beyond the rails and
rail-to-rail output that swings within 50 mV of the rails.
Single or dual supplies as low as 1.8 V (±0.9 V), and
up to 5.5 V (±2.75 V) can be used. This device is
optimized for low-voltage single-supply operation.
1
•
•
•
•
•
•
•
AEC qualified for automotive applications
– Temperature grade 1: –40°C to +125°C, TA
Low offset voltage: 23 μV (Max)
0.01-Hz to 10-Hz noise: 1.1 μVPP
Quiescent current: 17 μA
Single-supply operation
Supply voltage: 1.8 V to 5.5 V
Rail-to-rail input/output
Packages: 8-pin SOIC and VSSOP
2 Applications
•
•
•
•
•
Pump
Position sensor
Vehicle occupant detection sensor
Brake system
Airbag
The OPA2333-Q1 offers excellent common-mode
rejection ratio (CMRR) without the crossover
associated with traditional complementary input
stages. This design results in superior performance
for driving analog-to-digital converters (ADCs) without
degradation of differential linearity.
The OPA2333-Q1 is specified for operation from
–40°C to +125°C.
Device Information(1)
PART NUMBER
OPA2333-Q1
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
500 nV/div
0.1-Hz to 10-Hz Noise
1 s/div
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA2333-Q1
SBOS463B – DECEMBER 2008 – REVISED FEBRUARY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: VS = 1.8 V to 5.5 V ..........
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application .................................................. 11
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
11 Device and Documentation Support ................. 16
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
Changes from Revision A (June 2010) to Revision B
Page
•
Added Device Information table, Pin Functions table, ESD Ratings table, Recommended Operating Conditions
table, Thermal Information table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
•
Changed input offset voltage (over full temp range) from 22 µV to 15 µV in Electrical Characteristics table ...................... 5
•
Added maximum value of 0.05 µV/°C to the VOS drift parameter in the Electrical Characteristics table ............................... 5
•
Deleted Thermal resistance parameter from Electrical Characteristics table ....................................................................... 5
2
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SBOS463B – DECEMBER 2008 – REVISED FEBRUARY 2020
5 Pin Configuration and Functions
D and DGK Packages
8-Pin SOIC and VSSOP
Top View
OUT A
1
8
V+
±IN A
2
7
OUT B
+IN A
3
6
±IN B
V±
4
5
+IN B
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
OUT A
O
Channel A output
2
–IN A
I
Channel A inverting input
3
+IN A
I
Channel A noninverting input
4
V–
—
5
+IN B
I
Channel B noninverting input
6
–IN B
I
Channel B inverting input
7
OUT B
O
Channel B output
8
V+
—
Positive (highest) supply voltage
Negative (lowest) supply voltage
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SBOS463B – DECEMBER 2008 – REVISED FEBRUARY 2020
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VCC
MAX
VI
Input voltage, signal input pins
(2)
–0.3
Output short-circuit (3)
Operating free-air temperature
TJ
Operating virtual-junction temperature
Tstg
Storage temperature
(2)
(3)
7
V
(V+) + 0.3
V
125
°C
150
°C
150
°C
Continuous
TA
(1)
UNIT
Supply voltage
–40
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10 mA or less.
Short circuit to ground, one amplifier per package
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
HBM ESD classification level 2
UNIT
(1)
±2000
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6
±1000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VS
Specified supply voltage
1.8
5.5
V
TA
Specified free-air temperature
–40
125
°C
6.4 Thermal Information
OPA2333-Q1
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
124.0
180.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
73.7
48.1
°C/W
RθJB
Junction-to-board thermal resistance
64.4
100.9
°C/W
ψJT
Junction-to-top characterization parameter
18.0
2.4
°C/W
ψJB
Junction-to-board characterization parameter
63.9
99.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: VS = 1.8 V to 5.5 V
At TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2 (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2
10
UNIT
OFFSET VOLTAGE
VS = 5 V
VOS
Input offset voltage
dVOS/dT
VOS drift
VS = 5 V, TA = –40°C to 125°C
PSRR
Power-supply rejection ratio
VS = 1.8 V to 5.5 V,
TA = –40°C to +125°C
Long-term stability
VS = 5 V, TA = –40°C to +125°C
μV
15
(1)
0.05
μV/°C
1
6
μV/V
1
Channel separation, dc
μV
0.02
(1)
µV
0.1
μV/V
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
±70
TA = –40°C to +125°C
±200
pA
±150
±140
pA
±400
pA
NOISE
Input voltage noise
in
Input current noise
f = 0.01 Hz to 1 Hz
0.3
μVPP
f = 0.1 Hz to 10 Hz
1.1
μVPP
f = 10 Hz
100
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode supply voltage
CMRR
Common-mode rejection ratio
(V–) – 0.1
(V–) – 0.1 V < VCM < (V+) + 0.1 V,
TA = –40°C to +125°C
102
(V+) + 0.1
V
130
dB
Differential
2
pF
Common-mode
4
pF
130
dB
INPUT CAPACITANCE
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 100 mV < VO < (V+) – 100 mV,
RL = 10 kΩ, TA = –40°C to +125°C
104
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
CL = 100 pF
350
kHz
SR
Slew rate
G=1
0.16
V/μs
OUTPUT
Voltage output swing from rail
ISC
Short-circuit current
CL
Capacitive load drive
(2)
Open-loop output impedance
RL = 10 kΩ
30
RL = 10 kΩ, TA = –40°C to +125°C
f = 350 kHz, IO = 0 A
50
mV
85
mV
±5
mA
2
kΩ
POWER SUPPLY
IQ
Quiescent current per amplifier
Turn-on time
(1)
(2)
IO = 0 A
17
IO = 0 A, TA = –40°C to +125°C
VS = 5 V
25
μA
30
μA
100
μs
300-hour life test at 150°C demonstrated randomly distributed variation of approximately 1 μV.
See the Typical Characteristics section.
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6.6 Typical Characteristics
0
0.0025
0.0050
0.0075
0.0100
0.0125
0.0150
0.0175
0.0200
0.0225
0.0250
0.0275
0.0300
0.0325
0.0350
0.0375
0.0400
0.0425
0.0450
0.0475
0.0500
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
1
2
3
4
5
6
7
8
9
10
Population
Population
At TA = 25°C, VS = 5 V, and CL = 0 pF (unless otherwise noted)
Offset Voltage (µV)
Offset Voltage Drift (µV/°C)
Figure 2. Offset Voltage Drift Production Distribution
140
100
200
120
80
150
100
60
100
40
50
20
0
40
−50
20
−100
0
0
−20
10
100
1k
10k
100k
CMRR (dB)
250
Phase (°)
AOL (dB)
Figure 1. Offset Voltage Production Distribution
120
80
60
1
1M
10
100
Frequency (Hz)
1k
10k
Figure 3. Open-Loop Gain vs Frequency
3
VS = ±2.75 V
VS = ±0.9 V
+PSRR
2
100
Output Swing (V)
PSRR (dB)
−PSRR
80
60
40
6
−40°C
1
−3
10k
100k
1M
−40°C
+125°C
0
1k
+25°C
−1
−2
100
+25°C
+125°C
0
20
10
1M
Figure 4. Common-Mode Rejection Ratio vs Frequency
120
1
100k
Frequency (Hz)
+25°C
−40°C
0
1
2
3
4
5
6
7
8
9
10
Frequency (Hz)
Output Current (mA)
Figure 5. Power-Supply Rejection Range vs Frequency
Figure 6. Output Voltage Swing vs Output Current
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Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, and CL = 0 pF (unless otherwise noted)
100
200
80
60
VS = 5 V
−IB
50
IB (pA)
20
0
−20
0
+IB
−50
−40
−100
−60
+IB
−80
+I B
−150
−200
−100
0
1
2
3
4
5
−25
−50
0
Common-Mode Voltage (V)
25
50
75
100
125
Temperature (°C)
Figure 7. Input Bias Current vs Common-Mode Voltage
Figure 8. Input Bias Current vs Temperature
25
G=1
RL = 10 kΩ
Output Voltage (1 V/div)
20
VS = 5.5 V
IQ (µA)
VS = 5.5 V
VS = 1.8 V
−IB
100
40
IB (pA)
150
−IB
15
VS = 1.8 V
10
5
0
−50
−25
0
25
50
75
100
Time (50 µs/div)
125
Temperature (°C)
Figure 10. Large-Signal Step Response
2 V/div
G = +1
RL = 10 kΩ
0
Input
Output
10 kW
1 V/div
Output Voltage (50 mV/div)
Figure 9. Quiescent Current vs Temperature
+2.5 V
1 kW
0
1/2
Device
–2.5 V
Time (5 µs/div)
Time (50 µs/div)
Figure 11. Small-Signal Step Response
Figure 12. Positive Over-Voltage Recovery
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Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, and CL = 0 pF (unless otherwise noted)
600
Settling Time (µs)
2 V/div
4V Step
500
Input
0
0
1 V/div
10 kW
+2.5 V
1 kW
Output
400
300
200
0.001%
1/2
Device
100
0.01%
–2.5 V
0
Time (50 µs/div)
10
1
100
Gain (dB)
Figure 13. Negative Over-Voltage Recovery
Figure 14. Settling Time vs Closed-Loop Gain
40
35
500 nV/div
Overshoot (%)
30
25
20
15
10
5
0
10
100
1 s/div
1000
Load Capacitance (pF)
Figure 16. 0.1-Hz to 10-Hz Noise
Figure 15. Small-Signal Overshoot vs Load Capacitance
Voltage Noise (nV//Hz)
Continues with no 1/f (flicker) noise.
Current Noise
100
100
Voltage Noise
Current Noise (fA//Hz)
1000
1000
10
10
1
10
100
1k
10k
Frequency (Hz)
Figure 17. Current and Voltage Spectral Density vs Frequency
8
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7 Detailed Description
7.1 Overview
The OPA2333-Q1 device is a zero-drift, low-power, rail-to-rail input and output operational amplifier. The device
operates from 1.8 V to 5.5 V, is unity-gain stable, and is designed for a wide range of general-purpose
applications. The zero-drift architecture provides ultra-low offset voltage and near-zero offset voltage drift.
The OPA2333-Q1 is unity-gain stable and free from unexpected output phase reversal. The device uses a
proprietary auto-calibration technique to provide low offset voltage and very low drift over time and temperature.
7.2 Functional Block Diagram
C2
CHOP1
GM1
CHOP2
Notch
Filter
GM2
GM3
OUT
+IN
±IN
GM_FF
C1
7.3 Feature Description
7.3.1 Rail-to-Rail Input Voltage
The OPA2333-Q1 input common-mode voltage range extends 0.1 V beyond the supply rails. The device is
designed to cover the full range without the troublesome transition region found in some other rail-to-rail
amplifiers.
Normally, input bias current is approximately 70 pA; however, input voltages exceeding the power supplies can
cause excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply
can be tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input
resistor (see Figure 18).
+5 V
IOVERLOAD
10 mA max
1/2
OPA2333
VOUT
VIN
5 kW
(see Note)
NOTE: A current-limiting resistor required if the input voltage exceeds the supply rails by ≥ 0.5 V.
Figure 18. Input Current Protection
7.3.2 Internal Offset Correction
The OPA2333-Q1 op amps use an auto-calibration technique with a time-continuous 350-kHz op amp in the
signal path. This amplifier is zero corrected every 8 μs using a proprietary technique. At power up, the amplifier
requires approximately 100 μs to achieve the specified VOS accuracy. This design has no aliasing or flicker noise.
7.4 Device Functional Modes
The OPA2333-Q1 has a single functional mode. The device is powered on as long as the power-supply voltage
is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA2333-Q1 is a unity-gain stable, precision operational amplifier with very low offset voltage drift. The
device is also free from output phase reversal. Applications with noisy or high-impedance power supplies require
decoupling capacitors close to the device power-supply pins. In most cases, 0.1-μF capacitors are adequate.
8.1.1 Achieving Output Swing to the Op Amp Negative Rail
Some applications require output voltage swings from 0 V to a positive full-scale voltage (such as 2.5 V) with
excellent accuracy. With most single-supply op amps, problems arise when the output signal approaches 0 V,
near the lower output swing limit of a single-supply op amp. A good single-supply op amp may swing close to
single-supply ground, but does not reach ground. The output of the OPA2333-Q1 can be made to swing to
ground or slightly below on a single-supply power source. To do so requires the use of another resistor and an
additional, more negative, power supply than the op amp negative supply. A pulldown resistor may be connected
between the output and the additional negative supply to pull the output down below the value that the output
would otherwise achieve (see Figure 19).
V+ = 5 V
1/2
OPA2333
V OUT
V IN
RP
20 k
Op Amp
V² = Ground
ï5 V
Additional
Negative Supply
Figure 19. VOUT Range to Ground
The OPA2333-Q1 has an output stage that allows the output voltage to be pulled to its negative supply rail, or
slightly below, using the technique previously described. This technique only works with some types of output
stages. The OPA2333-Q1 has been characterized to perform with this technique; however, the recommended
resistor value is approximately 20 kΩ.
NOTE
This configuration increases the current consumption by several hundreds of microamps.
Accuracy is excellent down to 0 V and as low as –2 mV. Limiting and nonlinearity occurs below –2 mV, but
excellent accuracy returns as the output is again driven above –2 mV. Lowering the resistance of the pulldown
resistor allows the op amp to swing even further below the negative rail. Resistances as low as 10 kΩ can be
used to achieve excellent accuracy down to –10 mV.
10
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8.2 Typical Application
8.2.1 High-Side Voltage-to-Current (V-I) Converter
The circuit shown in Figure 20 is a high-side voltage-to-current (V-I) converter. It translates in input voltage of 0 V
to 2 V to and output current of 0 mA to 100 mA. Figure 21 shows the measured transfer function for this circuit.
The low offset voltage and offset drift of the OPA333-Q1 device facilitate excellent dc accuracy for the circuit.
V+
RS2
470
RS3
4.7
IRS2
R4
10 k
VRS2
IRS3
VRS3
C7
2200 pF
R5
330
A2
+
Q2
V+
R3
200
+
Q1
A1
+
VIN
±
C6
1000 pF
R2
10 k
VRS1
RS1
IRS1
VLOAD
RLOAD
2k
ILOAD
Figure 20. High-Side Voltage-to-Current (V-I) Converter
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Typical Application (continued)
8.2.1.1 Design Requirements
The design requirements are as follows:
• Supply voltage: 5 V dc
• Input: 0 V to 2 V dc
• Output: 0 mA to 100 mA dc
8.2.1.2 Detailed Design Procedure
The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, and the three
current sensing resistors, RS1, RS2, and RS3. The relationship between VIN and RS1 determines the current that
flows through the first stage of the design. The current gain from the first stage to the second stage is based on
the relationship between RS2 and RS3.
For a successful design, pay close attention to the dc characteristics of the operational amplifier chosen for the
application. To meet the performance goals, this application benefits from an operational amplifier with low offset
voltage, low temperature drift, and rail-to-rail output. The OPA2333-Q1 CMOS operational amplifier is a highprecision, 5-µV offset, 0.05-μV/°C drift amplifier optimized for low-voltage, single-supply operation with an output
swing to within 50 mV of the positive rail. The OPA2333-Q1 uses chopping techniques to provide low initial offset
voltage and near-zero drift over time and temperature. Low offset voltage and low drift reduce the offset error in
the system, making these devices appropriate for precise dc control. The rail-to-rail output stage of the
OPA2333-Q1 makes sure that the output swing of the operational amplifier is able to fully control the gate of the
MOSFET devices within the supply rails.
A detailed error analysis, design procedure, and additional measured results are given in the High-Side V-I
Converter reference design.
8.2.1.3 Application Curve
0.1
Load
Output Current (A)
0.075
0.05
0.025
0
0
0.5
1
Input Voltage (V)
1.5
2
D001
Figure 21. Measured Transfer Function for High-Side V-I Converter
12
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Typical Application (continued)
8.2.1.4 Single Op Amp Bridge Amplifier
Figure 22 shows the basic configuration for a bridge amplifier.
VEX
R1
+5V
R R
R R
1/2
OPA2333
VOUT
R1
VREF
Figure 22. Single Op-Amp Bridge Amplifier
8.2.1.5 Low-Side Current Monitor
A low-side current shunt monitor is shown in Figure 23. RN are operational resistors used to isolate the ADS1100
from the noise of the digital I2C bus. Because the ADS1100 is a 16-bit converter, a precise reference is essential
for maximum accuracy. If absolute accuracy is not required, and the 5-V power supply is sufficiently stable, the
REF3130 may be omitted.
5V
REF3130
3V
Load
R1
4.99 k:
R2
49.9 k:
R6
71.5 k:
V
I LOAD
RN
56 :
1/2
OPA2333
R SHUNT
1:
R3
4.99 k:
R4
48.7 k:
Stray Ground-Loop Resistance
ADS1100
R7
1.18 k:
RN
56 :
I 2C
(PGA Gain = 4)
FS = 3.0 V
NOTE: 1% resistors provide adequate common-mode rejection at small ground-loop errors.
Figure 23. Low-Side Current Monitor
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Typical Application (continued)
8.2.1.6 High-Side Current Monitor
Figure 24 shows the use case for a precision single-supply amplifier for a high-side current sensing circuit.
RG
R SHUNT
zener(A)
V+
R 1(B)
10k:
1/2
OPA2333
MOSFET rated to
standoff supply voltage
such as BSS84 for
up to 50 V.
+5V
V+
Two zener
biasing methods
are shown.(C)
Output
R BIAS
Load
RL
A.
Zener rated for op amp supply capability (that is, 5.1 V for the OPA2333).
B.
Current-limiting resistor.
C.
Choose a Zener biasing resistor or dual NMOSFETs (FDG6301N, NTJD4001N, or Si1034).
Figure 24. High-Side Current Monitor
8.2.1.7 Precision Instrumentation Amplifier
Figure 25 shows a three op amp implementation for a high-CMRR instrumentation amplifier..
V1
ïIn
OPA333
1/2
OPA2333
2
R2
R1
5
6
R2
3
V2
+In
VO
1
1/2
OPA2333
V O =(1 +2R 2/R 1) (V 2 ïV 1)
Figure 25. Precision Instrumentation Amplifier
14
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9 Power Supply Recommendations
The OPA2333-Q1 is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply
from –40°C to +125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages greater than 7 V can permanently damage the device (see the
Absolute Maximum Ratings table).
Place 0.1-μF bypass capacitors near the power-supply pins to reduce coupling errors from noisy or highimpedance power supplies. For more details on bypass capacitor placement, see the Layout section.
10 Layout
10.1 Layout Guidelines
Pay attention to good layout practices. Keep traces short and when possible, use a printed-circuit-board (PCB)
ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-μF
capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to improve
performance and provide benefits, such as reducing the electromagnetic interference (EMI) susceptibility.
Operational amplifiers vary in susceptibility to radio frequency interference (RFI). RFI can generally be identified
as a variation in offset voltage or dc signal levels with changes in the interfering RF signal. The OPA2333-Q1 is
specifically designed to minimize susceptibility to RFI and demonstrates remarkably low sensitivity compared to
previous generation devices. Strong RF fields may still cause varying offset levels.
For lowest offset voltage and precision performance, optimize circuit layout and mechanical conditions. Avoid
temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from
connecting dissimilar conductors. Cancel these thermally-generated potentials by assuring they are equal on
both input terminals. Other layout and design considerations include:
• Use low-thermoelectric-coefficient connections (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltages of 0.1 μV/°C or higher, depending on materials used.
10.2 Layout Example
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
NC
NC
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
VS±
GND
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 26. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, ADS1100 Self-Calibrating, 16-Bit Analog-to-Digital Converter data sheet
• Texas Instruments, REF31xx 15ppm/°C Maximum, 100-μA, SOT-23 Series Voltage Reference data sheet
• Texas Instruments, INAx321 microPower, Single-Supply, CMOS Instrumentation Amplifier data sheet
• Texas Instruments, INA32x Precision, Rail-to-Rail I/O Instrumentation Amplifier data sheet
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2333AQDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
OPA2333AQDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
OCOQ
-40 to 125
02333Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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