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OPA355, OPA2355, OPA3355
SBOS195E – MARCH 2001 – REVISED APRIL 2018
OPAx355 200-MHz CMOS Operational Amplifiers With Shutdown
1 Features
3 Description
•
•
•
•
The OPA355 series of high-speed, voltage-feedback
CMOS operational amplifiers are designed for video
and other applications requiring wide bandwidth. The
OPA355 series is unity-gain stable and can drive
large output currents. In addition, the OPAx355 series
has a digital shutdown (enable) function. This feature
provides power saving during idle periods and places
the output in a high-impedance state to support
output multiplexing. The differential gain is 0.02% and
the differential phase is 0.05°. The quiescent current
is 8.3 mA per channel.
1
•
•
•
•
•
•
•
•
Unity-Gain Bandwidth: 450 MHz
Wide Bandwidth: 200 MHz GBW
Low Noise: 5.8 nV/√Hz
Excellent Video Performance
– Differential Gain: 0.02%
– Differential Phase: 0.05°
– 0.1-dB Gain Flatness: 75 MHz
Input Range Includes Ground
Rail-to-Rail Output (within 100 mV)
Low Input Bias Current: 3 pA
Low Shutdown Current: 3.4 µA
Enable and Disable Time: 100 ns and 30 ns
Thermal Shutdown
Single-Supply Operating Range: 2.5 V to 5.5 V
MicroSIZE Packages
The OPAx355 series is optimized for operation on
single supply or dual supplies as low as 2.5 V (±1.25
V) and up to 5.5 V (±2.75 V). The common-mode
input range for the OPAx355 series extends 100 mV
below ground and up to 1.5 V from V+. The output
swing is within 100 mV of the rails, supporting wide
dynamic range.
The OPAx355 series is available in single (SOT-23-6
and SO-8), dual (VSSOP-10), and triple (TSSOP-14
and SO-14) versions. Multichannel versions feature
completely independent circuitry for lowest crosstalk
and freedom from interaction. All packages are
specified from –40°C to +125°C.
2 Applications
•
•
•
•
•
•
•
•
•
•
Video Processing
Ultrasound
Optical Networking, Tunable Lasers
Photodiode Transimpedance Amplifiers
Active Filters
High-Speed Integrators
Analog-to-Digital Converter (ADC) Input Buffers
Digital-to-Analog Converter (DAC) Output
Amplifiers
Barcode Scanners
Communications
Device Information(1)
PART NUMBER
OPA355
OPA2355
OPA3355
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
SOT-23 (6)
2.90 mm × 1.60 mm
VSSOP (10)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
V+
±VIN
OPA355
Out
+VIN
V± Enable
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA355, OPA2355, OPA3355
SBOS195E – MARCH 2001 – REVISED APRIL 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Absolute Maximum Ratings ...................................... 7
ESD Ratings ............................................................ 7
Recommended Operating Conditions....................... 7
Thermal Information: OPA355 .................................. 8
Thermal Information: OPA2355 ................................ 8
Thermal Information: OPA3355 ................................ 8
Electrical Characteristics: VS = 2.7 V to 5.5 V (SingleSupply) ....................................................................... 9
7.8 Typical Characteristics ............................................ 11
8
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 17
9
Application and Implementation ........................ 18
9.1
9.2
9.3
9.4
Application Information............................................
Typical Applications ................................................
Video .......................................................................
Wideband Video Multiplexing..................................
18
18
22
23
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2004) to Revision E
Page
•
Updated data sheet to latest TIS documentation and translation standards ........................................................................ 1
•
Changed pin type typo from MSOP to VSSOP in Description section .................................................................................. 1
•
Added Device Information table ............................................................................................................................................. 1
•
Deleted the Absolute Maximum Ratings table note: Input terminals are diode-clamped to the power-supply rails.
Input signals that can swing more than 0.5 V beyond the supply rails should be current limited to 10 mA or less. ............. 7
•
Added ESD Ratings table....................................................................................................................................................... 7
•
Added Recommended Operating Conditions table ............................................................................................................... 7
•
Added Thermal Information tables ......................................................................................................................................... 8
•
Changed pin type typo from MSOP to VSSOP in Electrical Characteristics section .......................................................... 10
•
Deleted the test conditions statement from Typical Characteristics graphs and moved the conditions to tablenotes
below the graphs ................................................................................................................................................................. 11
•
Added Detailed Description section ..................................................................................................................................... 16
•
Added Functional Block Diagram graphic ............................................................................................................................ 16
•
Deleted Input and ESD Protection section .......................................................................................................................... 16
•
Added Application and Implementation section .................................................................................................................. 18
•
Deleted Internal ESD Protection application ....................................................................................................................... 18
•
Added Power Supply Recommendations section ............................................................................................................... 25
•
Added Layout Guidelines section ........................................................................................................................................ 25
2
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Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: OPA355 OPA2355 OPA3355
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SBOS195E – MARCH 2001 – REVISED APRIL 2018
5 Device Comparison Table
OPAx355 RELATED PRODUCTS
FEATURES
OPA356
200-MHz, Rail-to-Rail Output, CMOS, No Shutdown
OPAx350
38-MHz, Rail-to-Rail Input and Output, CMOS
OPAx631
75-MHz, Rail-to-Rail Output
OPAx634
150-MHz, Rail-to-Rail Output
THS412x
Differential Input and Output, 3.3-V Supply
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: OPA355 OPA2355 OPA3355
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SBOS195E – MARCH 2001 – REVISED APRIL 2018
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6 Pin Configuration and Functions
OPA355 DBV Package
6-Pin SOT-23
Top View
OUT 1
6
V± 2
5
+IN 3
(1)
OPA355 D Package
8-Pin SOIC
Top View
4
V+
NC (2)
1
±IN
2
+IN
3
V±
4
8
ENABLE
±
7
V+
+
6
OUT
5
NC(2)
ENABLE
±IN
Pin 1 of the SOT-23-6 is determined by
orienting the package marking as indicated
in the diagram.
(1)
Pin 1 of the SOT-23-6 is determined by
orienting the package marking as indicated
in the diagram.
(2)
NC - no internal connection
Pin Functions: OPA355
PIN
NAME
I/O
DESCRIPTION
SOT-23
SOIC
ENABLE
5
8
—
IN+
3
3
I
Noninverting input pin
IN–
4
2
I
Inverting input pin
NC
—
1,5
—
Do not connect.
OUT
1
6
O
Output pin
V+
6
7
—
Positive power supply
V–
2
4
—
Negative power supply
4
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Amplifier power down.
Low = disabled, high = normal operation (pin must be driven)
Copyright © 2001–2018, Texas Instruments Incorporated
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SBOS195E – MARCH 2001 – REVISED APRIL 2018
OPA2355 DGS Package
10-Pin VSSOP
Top View
OUT A
1
±IN A
2
+IN A
3
±
A
+
±
10
V+
9
OUT B
8
±IN B
7
+IN B
6
ENABLE B
B
V±
4
ENABLE A
5
+
Pin Functions: OPA2355
PIN
NAME
NO.
I/O
DESCRIPTION
ENABLE A
5
—
Amplifier power down, channel A.
Low = disabled, high = normal operation (pin must be driven)
ENABLE B
6
—
Amplifier power down, channel B.
Low = disabled, high = normal operation (pin must be driven)
+IN A
3
I
Noninverting input pin, channel A
+IN B
7
I
Noninverting input pin, channel B
–IN A
2
I
Inverting input pin, channel A
–IN B
8
I
Inverting input pin, channel B
OUT A
1
O
Output pin, channel A
OUT B
9
O
Output pin, channel B
V+
10
—
Positive power supply
V–
4
—
Negative power supply
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OPA3355 D and PW Packages
14-Pin SOIC, TSSOP
Top View
ENABLE A
1
ENABLE B
2
14
OUT C
13
±IN C
12
+IN C
11
V±
+
10
+IN B
±
9
±IN B
8
OUT B
±
C
ENABLE C
3
V+
4
+IN A
5
+
+
A
±IN A
6
OUT A
7
B
±
Pin Functions: OPA3355
PIN
NAME
NO.
I/O
DESCRIPTION
ENABLE A
1
—
Amplifier power down, channel A.
Low = disabled, high = normal operation (pin must be driven)
ENABLE B
2
—
Amplifier power down, channel B.
Low = disabled, high = normal operation (pin must be driven)
ENABLE C
3
—
Amplifier power down, channel C.
Low = disabled, high = normal operation (pin must be driven)
+IN A
5
I
Noninverting input pin, channel A
+IN B
10
I
Noninverting input pin, channel B
+IN C
12
I
Noninverting input pin, channel C
–IN A
6
I
Inverting input pin, channel A
–IN B
9
I
Inverting input pin, channel B
–IN C
13
I
Inverting input pin, channel C
OUT A
7
O
Output, channel A
OUT B
8
O
Output channel B
OUT C
14
O
Output, channel C
V+
4
—
Positive power supply
V–
11
—
Negative power supply
6
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SBOS195E – MARCH 2001 – REVISED APRIL 2018
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage
Signal input terminals
V+ to V–
Voltage
(V–) – 0.5
Current
Output short circuit (2)
MAX
UNIT
7.5
V
(V+) + 0.5
V
10
mA
Continuous
Operating temperature
150
°C
Junction temperature
–55
160
°C
Lead temperature (soldering, 10 seconds)
300
°C
150
°C
Storage temperature range, Tstg
(1)
(2)
–65
Stresses above Absolute Maximum Ratings may cause permanent damage. Exposure to absolute maximum conditions for extended
periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those specified is not implied.
Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±250 V may actually have higher performance.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS Total supply voltage
2.7
TA Ambient temperature
–40
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NOM
25
MAX
UNIT
5.5
V
125
°C
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OPA355, OPA2355, OPA3355
SBOS195E – MARCH 2001 – REVISED APRIL 2018
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7.4 Thermal Information: OPA355
OPA355
THERMAL METRIC (1)
D (SOIC)
DBV (SOT-23)
8 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
136.3
166.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
76.7
104.3
°C/W
RθJB
Junction-to-board thermal resistance
79.8
38.7
°C/W
ψJT
Junction-to-top characterization parameter
26.3
23.4
°C/W
ψJB
Junction-to-board characterization parameter
79
38.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: OPA2355
OPA2355
THERMAL METRIC
(1)
DGS (VSSOP)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
6.7
°C/W
ψJB
Junction-to-board characterization parameter
91.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
171.1
°C/W
58
°C/W
92.9
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information: OPA3355
OPA3355
THERMAL METRIC
(1)
D (SOIC)
PW (TSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
85.3
113.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
41.4
38
°C/W
RθJB
Junction-to-board thermal resistance
41.5
58.1
°C/W
ψJT
Junction-to-top characterization parameter
8.3
2.8
°C/W
ψJB
Junction-to-board characterization parameter
41.2
57.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS195E – MARCH 2001 – REVISED APRIL 2018
7.7 Electrical Characteristics: VS = 2.7 V to 5.5 V (Single-Supply)
at TA = 25°C, RF = 604 Ω, RL = 150 Ω, and connected to VS / 2, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage vs
temperature
VS = 5 V
±2
TA = –40°C to +125°C
±9
mV
±15
TA = –40°C to +125°C
±7
Input offset voltage vs power
supply
µV/°C
±80
±350
µV/V
3
±50
pA
±1
±50
pA
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
NOISE
Input noise voltage density
f = 1 MHz
5.8
nV/√Hz
Current noise density
f = 1 MHz
50
fA/√Hz
INPUT VOLTAGE RANGE
VCM
CMRR
Common-mode voltage range
Common-mode rejection ratio
(V–) – 0.1
VS = 5.5 V, –0.1 V < VCM < 4 V
66
VS = 5.5 V, –0.1 V < VCM < 4 V
TA = –40°C to +125°C
66
(V+) – 1.5
V
80
dB
dB
INPUT IMPEDANCE
Differential
1013 || 1.5
Ω || pF
Common-mode
1013 || 1.5
Ω || pF
OPEN-LOOP GAIN
Open-loop gain
VS = 5 V, 0.3 V < VO < 4.7 V
84
OPA355:
VS = 5 V, 0.3 V < VO < 4.7 V
TA = –40°C to +125°C
92
dB
80
dB
OPA2355, OPA3355:
VS = 5 V, 0.4 V < VO < 4.6 V
80
dB
FREQUENCY RESPONSE
f–3dB
Small-signal bandwidth
G = 1, VO = 100 mVp-p, RF = 0 Ω
450
MHz
G = 2, VO = 100 mVp-p, RL = 50 Ω
100
MHz
G = 2, VO = 100 mVp-p, RL = 150 Ω
170
MHz
G = 2, VO = 100 mVp-p, RL = 1 kΩ
200
MHz
200
MHz
75
MHz
300 / –360
V/µs
GBW
Gain-bandwidth product
G = 10, RL = 1 kΩ
f0.1dB
Bandwidth for 0.1-dB gain
flatness
G = 2, VO = 100 mVp-p, RF = 560 Ω
SR
Slew rate
VS = 5 V, G = 2, 4-V output step
Rise and fall time
Settling time
Overload recovery time
G = 2, VO = 200 Vp-p, 10% to 90%
2.4
ns
G = 2, VO = 2 Vp-p, 10% to 90%
8
ns
0.1%:
VS = 5 V, G = 2, 2-V output step
30
ns
0.01%:
VS = 5 V, G = 2, 2-V output step
120
ns
8
ns
VIN × gain = VS
HARMONIC DISTORTION
Second harmonic
G = 2, f = 1 MHz, VO = 2 Vp-p, RL =
200 Ω
–81
dBc
Third harmonic
G = 2, f = 1 MHz, VO = 2 Vp-p, RL =
200 Ω
–93
dBc
Differential gain error
NTSC, RL = 150 Ω
0.02
%
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Electrical Characteristics: VS = 2.7 V to 5.5 V (Single-Supply) (continued)
at TA = 25°C, RF = 604 Ω, RL = 150 Ω, and connected to VS / 2, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Differential phase error
Channel-to-channel crosstalk
MIN
TYP
MAX
UNIT
NTSC, RL = 150 Ω
0.05
°
OPA2355: f = 5 MHz
–90
dB
OPA3335: f = 5 MHz
–70
dB
VS = 5 V, RL = 150 Ω, AOL > 84 dB
0.2
VS = 5 V, RL = 1 kΩ
0.1
V
±60
mA
VS = 5 V
±100
mA
VS = 3 V
±80
mA
f < 100 kHz
0.02
Ω
OUTPUT
Voltage output swing from rail
Continuous output current
IO
Peak output current
(1)
(1)
Closed-loop output impedance
(1)
0.3
V
POWER SUPPLY
VS
Specified voltage range
2.7
Operating voltage range
IQ
5.5
2.5 to 5.5
Quiescent current (per amplifier)
VS = 5 V, enabled, IO = 0
8.3
TA = –40°C to +125°C
V
V
11
mA
14
mA
0.8
V
SHUTDOWN
Disabled (logic-LOW threshold)
Enabled (logic-HIGH threshold)
2
Enable time
V
100
Disable time
30
Shutdown current (per amplifier) VS = 5 V, disabled
3.4
ns
ns
6
µA
THERMAL SHUTDOWN
Junction temperature
Shutdown
160
Reset from shutdown
140
°C
TEMPERATURE RANGE
θJA
(1)
10
Specified range
–40
125
°C
Operating range
–55
150
°C
Storage range
–65
150
Thermal resistance
°C
SOT-23-6, VSSOP-10
150
°C/W
SO-8
125
°C/W
SO-14, TSSOP-14
100
°C/W
See Output Voltage Swing vs Output Current.
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7.8 Typical Characteristics
TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2, (unless otherwise noted)
3
6
G=1
RF = 0
0
Normalized Gain (dB)
Normalized Gain (dB)
3
0
–3
G=2
–6
G=5
–9
G = 10
1M
G = –5
G = –2
–6
G =–15
–10
–9
–12
–12
–15
100k
G = –1
–3
10M
Frequency (Hz)
100M
100k
1G
VO = 0.1 VP-P
1M
10M
Frequency (Hz)
100M
1G
VO = 0.1 VP-P
Figure 2. Inverting Small-Signal Frequency Response
Output Voltage (50 mV/div)
Output Voltage (500 mV/div)
Figure 1. Noninverting Small-Signal Frequency Response
Time (20 ns/div)
Time (20 ns/div)
G=2
G=2
Figure 3. Noninverting Small-Signal Step Response
0.5
Enabled
4.5
0.4
RF = 604
3.5
2.5
1.5
VO
Normalized Gain (dB)
0.3
Disable Voltage (V)
Output Voltage (500 mV/div)
fIN = 5 MHz
Disabled
Figure 4. Noninverting Large-Signal Step Response
0.2
0.1
0
–0.1
RF = 560
–0.2
–0.3
RF = 500
–0.4
0.5
–0.5
1
Time (200 ns/div)
CL = 0 pF
Figure 5. Large-Signal Disable and Enable Response
10
Frequency (MHz)
100
VO = 0.1 VP-P
Figure 6. 0.1-dB Gain Flatness for Various RF Values
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Typical Characteristics (continued)
–50
–50
–60
–60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2, (unless otherwise noted)
–70
2nd Harmonic
–80
3rd Harmonic
–90
–100
–70
2nd-Harmonic
–80
3rd-Harmonic
–90
–100
0
RL = 200
1
2
Output Voltage (Vp-p)
3
4
1
ƒ = 1 MHz
RL = 200
Figure 7. Harmonic Distortion vs Output Voltage
VO = 2 VP-P
Harmonic Distortion (dBc)
–50
–60
–70
2nd-Harmonic
–80
3rd-Harmonic
–90
–100
1
–60
2nd-Harmonic
–70
–80
3rd-Harmonic
–90
–100
100k
10
1M
Frequency (Hz)
Gain (V/V)
RL = 200
VO = 2 VP-P
ƒ = 1 MHz
RL = 200
Harmonic Distortion (dBc)
–60
–70
–80
2nd-Harmonic
–90
3rd-Harmonic
–100
100
1k
RL (Ω)
ƒ = 1 MHz
VO = 2 VP-P
10k
1k
Voltage Noise
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Current Noise
100
10
1
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
VO = 2 VP-P
Figure 11. Harmonic Distortion vs Load Resistance
10M
Figure 10. Harmonic Distortion vs Frequency
Voltage Noise (nV/√Hz), Current Noise (fA/√Hz)
Figure 9. Harmonic Distortion vs Inverting Gain
–50
12
ƒ = 1 MHz
Figure 8. Harmonic Distortion vs Noninverting Gain
–50
Harmonic Distortion (dBc)
10
Gain (V/V)
Figure 12. Input Voltage and Current Noise Spectral Density
vs Frequency
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Typical Characteristics (continued)
TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2, (unless otherwise noted)
9
3
RL = 10 k
RL = 50
–6
RL = 150
–9
RL = 1 k
0
–3
CL = 5.6 pF
–6
–9
–12
–15
100k
1M
10M
Frequency (Hz)
CL = 0 pF
100M
–15
100k
1G
VO = 0.1 VP-P
Figure 13. Frequency Response for Various RL Values
0
Normalized Gain (dB)
100
80
VI
RS
VO
OPAx355
40
CL
1k
604
20
0
100M
1G
VO = 0.1 VP-P
CL = 5.6 pF
RS = 80
CL = 100 pF
RS = 24
D3
VI
D6
RS
VO
OPAx355
CL
D9
CL = 47 pF
RS = 36
1k
604
D12
(1k is
Optional)
604
10M
Frequency (Hz)
Figure 14. Frequency Response for Various CL Values
3
60
1M
RS = 0
120
RS (Ω)
CL = 47 pF
3
Normalized Gain (dB)
Normalized Gain (dB)
–3
–12
(1k is
Optional)
604
D15
1
10
Capacitive Load (pF)
100
1M
Figure 15. Recommended RS Values vs Capacitive Load
10M
100M
Frequency (Hz)
1G
Figure 16. Frequency Response vs Capacitive Load
100
180
90
160
Open-Loop Phase (degrees)
Open-Loop Gain (dB)
DPSRR
80
CMRR, PSRR (dB)
CL = 100 pF
6
0
+PSRR
70
60
CMRR
50
40
30
20
10
140
120
Phase
100
80
60
Gain
40
20
RL = 1 kW
RL = 150 kW
0
0
–20
10k
100k
1M
10M
Frequency (Hz)
100M
1G
Figure 17. Common-Mode Rejection Ratio and PowerSupply Rejection Ratio vs Frequency
1k
10k
100k
1M
10M
Frequency (Hz)
100M
1G
Figure 18. Open-Loop Gain and Phase
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Typical Characteristics (continued)
TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2, (unless otherwise noted)
0.40
10n
Input Bias Current (pA)
0.35
dG/dP (%/degrees)
0.30
0.25
0.20
dP
0.15
1n
100
10
0.10
dG
0.05
1
0
1
2
3
Number of 150 Loads
–55
4
Figure 19. Composite Video Differential Gain and Phase
–35
–15
5
12
VS = 5.5 V
Supply Current (mA)
–55°C
Output Voltage (V)
105 125 135
Figure 20. Input Bias Current vs Temperature
25°C
2
125°C
125°C
1
–55°C
25°C
0
30
60
90
Output Current (mA)
10
8
6
VS = 5 V
120
0
150
–55
–35
–15
5
Continuous currents above 60 mA are not recommended
VS = 3 V
Figure 21. Output Voltage Swing vs Output Current
25
45
65
Temperature (°C)
4.5
25°C
Shutdown Current (A)
125°C
3
2
125°C
1
VS = 5.5 V
3.5
VS = 5 V
3.0
2.5
2.0
1.5
VS = 3 V
1.0
0.5
0
200
250
0
–55
–35
–15
Continuous currents above 60 mA are not recommended
VS = 5 V
Figure 23. Output Voltage Swing vs Output Current
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VS = 2.5 V
–55°C
25°C
100
150
Output Current (mA)
105 125 135
4.0
–55°C
4
50
85
Figure 22. Supply Current vs Temperature
5
0
VS = 2.5 V
VS = 3 V
4
2
0
Output Voltage (V)
85
14
3
14
25
45
65
Temperature (°C)
5
25
45
65
Temperature (°C)
85
105 125 135
Figure 24. Shutdown Current vs Temperature
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Typical Characteristics (continued)
TA = 25°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2, (unless otherwise noted)
6
100
VS = 5.5 V
5
Output Voltage (Vp-p)
Output Impedance (Ω)
10
1
OPAx355
0.1
ZO
604
0.01
4
3
VS = 2.7 V
2
1
604
0.001
0
10k
100k
1M
10M
Frequency (Hz)
100M
1G
1
10
Frequency (MHz)
100
Maximum output voltage without slew-rate induced distortion
Figure 25. Closed-Loop Output Impedance vs Frequency
Figure 26. Maximum Output Voltage vs Frequency
0.2
110
RL = 1k
100
Open-Loop Gain (dB)
Output Error (%)
0.1
0
–0.1
–0.2
–0.3
–0.4
90
RL = 150
80
70
60
0
5
10
15
20 25
30
Time (ns)
35
40
45
50
–55
–35
–15
5
25
45
65
Temperature (°C)
85
105 125 135
VO = 2 VP-P
Figure 27. Output Settling Time to 0.1%
Figure 28. Open-Loop Gain vs Temperature
20
100
Power-Supply Rejection Ratio
16
90
CMRR, PSRR (dB)
Percent of Amplifiers (%)
18
14
12
10
8
6
4
80
Common-Mode Rejection Ratio
70
60
2
0
50
–9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9
Offset Voltage (mV)
Figure 29. Offset Voltage Production Distribution
–55
–35
–15
5
25
45
65
Temperature (°C)
85
105 125 135
Figure 30. Common-Mode Rejection Ratio and PowerSupply Rejection Ratio vs Temperature
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8 Detailed Description
8.1 Overview
The OPA355 series is a CMOS, high-speed, voltage-feedback, operational amplifier designed for video and other
general-purpose applications. The series is available as a single, dual, or triple op amp. The family features a
200-MHz gain bandwidth and 360 V/µs slew rate, but the series is unity-gain stable and can operate as a 1 V/V
voltage follower.
The input common-mode range includes ground, allowing the OPAx355 family to be used in virtually any singlesupply application up to a supply voltage of 5.5 V.
8.2 Functional Block Diagram
V+
Reference
Current
VIN+
VIN±
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V±
(Ground)
8.3 Feature Description
8.3.1 Operating Voltage
The OPAx355 family is specified over a power-supply range of 2.7 V to 5.5 V (±1.35 to ±2.75 V). However, the
supply voltage ranges from 2.5 to 5.5 V (±1.25 to ±2.75 V). Supply voltages higher than 7.5 V (absolute
maximum) can permanently damage the amplifier.
Parameters that vary significantly over supply voltage or temperature are shown in the Typical Characteristics
section of this data sheet.
8.3.2 Enable Function
The OPAx355 series is enabled by applying a TTL high-voltage level to the enable pin. Conversely, a TTL low voltage level disables the amplifier, which reduces the supply current from 8.3 mA to 3.4 μA per amplifier. This
pin voltage is referenced to a single-supply ground. When using a split-supply, such as ±2.5 V, the enable and
disable voltage levels are referenced to V–. For portable battery-operated applications, this feature greatly
reduces the average current and as a result, extends battery life.
The enable input is modeled as a CMOS input gate with a 100-kΩ pullup resistor to V+. The enable pin assumes
a logic high and the amplifier turns on if the enable pin is left open.
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Feature Description (continued)
The enable time is 100 ns and the disable time is 30 ns, which allows the OPAx355 series to operate as a gated
amplifier, or to have the output multiplexed onto a common output bus. When disabled, the output assumes a
high-impedance state.
8.3.3 Output Drive
The output stage supplies a high short-circuit current (typically over 200 mA). Therefore, an on-chip thermal
shutdown circuit is provided to protect the OPAx355 series from dangerously-high junction temperatures. At
160°C, the protection circuit shuts down the amplifier. Normal operation resumes when the junction temperature
cools to below 140°C.
NOTE
Running a continuous DC current in excess of ±60 mA is not recommended. See the
Output Voltage Swing vs Output Current graphs (Figure 21 and Figure 22) in the Typical
Characteristics section.
8.4 Device Functional Modes
The OPAx355 family is powered on when the supply is connected. The series operates as a single supply
operational amplifier or dual supply amplifier depending on the application. The series is used with asymmetrical
supplies as long as the differential voltage (V– to V+) is at least 1.8 V and no greater than 5.5 V (example: V– set
to –3.5 V and V+ set to 1.5 V).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPAx355 series is a CMOS, high-speed, voltage-feedback, operational amplifier (op amp) designed for
general-purpose applications.
The amplifiers feature a 200-MHz gain bandwidth and 300-V/μs slew rate, but the devices are unity-gain stable
and operate as a 1-V/V voltage follower.
The input common-mode voltage range of the series includes ground, which allows the OPAx355 to be used in
virtually any single-supply application up to a supply voltage of 5.5 V.
9.2 Typical Applications
9.2.1 Transimpedance Amplifier
Wide gain bandwidth, low input bias current, low input voltage, and current noise make the OPAx355 series a
preferred wideband photodiode transimpedance amplifier family. Low voltage noise is important because
photodiode capacitance causes the effective noise gain of the circuit to increase at high frequencies.
The key elements to a transimpedance design, as shown in Figure 31, are the expected diode capacitance (C[D]),
which must include the parasitic input common-mode and differential-mode input capacitance (4 pF + 5 pF), the
desired transimpedance gain (R[FB]), and the gain-bandwidth (GBW) for the OPAx355 family (20 MHz). With
these three variables set, the feedback capacitor value (C[FB]) controls the frequency response. C[FB] includes the
stray capacitance of R[FB], which is 0.2 pF for a typical surface-mount resistor.
(1)
C
(F)
< 1 pF
R (F)
10 M
V(V+)
l
C
(D)
OPAx355
V
V
O
(V±)
(1) C(FB) is optional to prevent gain peaking. C(FB) includes the stray capacitance of R(FB).
Figure 31. Dual-Supply Transimpedance Amplifier
9.2.1.1 Design Requirements
PARAMETER
18
VALUE
Supply voltage V(V+)
2.5 V
Supply voltage V(V–)
–2.5 V
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9.2.1.2 Detailed Design Procedure
To achieve a maximally-flat, second-order Butterworth frequency response, set the feedback pole to:
1
=
2 ´ p ´ R(FB) ´ C(FB)
GBW
4 ´ p ´ R(FB) ´ C(D)
(1)
Use Equation 2 to calculate the bandwidth.
ƒ(–3 dB) =
GBW
2 ´ p ´ R(FB) ´ C(D)
(2)
For other transimpedance bandwidths, consider the high-speed CMOS OPA380 (90-MHz GBW), OPA354 (100MHz GBW), OPA300 (180-MHz GBW), OPA355 (200-MHz GBW), or OPA656 and OPA657 (400-MHz GBW).
For single-supply applications, the +INx input is biased with a positive DC voltage to allow the output to reach
true zero when the photodiode is not exposed to any light, and respond without the added delay that results from
coming out of the negative rail. Figure 32 shows this configuration. This bias voltage appears across the
photodiode, providing a reverse bias for faster operation.
0.5 pF
100 k
±
OPA355
VOUT
+
13.7 k
SFH213
1 F
280
5V
Figure 32. Single-Supply Transimpedance Amplifier
For additional information, see Compensate Transimpedance Amplifiers Intuitively.
9.2.1.2.1 Optimizing The Transimpedance Circuit
To achieve the best performance, select components according to the following guidelines:
1. For lowest noise, select R(FB) to create the total required gain. Using a lower value for R(FB) and adding gain
after the transimpedance amplifier generally results in poorer noise performance. R(FB) produces noise that
increases with the square root of R(FB), whereas the signal increases linearly. Therefore, signal-to-noise ratio
improves when all the required gain is placed in the transimpedance stage.
2. Minimize photodiode capacitance and stray capacitance at the summing junction (inverting input). This
capacitance causes the voltage noise of the op amp to amplify (increasing amplification at high frequencies).
Using a low-noise voltage source to reverse-bias a photodiode can significantly reduce the capacitance.
Smaller photodiodes have lower capacitance. Use optics to concentrate light on a small photodiode.
3. Noise increases with increased bandwidth. Only use the required circuit bandwidth. Use a capacitor across
the R(FB) to limit bandwidth, even if a capacitor is not required for stability.
4. Circuit board leakage can degrade the performance of an otherwise well-designed amplifier. Clean the circuit
board carefully. Control leakage by using a circuit board guard trace that encircles the summing junction and
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drives at the same voltage.
For additional information, see Noise Analysis of FET Transimpedance Amplifiers and Noise Analysis for HighSpeed Op Amps).
9.2.1.3 Application Curve
105
100
Gain (dB, V/A)
95
90
85
80
75
70
65
60
1000
10000
100000
1000000
Frequency (Hz)
1E+7
5E+7
D001
–3 dB bandwidth is 4.56 MHz
Figure 33. AC Transfer Function
9.2.2 High-Impedance Sensor Interface
Many sensors have high source impedances that may range up to 10 MΩ, or even higher. The output signal of
sensors often must be amplified or otherwise conditioned by an amplifier. The input bias current of this amplifier
loads the sensor output and causes a voltage drop across the source resistance, Figure 34 shows (V(+INx) = VS –
I(BIAS) × R(S).)The last term (I(BIAS) × R(S)) shows the voltage drop across R(S). To prevent errors introduced to the
system as a result of this voltage, use an op amp with low input bias current with high-impedance sensors. This
low current keeps the I(BIAS) × R(S) error contribution less than the input voltage noise of the amplifier so that input
voltage noise is not the dominant noise factor. The OPAx355 op amps feature low input bias current (typically
200 fA), and as a result, a preferred choice for these applications.
R(S)
100 kΩ
IIB
V(+INx)
V(V+)
Device
V(V–)
VO
R(F)
R(G)
Figure 34. Noise as a Result of I(BIAS)
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9.2.3 Driving ADCs
The OPAx355 op amps are designed to drive sampling analog-to-digital converters (ADCs) with sampling speeds
up to 1 MSPS. The zero-crossover distortion input stage topology allows the OPAx355 series to drive ADCs
without degrading differential linearity and THD.
The OPAx355 series buffers the ADC switched input capacitance and resulting charge injection while providing
signal gain. Figure 35 shows the OPAx355 series configured to drive the ADS8326.
5V
C1
100 nF
V
5V
(1)
R1
100
(V+)
+INx
OPAx355
ADS8326
16-Bit
250kSPS
(1)
V
C3
1 nF
(V±)
V
I
0 to 4.096 V
±INx
REF IN
(2)
5V
Optional
R2
50 k
SD1
BAS40
±5 V
C2
100 nF
REF3240
4.096 V
C4
100 nF
(1) Suggested value; may require adjustment based on specific application.
(2) Single-supply applications lose a small number of ADC codes near ground as a result of op amp output swing limitation. If a negative
power supply is available, this simple circuit creates a –0.3-V supply to allow output swing to true ground potential.
Figure 35. Driving the ADS8326
9.2.4 Active Filter
The OPAx355 series is designed for active filter applications that require a wide bandwidth, fast slew rate, lownoise, single-supply operational amplifier. Figure 36 shows a 500 kHz, second-order, low-pass filter using the
multiple-feedback (MFB) topology. The components are selected to provide a maximally-flat Butterworth
response. Beyond the cutoff frequency, roll-off is –40 dB/dec. The Butterworth response is preferred for
applications requiring predictable gain characteristics, such as the anti-aliasing filter used in front of an ADC.
One point to observe when considering the MFB filter is that the output is inverted, relative to the input. If this
inversion is not required, or not desired, a noninverting output can be achieved through one of the following
options:
1. Adding an inverting amplifier
2. Adding an additional second-order MFB stage
3. Using a noninverting filter topology, such as the Sallen-Key (see Figure 37).
MFB and Sallen-Key, low-pass and high-pass filter synthesis is quickly accomplished using TI’s FilterPro™
program. This software is available as a free download at www.ti.com.
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R3
549 Ω
C2
150 pF
R1
549 Ω
R2
1.24 kΩ
V(V+)
VI
VO
Device
C1
1 nF
V(V–)
Figure 36. Second-Order Butterworth 500-kHz Low-Pass Filter
220 pF
1.8 kΩ
19.5 kΩ
V(V+)
150 kΩ
VI = 1 VRMS
3.3 nF
47 pF
Device
VO
V(V–)
Figure 37. OPAx355 Configured as a Three-Pole, 20-kHz, Sallen-Key Filter
9.3 Video
The OPAx355 output stage is capable of driving a standard back-terminated 75-Ω video cable. By backterminating a transmission line, the line does not exhibit a capacitive load to the driver. A properly backterminated 75-Ω cable does not appear as capacitance; the cable presents only a 150-Ω resistive load to the
OPAx355 output.
The OPAx355 can be used as an amplifier for RGB graphic signals, which have a voltage of zero at the video
black level by offsetting and AC-coupling the signal, as shown in Figure 38.
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Video (continued)
604
+3 V
+
1 µF 10 nF
604 Ÿ
V+
±
1/3
OPA355
R1
Red
(1)
220 µF
75
+
Red
75
R2
604
604 Ÿ
V+
±
1/3
OPA355
+
R1
Green (1)
220 µF
75
Green
75
R2
604
604 Ÿ
V+
±
1/3
OPA355
R1
Blue
(1)
220 µF
75
+
Blue
75
R2
Figure 38. RGB Cable Driver
9.4 Wideband Video Multiplexing
One common application for video speed amplifiers which include an enable pin is to wire multiple amplifier
outputs together, then select which one of several possible video inputs to source onto a single line. This simple
wired-OR video multiplexer can be easily implemented using the OPA357; see Figure 39.
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Wideband Video Multiplexing (continued)
+2.5 V
+
1 µF
10 nF
+
A
OPA355
49.9
Signal #1
±
+
1 µF
±2.5 V
10 nF
49.9
1k
VOUT
49.9
1k
+2.5 V
+
1 µF
10 nF
+
49.9
Signal #2
B
OPA355
±
+
1 µF
±2.5 V
10 nF
1k
1k
HCO4
BON
AON
Select
Figure 39. Multiplexed Output
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10 Power Supply Recommendations
The OPAx355 is specified for operation from 2.7 to 5.5 V (±1.35 to ±2.75 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are shown in the Typical Characteristics section.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
Power dissipation depends on power-supply voltage, signal and load conditions. With DC signals, power
dissipation is equal to the product of output current times the voltage across the conducting output transistor,
VS – VO. Minimize power dissipation by using the lowest possible power-supply voltage required to ensure the
required output voltage swing.
For resistive loads, the maximum power dissipation occurs at a DC output voltage of one-half the power-supply
voltage. Dissipation with AC signals is lower. Power Amplifier Stress and Power Handling Limitations explains
how to calculate or measure power dissipation with unusual signals and loads, and is available on www.ti.com.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, limit junction temperature to 150°C maximum. To estimate the margin of safety
in a complete design, increase the ambient temperature to trigger the thermal protection at 160°C. The thermal
protection must trigger more than 35°C above the maximum expected ambient condition of the application.
11 Layout
11.1 Layout Guidelines
Good high-frequency printed-circuit board (PCB) layout techniques must be used for the OPAx355 amplifiers.
Generous use of ground planes, short direct-signal traces, and a preferred bypass capacitor located at the V+
pin ensures clean and stable operation. Large areas of copper help dissipate heat generated within the amplifiers
in normal operation.
Sockets are not recommended for use with any high-speed amplifier.
A 10-nF ceramic bypass capacitor is the minimum recommended value; adding a 1-μF or larger tantalum
capacitor in parallel is beneficial when driving a low-resistance load. Providing adequate bypass capacitance is
essential to achieving very low harmonic and intermodulation distortion.
11.2 Layout Example
Ground and power plane exist on
inner layers
Ground and power plane removed
from inner layers
Place output resistors close
to output pins to minimize
parasitic capacitance
1
6
2
Noninverting input
terminated in 50 Ÿ
3
±
Place bypass capacitors
close to power pins
+
Place bypass capacitors
close to power pins
5
Power control (disable) pin
Must be driven
4
Place input resistor close to pin 4
to minimize stray capacitance
Place feedback resistor on the bottom
of PCB between pins 4 and 6
Remove GND and Power plane
under pins 1 and 4 to minimize
stray PCB capacitance
Figure 40. Layout Example
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Product Folder Links: OPA355 OPA2355 OPA3355
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OPA355, OPA2355, OPA3355
SBOS195E – MARCH 2001 – REVISED APRIL 2018
www.ti.com
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA355
Click here
Click here
Click here
Click here
Click here
OPA2355
Click here
Click here
Click here
Click here
Click here
OPA3355
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
FilterPro is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
26
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Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: OPA355 OPA2355 OPA3355
OPA355, OPA2355, OPA3355
www.ti.com
SBOS195E – MARCH 2001 – REVISED APRIL 2018
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2001–2018, Texas Instruments Incorporated
Product Folder Links: OPA355 OPA2355 OPA3355
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27
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
OPA2355DGSA/250
ACTIVE
VSSOP
DGS
10
250
RoHS & Green
Call TI | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D55
Samples
OPA2355DGSA/250G4
ACTIVE
VSSOP
DGS
10
250
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
D55
Samples
OPA3355EA/250
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
3355EA
Samples
OPA3355EA/2K5
ACTIVE
TSSOP
PW
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
3355EA
Samples
OPA3355UA
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA3355UA
Samples
OPA355NA/250
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
C55
Samples
OPA355NA/250G4
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
C55
Samples
OPA355NA/3K
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
C55
Samples
OPA355NA/3KG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
C55
Samples
OPA355UA
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
355UA
Samples
OPA355UA/2K5
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
355UA
Samples
OPA355UAG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
355UA
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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