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OPA357, OPA2357
SBOS235F – MARCH 2002 – REVISED APRIL 2018
OPAx357 250-MHz, Rail-to-Rail I/O, CMOS Operational Amplifier With Shutdown
1 Features
3 Description
•
•
•
•
•
•
•
The OPA357 series of high-speed, voltage-feedback
CMOS operational amplifiers is designed for video
and other applications requiring wide bandwidth.
These devices are unity-gain stable and can drive
large output currents. Differential gain is 0.02% and
differential phase is 0.09°. Quiescent current is only
4.9 mA per channel.
1
•
•
•
•
•
•
•
Unity-Gain Bandwidth: 250 MHz
Wide Bandwidth: 100-MHz GBW
High Slew Rate: 150 V/µs
Low Noise: 6.5 nV/√Hz
Rail-to-Rail I/O
High Output Current: > 100 mA
Excellent Video Performance:
– Differential Gain: 0.02%, Differential Phase:
0.09°
– 0.1-dB Gain Flatness: 40 MHz
Low Input Bias Current: 3 pA
Quiescent Current: 4.9 mA
Thermal Shutdown
Supply Range: 2.5 V to 5.5 V
Shutdown IQ < 6 µA
MicroSIZE Package
Create a Custom Design Using the OPA357 With
the WEBENCH® Power Designer
The OPA357 series of op amps is optimized for
operation on single or dual supplies as low as 2.5 V
(±1.25 V) and up to 5.5 V (±2.75 V). Common-mode
input range extends beyond the supplies. The output
swing is within 100 mV of the rails, supporting wide
dynamic range.
The single version (OPA357) comes in the miniature
SOT23-6 package. The dual version (OPA2357) is
offered in the VSSOP-10 package.
The dual version features completely independent
circuitry for lowest crosstalk and freedom from
interaction. Both versions are specified over the
extended –40°C to +125°C temperature range.
Device Information(1)
2 Applications
•
•
•
•
•
•
•
•
•
•
PART NUMBER
Video Processing
Ultrasound
Optical Networking, Tunable Lasers
Photodiode Transimpedance Amplifiers
Active Filters
High-Speed Integrators
Analog-to-Digital (A/D) Converter Input Buffers
Digital-to-Analog (D/A) Converter Output
Amplifiers
Barcode Scanners
Communications
PACKAGE
BODY SIZE (NOM)
OPA357
SOT23 (6)
2.90 mm × 1.60 mm
OPA2357
VSSOP (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
V+
-VIN
VOUT
OPA357
+VIN
V-
Enable
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA357, OPA2357
SBOS235F – MARCH 2002 – REVISED APRIL 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
4
4
4
4
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: VS = +2.7-V to +5.5-V
Single-Supply .............................................................
6.6 Typical Characteristics ..............................................
7
5
7
Detailed Description ............................................ 13
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
14
19
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Applications ............................................... 20
9
Power Supply Recommendations...................... 26
9.1 Power Dissipation ................................................... 26
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
28
28
28
28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (May 2009) to Revision F
Page
•
Added Device Information table, Pin Functions table, ESD Ratings table, Recommended Operating Conditions
table, Thermal Information table, Overview section, Functional Block Diagram section, Feature Description section,
Device Functional Modes section, Application and Implementation section, Power Supply Recommendations
section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section ................................................................................................................................................................ 1
•
Changed MSOP to VSSOP throughout document ................................................................................................................ 1
•
Deleted DDA package (SO-8 PowerPAD) from document ................................................................................................... 1
•
Changed MSOP to VSSOP throughout document ................................................................................................................ 1
•
Added WEBENCH Features bullet ........................................................................................................................................ 1
•
Deleted OADI from DBV pin drawing ..................................................................................................................................... 3
•
Deleted Package/Ordering Information table ......................................................................................................................... 4
•
Deleted footnote from Signal input pins parameter in Absolute Maximum Ratings table ...................................................... 4
•
Changed Temperature Range section of Electrical Characteristics table: changed θJA to RθJA and deleted Specified
range, Operating range, and Storage range parameters ....................................................................................................... 6
•
Added OPAx357 Comparison section and moved OPAx357 Related Products table to this section from page 1 ............. 14
•
Deleted first paragraph of Power Dissipation section........................................................................................................... 26
•
Changed PCB Layout title to Layout Guidelines .................................................................................................................. 26
•
Deleted PowerPAD Thermall Enhanced Package and PowerPAD Assembly Process sections......................................... 26
•
Added Custom Design With WEBENCH® Tools section ..................................................................................................... 27
2
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SBOS235F – MARCH 2002 – REVISED APRIL 2018
5 Pin Configuration and Functions
OPA357: DBV Package
6-Pin SOT-23
Top View
Out
1
6
V+
Out A 1
V-
2
5
Enable
-In A 2
+In
(1)
OPA2357: DGS Package
10-Pin VSSOP
Top View
3
4
10 V+
+In A 3
-In
9
Out B
8
-In B
A
B
V-
4
7
+In B
Enable A
5
6
Enable B
Pin 1 of the SOT23-6 is determined by orienting the package marking as indicated in the diagram.
Pin Functions
PIN
NAME
DBV
(SOT-23)
DGS
(VSSOP)
I/O
DESCRIPTION
Enable
5
—
—
Amplifier power down.
Low = disabled, high = normal operation (pin must be driven).
Enable A
—
5
—
Amplifier power down, channel A.
Low = disabled, high = normal operation (pin must be driven).
Enable B
—
6
—
Amplifier power down, channel B.
Low = disabled, high = normal operation (pin must be driven).
–In
4
—
I
Inverting input pin
–In A
—
2
I
Inverting input pin, channel A
–In B
—
8
I
Inverting input pin, channel B
+In
3
—
I
Noninverting input pin
+In A
—
3
I
Noninverting input pin, channel A
+In B
—
7
I
Noninverting input pin, channel B
Out
1
—
O
Output pin
Out A
—
1
O
Output pin, channel A
Out B
—
9
O
Output pin, channel B
V–
2
4
—
Negative power supply
V+
6
10
—
Positive power supply
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SBOS235F – MARCH 2002 – REVISED APRIL 2018
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6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN
Supply voltage, V+ to V−
Voltage
Signal input pins
(V–) – 0.5
(V–) – 0.5
Output short-circuit
(2)
–55
Junction temperature
Storage temperature, Tstg
(2)
V
V
10
mA
(V+) + 0.5
V
Continuous
Operating temperature
(1)
UNIT
7.5
(V+) + 0.5
Current
Enable input
MAX
–65
150
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Total supply voltage
TA
Ambient temperature
–40
NOM
MAX
25
UNIT
5.5
V
125
°C
6.4 Thermal Information
THERMAL METRIC (1)
OPA357
OPA2357
DBV (SOT-23)
DGS (VSSOP)
6 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
166.4
171.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
104.6
58.2
°C/W
RθJB
Junction-to-board thermal resistance
38.9
93.1
°C/W
ψJT
Junction-to-top characterization parameter
23.6
6.8
°C/W
ψJB
Junction-to-board characterization parameter
38.7
91.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS235F – MARCH 2002 – REVISED APRIL 2018
6.5 Electrical Characteristics: VS = +2.7-V to +5.5-V Single-Supply
at TA = 25°C, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±2
±8
UNIT
OFFSET VOLTAGE
VS = +5 V
VOS
Input offset voltage
dVOS/dT
VOS vs temperature
PSRR
Power-supply rejection ratio
Specified temperature range,
TA = –40°C to +125°C
mV
±10
Specified temperature range,
TA = –40°C to +125°C
±4
VS = +2.7 V to +5.5 V,
VCM = (VS / 2) – 0.55 V
±200
µV/°C
±800
µV/V
Specified temperature range,
TA = –40°C to +125°C
±900
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
3
±50
pA
±1
±50
pA
NOISE
en
Input voltage noise density
f = 1 MHz
6.5
nV/√Hz
in
Current noise density
f = 1 MHz
50
fA/√Hz
INPUT VOLTAGE RANGE
VCM
CMRR
Common-mode voltage range
Common-mode rejection ratio
(V–) – 0.1
VS = +5.5 V, –0.1 V < VCM < +3.5 V
66
Specified temperature range,
TA = –40°C to +125°C
64
VS = +5.5 V, –0.1 V < VCM < +5.6 V
56
Specified temperature range,
TA = –40°C to +125°C
55
(V+) + 0.1
V
80
dB
68
INPUT IMPEDANCE
Differential
1013 || 2
Ω || pF
Common-mode
1013 || 2
Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop gain
VS = +5 V, +0.3 V < VO < +4.7 V
94
Specified temperature range,
TA = –40°C to +125°C, VS = +5 V,
+0.4 V < VO < +4.6 V
90
110
dB
FREQUENCY RESPONSE
G = +1, VO = 100 mVPP, RF = 25 Ω
f−3dB
Small-signal bandwidth
GBP
Gain-bandwidth product
G = +10
f0.1dB
Bandwidth for 0.1-dB gain flatness
G = +2, VO = 100 mVPP
SR
Slew rate
Rise-and-fall time
Settling time, 0.1%
G = +2, VO = 100 mVPP
250
90
MHz
100
MHz
40
MHz
VS = +5 V, G = +1, 4-V step
150
VS = +5 V, G = +1, 2-V step
130
VS = +3 V, G = +1, 2-V step
110
V/µs
G = +1, VO = 100 mVPP, 10% to
90%
2
G = +1, VO = 2 VPP, 10% to 90%
11
VS = +5 V, G = +1, 2-V output step
30
ns
60
ns
5
ns
Settling time, 0.01%
ns
Overload recovery time
VIN × gain = VS
HD2
2nd-order harmonic distortion
G = +1, f = 1 MHz, VO = 2 VPP,
RL = 200 Ω, VCM = 1.5 V
–75
dBc
HD3
3rd-order harmonic distortion
G = +1, f = 1 MHz, VO = 2 VPP,
RL = 200 Ω, VCM = 1.5 V
–83
dBc
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Electrical Characteristics: VS = +2.7-V to +5.5-V Single-Supply (continued)
at TA = 25°C, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE (continued)
Differential gain error
NTSC, RL = 150 Ω
0.02%
Differential phase error
NTSC, RL = 150 Ω
0.09
Degrees
Channel-to-channel crosstalk,
OPA2357
f = 5 MHz
–100
dB
OUTPUT
VS = +5 V, RL = 1 kΩ, AOL > 94 dB
Voltage output swing from rail
Output current (1) (2)
IO
0.1
Specified temperature range,
TA = –40°C to +125°C, VS = +5 V,
RL = 1 kΩ, AOL > 90 dB
VS = +5 V, single
0.4
100
VS = +3 V, dual
Open-loop output resistance
V
mA
50
Closed-loop output impedance
RO
0.3
0.05
Ω
35
Ω
POWER SUPPLY
VS
Specified voltage range
2.7
Operating voltage range
VS = +5 V, enabled, IO = 0 V
IQ
Quiescent current (per amplifier)
5.5
2.5 to 5.5
4.9
Specified temperature range,
TA = –40°C to +125°C
V
V
6
7.5
mA
ENABLE, SHUTDOWN FUNCTION
Disabled (logic−low threshold)
0.8
Enabled (logic−high threshold)
Logic input current
2
V
200
nA
Turn-on time
100
ns
Turn-off time
30
ns
74
dB
Off isolation
Logic low
V
G = +1, 5 MHz, RL = 10 Ω
Quiescent current (per amplifier)
3.4
6
µA
THERMAL SHUTDOWN
TJ
Junction temperature
Shutdown
160
Reset from shutdown
140
SOT23-6
150
VSSOP-10
150
°C
TEMPERATURE RANGE
RθJA
(1)
(2)
6
Thermal resistance
°C/W
See Figure 21 and Figure 23.
Specified by design.
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6.6 Typical Characteristics
at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
3
VO = 0.1 VPP, RF = 604 W
0
Normalized Gain (dB)
0
Normalized Gain (dB)
3
G = +1,
RF = 25 W
VO = 0.1 VPP
G = +2, RF = 604 W
-3
G = +5, RF = 604 W
-6
G = +10, RF = 604 W
-9
-12
-3
G = -1
-6
G = -5
G = -10
-12
-15
100k
1M
10M
Frequency (Hz)
100M
-15
100k
1G
1M
10M
Frequency (Hz)
100M
1G
Figure 2. Inverting Small-Signal Frequency Response
Output Voltage (40 mV/div)
Output Voltage (500 mV/div)
Figure 1. Noninverting Small-Signal Frequency Response
Time (20 ns/div)
Time (20 ns/div)
Figure 3. Noninverting Small-Signal Step Response
Figure 4. Noninverting Large-Signal Step Response
0.5
0.4
Enabled
2.5
1.5
0.5
Normalized Gain (dB)
3.5
Disabled
VO = 0.1 VPP
0.3
4.5
Disable Voltage (V)
Output Voltage (400 mV/div)
G = -2
-9
G = +1,
RF = 25 W
0.2
0.1
0
-0.1
-0.2
G = +2,
RF = 604 W
-0.3
VOUT,
fIN = 5 MHz
-0.4
-0.5
100k
Time (200 ns/div)
Figure 5. Large-Signal Disable, Enable Response
1M
10M
Frequency (Hz)
100M
Figure 6. 0.1-dB Gain Flatness
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
-50
G = -1
f = 1 MHz
RL = 200 W
-60
-70
2nd-Harmonic
-80
-90
VO = 2 VPP
f = 1 MHz
RL = 200 W
-60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-50
-70
2nd-Harmonic
-80
-90
3rd-Harmonic
3rd-Harmonic
-100
-100
0
1
2
Output Voltage (VPP)
3
4
1
Figure 7. Harmonic Distortion vs Output Voltage
VO = 2 VPP
f = 1 MHz
RL = 200 W
-60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
Figure 8. Harmonic Distortion vs Noninverting Gain
-50
-50
10
Gain (V/V)
-70
2nd-Harmonic
-80
3rd-Harmonic
-90
-100
1
10
-60
G = +1
VO = 2 VPP
RL = 200 W
VCM = 1.5 V
-70
2nd-Harmonic
-80
3rd-Harmonic
-90
-100
100k
1M
Frequency (Hz)
Gain (V/V)
Figure 9. Harmonic Distortion vs Inverting Gain
-60
G = +1
VO = 2 VPP
f = 1 MHz
VCM = 1.5 V
-70
Figure 10. Harmonic Distortion vs Frequency
10k
Voltage Noise (nV/ÖHz),
Current Noise (fA/ÖHz)
Harmonic Distortion (dBc)
-50
2nd-Harmonic
-80
3rd-Harmonic
-90
-100
1k
Voltage Noise
Current Noise
100
10
1
100
1k
10
100
RL (W)
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 11. Harmonic Distortion vs Load Resistance
8
10M
Figure 12. Input Voltage and Current Noise Spectral Density
vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
3
9
RL = 10 kW
-3
-6
3
Normalized Gain (dB)
Normalized Gain (dB)
0
G = +1
RF = 0 W
VO = 0.1 VPP
CL = 0 pF
G = +1
VO = 0.1 VPP
RS = 0 W
6
RL = 1 kW
RL = 100 W
-9
RL = 50 W
-12
0
-3
CL = 47 pF
-6
-9
CL = 5.6 pF
-12
-15
100k
1M
10M
Frequency (Hz)
100M
-15
100k
1G
Figure 13. Frequency Response for Various RL
3
For 0.1-dB
Flatness
140
Normalized Gain (dB)
120
100
80
60
VIN
RS
VO
OPA357
CL
1 kW
0
1k
10
100
Capacitive Load (pF)
100M
1G
CL = 5.6 pF, RS = 0 W
CL = 47 pF, RS = 140 W
-3
CL = 100 pF, RS = 120 W
-6
-9
VIN
RS
VO
OPA357
CL
-12
20
1
10M
Frequency (Hz)
G = +1
VO = 0.1 VPP
0
40
1M
Figure 14. Frequency Response for Various CL
160
RS (W)
CL = 100 pF
-15
100k
Figure 15. Recommended RS vs Capacitive Load
1M
1 kW
10M
Frequency (Hz)
1G
100M
Figure 16. Frequency Response vs Capacitive Load
100
180
160
Open-Loop Phase (Degrees)
Open-Loop Gain (dB)
CMRR
CMRR, PSRR (dB)
80
PSRR+
60
PSRR40
20
140
120
Phase
100
80
60
40
Gain
20
0
-20
0
-40
10k
100k
1M
10M
Frequency (Hz)
100M
1G
Figure 17. Common-Mode Rejection Ratio and PowerSupply Rejection Ratio vs Frequency
10
100
1k
10k 100k
1M
Frequency (Hz)
10M
100M
1G
Figure 18. Open-Loop Gain and Phase
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
0.8
10k
Input Bias Current (pA)
dG/dP (%/Degrees)
0.7
0.6
0.5
dP
0.4
0.3
0.2
0.1
1k
100
10
dG
1
0
1
2
3
Number of 150-W Loads
4
-55
Figure 19. Composite Video differential Gain and Phase
-35
-15
5
25
45
65
Temperature (°C)
85
105 125 135
Figure 20. Input Bias Current vs Temperature
3
7
Supply Current (mA)
Output Voltage (V)
6
2
+125°C
+25°C
-55°C
1
VS = 5 V
5
4
VS = 2.5 V
3
2
1
0
0
0
20
40
60
80
Output Current (mA)
100
120
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105 125 135
VS = 3 V
Figure 21. Output Voltage Swing vs Output Current
Figure 22. Supply Current vs Temperature
5
4.5
VS = 5.5 V
4.0
Shutdown Current (mA)
Output Voltage (V)
4
3
+125°C
+25°C
-55°C
2
1
3.5
3.0
VS = 5 V
2.5
2.0
1.5
1.0
0
VS = 2.5 V
VS = 3 V
0.5
0
0
25
50
75
100
125
Output Current (mA)
150
175
200
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105
125 135
VS = 5 V
Figure 23. Output Voltage Swing vs Output Current
10
Figure 24. Shutdown Current vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
0
Output Impedance (W)
-20
Feedthrough (dB)
100
VDISABLE = 0
RL = 10 W
-40
-60
Forward
Reverse
-80
10
1
0.1
OPA357
-100
ZO
-120
100k
1M
10M
Frequency (Hz)
100M
0.01
100k
1G
Figure 25. Disable Feedthrough vs Frequency
10M
Frequency (Hz)
100M
1G
Figure 26. Closed-Loop Output Impedance vs Frequency
6
0.5
VS = 5.5 V
0.4
5
4
VO = 2 VPP
0.3
Maximum Output
Voltage Without
Slew-Rate
Induced Distortion
Output Error (%)
Output Voltage (VPP)
1M
3
VS = 2.7 V
2
0.2
0.1
0
-0.1
-0.2
-0.3
1
-0.4
0
-0.5
1
10
Frequency (MHz)
100
0
Figure 27. Maximum Output Voltage vs Frequency
10
20
30
40
50
60
Time (ns)
70
80
90
100
Figure 28. Output Settling Time to 0.1%
120
RL = 1 kW
Population
Open-Loop Gain (dB)
110
100
90
80
70
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105 125 135
Figure 29. Open-Loop Gain vs Temperature
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3
Offset Voltage (mV)
4 5 6
7 8
Figure 30. Offset Voltage Production Distribution
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS / 2 (unless otherwise noted)
0
Crosstalk, Input-Referred (dB)
100
CMRR, PSRR (dB)
90
Common-Mode Rejection Ratio
80
Power-Supply Rejection Ratio
70
60
50
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105 125 135
-40
-60
OPA2357
-80
-100
-120
100k
1M
10M
100M
1G
Frequency (Hz)
Figure 31. Common-Mode Rejection Ratio and PowerSupply Rejection Ratio vs Temperature
12
-20
Figure 32. Channel-to-Channel Crosstalk
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7 Detailed Description
7.1 Overview
The OPA357 is a CMOS, rail-to-rail I/O, high-speed, voltage-feedback operational amplifier designed for video,
high-speed, and other applications. The device is available as a single or dual op amp.
The amplifier features a 100-MHz gain bandwidth, and 150-V/µs slew rate, but is unity-gain stable and can be
operated as a +1-V/V voltage follower.
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
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7.3 Feature Description
7.3.1 OPAx357 Comparison
Table 1 lists several members of the device family that includes the OPAx357.
Table 1. OPAx357 Related Products
PART NUMBER
FEATURED
OPAx354
Non-shutdown version of OPA357 family
OPAx355
200-MHz GBW, rail-to-rail output, CMOS, shutdown
OPAx356
200-MHz GBW, rail-to-rail output, CMOS
OPAx350, OPAx353
38-MHz GBW, rail-to-rail input/output, CMOS
OPAx631
75-MHz BW G = 2, rail-to-rail output
OPAx634
150-MHz BW G = 2, rail-to-rail output
THS412x
100-MHz BW, differential input/output, 3.3-V supply
7.3.2 Operating Voltage
The OPA357 is specified over a power-supply range of +2.7 V to +5.5 V (±1.35 V to ±2.75 V). However, the
supply voltage can range from +2.5 V to +5.5 V (±1.25 V to ±2.75 V). Supply voltages higher than 7.5 V
(absolute maximum) can permanently damage the amplifier.
Parameters that vary over supply voltage or temperature are shown in the Typical Characteristics section.
7.3.3 Enable Function
The OPA357 enable function is implemented using a Schmitt trigger. The amplifier is enabled by applying a TTL
high voltage level (referenced to V−) to the Enable pin. Conversely, a TTL low voltage level (referenced to V−)
disables the amplifier, reducing its supply current from 4.9 mA to only 3.4 µA per amplifier. Independent Enable
pins are available for each channel (dual version), providing maximum design flexibility. For portable batteryoperated applications, this feature can be used to greatly reduce the average current and thereby extend battery
life.
The Enable input can be modeled as a CMOS input gate with a 100-kΩ pull-up resistor to V+. Connect this pin to
a valid high or low voltage or driven, not left open circuit.
The enable time is 100 ns and the disable time is only 30 ns. This time allows the OPA357 to be operated as a
gated amplifier, or to have its output multiplexed onto a common output bus. When disabled, the output assumes
a high-impedance state.
7.3.4 Rail-to-Rail Input
The specified input common-mode voltage range of the OPA357 extends 100 mV beyond the supply rails. This
range is achieved with a complementary input stage—an N-channel input differential pair in parallel with a Pchannel differential pair; see the Functional Block Diagram section. The N-channel pair is active for input
voltages close to the positive rail, typically (V+) − 1.2 V to 100 mV above the positive supply, whereas the Pchannel pair is on for inputs from 100 mV below the negative supply to approximately (V+) − 1.2 V. There is a
small transition region, typically (V+) − 1.5 V to (V+) − 0.9 V, in which both pairs are on. This 600-mV transition
region can vary ±500 mV with process variation. Thus, the transition region (both input stages on) can range
from (V+) − 2.0 V to (V+) − 1.5 V on the low end, up to (V+) − 0.9 V to (V+) − 0.4 V on the high end.
A double-folded cascode adds the signal from the two input pairs and presents a differential signal to the class
AB output stage.
7.3.5 Rail-to-Rail Output
A class AB output stage with common-source transistors is used to achieve rail-to-rail output. For highimpedance loads (> 200 Ω), the output voltage swing is typically 100 mV from the supply rails. With 10-Ω loads,
a useful output swing can be achieved while maintaining high open-loop gain; see Figure 21 and Figure 23.
14
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7.3.6 Output Drive
The OPA357 output stage can supply a continuous output current of ±100 mA and still provide approximately
2.7 V of output swing on a 5-V supply, as shown in Figure 33. For maximum reliability, TI recommends running a
continuous DC current in excess of ±100 mA; see Figure 21 and Figure 23. For supplying continuous output
currents greater than ±100 mA, the OPA357 can be operated in parallel as shown in Figure 34.
The OPA357 provides peak currents up to 200 mA, which corresponds to the typical short-circuit current.
Therefore, an on-chip thermal shutdown circuit is provided to protect the OPA357 from dangerously high junction
temperatures. At 160°C, the protection circuit shuts down the amplifier. Normal operation resumes when the
junction temperature cools to below 140°C.
R2
1 kW
C1
50 pF
+
-
V1
5V
1 mF
R1
10 kW
V+
OPA357
+
R3
VIN 10 kW
VRSHUNT
R4
1 kW
-
1-V In = 100-mA
Out, as Shown
Laser Diode
Figure 33. Laser Diode Driver
R2
10 kW
C1
200 pF
+5 V
1 mF
R1
100 kW
R5 = 1 W
OPA2357
R3
100 kW
+
-
2-V In = 200-mA
Out, as Shown
R6 = 1 W
RSHUNT
1W
OPA2357
R4
10 kW
Laser Diode
Figure 34. Parallel Operation
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7.3.7 Video
The OPA357 output stage is capable of driving standard back-terminated 75-Ω video cables, as shown in
Figure 35. By back-terminating a transmission line, the cable does not exhibit a capacitive load to its driver. A
properly back-terminated 75-Ω cable does not appear as capacitance; this cable presents only a 150-Ω resistive
load to the OPA357 output.
+5 V
Video
In
75 W
OPA357
75 W
+2.5 V
Video
Output
To enable,
connect to V+
or drive with logic.
604 W
604 W
+2.5 V
Figure 35. Single-Supply Video Line Driver
The OPA357 can be used as an amplifier for RGB graphic signals, which have a voltage of zero at the video
black level, by offsetting and AC-coupling the signal, as shown in Figure 36.
604 W
+3 V
+
V+
Red
10 nF
604 W
75 W
1/2
OPA2357
R1
(1)
1 mF
Red
75 W
R2
V+
Green
R1
(1)
R2
604 W
75 W
1/2
OPA2357
Green
75 W
604W
604 W
+3 V
+
V+
Blue
(1)
1 mF
10 nF
604 W
R1
75 W
OPA357
Blue
75 W
R2
(1)
The source video signal offset is 300 mV above ground to accommodate the op amp swing-to-ground capability.
Figure 36. RGB Cable Driver
16
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7.3.8 Wideband Video Multiplexing
One common application for video speed amplifiers that include an Enable pin is to wire multiple amplifier
outputs together, then select which one of several possible video inputs to source onto a single line. This simple
wired-OR video multiplexer can be easily implemented using the OPA357, as shown in Figure 37.
+2.5 V
+
49.9 W
Signal 1
1 mF
10 nF
1 mF
10 nF
A
OPA357
+
-2.5 V
1 kW
49.9 W
VOUT
1 kW
49.9 W
+2.5 V
+
49.9 W
Signal 2
1 mF
10 nF
1 mF
10 nF
B
OPA357
+
-2.5 V
1 kW
1 kW
HCO4
BON
Select
AON
Figure 37. Multiplexed Output
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7.3.9 Driving Analog-to-Digital Converters
The OPA357 series op amps offer 60 ns of settling time to 0.01%, making the series a good choice for driving
high- and medium-speed sampling A/D converters and reference circuits. The OPA357 series provides an
effective means of buffering the A/D converter input capacitance and resulting charge injection while providing
signal gain.
Figure 38 shows the OPA357 driving an A/D converter. With the OPA357 in an inverting configuration, a
capacitor across the feedback resistor can be used to filter high-frequency noise in the signal, as shown in
Figure 38.
+5 V
330 pF
5 kW
5 kW
VIN
V+
5 kW
ADS7818, ADS7861,
or ADS7864
12-Bit A/D Converter
+In
OPA357
+2.5 V
VREF
0.1 mF -In
GND
NOTE: A/D converter input = 0 V to VREF.
NOTE: VIN = 0 V to –5 V for a 0-V to 5-V output.
Figure 38. The OPA357 in Inverting Configuration Driving an A/D Converter
7.3.10 Capacitive Load and Stability
The OPA357 series of op amps can drive a wide range of capacitive loads. However, all op amps under certain
conditions may become unstable. Op amp configuration, gain, and load value are just a few factors to consider
when determining stability. An op amp in unity-gain configuration is most susceptible to the effects of capacitive
loading. The capacitive load reacts with the op amp output resistance, along with any additional load resistance,
to create a pole in the small-signal response that degrades the phase margin; see Figure 14 for details.
The OPA357 topology enhances its ability to drive capacitive loads. In unity gain, these op amps perform well
with large capacitive loads. See Figure 15 for details.
One method of improving capacitive load drive in the unity-gain configuration is to insert a 10-Ω to 20-Ω resistor
in series with the output, as shown in Figure 39. This method significantly reduces ringing with large capacitive
loads; see Figure 14. However, if there is a resistive load in parallel with the capacitive load, RS creates a voltage
divider. This process introduces a DC error at the output and slightly reduces output swing. This error can be
insignificant. For instance, with RL = 10 kΩ and RS = 20 Ω, there is only about a 0.2% error at the output.
V+
RS
VOUT
OPA357
VIN
RL
CL
To enable,
connect to V+
or drive with logic.
Figure 39. Series Resistor in Unity-Gain Configuration Improves Capacitive Load Drive
18
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7.3.11 Wideband Transimpedance Amplifier
Wide bandwidth, low input bias current, and low input voltage and current noise make the OPA357 an ideal
wideband photodiode transimpedance amplifier for low-voltage single-supply applications. Low-voltage noise is
important because photodiode capacitance causes the effective noise gain of the circuit to increase at high
frequency.
The key elements to a transimpedance design, as shown in Figure 40, are the expected diode capacitance
(including the parasitic input common-mode and differential-mode input capacitance (2 + 2)pF for the OPA357),
the desired transimpedance gain (RF), and the gain bandwidth product (GBP) for the OPA357 (100 MHz). With
these three variables set, the feedback capacitor value (CF) can be set to control the frequency response.
CF
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